TPS7A19 [TI]

具有电源正常指示和使能功能的 450mA、40V、低 IQ、可调节低压降稳压器;


型号：	TPS7A19
厂家：	TEXAS INSTRUMENTS
描述：	具有电源正常指示和使能功能的 450mA、40V、低 IQ、可调节低压降稳压器稳压器
文件：	总24页 (文件大小：1096K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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TPS7A19

ZHCSFK0A –MAY 2016–REVISED SEPTEMBER 2016

TPS7A19

是具有电源正常指示功能的 40V、450mA、宽 V_IN、低 I_Q、低压降稳压器

1 特性

3 说明

•

宽输入电压范围：4V 到 40V

TPS7A19 是具有高达 40V 宽输入电压 (V_IN) 范围的低

压降稳压器 (LDO)，能够提供高达 450mA (I_OUT) 的高

输出电流。此稳压器非常适用于从宽输入电压轨生成低

压电源。TPS7A19 不但能够提供一个充分稳压的电压

轨，而且能够通过充当简单的浪涌保护电路承受电压瞬

变并在其间保持稳压状态。

可调节输出电压：1.5V 至 18V

输出电流：450mA

低静态电流 (I_Q)：15µA

低压降电压：400mA 时为 450mV（最大值）

具有可编程延迟的电源正常指示功能

热关断及过流保护功能

TPS7A19 在轻负载下仅消耗 15µA 的静态电流 (I_Q)，

因此可降低常开系统或电池供电的功耗应用的外部组

件尺寸。

与陶瓷输出电容搭配使用时可保持稳定：

–

当 V_OUT≥ 2.5V 时，电容为 10µF 到 500µF

当 V_OUT< 2.5V 时，电容为 22µF 到 500µF

TPS7A19 特性集成热关断及过流保护。TPS7A19 还

提供具有可编程延迟的电源正常指示输出 (PG)，指示

输出电压处于稳压状态。此特性对电源轨排序功能极为

有用。

•

工作温度：-40°C 至 +125°C

封装方式：3mm x 3mm 小外形尺寸无引线 (SON)-

2 应用范围

此 LDO 采用小型 3mm × 3mm 耐热增强型 8 引脚

SON 封装。

•

智能电网基础设施和计量

电动工具

器件信息⁽¹⁾

电机驱动

器件型号

TPS7A19

封装

SON (8)

封装尺寸（标称值）

访问控制系统

测试和测量

3.00mm × 3.00mm

(1) 要了解所有可用封装，请参见数据表末尾的封装选项附录。

典型应用电路原理图

静态电流与输入电压间的关系

V_OUT= 1.5V 时

4 V to 40 V

MSP430

V_IN

V_OUT

OUT

VDD

TPS7A19

DELAY

GND

œ40°C

25°C

125°C

Input Voltage (V)

C003

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

English Data Sheet: SBVS256

TPS7A19

ZHCSFK0A –MAY 2016–REVISED SEPTEMBER 2016

www.ti.com.cn

7.4 Device Functional Modes........................................ 10

Application and Implementation ........................ 11

8.1 Application Information............................................ 11

8.2 Typical Application .................................................. 11

Power Supply Recommendations...................... 13

特性.......................................................................... 1

应用范围................................................................... 1

说明.......................................................................... 1

修订历史记录 ........................................................... 2

Pin Configuration and Functions......................... 3

Specifications......................................................... 4

6.1 Absolute Maximum Ratings ...................................... 4

6.2 ESD Ratings.............................................................. 4

6.3 Recommended Operating Conditions....................... 4

6.4 Thermal Information.................................................. 4

6.5 Electrical Characteristics........................................... 5

6.6 Timing Requirements................................................ 5

6.7 Typical Characteristics.............................................. 6

Detailed Description .............................................. 8

7.1 Overview ................................................................... 8

7.2 Functional Block Diagram ......................................... 8

7.3 Feature Description................................................... 8

10 Layout................................................................... 13

10.1 Layout Guidelines ................................................. 13

10.2 Layout Example .................................................... 13

11 器件和文档支持 ..................................................... 14

11.1 器件支持................................................................ 14

11.2 文档支持 ............................................................... 14

11.3 接收文档更新通知 ................................................. 14

11.4 社区资源................................................................ 14

11.5 商标....................................................................... 14

11.6 静电放电警告......................................................... 15

11.7 Glossary................................................................ 15

12 机械、封装和可订购信息....................................... 15

4 修订历史记录

Changes from Original (May 2016) to Revision A

Page

•

已从“产品预览”改为“量产数据”................................................................................................................................................ 1

TPS7A19

www.ti.com.cn

ZHCSFK0A –MAY 2016–REVISED SEPTEMBER 2016

5 Pin Configuration and Functions

DRB Package

8-Pin SON With Thermal Pad

Top View

DELAY

OUT

Thermal

Pad

GND

Not to scale

Pin Functions

I/O

DESCRIPTION

NAME

NO.

Delay pin. Connect a capacitor to GND to adjust the PG delay time; leave open if the PG function is not

needed.

DELAY

—

Enable pin. This pin turns the regulator on or off. If V_EN≥ V_{EN_HI}, the regulator is enabled. If V_EN

≤

V_{EN_LO}, the regulator is disabled. If not used, the EN pin can be connected to IN.

4,5

—

Feedback pin. The feedback pin is the input to the control-loop error amplifier.

GND

Ground pin.

Regulator input supply pin.

Regulator output pin. When the output voltage is larger than 2.5 V, connect a 10-μF to 500-μF ceramic

capacitor with an equivalent series resistance (ESR) from 0.001 to 20 Ω to assure stability. When the

output voltage is from 1.5 V to 2.5 V, the minimum, stable capacitor value should be 22 μF.

OUT

Power good. This open-drain pin must be connected to V_OUTthrough an external resistor. PG is pulled

low when the output voltage goes below threshold.

Solder to printed-circuit-board (PCB) to enhance thermal performance. Although the thermal pad can be

left floating, connect the thermal pad to the ground plane for optimal performance.

Thermal pad

—

TPS7A19

ZHCSFK0A –MAY 2016–REVISED SEPTEMBER 2016

www.ti.com.cn

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range –40°C to 125°C(unless otherwise noted)⁽¹⁾

MIN

MAX

UNIT

Input

IN, EN

–0.3

OUT⁽³⁾

DELAY⁽⁴⁾

FB, PG

V_IN+ 0.3

Voltage⁽²⁾

Output

Internally limited

150

Current

Peak output

Operating junction, T_J

Storage, T_stg

–40

–65

Temperature

°C

150

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings

only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating

conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltage values are with respect to GND.

(3) The absolute maximum rating is VIN + 0.3 V or 22 V, whichever is lower.

(4) The voltage at the DELAY pin must be lower than the V_INvoltage.

6.2 ESD Ratings

VALUE

±2000

±500

UNIT

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾

Charged-device model (CDM), per JEDEC specification JESD22-C101⁽²⁾

V_(ESD)

Electrostatic discharge

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN

MAX

UNIT

V_IN

Input supply voltage

Output voltage

1.5

V_OUT

V_EN

T_J

Enable voltage

Operating junction temperature

–40

125

°C

6.4 Thermal Information

TPS7A19

THERMAL METRIC⁽¹⁾

DRB (VSON)

8 PINS

UNIT

R_θJA

Junction-to-ambient thermal resistance

°C/W

R_θJC(top)

R_θJB

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

56.3

22.4

ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

0.9

ψ_JB

22.5

R_θJC(bot)

4.6

(1) For information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

TPS7A19

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ZHCSFK0A –MAY 2016–REVISED SEPTEMBER 2016

6.5 Electrical Characteristics

at T_J= –40°C to +125°C, V_IN= 14 V , V_EN= V_IN, I_OUT= 200 μA, C_IN= 22 μF, and C_OUT= 47 μF (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

SUPPLY VOLTAGE AND CURRENT

_OUT≤ 3.5 V , I_OUT= 0 mA to 450 mA

_OUT≥ 3.5 V , I_OUT= 0 mA to 450 mA

V_IN

Input voltage

V_OUT+ 0.5

V_IN= 4 V to 40 V, V_OUT= 1.5 V, V_EN= 5 V, I_OUT= 0.2 mA

V_IN= 18.5 V to 40 V, V_OUT= 18 V, V_EN= 5 V, I_OUT= 0.2 mA

V_EN= 0 V, I_OUT= 0 mA , V_IN= 18 V, V_OUT= 1.5 V

Reference voltage for FB pin

I_Q

Quiescent current

µA

I_SHDN

Shutdown current

Feedback voltage

Undervoltage lockout

µA

V_FB

1.208

1.233

1.258

2.6

V_{IN_UVLO}

Ramp V_INdown until output is turned off

Undervoltage detection

hysteresis

UVLO_Hys

V_INrising

ENABLE INPUT (EN)

V_{EN_LO}

V_{EN_HI}

I_EN

Logic input low level

0.4

Logic input high level

EN pin current

1.7

V_EN= 40 V , V_IN= 14 V

µA

REGULATED OUTPUT

V_IN= V_OUT+ 1 V to 40 V and V_IN≥ 4 V,

I_OUT= 100 µA to 450 mA

V_OUT

Regulated output⁽¹⁾

–2%

ΔV_O(ΔVI)

ΔV_O(ΔIL)

Line regulation

Load regulation

V_IN= V_OUT+ 1 V to 40 V and V_IN≥ 4 V, I_OUT= 100 mA

I_OUT= 1 mA to 450 mA, V_IN= V_OUT+ 1 V and V_IN≥ 4 V

V_IN– V_OUT, I_OUT= 400 mA

240

160

450

300

450

360

850

V_DO

I_OUT

I_CL

Dropout voltage

Output current

V_IN– V_OUT, I_OUT= 200 mA

V_OUTin regulation

140

470

V_OUTshort to ground

Output current-limit

V_OUT= V_OUTnominal × 0.9

f = 100 Hz

I_OUT= 100 mA, C_OUT= 22 µF

f = 100 kHz

PSRR

Power-supply ripple rejection⁽²⁾

V_OL

PG output low voltage

PG leakage current

Power good threshold

Hysteresis

I_OL= 0.5 mA

0.4

I_OH

PG pulled to V_OUTwith 10-kΩ resistor

V_OUTpower-up

µA

V_T(PG)

V_hys

89.6

91.6

93.6 % of V_OUT

% of V_OUT

V_OUTpower-down

PG DELAY

I_Delay

Delay capacitor charging current

9.5

µA

Delay pin comparator threshold

voltage

V_{T(PG_DLY)}

TEMPERATURE

T_sd

Junction shutdown temperature

Hysteresis of thermal shutdown

Temperature increasing

175

°C

T_hys

(1) Accuracy specification does not apply on any application condition that exceeds the power dissipation limit of the package under test.

External resistor divider variation is not considered for accuracy measurement.

(2) Design information; not tested, specified by characterization.

6.6 Timing Requirements

MIN

TYP

MAX

UNIT

TIMING FOR PG

t_{PG_DLY}Power good delay

t_PG-fixedPower good delay

C = delay-capacitor value capacitance = 100 nF⁽¹⁾

No capacitor on pin

10.5

325

180

µs

t_PG(HL)

PG falling propagation delay V_OUTlow to PG low

(1) Information only; not tested in production. The equation is based on: (C × 1) / (9.5 × 10^–6) = t_{PG_DLY}, where C = delay capacitor value

capacitance; range = 100 pF to 500 nF.

TPS7A19

ZHCSFK0A –MAY 2016–REVISED SEPTEMBER 2016

www.ti.com.cn

6.7 Typical Characteristics

at T_J= –40°C to +125°C, V_IN= 14 V , V_EN= V_IN, I_OUT= 200 μA, C_IN= 22 μF, and C_OUT= 47 μF (unless otherwise noted)

1.60

1.58

1.56

1.54

1.52

1.50

1.48

1.46

1.44

1.42

1.40

160

140

120

100

œ40°C

25°C

œ40°C

25°C

125°C

100 150 200 250 300 350 400 450

Input Voltage (V)

Output Current (mA)

V_OUT= 1.5 V, I_OUT= 100 mA

Figure 1. Line Regulation

V_IN= 14 V, V_OUT= 1.5 V

Figure 2. Ground Current vs Output Current

160

140

120

100

œ40°C

25°C

œ40°C

25°C

125°C

100 150 200 250 300 350 400 450

Input Voltage (V)

C003

Output Current (mA)

C004

V_OUT= 1.5 V

V_IN= 24 V, V_OUT= 18 V

Figure 3. Quiescent Current vs Input Voltage

Figure 4. Ground Current vs Output Current

400

350

300

250

200

150

100

œ40°C

25°C

125°C

100 150 200 250 300 350 400 450

Output Current (mA)

Input Voltage (V)

C005

V_OUT= 18 V

Figure 5. Quiescent Current vs Input Voltage

Figure 6. Dropout Voltage vs Output Current

TPS7A19

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ZHCSFK0A –MAY 2016–REVISED SEPTEMBER 2016

Typical Characteristics (continued)

at T_J= –40°C to +125°C, V_IN= 14 V , V_EN= V_IN, I_OUT= 200 μA, C_IN= 22 μF, and C_OUT= 47 μF (unless otherwise noted)

1.60

1.58

1.56

1.54

1.52

1.50

1.48

1.46

1.44

1.42

1.40

120

100

œ40°C

25°C

125°C

10M

10 100 1k

10 100

10k

100k

100 150 200 250 300 350 400 450

1000 10000 100000 100000010000001000000000

Frequency (Hz)

Output Current (mA)

C007

V_IN= 14 V, V_OUT= 1.5 V

V_OUT= 5 V, C_OUT= 47 µF, I_OUT= 10 mA

Figure 7. Load Regulation

Figure 8. Power-Supply Rejection Ratio vs Frequency

220

215

210

205

200

195

190

630

620

610

600

590

580

570

560

550

540

530

520

œ40 œ25 œ10

20 35 50 65 80 95 110 125

œ40 œ25 œ10

20 35 50 65 80 95 110 125

Temperature (°C)

C013

C014

Figure 9. Short to GND Current-Limit vs Temperature

Figure 10. Current-Limit vs Temperature

Figure 11. Load Transient

10-µF Ceramic Output Capacitor

TPS7A19

ZHCSFK0A –MAY 2016–REVISED SEPTEMBER 2016

www.ti.com.cn

7 Detailed Description

7.1 Overview

The TPS7A19 is a low-dropout linear regulator (LDO) combined with enable and power good functions. The

power good pin initializes when the output voltage, V_OUT, exceeds V_T(PG). The power good delay is a function of

the value set by an external capacitor on the DELAY pin before releasing the PG pin high.

7.2 Functional Block Diagram

OUT

UVLO

Pass

Device

Thermal

Shutdown

Current

Limit

Error

Amp

Enable

Power

Good

Control

DELAY

7.3 Feature Description

7.3.1 Enable Pin (EN)

The enable pin is a high-voltage-tolerant pin. A logic-high input on EN actives the device and turns on the LDO.

For self-bias applications, connect this input to the IN pin.

7.3.2 Regulated Output Pin (OUT)

The OUT pin is the regulated output based on the required voltage. The output is protected by internal current

limiting. During initial power up, the LDO has a soft start feature incorporated to control the initial current through

the pass element.

In the event that the LDO drops out of regulation, the output tracks the input minus a voltage drop based on the

load current. When the input voltage drops below the UVLO threshold, the LDO shuts down until the input

voltage exceeds the minimum start-up level.

7.3.3 Power-Good Pin (PG)

The power good pin is an output with an external pullup resistor to the regulated supply. The output remains low

until the regulated V_OUTexceeds approximately 91.6% of the set value, and the power good delay has expired.

The regulated output falling below the 89.6% level asserts this output low after a short deglitch time of

approximately 180 µs (typical).

TPS7A19

www.ti.com.cn

ZHCSFK0A –MAY 2016–REVISED SEPTEMBER 2016

Feature Description (continued)

7.3.4 Delay Timer Pin (DELAY)

An external capacitor on the DELAY pin sets the timer delay before the PG pin is asserted high. The constant

output current charges an external capacitor until the voltage exceeds a threshold that trips an internal

comparator. If this pin is open, the default delay time is 325 µs (typical).

The pulse delay time, t_{PG_DLY}, is defined with the charge time of an external capacitor DELAY, as shown in

Equation 1.

≈

∆

’

◊

C_DELAYì 1 V

9.5 ꢀA

t_{PG_DLY}

+ 325 ꢀs

(1)

The PG pin initializes when V_OUTexceeds 91.6% of the programmed value. The delay is a function of the value

set by an external capacitor on the DELAY pin before the PG pin is released high.

V_IN

t < t_PG(HL)

V_T(PG)

V_{T(PG) œ}V_hys

V_OUT

V_{T(PG_DLY)}

V_DELAY

t_{PG_DLY}

t_PG(HL)

V_PG

Figure 12. Conditions to Activate PG

7.3.5 Adjustable Output Voltage (ADJ for TPS7A1901)

An output voltage between 1.5 V and 18 V can be selected by using the external resistor dividers. Use

Equation 2 to calculate the output voltage, where V_FB= 1.233 V. In order to avoid a large leakage current and to

prevent a divider error, the value of (R1 + R2) must between 10 kΩ and 100 kΩ.

≈

’

V_OUT= V_FBì 1 +

∆

◊

(2)

7.3.6 Undervoltage Shutdown

The TPS7A19 family of devices has an internally-fixed, undervoltage-shutdown threshold. Undervoltage

shutdown activates when the input voltage on V_INdrops below V_{IN_UVLO}. This activation makes sure that the

regulator is not latched in an unknown state when there is a low-input supply voltage. If the input voltage has a

negative transient that drops below the UVLO threshold and recovers, the regulator shuts down and powers up,

similar to a typical power-up sequence when the input voltage exceeds the required levels.

TPS7A19

ZHCSFK0A –MAY 2016–REVISED SEPTEMBER 2016

www.ti.com.cn

Feature Description (continued)

7.3.7 Thermal Shutdown

The TPS7A19 incorporates a thermal shutdown (TSD) circuit as protection from overheating. For continuous

standard operation, the junction temperature must not exceed the TSD trip point. If the junction temperature

exceeds the TSD trip point, the output turns off. When the junction temperature falls below the TSD trip point

minus the TSD hysteresis value, the output turns on again.

Thermal protection disables the output when the junction temperature rises to approximately 175°C, and allows

the device to cool. When the junction temperature cools to approximately 150°C, the output circuitry enables.

Based on power dissipation, thermal resistance, and ambient temperature, the thermal protection circuit may

cycle on and off. This cycling limits the temperature of the regulator, and protects the device from damage as a

result of overheating.

Although the internal protection circuitry of the TPS7A19 device is designed to protect against overload

conditions, the circuitry is not intended to replace proper heat-sink methods. Continuously running the TPS7A19

device into thermal shutdown degrades device reliability.

7.4 Device Functional Modes

7.4.1 Operation With V_IN< 4 V

The devices operate with input voltages above 4 V. The devices do not operate at input voltages below the

actual UVLO voltage.

7.4.2 Operation With EN Control

The enable rising edge threshold voltage is 1.7 V, maximum. When the EN pin is held above 1.7 V, and the input

voltage is greater than the UVLO rising voltage, the device enables.

The enable falling edge is 0.4 V, minimum. When the EN pin is held below 0.4 V, the device is disabled. The

quiescent current is reduced in this state.

TPS7A19

www.ti.com.cn

ZHCSFK0A –MAY 2016–REVISED SEPTEMBER 2016

8 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

8.1 Application Information

Figure 13 shows a typical application circuit for the TPS7A1901. Based on the end-application, different values of

external components can be used. Some applications may require a larger output capacitor during fast load

steps in order to prevent a PG low from occurring. Use a low-ESR ceramic capacitor with a dielectric of type X5R

or X7R for better load transient response.

8.2 Typical Application

V_PG

V_IN

V_OUT

OUT

TPS7A19

R₁

R₂

C_IN

C_OUT

DELAY

GND

C_DELAY

Figure 13. Adjustable Operation

8.2.1 Design Requirements

For this design example, use the parameters listed in Table 1.

Table 1. Design Parameters

DESIGN PARAMETER

Input voltage

EXAMPLE VALUE

12 V, ±10%

3.3 V

Output voltage

Output current

50 mA (max)

1 ms

PG delay time

8.2.2 Detailed Design Procedure

To begin the design process:

1. First, make sure that the combination of maximum current, maximum ambient temperature, maximum input

voltage, and minimum output voltage does not exceed the maximum operating condition of T_J= 125°C. The

Power Dissipation and Thermal Considerations section describes how to calculate the maximum ambient

temperature and power dissipation.

2. Next, set the feedback resistors to give the desired output voltage. See Equation 2 for the V_OUTrelationship

to R1 and R2. A good nominal value for R2 is 10 kΩ.

3. Then, calculate the required C_DELAYcapacitor to achieve the desired PG delay time using Equation 1. For 1

ms of delay, the nearest standard value capacitor is 10 nF.

4. Finally, select an output capacitor with a total effective capacitance between 22 µF and 500 µF, a sufficient

voltage rating, and an ESR below 20 Ω. Higher capacitance gives improved transient response, but results in

higher inrush current at startup.

TPS7A19

ZHCSFK0A –MAY 2016–REVISED SEPTEMBER 2016

www.ti.com.cn

8.2.2.1 Power Dissipation and Thermal Considerations

Device power dissipation is calculated with Equation 3.

P_D= I_OUTì V - V_OUT+ I ì V

(

)

where

•

P_D= continuous power dissipation

I_OUT= output current

V_IN= input voltage

V_OUT= output voltage

(3)

As I_Q« I_OUT, the term I_Q× V_INin Equation 3 can be ignored.

For a device under operation at a given ambient air temperature (T_A), calculate the junction temperature (T_J) with

Equation 4.

T = T + q ´ P_D

(

)

where

•

θ_JA= junction-to-ambient air thermal impedance

(4)

(5)

A rise in junction temperature because of power dissipation can be calculated with Equation 5.

DT = T - T = q ´ P_D

(

)

For a given maximum junction temperature (T_JM), the maximum ambient air temperature (T_AM) at which the

device can operate is calculated with Equation 6.

T_AM= T_JM- (q_JA´ P_D)

(6)

8.2.3 Application Curves

V_IN(10 V/div)

V_IN(5 V/div)

V_EN(10 V/div)

V_OUT(1 V/div)

V_EN(5 V/div)

V_PG(2 V/div)

V_OUT(1 V/div)

V_PG(2 V/div)

Time (1ms/div)

V_IN= 12 V, V_ENstep from 0 V to 12 V, C_IN= 10 µF,

V_IN= 12 V, V_ENstep from 12 V to 0 V, C_IN= 10 µF,

C_OUT= 22 µF, R_LOAD= 66 Ω

Figure 14. Enable Startup

Figure 15. Enable Shutdown

TPS7A19

www.ti.com.cn

ZHCSFK0A –MAY 2016–REVISED SEPTEMBER 2016

9 Power Supply Recommendations

The device operates from an input voltage supply range between 4 V and 40 V. This input supply must be well

regulated. If the input supply is located more than a few inches from the TPS7A19 device, add an electrolytic

capacitor with a value of 47 µF and a ceramic bypass capacitor at the input.

10 Layout

10.1 Layout Guidelines

•

To improve ac performance such as PSRR, output noise, and transient response, design the board with

separate ground planes for V_INand V_OUT, with each ground plane connected only at the GND pin of the

device. In addition, connect the ground connection for the output capacitor directly to the GND pin of the

device.

•

Minimize equivalent series inductance (ESL) and equivalent series resistance (ESR) in order to maximize

performance and stability. Place every capacitor as close to the device as possible, and on the same side of

the PCB as the regulator.

Do not place any of the capacitors on the opposite side of the PCB from where the regulator is installed. The

use of vias and long traces are strongly discouraged because of the negative impact on system performance.

Vias and long traces can also cause instability.

If possible, and to maximize the performance listed in this data sheet, use the same layout pattern used for

the TPS7A19 evaluation module, TPS7A1901EVM-760 (SBVU031).

10.2 Layout Example

Input Ground Plane

V_OUT

C_DELAY

C_IN

DELAY

OUT

Thermal

Pad

C_OUT

R₁

GND

Sense Line

V_IN

GND

R₂

Output Ground Plane

Notes: C_INand C_OUTare 1208 packages

C_DELAY, R₁, and R₂are 0402 packages

Denotes a via to a connection made on another layer

Figure 16. TPS7A19 Layout Example

TPS7A19

ZHCSFK0A –MAY 2016–REVISED SEPTEMBER 2016

www.ti.com.cn

11 器件和文档支持

11.1 器件支持

11.1.1 开发支持

11.1.1.1 评估模块

评估模块 (EVM) 可与 TPS7A19 配套使用，帮助评估初始电路性能。有关此固定装置的相关摘要信息，请参见表

2。

表 2. 评估模块

名称

EVM 文件夹

TPS7A19 40V、450mA 高电压、超低 IQ、低压降稳压器评估模块

TPS7A1901EVM-760

11.1.1.2 Spice 模型

分析模拟电路和系统的性能时，使用 SPICE 模型对电路性能进行计算机仿真非常有用。您可以从 TPS7A19 产品

文件夹中的工具和软件选项卡下获取 TPS7A19 的 SPICE 模型。

11.1.2 器件命名规则

表 3. 订购信息⁽¹⁾

产品

说明

XX 为标称输出电压选项；01 表示可调节。

YYY 为封装标识符。

TPS7A19XXYYYZ

Z 为封装数量。

(1) 欲获得最新的封装和订货信息，请参阅本文档末尾的封装选项附录，或者访问 www.ti.com 查看器件产品文件夹。

11.2 文档支持

11.2.1 相关文档

《TPS7A1901EVM-760 评估模块用户指南》（文献编号：SBVU031）

11.3 接收文档更新通知

如需接收文档更新通知，请访问 www.ti.com.cn 网站上的器件产品文件夹。点击右上角的提醒我 (Alert me) 注册

后，即可每周定期收到已更改的产品信息。有关更改的详细信息，请查阅已修订文档中包含的修订历史记录。

11.4 社区资源

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective

contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of

Use.

TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration

among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help

solve problems with fellow engineers.

Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and

contact information for technical support.

11.5 商标

E2E is a trademark of Texas Instruments.

All other trademarks are the property of their respective owners.

TPS7A19

www.ti.com.cn

ZHCSFK0A –MAY 2016–REVISED SEPTEMBER 2016

11.6 静电放电警告

ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可

能会损坏集成电路。

ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可

能会导致器件与其发布的规格不相符。

11.7 Glossary

SLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

12 机械、封装和可订购信息

以下页中包括机械、封装和可订购信息。这些信息是针对指定器件可提供的最新数据。这些数据会在无通知且不对

本文档进行修订的情况下发生改变。欲获得该数据表的浏览器版本，请查阅左侧的导航栏。

PACKAGE OPTION ADDENDUM

www.ti.com

18-Jul-2023

PACKAGING INFORMATION

Orderable Device

Status Package Type Package Pins Package

Eco Plan

Lead finish/

Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

(1)

(2)

(3)

(4/5)

(6)

TPS7A1901DRBR

TPS7A1901DRBT

ACTIVE

SON

DRB

3000 RoHS & Green

250 RoHS & Green

NIPDAU

Level-1-260C-UNLIM

-40 to 125

A1901

Samples

NIPDAU

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

⁽³⁾MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

⁽⁵⁾Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6)

Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

18-Jul-2023

Addendum-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

20-Apr-2023

TAPE AND REEL INFORMATION

REEL DIMENSIONS

TAPE DIMENSIONS

Reel

Diameter

Cavity

A0 Dimension designed to accommodate the component width

B0 Dimension designed to accommodate the component length

K0 Dimension designed to accommodate the component thickness

Overall width of the carrier tape

P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2

Q3 Q4

Q1 Q2

Q3 Q4

User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

TPS7A1901DRBR

TPS7A1901DRBT

SON

DRB

3000

250

330.0

180.0

12.4

3.3

1.1

8.0

12.0

250

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

20-Apr-2023

TAPE AND REEL BOX DIMENSIONS

Width (mm)

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

TPS7A1901DRBR

TPS7A1901DRBT

SON

DRB

3000

250

346.0

367.0

210.0

346.0

367.0

185.0

33.0

35.0

250

Pack Materials-Page 2

PACKAGE OUTLINE

DRB0008B

VSON - 1 mm max height

SCALE 4.000

PLASTIC SMALL OUTLINE - NO LEAD

3.1

2.9

PIN 1 INDEX AREA

3.1

2.9

1 MAX

SEATING PLANE

0.08 C

0.05

0.00

EXPOSED

THERMAL PAD

1.65 0.05

(0.2) TYP

1.95

2.4 0.05

6X 0.65

0.35

0.25

PIN 1 ID

0.1

C A B

0.5

0.3

(OPTIONAL)

0.05

4218876/A 12/2017

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

www.ti.com

EXAMPLE BOARD LAYOUT

DRB0008B

VSON - 1 mm max height

PLASTIC SMALL OUTLINE - NO LEAD

(1.65)

SYMM

8X (0.6)

8X (0.3)

(2.4)

(0.95)

6X (0.65)

(R0.05) TYP

(0.575)

(2.8)

(

0.2) VIA

TYP

LAND PATTERN EXAMPLE

SCALE:20X

0.07 MIN

ALL AROUND

0.07 MAX

ALL AROUND

SOLDER MASK

OPENING

METAL

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

NON SOLDER MASK

DEFINED

SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

4218876/A 12/2017

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

number SLUA271 (www.ti.com/lit/slua271).

5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown

on this view. It is recommended that vias under paste be filled, plugged or tented.

www.ti.com

EXAMPLE STENCIL DESIGN

DRB0008B

VSON - 1 mm max height

PLASTIC SMALL OUTLINE - NO LEAD

SYMM

METAL

TYP

8X (0.6)

8X (0.3)

(0.63)

SYMM

(1.06)

6X (0.65)

(R0.05) TYP

(1.47)

(2.8)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

EXPOSED PAD

81% PRINTED SOLDER COVERAGE BY AREA

SCALE:25X

4218876/A 12/2017

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

www.ti.com

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邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

TPS7A19 [TI]

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