TPS7A20285PDQNR_技术文档

TPS7A20

SBVS338E – MARCH 2020 – REVISED DECEMBER 2021

TPS7A20 300-mA, Ultra-Low-Noise, Low-I_Q, High PSRR LDO

1 Features

3 Description

•

Low output voltage noise: 7 µV_RMS

– No noise-bypass capacitor required

High PSRR: 95 dB at 1 kHz

Very low I_Q: 6.5 µA

Input voltage range: 1.6 V to 6.0 V

Output voltage range: 0.8 V to 5.5 V

Output voltage tolerance: ±1.5% (max)

Very low dropout:

– 140 mV (max) at 300 mA (V_OUT= 3.3 V)

– 145 mV (max) at 300 mA (V_OUT= 3.3 V, DBV)

Low inrush current

Smart enable pulldown

Stable with 1-µF minimum ceramic output

capacitor

The TPS7A20 is an ultra-small, low-dropout (LDO)

linear regulator that can source 300 mA of output

current. The TPS7A20 is designed to provide low

noise, high PSRR, and excellent load and line

transient performance that can meet the requirements

of RF and other sensitive analog circuits. Using

innovative design techniques, the TPS7A20 offers an

ultra-low noise performance without the addition of a

noise bypass capacitor. The TPS7A20 also provides

the advantage of low quiescent current, which can be

ideal for battery-powered applications. With an input

voltage range of 1.6 V to 6.0 V and an output range of

0.8 V to 5.5 V, the TPS7A20 can be used for a wide

variety of applications. The device uses a precision

reference circuit to provide a maximum accuracy of

1.5% over load, line, and temperature variations.

•

Packages:

– 1-mm × 1-mm X2SON

– 0.603-mm × 0.603-mm DSBGA

– 2.90-mm × 1.60-mm SOT23-5

The TPS7A20 features an internal soft-start to lower

the inrush current, thus minimizing the input voltage

drop during start up. The device is stable with

small ceramic capacitors, allowing for a small overall

solution size.

2 Applications

•

Smartphones and tablets

IP network cameras

Portable medical equipment

Smart meters and field transmitters

Motor drives

The TPS7A20 has a smart enable input circuit with an

internally controlled pulldown resistor that keeps the

LDO disabled even when the EN pin is left floating

and helps eliminate the external components used to

pulldown the EN pin.

Wearables

Device Information⁽¹⁾

PART NUMBER

PACKAGE

BODY SIZE (NOM)

1.00 mm × 1.00 mm

0.603 mm × 0.603 mm

2.90 mm × 1.60 mm

X2SON (4)

TPS7A20

DSBGA (4)

SOT-23 (5)

(1) For all available packages, see the orderable addendum at

the end of the data sheet.

Simplified Schematic

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

TPS7A20

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SBVS338E – MARCH 2020 – REVISED DECEMBER 2021

Table of Contents

1 Features............................................................................1

2 Applications.....................................................................1

3 Description.......................................................................1

4 Revision History.............................................................. 2

5 Pin Configuration and Functions...................................3

6 Specifications.................................................................. 5

6.1 Absolute Maximum Ratings........................................ 5

6.2 ESD Ratings............................................................... 5

6.3 Recommended Operating Conditions.........................5

6.4 Thermal Information....................................................6

6.5 Electrical Characteristics.............................................6

6.6 Switching Characteristics............................................7

6.7 Typical Characteristics................................................8

7 Detailed Description......................................................23

7.1 Overview...................................................................23

7.2 Functional Block Diagram.........................................23

7.3 Feature Description...................................................24

7.4 Device Functional Modes..........................................26

8 Application and Implementation..................................27

8.1 Application Information............................................. 27

8.2 Typical Application.................................................... 31

9 Power Supply Recommendations................................32

10 Layout...........................................................................33

10.1 Layout Guidelines................................................... 33

10.2 Layout Examples.................................................... 33

11 Device and Documentation Support..........................34

11.1 Device Support........................................................34

11.2 Receiving Notification of Documentation Updates..34

11.3 Support Resources................................................. 34

11.4 Trademarks............................................................. 34

11.5 Electrostatic Discharge Caution..............................34

11.6 Glossary..................................................................34

12 Mechanical, Packaging, and Orderable

Information.................................................................... 34

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision D (July 2021) to Revision E (December 2021)

Page

•

Changed YCJ and YCK packages from Preview to Production Data ................................................................1

Changed maximum current limit for YCJ and YCK packages............................................................................ 6

Changed minimum UVLO thresholds for YCJ and YCK packages.................................................................... 6

Changes from Revision C (November 2020) to Revision D (July 2021)

Page

•

Added YCJ package to document...................................................................................................................... 1

Changed maximum operating junction temperature T_Jto 150°C....................................................................... 5

Added thermal information for DSBGA packages.............................................................................................. 6

2

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5 Pin Configuration and Functions

1

2

1

2

A

IN

OUT

B

EN

GND

B

EN

GND

A

IN

OUT

Not to scale

Figure 5-1. YCJ and YCK Packages,

4-Pin DSBGA (Top View)

Figure 5-2. YCJ and YCK Packages,

4-Pin DSBGA (Bottom View)

Pin Functions: DSBGA

I/O

DESCRIPTION

NO.

NAME

Input voltage supply. For best transient response and to minimize input impedance, use

the nominal value or larger capacitor from IN to ground as listed in the Recommended

Operating Conditions table. Place the input capacitor as close to the IN and GND pins of the

device as possible.

A1

A2

IN

I

Regulated output voltage. A low equivalent series resistance (ESR) capacitor is required

from OUT to ground for stability. For best transient response, use the nominal

recommended value or larger capacitor listed in the Recommended Operating Conditions

table. Place the output capacitor as close to the OUT and GND pins of the device as

possible. An internal 150-Ω (typical) pulldown resistor prevents a charge from remaining on

OUT

O

V

_OUTwhen the regulator is in shutdown mode (V_EN< V_EN(LOW)).

Enable input. A low voltage (< V_EN(LOW)) on this input turns the regulator off and discharges

the output pin to GND. A high voltage (> V_EN(HI)) on this pin enables the regulator output.

This pin has an internal 500-kΩ pulldown resistor to hold the regulator off by default. When

V_EN> V_EN(HI), the 500-kΩ pulldown is disconnected to reduce input current.

B1

B2

EN

I

GND

—

Common ground.

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OUT

1

4

IN

GND

EN

1

2

3

5

OUT

5

Thermal Pad

4

N/C

GND

2

3

EN

Not to scale

Figure 5-3. DQN Package, 4-Pin X2SON (Top View)

Figure 5-4. DBV Package, 5-Pin SOT-23 (Top View)

Pin Functions: X2SON, SOT-23

I/O

DESCRIPTION

NAME

X2SON

SOT-23

Input voltage supply. For best transient response and to minimize input

impedance, use the nominal value or larger capacitor from IN to ground as listed

in the Recommended Operating Conditions table. Place the input capacitor as

close to the IN and GND pins of the device as possible.

IN

4

1

I

Regulated output voltage. A low equivalent series resistance (ESR) capacitor

is required from OUT to ground for stability. For best transient response, use

the nominal recommended value or larger capacitor listed in the Recommended

Operating Conditions table. Place the output capacitor as close to the OUT and

GND pins of the device as possible. An internal 150-Ω (typical) pulldown resistor

prevents a charge from remaining on V_OUTwhen the regulator is in shutdown

mode (V_EN< V_EN(LOW)).

OUT

5

O

Enable input. A low voltage (< V_EN(LOW)) on this pin turns the regulator off

and discharges the output pin to GND. A high voltage (> V_EN(HI)) on this pin

enables the regulator output. This pin has an internal 500-kΩ pulldown resistor

to hold the regulator off by default. When V_EN> V_EN(HI), the 500-kΩ pulldown is

disconnected to reduce input current.

EN

3

I

GND

N/C

2

4

—

Common ground.

—

No internal electrical connection.

Thermal pad for the X2SON package. Connect this pad to GND or leave floating.

Do not connect to any potential other than GND. Connect the thermal pad to a

large-area ground plane for best thermal performance.

Thermal Pad

5

—

4

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6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)^{(1) (3)}

MIN

–0.3

MAX

UNIT

V_IN

6.5

6.5 or V_IN+ 0.3 ⁽²⁾

6.5

Voltage

V_OUT

V

V_EN

Current

Maximum output⁽⁴⁾

Operating junction, T_J

Storage, T_stg

Internally limited

A

–40

–65

150

°C

Temperature

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating

Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) The maximum value of V_OUTis the lesser of 6.5 V or (V_IN+ 0.3 V).

(3) All voltages are with respect to the GND pin.

(4) Internal thermal shutdown circuitry protects the device from permanent damage.

6.2 ESD Ratings

VALUE

±2000

±750

UNIT

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾

V_(ESD)

Electrostatic discharge

V

Charged-device model (CDM), per JEDEC specification JESD22-C101⁽²⁾

(1) JEDEC document JEP155 states that 500-V HBM allows safemanufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safemanufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

MIN

1.6

0

NOM

MAX

6.0

UNIT

V

V_IN

Input supply voltage

V_EN

V_OUT

I_OUT

C_IN

Enable input voltage

6.0

V

Nominal output voltage range

Output current

0.8

0

5.5

V

300

mA

µF

mΩ

°C

Input capacitor⁽²⁾

1

C_OUT

ESR

T_J

Output capacitor⁽³⁾

1

200

100

125

Output capacitor effective series resistance

Operating junction temperature

–40

(1) All voltages are with respect to GND.

(2) An input capacitor is not required for LDO stability. However, an input capacitor with an effective value of 0.47 μF minimum is

recommended to counteract the effect of source resistance and inductance, which may in some cases cause symptoms of system-

level instability such as ringing or oscillation, especially in the presence of load transients.

(3) Effective output capacitance of 0.47 μF minimum and 200 μF maximum is required for stability.

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6.4 Thermal Information

TPS7A20

DQN YCJ

DBV

YCK

THERMAL METRIC⁽¹⁾

UNIT

(SOT-23) (X2SON) (DSBGA) (DSBGA)

5 PINS

187.1

85.5

4 PINS

166.1

103.6

110.6

3.0

4 PINS

199.6

2.8

4 PINS

201.4

2.8

R_θJA

Junction-to-ambient thermal resistance

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

°C/W

R_θJC(top)

R_θJB

54.4

67.5

1.4

69.3

1.4

ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

27.1

ψ_JB

54.1

103.3

98.8

67.4

N/A

69.2

N/A

R_θJC(bot)

N/A

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

6.5 Electrical Characteristics

at operating temperature range (T_J= –40℃ to +125℃), V_IN= V_OUT(NOM)+ 0.3 V or 1.6V, whichever is greater, V_EN= 1.0 V,

I_OUT= 1 mA, C_IN= 1 µF, C_OUT= 1 µF (unless otherwise noted); all typical values are at T_J= 25℃

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

V_IN= (V_OUT(NOM)+ 0.3 V) to 6.0 V,

I_OUT= 1 mA to 300 mA,

–1.5

1.5

V_OUT≥ 1.85 V (DQN, YCJ, YCK packages)

%

V_IN= (V_OUT(NOM)+ 0.3 V) to 6.0 V,

I_OUT= 1 mA to 300 mA,

V_OUT≥ 2.8 V (DBV package)

-1.5

–30

-40

1.5

30

40

ΔV_OUT

Output voltage tolerance

V_IN= (V_OUT(NOM)+ 0.5 V) to 6.0 V,

I_OUT= 1 mA to 300 mA

V_OUT< 1.85 V (DQN, YCJ, YCK packages)

mV

V_IN= (V_OUT(NOM)+ 0.3 V) to 6.0 V,

I_OUT= 1 mA to 300 mA,

V_OUT< 2.8 V (DBV package)

V_IN= (V_OUT(NOM)+ 0.3 V) to 6.0 V,

I_OUT= 1 mA

ΔV_OUT

Line regulation

Load regulation

0.03

%/V

mV

I_OUT= 1 mA to 300 mA (DQN, YCJ, YCK packages)

I_OUT= 1 mA to 300 mA (DBV package)

T_J= 25°C

V_EN= V_IN= 6 V,

T_J= –40°C to 85°C

I_OUT= 0 mA

T_J= –40°C to 125°C

V_EN= V_IN= 6 V, I_OUT= 300 mA

V_EN= 0 V (disabled), V_IN= 6.0 V, T_J= 25°C

V_IN≤ V_OUT(NOM), I_OUT= 0 mA, V_EN= V_IN

0.8 V ≤ V_OUT< 1.0 V⁽¹⁾

13

19

6.5

8.5

10

15

I_GND

Quiescent ground current

µA

2000

0.07

6.5

I_SHDN

Shutdown ground current

I_GNDin dropout

0.2

15

µA

I_GND(DO)

690

490

355

200

1.0 V ≤ V_OUT< 1.2 V⁽¹⁾

1.2 V ≤ V_OUT< 1.5 V⁽¹⁾

I_OUT= 300 mA,

V_OUT= 95% x V_OUT(NOM)

1.5 V ≤ V_OUT< 2.5 V

,

V_DO

Dropout voltage

mV

(DQN, YCJ, YCK packages

unless otherwise noted)

1.5 V ≤ V_OUT< 2.5 V

(DBV)

205

140

145

2.5 V ≤ V_OUT< 5.5 V

(DBV)

6

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6.5 Electrical Characteristics (continued)

at operating temperature range (T_J= –40℃ to +125℃), V_IN= V_OUT(NOM)+ 0.3 V or 1.6V, whichever is greater, V_EN= 1.0 V,

I_OUT= 1 mA, C_IN= 1 µF, C_OUT= 1 µF (unless otherwise noted); all typical values are at T_J= 25℃

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

V_OUT= 0.9 x V_OUT(NOM)V_OUT< 1.5 V (YCJ, YCK

,

360

520

770

V_IN= V_OUT(NOM)+ 0.5 V

packages)

V_OUT= 0.9 x V_OUT(NOM)

V_IN= V_OUT(NOM)+ 0.5 V

,

V_OUT< 1.5 V (DQN

package)

360

520

730

770

730

V_OUT= V_OUT(NOM)- 150 mV, V_OUT< 1.5 V (DBV

V_IN= V_OUT(NOM)+ 0.5 V

I_CL

Output current limit

mA

package)

V_OUT= 0.9 x V_OUT(NOM)

,

V_OUT≥ 1.5 V (YCJ, YCK

packages)

V_IN= V_OUT(NOM)+ 0.3 V

V_OUT= 0.9 x V_OUT(NOM)

,

V_OUT≥ 1.5 V (DQN

package)

V_IN= V_OUT(NOM)+ 0.3 V

I_SC

Short-circuit current limit

V_OUT= 0 V

160

95

75

45

65

92

75

60

40

7

mA

f = 100 Hz

f = 1 kHz

I_OUT= 20 mA,

V_IN= V_OUT+ 1.0 V

f = 10 kHz

f = 100 kHz

f = 1 MHz

f = 100 Hz

f = 1 kHz

PSRR

Power-supply rejection ratio

dB

I_OUT= 300 mA,

V_IN= V_OUT+ 1.0 V

f = 10 kHz

f = 100 kHz

f = 1 MHz

I_OUT= 300 mA

I_OUT= 1 mA

BW = 10 Hz to 100 kHz,

V_OUT= 2.8 V

V_N

Output noise voltage

µV_RMS

10

Output automatic discharge

pulldown resistance

R_PULLDOWN

V_EN< V_EN(LOW)(output disabled), V_IN= 3.1 V

150

Ω

T_Jrising

T_Jfalling

165

140

T_SD

Thermal shutdown

°C

V_IN= 1.6 V to 6.0 V,

V_ENfalling until the output is disabled

V_EN(LOW)

V_EN(HI)

Low input threshold

High input threshold

0.3

V

V_IN= 1.6 V to 6.0 V

V_ENrising until the output is enabled

0.9

V_INrising (YCJ and YCK packages)

V_INrising (DBV and DQN packages)

V_INrising (YCJ and YCK packages)

V_INfalling (DBV and DQN packages)

1.11

1.17

1.05

1.11

1.35

1.3

50

1.59

1.55

V_UVLO

UVLO threshold

V

V_UVLO(HYST)

I_EN

UVLO hysteresis

mV

nA

EN input leakage current

V_EN= 6.0 V and V_IN= 6.0 V

V_EN= 0.25 V

90

250

R_EN(PULL-

Smart enable pulldown resistor

500

KΩ

DOWN)

(1) Design simulation data only

6.6 Switching Characteristics

at operating temperature range (T_J= –40℃ to +125℃), V_IN= V_OUT(NOM)+ 0.3 V or 1.6V, whichever is greater, V_EN= 1.0 V,

I_OUT= 1 mA, C_IN= 1 µF, C_OUT= 1 µF (unless otherwise noted); all typical values are at T_J= 25℃

PARAMETER

Start-up time

TEST CONDITIONS

MIN

TYP

MAX

UNIT

From V_EN> V_EN(HI)to V_OUT= 95% of V_OUT(NOM)

,

t_STR

750

1150

µs

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6.7 Typical Characteristics

V_IN= V_OUT(NOM)+ 0.3 V or 1.6 V (whichever is greater), V_OUT= 2.8 V, I_OUT= 1 mA, C_IN= 1 µF, C_OUT= 1 µF, and T_A= 25°C

(unless otherwise noted)

3

2

9

6

T_J

-55°C

-40°C

0°C

25°C

85°C

125°C

150°C

-55°C

-40°C

0°C

25°C

85°C

125°C

150°C

1

3

0

-1

-2

-3

-4

-5

-6

-3

-6

-9

-12

-15

5.6

5.65

5.7

5.75

5.8

Input Voltage (V)

5.85

5.9

5.95

6

3.1 3.4 3.7

4

4.3 4.6 4.9 5.2 5.5 5.8

Input Voltage (V)

6

V_OUT= 5.5 V, V_EN= 1 V, DQN, YCJ, and YCK packages

V_EN= 1 V, DQN, YCJ, and YCK packages

Figure 6-2. Line Regulation vs V_IN

Figure 6-1. Line Regulation vs V_IN

V_OUT= 5.5 V, V_EN= 1 V, DBV package

V_EN= 1 V, DBV package

Figure 6-4. Line Regulation vs V_IN

Figure 6-3. Line Regulation vs V_IN

15

10

5

16

12

8

T_J

-55°C

-40°C

0°C

25°C

85°C

125°C

150°C

-55°C

-40°C

0°C

25°C

85°C

125°C

150°C

0

-5

4

-10

-15

-20

-25

0

-4

-8

0

25 50 75 100 125 150 175 200 225 250 275 300

Output Current (mA)

0

0.2 0.4 0.6 0.8

1

Output Current (mA)

1.2 1.4 1.6 1.8

2

V_IN= 3.1 V, V_EN= 1 V, DQN, YCJ, and YCK packages

Figure 6-5. Load Regulation vs I_OUT

Figure 6-6. Load Regulation vs I_OUT

8

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6.7 Typical Characteristics (continued)

V_IN= V_OUT(NOM)+ 0.3 V or 1.6 V (whichever is greater), V_OUT= 2.8 V, I_OUT= 1 mA, C_IN= 1 µF, C_OUT= 1 µF, and T_A= 25°C

(unless otherwise noted)

V_IN= 2.8 V, V_EN= 1 V, DBV package

Figure 6-8. Load Regulation vs I_OUT

Figure 6-7. Load Regulation vs I_OUT

15

10

5

15

10

5

T_J

-55°C

-40°C

0°C

25°C

85°C

125°C

150°C

-55°C

-40°C

0°C

25°C

85°C

125°C

150°C

0

-5

0

-10

-15

-20

-25

-30

-35

-5

-10

-15

-20

0

30

60

90 120 150 180 210 240 270 300

Output Current (mA)

0

0.2 0.4 0.6 0.8

1

Output Current (mA)

1.2 1.4 1.6 1.8

2

V_OUT= 5.5 V, V_EN= 1 V, DQN, YCJ, and YCK packages

Figure 6-9. Load Regulation vs I_OUT

Figure 6-10. Load Regulation vs I_OUT

V_OUT= 5.5 V, V_EN= 1 V, DBV package

Figure 6-11. Load Regulation vs I_OUT

Figure 6-12. Load Regulation vs I_OUT

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6.7 Typical Characteristics (continued)

V_IN= V_OUT(NOM)+ 0.3 V or 1.6 V (whichever is greater), V_OUT= 2.8 V, I_OUT= 1 mA, C_IN= 1 µF, C_OUT= 1 µF, and T_A= 25°C

(unless otherwise noted)

0.6

0.4

0.2

0

0.6

0.5

0.4

0.3

0.2

0.1

0

T_J

-55°C

-40°C

0°C

25°C

85°C

125°C

150°C

-55°C

-40°C

0°C

25°C

85°C

125°C

150°C

-0.2

-0.4

-0.6

-0.8

-1

-0.1

-0.2

-0.3

0

0.2 0.4 0.6 0.8

1 1.2 1.4 1.6 1.8

Output Current (mA)

2

0

25 50 75 100 125 150 175 200 225 250 275 300

Output Current (mA)

D076

V_EN= 1 V, DQN, YCJ, and YCK packages

Figure 6-14. Output Voltage Accuracy vs I_OUT

Figure 6-13. Output Voltage Accuracy vs I_OUT

V_EN= 1 V, DBV package

Figure 6-15. Output Voltage Accuracy vs I_OUT

Figure 6-16. Output Voltage Accuracy vs I_OUT

0.2

0.1

0.3

0.2

0.1

0

T_J

-55°C

-40°C

0°C

25°C

85°C

125°C

150°C

-55°C

-40°C

0°C

25°C

85°C

125°C

150°C

0

-0.1

-0.2

-0.3

-0.4

-0.5

-0.6

-0.1

-0.2

-0.3

0

30

60

90 120 150 180 210 240 270 300

Output Current (mA)

0

0.2 0.4 0.6 0.8

1 1.2 1.4 1.6 1.8

Output Current (mA)

2

V_OUT= 5.5 V, V_EN= 1 V, DQN, YCJ, and YCK packages

Figure 6-17. Output Voltage Accuracy vs I_OUT

Figure 6-18. Output Voltage Accuracy vs I_OUT

10

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6.7 Typical Characteristics (continued)

V_IN= V_OUT(NOM)+ 0.3 V or 1.6 V (whichever is greater), V_OUT= 2.8 V, I_OUT= 1 mA, C_IN= 1 µF, C_OUT= 1 µF, and T_A= 25°C

(unless otherwise noted)

V_OUT= 5.5 V, V_EN= 1 V, DBV package

Figure 6-19. Output Voltage Accuracy vs I_OUT

Figure 6-20. Output Voltage Accuracy vs I_OUT

0.15

T_J

0.1

0.05

0

-55°C

-40°C

0°C

25°C

85°C

125°C

150°C

-55°C

-40°C

0°C

25°C

85°C

125°C

150°C

0.1

0.05

0

-0.05

-0.1

-0.15

-0.2

-0.25

-0.3

-0.05

-0.1

-0.15

-0.2

-0.25

3.1

3.6

4.1 4.6

Input Voltage (V)

5.1

5.6

6

5.6

5.65

5.7

5.75

5.8

Input Voltage (V)

5.85

5.9

5.95

6

V_EN= 1 V, I_OUT= 1 mA, DQN, YCJ, and YCK packages

V_OUT= 5.5 V, V_EN= 1 V, DQN, YCJ, and YCK packages

Figure 6-21. Output Voltage Accuracy vs V_IN

Figure 6-22. Output Voltage Accuracy vs V_IN

V_EN= 1 V, I_OUT= 1 mA, DBV package

V_OUT= 5.5 V, V_EN= 1 V, DBV package

Figure 6-23. Output Voltage Accuracy vs V_IN

Figure 6-24. Output Voltage Accuracy vs V_IN

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6.7 Typical Characteristics (continued)

V_IN= V_OUT(NOM)+ 0.3 V or 1.6 V (whichever is greater), V_OUT= 2.8 V, I_OUT= 1 mA, C_IN= 1 µF, C_OUT= 1 µF, and T_A= 25°C

(unless otherwise noted)

130

120

110

100

90

85

80

75

70

65

60

55

T_J

-55°C

-40°C

0°C

25°C

85°C

125°C

150°C

-55°C

-40°C

0°C

25°C

85°C

125°C

150°C

80

70

60

50

0

30

60

90 120 150 180 210 240 270 300

Output Current (mA)

0

1

2

3

4

5

6

Output Current (mA)

7

8

9

10

V_EN= 1 V, DQN, YCJ, and YCK packages

Figure 6-25. Dropout Voltage vs I_OUT

Figure 6-26. Dropout Voltage vs I_OUT

V_EN= 1 V, DBV package

Figure 6-27. Dropout Voltage vs I_OUT

Figure 6-28. Dropout Voltage vs I_OUT

160

150

140

130

120

110

100

90

95

90

85

80

75

70

65

60

55

T_J

-55°C

-40°C

0°C

25°C

85°C

125°C

150°C

-55°C

-40°C

0°C

25°C

85°C

125°C

150°C

80

70

60

0

30

60

90 120 150 180 210 240 270 300

Output Current (mA)

0

1

2

3

4

5

6

Output Current (mA)

7

8

9

10

D099

D100

V_OUT= 1.8 V, V_EN= 1 V, DQN, YCJ, and YCK packages

Figure 6-29. Dropout Voltage vs I_OUT

Figure 6-30. Dropout Voltage vs I_OUT

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6.7 Typical Characteristics (continued)

V_IN= V_OUT(NOM)+ 0.3 V or 1.6 V (whichever is greater), V_OUT= 2.8 V, I_OUT= 1 mA, C_IN= 1 µF, C_OUT= 1 µF, and T_A= 25°C

(unless otherwise noted)

V_OUT= 1.8 V, V_EN= 1 V, DBV package

Figure 6-31. Dropout Voltage vs I_OUT

Figure 6-32. Dropout Voltage vs I_OUT

180

170

160

150

140

130

120

110

100

90

14

13

12

11

10

9

T_J

0°C

25°C

T_J

-40°C

-20°C

50°C

85°C

125°C

-55°C

-40°C

0°C

25°C

85°C

125°C

150°C

8

7

6

5

4

1.6

1.5

2

2.5

3

3.5

4

Output Voltage ( V)

4.5

5

5.5

2.1

2.6

3.1

3.6

4.1

Input Voltage (V)

4.6

5.1

5.6

6

I_OUT= 300 mA

V_EN= 1 V, I_OUT= 0 mA

Figure 6-33. Dropout Voltage vs V_OUT

Figure 6-34. I _GNDvs V_IN

13

12

11

10

9

12

11

10

9

T_J

-55°C

-40°C

0°C

25°C

85°C

125°C

150°C

-55°C

-40°C

0°C

25°C

85°C

125°C

150°C

8

7

6

5

4

1.6

2.1

2.6

3.1

3.6

Input Voltage (V)

4.1

4.6

5.1 5.5

1.6

2.1

2.6

3.1

3.6

4.1

4.6

5.1

5.6

6

Input Voltage (V)

V_EN= V_IN, I_OUT= 0 mA

Figure 6-35. I_GNDvs V_IN

V_OUT(NOM)= 5.5 V, V_EN= 1 V, I_OUT= 0 mA

Figure 6-36. I_GNDvs V_INin the Dropout Region

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6.7 Typical Characteristics (continued)

V_IN= V_OUT(NOM)+ 0.3 V or 1.6 V (whichever is greater), V_OUT= 2.8 V, I_OUT= 1 mA, C_IN= 1 µF, C_OUT= 1 µF, and T_A= 25°C

(unless otherwise noted)

3250

3000

2750

2500

2250

2000

1750

1500

1250

1000

750

12

11

10

9

T_J

-55°C

-40°C

0°C

25°C

85°C

125°C

150°C

-55°C

-40°C

0°C

25°C

85°C

125°C

150°C

8

7

6

500

5

250

0

4

0

30

60

90 120 150 180 210 240 270 300

Output Current (mA)

1.6

2.1

2.6

3.1

3.6

Input Voltage (V)

4.1

4.6

5.1 5.5

V_EN= 1 V

V_OUT(NOM)= 5.5 V, V_EN= V_IN, I_OUT= 0 mA

Figure 6-37. I_GNDvs V_INin the Dropout Region

Figure 6-38. I_GNDvs I_OUT

4000

500

450

400

350

300

250

200

150

100

50

T_J

-55°C

-40°C

0°C

25°C

T_J

85°C

125°C

150°C

-55°C

-40°C

0°C

25°C

85°C

125°C

150°C

1000

100

10

2

0

0.001

0.01

0.1

Output Current (mA)

1

10

100 300

0

0.5

1

1.5

2

2.5

Output Current (mA)

3

3.5

4

4.5

5

D072

D073

V_EN= 1 V

Figure 6-39. I_GNDvs I_OUT

Figure 6-40. I_GNDvs I_OUT

4000

3500

3000

2500

2000

1500

1000

500

45

T_J

125°C

T_J

-40°C

40

35

30

25

20

15

10

5

85°C

150°C

-55°C

0°C

25°C

0

1.6

-5

1.6

2.1

2.6

3.1

3.6

4.1

Input Voltage (V)

4.6

5.1

5.6

6

2.1

2.6

3.1

3.6

4.1

Input Voltage (V)

4.6

5.1

5.6

6

V_EN= 0 V

Figure 6-42. Shutdown Current vs V_IN

Figure 6-41. Shutdown Current vs V_IN

14

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6.7 Typical Characteristics (continued)

V_IN= V_OUT(NOM)+ 0.3 V or 1.6 V (whichever is greater), V_OUT= 2.8 V, I_OUT= 1 mA, C_IN= 1 µF, C_OUT= 1 µF, and T_A= 25°C

(unless otherwise noted)

4500

4000

3500

3000

2500

2000

1500

1000

500

4.5

4

T_J

0°C

25°C

-55°C

-40°C

85°C

125°C

3.5

3

2.5

2

1.5

1

T_J

-55°C

-40°C

0°C

25°C

85°C

125°C

150°C

5.5

0.5

0

0.5

1

1.5

2

2.5

3

3.5

V_EN- V_IN(V)

4

4.5

5

6

0

50 100 150 200 250 300 350 400 450 500 550 600

Output Current (mA)

V_EN= 6 V, I_OUT= 0 mA

V_EN= 1 V

Figure 6-43. Enable Pin Leakage Current vs

V_EN- V_IN

Figure 6-44. Current Limit

1.2

1

1.4

1.39

1.38

1.37

1.36

1.35

1.34

1.33

1.32

1.31

1.3

T_J

V

UVLO+ (V_INrising)

V_{UVLO- (V}

-55°C

-40°C

0°C

25°C

85°C

125°C

150°C

_INfalling)

0.8

0.6

0.4

0.2

0

50 100 150 200 250 300 350 400 450 500 550 600

Output Current (mA)

-60 -40 -20

0

20 40 60 80 100 120 140 160

Temperature (°C)

D088

V_OUT= 0.8 V, V_EN= 1 V

V_EN= 1 V

Figure 6-45. Current Limit

Figure 6-46. UVLO Threshold vs Temperature

1

0.95

0.9

0.85

0.8

V_IN

1.6 V ( Vout = 0.8 V )

2.1 V ( Vout = 1.8 V )

3.1 V ( Vout = 2.8 V )

5.8 V ( Vout = 5.5 V )

6.0 V ( Vout = 0.8 V - 5.5 V )

1.6 V ( Vout = 0.8 V )

2.1 V ( Vout = 1.8 V )

3.1 V ( Vout = 2.8 V )

5.8 V ( Vout = 5.5 V )

6.0 V ( Vout = 0.8 V - 5.5 V )

0.85

0.8

0.75

0.7

0.75

0.7

0.65

0.6

0.65

0.6

0.55

0.5

0.55

0.5

0.45

0.4

0.45

0.4

0.35

-60 -40 -20

0

20 40 60 80 100 120 140 160

Temperature (°C)

-60 -40 -20

0

20 40 60 80 100 120 140 160

Temperature (°C)

Figure 6-47. Enable Logic High Threshold vs Temperature

Figure 6-48. Enable Logic Low Threshold Low vs Temperature

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6.7 Typical Characteristics (continued)

V_IN= V_OUT(NOM)+ 0.3 V or 1.6 V (whichever is greater), V_OUT= 2.8 V, I_OUT= 1 mA, C_IN= 1 µF, C_OUT= 1 µF, and T_A= 25°C

(unless otherwise noted)

400

350

300

250

200

150

100

540

520

500

480

460

440

420

V_IN

1.6 V

1.6 V ( V_OUT= 0.8 V )

2.1 V ( V_OUT= 1.8 V )

3.1 V ( V_OUT= 2.8 V )

6 V ( V_OUT= 5.5 V )

2.4 V

3.4 V

4.4 V

5.4 V

6.0 V

-60

-30

0

30 60

Temperature (°C)

90

120

150

-60

-35

-10

15

40

65

Temperature (°C)

90

115 140 160

V_EN= 0.25 V

Figure 6-50. Smart Enable Pulldown Resistor vs Temperature

and V_IN

Figure 6-49. Output Pulldown Resistor vs Temperature

1

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0

20

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0

40

I_OUT

V_OUT

10

30

0

20

-10

-20

-30

-40

-50

-60

-70

-80

10

0

-10

-20

-30

-40

-50

-60

I_OUT

V_OUT

-0.1

0

2

4

6

8

10

Time (ms)

12

14

16

18

20

0

4

8

12

16

20

Time (µs)

24

28

32

36

40

D030

D033

I_OUT= 1 mA to 300 mA, t_RISING= 1 µs

I_OUT= 300 mA to 1 mA, t_FALLING= 1 µs

Figure 6-51. Load Transient

Figure 6-52. Load Transient

1

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0

20

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0

40

I_OUT

V_OUT

0

30

-20

-40

-60

-80

-100

-120

-140

-160

-180

20

10

0

-10

-20

-30

-40

-50

-60

I_OUT

V_OUT

-0.1

0

2

4

6

8

10

Time (ms)

12

14

16

18

20

0

10

20

30

40

50

Time (µs)

60

70

80

90 100

D031

D032

I_OUT= 1 mA to 300 mA, t_RISING= 200 ns

I_OUT= 300 mA to 1 mA, t_FALLING= 200 ns

Figure 6-53. Load Transient

Figure 6-54. Load Transient

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6.7 Typical Characteristics (continued)

V_IN= V_OUT(NOM)+ 0.3 V or 1.6 V (whichever is greater), V_OUT= 2.8 V, I_OUT= 1 mA, C_IN= 1 µF, C_OUT= 1 µF, and T_A= 25°C

(unless otherwise noted)

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0

40

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0

30

I_OUT

V_OUT

0

20

-40

10

-80

0

-120

-160

-200

-240

-280

-320

-360

-10

-20

-30

-40

-50

-60

-70

I_OUT

V_OUT

-0.1

0

2

4

6

8

10

Time (µs)

12

14

16

18

20

0

50 100 150 200 250 300 350 400 450 500

Time (µs)

D035

D037

I_OUT= 0 mA to 300 mA, t_RISING= 1 µs

I_OUT= 300 mA to 0 mA, t_FALLING= 1 µs

Figure 6-55. Load Transient

Figure 6-56. Load Transient

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0

40

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0

30

I_OUT

V_OUT

0

20

-40

10

-80

0

-120

-160

-200

-240

-280

-320

-360

-10

-20

-30

-40

-50

-60

-70

I_OUT

V_OUT

-0.1

2

4

6

8

10

Time (µs)

12

14

16

18

20

0

50 100 150 200 250 300 350 400 450 500

Time (µs)

D034

D036

I_OUT= 0 mA to 300 mA, t_RISING= 200 ns

I_OUT= 300 mA to 0 mA, t_FALLING= 200 ns

Figure 6-57. Load Transient

Figure 6-58. Load Transient

6

5

7

6

5

6

V_OUT

V_IN

V_OUT

V_IN

6

5

4

5

4

3

4

3

2

3

2

1

2

1

0

1

0

-1

-2

-3

-4

0

-1

-2

-3

-4

-1

-2

-3

-4

-1

-2

-3

10

20

30

40

50

Time (µs)

60

70

80

90 100

0

10

20

30

40

50

Time (ms)

60

70

80

90 100

D060

D061

V_IN= 3.1 V → 4.1 V → 3.1 V, V_INt_RISING= 5 µs, I_OUT= 1 mA

V_IN= 3.1 V → 4.1 V → 3.1 V, V_INt_RISING= 5 µs,

I_OUT= 300 mA

Figure 6-60. Line Transient

Figure 6-59. Line Transient

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6.7 Typical Characteristics (continued)

V_IN= V_OUT(NOM)+ 0.3 V or 1.6 V (whichever is greater), V_OUT= 2.8 V, I_OUT= 1 mA, C_IN= 1 µF, C_OUT= 1 µF, and T_A= 25°C

(unless otherwise noted)

120

110

100

90

80

70

60

50

40

30

20

10

0

120

110

100

90

80

70

60

50

40

30

20

10

0

V_IN

3.10 V

3.30 V

3.80 V

V_IN

3.1 V

3.3 V

3.8 V

10

100

1k

10k

Frequency (Hz)

100k

1M

10M

10

100

1k

10k

Frequency (Hz)

100k

1M

10M

D011

D00115

I_OUT= 20 mA

I_OUT= 300 mA

Figure 6-61. PSRR vs V_INvs Frequency and V_IN

Figure 6-62. PSRR vs Frequency and V_IN

120

110

100

90

120

110

100

90

80

70

60

50

40

30

20

10

0

C_OUT

1 mF

10 mF

200 mF

80

70

60

50

40

30

I_OUT

100 mA

200 mA

20

10

0

0.01 mA

20 mA

300 mA

100k

10

100

1k

10k

1M

10M

10

100

1k

10k

Frequency (Hz)

100k

1M

10M

Frequency (Hz)

D012

D00113

I_OUT= 20 mA

Figure 6-63. PSRR vs Frequency and I_OUT

Figure 6-64. PSRR vs Frequency and C_OUT

2

1

2

I_OUT

1 mA, RMS noise = 8.63 mV_RMS

20 mA, RMS noise = 6.66 mV_RMS

100 mA, RMS noise = 6.69 mV_RMS

200 mA, RMS noise = 6.73 mV_RMS

300 mA, RMS noise = 7.76 mV_RMS

V_IN

1

3.1 V, RMS Noise = 6.66 mV_RMS

3.3 V, RMS Noise = 6.71 mV_RMS

3.8 V, RMS Noise = 6.70 mV_RMS

0.5

0.2

0.1

0.2

0.1

0.05

0.02

0.01

0.02

0.01

0.005

0.002

0.001

0.002

0.001

10

100

1k

10k 100k

Frequency (Hz)

1M

10M

10

100

1k

10k 100k

Frequency (Hz)

1M

10M

D002

D003

V_RMSBW = 10 Hz to 100 kHz

I_OUT= 20 mA, V_RMSBW = 10 Hz to 100 kHz

Figure 6-66. Noise vs Frequency and V_IN

Figure 6-65. Noise vs Frequency and I_OUT

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6.7 Typical Characteristics (continued)

V_IN= V_OUT(NOM)+ 0.3 V or 1.6 V (whichever is greater), V_OUT= 2.8 V, I_OUT= 1 mA, C_IN= 1 µF, C_OUT= 1 µF, and T_A= 25°C

(unless otherwise noted)

2

1

2

1

V_IN

C_OUT

3.1 V, RMS Noise = 6.76 mV_RMS

3.3 V, RMS Noise = 6.77 mV_RMS

3.8 V, RMS Noise = 7.10 mV_RMS

1 mF, RMS noise = 6.65 mV_RMS

10 mF, RMS noise = 6.94 mV_RMS

200 mF, RMS noise = 6.56 mV_RMS

0.5

0.2

0.1

0.2

0.1

0.05

0.02

0.01

0.02

0.01

0.005

0.002

0.001

0.002

0.001

10

100

1k

10k 100k

Frequency (Hz)

1M

10M

10

100

1k

10k 100k

Frequency (Hz)

1M

10M

D004

D006

I_OUT= 300 mA, V_RMSBW = 10 Hz to 100 kHz

Figure 6-67. Noise vs Frequency and V_IN

V_IN= 3.8 V, I_OUT= 20 mA, V_RMSBW = 10 Hz to 100 kHz

Figure 6-68. Noise vs Frequency and C_OUT

2

C_OUT

I_OUT

20 mA, RMS noise = 7.11 mV_RMS

300 mA, RMS noise = 7.04 mV_RMS

1

1 mF, RMS noise = 7.14 mV_RMS

10 mF, RMS noise = 7.14 mV_RMS

200 mF, RMS noise = 6.87 mV_RMS

0.5

0.2

0.1

0.2

0.1

0.05

0.02

0.01

0.02

0.01

0.005

0.002

0.001

0.002

0.001

10

100

1k

10k 100k

Frequency (Hz)

1M

10M

10

100

1k

10k 100k

Frequency (Hz)

1M

10M

D007

D010

V_IN= 3.8 V, I_OUT= 300 mA, V_RMSBW = 10 Hz to 100 kHz

V_OUT= 0.8 V, V_RMSBW = 10 Hz to 100 kHz

Figure 6-69. Noise vs Frequency and C_OUT

Figure 6-70. Noise vs Frequency and I_OUT

2

I_OUT

20 mA, RMS noise = 7.09 mV_RMS

300 mA, RMS noise = 7.19 mV_RMS

I_OUT

20 mA, RMS noise = 7.21 mV_RMS

300 mA, RMS noise = 7.69 mV_RMS

1

0.5

0.2

0.1

0.2

0.1

0.05

0.02

0.01

0.02

0.01

0.005

0.002

0.001

0.002

0.001

10

100

1k

10k 100k

Frequency (Hz)

1M

10M

10

100

1k

10k 100k

Frequency (Hz)

1M

10M

D009

D008

V_OUT= 0.8 V, V_IN= 1.8 V, V_RMSBW = 10 Hz to 100 kHz

V_OUT= 5.5 V, V_IN= 6 V, V_RMSBW = 10 Hz to 100 kHz

Figure 6-71. Noise vs Frequency and I_OUT

Figure 6-72. Noise vs Frequency and I_OUT

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6.7 Typical Characteristics (continued)

V_IN= V_OUT(NOM)+ 0.3 V or 1.6 V (whichever is greater), V_OUT= 2.8 V, I_OUT= 1 mA, C_IN= 1 µF, C_OUT= 1 µF, and T_A= 25°C

(unless otherwise noted)

2

1.8

1.6

1.4

1.2

1

900

850

800

750

700

650

600

550

0.8

0.6

0.4

0.2

0

V_IN

V_EN

V_OUT( I_OUT= 0 mA)

V_OUT( I_OUT= 1 mA)

V_OUT( I_OUT= 300 mA)

-0.2

-0.4

0

500 1000 1500 2000 2500 3000 3500 4000 4500 5000

Time (ms)

-60 -40 -20

0

20 40 60 80 100 120 140 160

Temperature (°C)

D048

V_OUT= 0.8 V, V_IN= 0 V to 1.8 V, V_EN= 0 V to 1.8 V, V_ENrises

500 µs behind V_IN, V_INand V_ENslew rate = 1 V/µs

From V_EN= V_EN(HI)to V_OUT= 95% of V_OUT(NOM), I_OUT= 0 mA

Figure 6-74. Start-Up

Figure 6-73. Start-Up Turn-On Time

2

1.8

1.6

1.4

1.2

1

2

1.8

1.6

1.4

1.2

1

0.8

0.6

0.8

0.6

0.4

V_IN

V_EN

0.2

V_IN/ V_EN

V_OUT( I_OUT= 0 mA)

V_OUT( I_OUT= 1 mA)

V_OUT( I_OUT= 300 mA)

V_OUT( I_OUT= 0 mA)

V_OUT( I_OUT= 1 mA)

V_OUT( I_OUT= 300 mA)

0

-0.2

-0.4

0

-0.2

-0.4

0

500 1000 1500 2000 2500 3000 3500 4000 4500 5000

Time (ms)

0

200 400 600 800 1000 1200 1400 1600 1800 2000

Time (ms)

D049

D050

V_OUT= 0.8 V, V_IN= 0 V to 1.8 V, V_EN= 0 V to 1.8 V, V_ENrises

500 µs ahead of V_IN, V_INand V_ENslew rate = 1 V/µs

V_OUT= 0.8 V, V_IN= 0 V to 1.8 V, V_EN= V_IN,

V_INslew rate = 1 V/µs

Figure 6-75. Start-Up

Figure 6-76. Start-Up

4.5

4

4.5

4

3.5

3

3.5

3

2.5

2

2.5

2

1.5

1

0.5

0

V_IN

V_EN

V_IN

V_EN

0.5

0

V_OUT( I_OUT= 0 mA)

V_OUT( I_OUT= 1 mA)

V_OUT( I_OUT= 300 mA)

V_OUT( I_OUT= 0 mA)

V_OUT( I_OUT= 1 mA)

V_OUT( I_OUT= 300 mA)

-0.5

0

500 1000 1500 2000 2500 3000 3500 4000 4500 5000

Time (ms)

0

500 1000 1500 2000 2500 3000 3500 4000 4500 5000

Time (ms)

D051

D052

V_IN= 0 V to 3.8 V, V_EN= 0 V to 3.8 V, V_ENrises 500 µs behind

V_IN, V_INand V_ENslew rate = 1 V/µs

V_IN= 0 V to 3.8 V, V_EN= 0 V to 3.8 V, V_ENrises 500 µs ahead

of V_IN, V_INand V_ENslew rate = 1 V/µs

Figure 6-77. Start-Up

Figure 6-78. Start-Up

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6.7 Typical Characteristics (continued)

V_IN= V_OUT(NOM)+ 0.3 V or 1.6 V (whichever is greater), V_OUT= 2.8 V, I_OUT= 1 mA, C_IN= 1 µF, C_OUT= 1 µF, and T_A= 25°C

(unless otherwise noted)

4.5

4

6.5

6

5.5

5

3.5

3

4.5

4

2.5

2

3.5

3

2.5

2

1.5

1

V_IN

V_EN

1.5

1

V_IN/ V_EN

0.5

0

V_OUT( I_OUT= 0 mA)

V_OUT( I_OUT= 1 mA)

V_OUT( I_OUT= 300 mA)

V_OUT( I_OUT= 0 mA)

V_OUT( I_OUT= 1 mA)

V_OUT( I_OUT= 300 mA)

0.5

0

-0.5

0

200 400 600 800 1000 1200 1400 1600 1800 2000

Time (ms)

0

500 1000 1500 2000 2500 3000 3500 4000 4500 5000

Time (us)

D053

D054

V_IN= 0 V to 3.8 V, V_EN= 0 V to 3.8 V, V_EN= V_IN, V_INand slew

rate = 1 V/µs

V_OUT= 5.5 V, V_IN= 0 V to 6.0 V, V_EN= 0 V to 6.0 V, V_ENrises

500 µs behind V_IN, V_INand V_ENslew rate = 1 V/µs

Figure 6-79. Start-Up

Figure 6-80. Start-Up

6.5

6

6.5

6

5.5

5

5.5

5

4.5

4

4.5

4

3.5

3

3.5

3

2.5

2

2.5

2

V_IN

V_EN

1.5

1

1.5

V_IN/ V_EN

V_OUT( I_OUT= 0 mA)

V_OUT( I_OUT= 1 mA)

V_OUT( I_OUT= 300 mA)

1

V_OUT( I_OUT= 0 mA)

V_OUT( I_OUT= 1 mA)

V_OUT( I_OUT= 300 mA)

0.5

0

0.5

0

-0.5

0

500 1000 1500 2000 2500 3000 3500 4000 4500 5000

Time (ms)

0

200 400 600 800 1000 1200 1400 1600 1800 2000

Time (ms)

D055

D056

V_OUT= 5.5 V, V_IN= 0 V to 6.0 V, V_EN= 0 V to 6.0 V, V_ENrises

500 µs ahead of V_IN, V_INand V_ENslew rate = 1 V/µs

V_OUT= 5.5 V, V_IN= 0 V to 6 V, V_EN= V_IN, V_INslew rate =

1 V/µs

Figure 6-81. Start-Up

Figure 6-82. Start-Up

20

18

16

14

12

10

8

2.5

2.25

2

300

5

I_IN

V_IN

V_EN

V_OUT

I_IN

V_IN

V_EN

V_OUT

270

240

210

180

150

120

90

4.5

4

1.75

1.5

1.25

1

3.5

3

2.5

2

6

0.75

0.5

0.25

0

1.5

1

4

60

2

30

0.5

0

120 240 360 480 600 720 840 960 1080 1200

Time (µs)

0

150 300 450 600 750 900 1050 1200 1350 1500

Time (µs)

D047

D043

V_OUT= 0.8 V, V_IN= 1.8 V, V_EN= 0 V to 1.8 V,

V_ENslew rate = 1 V/µs, C_OUT= 10 µF

V_IN= 3.8 V, V_EN= 0 V to 3.8 V, V_ENslew rate = 1 V/µs,

C_OUT= 10 µF

Figure 6-83. Inrush Current

Figure 6-84. Inrush Current

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6.7 Typical Characteristics (continued)

V_IN= V_OUT(NOM)+ 0.3 V or 1.6 V (whichever is greater), V_OUT= 2.8 V, I_OUT= 1 mA, C_IN= 1 µF, C_OUT= 1 µF, and T_A= 25°C

(unless otherwise noted)

800

720

640

560

480

400

320

240

160

80

8

I_IN

V_IN

V_EN

V_OUT

7.2

6.4

5.6

4.8

4

3.2

2.4

1.6

0.8

0

150 300 450 600 750 900 1050 1200 1350 1500

Time (µs)

D044

V_OUT= 5.5 V, V_IN= 6.0 V, V_EN= 0 V to 6.0 V,

V_ENslew rate = 1 V/µs, C_OUT= 10 µF

Figure 6-85. Inrush Current

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7 Detailed Description

7.1 Overview

Designed to meet the needs of sensitive RF and analog circuits, the TPS7A20 provides low noise, high

PSRR, low quiescent current, as well as low line and load transient response figures. Using innovative design

techniques, the TPS7A20 offers class-leading noise performance without the need for a separate noise filter

capacitor.

The TPS7A20 is designed to operate with a single 1-µF input capacitor and a single 1-µF ceramic output

capacitor.

7.2 Functional Block Diagram

Current

Limit

IN

OUT

Bandgap

+

Active Discharge

P-Version Only

œ

Error

Amp

+

UVLO

Internal

Controller

Thermal

Shutdown

EN

500kΩ

GND

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7.3 Feature Description

7.3.1 Low Output Noise

Any internal noise at the TPS7A20 reference voltage is reduced by a first-order, low-pass RC filter before being

passed to the output buffer stage. The low-pass RC filter has a –3-dB cut-off frequency of approximately 0.1 Hz.

During start-up, the filter resistor is bypassed to reduce output rise time; the filter begins normal operation after

the output voltage reaches the correct value.

7.3.2 Smart Enable

The enable (EN) input polarity is active high. The output voltage is enabled when the voltage of the enable input

is greater than V_EN(HI)and disabled when the enable input voltage is less than V_EN(LOW). If independent control

of the output voltage is not needed, connect EN to IN.

This device has a smart enable circuit to reduce quiescent current. When the voltage on the enable pin is

driven above V_EN(HI), as listed in the Electrical Characteristics table, the device is enabled and the smart enable

internal pulldown resistor (R_EN(PULLDOWN)) is disconnected. When the enable pin is floating, the R_EN(PULLDOWN)is

connected and pulls the enable pin low to disable the device. The R_EN(PULLDOWN)value is listed in the Electrical

Characteristics table.

7.3.3 Dropout Voltage

Dropout voltage (V_DO) is defined as the input voltage minus the output voltage (V_IN– V_OUT) at the rated output

current (I_RATED), where the pass transistor is fully on. I_RATEDis the maximum I_OUTlisted in the Recommended

Operating Conditions table. The pass transistor is in the ohmic or triode region of operation, and acts as a

switch. The dropout voltage indirectly specifies a minimum input voltage greater than the nominal programmed

output voltage at which the output voltage is expected to stay in regulation. If the input voltage falls to less than

the value required to maintain output regulation, then the output voltage falls as well.

For a CMOS regulator, the dropout voltage is determined by the drain-source on-state resistance (R_DS(ON)) of the

pass transistor. Therefore, if the linear regulator operates at less than the rated current, the dropout voltage for

that current scales accordingly. The following equation calculates the R_DS(ON)of the device.

V_DO

R_DS(ON)

=

I_RATED

(1)

7.3.4 Foldback Current Limit

The device has an internal current limit circuit that protects the regulator during transient high-load current faults

or shorting events. The current limit is a hybrid brickwall-foldback scheme. The current limit transitions from a

brickwall scheme to a foldback scheme at the foldback voltage (V_FOLDBACK). In a high-load current fault with

the output voltage above V_FOLDBACK, the brickwall scheme limits the output current to the current limit (I_CL).

When the voltage drops below V_FOLDBACK, a foldback current limit activates that scales back the current as the

output voltage approaches GND. When the output is shorted, the device supplies a typical current called the

short-circuit current limit (I_SC). I_CLand I_SCare listed in the Electrical Characteristics table.

The output voltage is not regulated when the device is in current limit. When a current limit event occurs, the

device begins to heat up because of the increase in power dissipation. When the device is in brickwall current

limit, the pass transistor dissipates power [(V_IN– V_OUT) × I_CL]. When the device output is shorted and the output

is below V_FOLDBACK, the pass transistor dissipates power [(V_IN– V_OUT) × I_SC]. If thermal shutdown is triggered,

the device turns off. After the device cools down, the internal thermal shutdown circuit turns the device back on.

If the output current fault condition continues, the device cycles between current limit and thermal shutdown. For

more information on current limits, see the Know Your Limits application report.

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Figure 7-1 shows a diagram of the foldback current limit.

V_OUT

Brickwall

V_OUT(NOM)

V_FOLDBACK

Foldback

0 V

I_OUT

I_RATED

0 mA

I_SC

I_CL

Figure 7-1. Foldback Current Limit

7.3.5 Undervoltage Lockout (UVLO)

The device has an independent undervoltage lockout (UVLO) circuit that monitors the input voltage, allowing a

controlled and consistent turn on and off of the output voltage. To prevent the device from turning off if the input

drops during turn on, the UVLO has hysteresis as specified in the Electrical Characteristics table.

7.3.6 Thermal Shutdown

A thermal shutdown protection circuit disables the LDO when the junction temperature (T_J) of the pass transistor

rises to T_SD(shutdown)(typical). Thermal shutdown hysteresis assures that the device resets (turns on) when the

temperature falls to T_SD(reset)(typical).

The thermal time-constant of the semiconductor die is fairly short, thus the device may cycle on and off

when thermal shutdown is reached until power dissipation is reduced. Power dissipation during startup can

be high from large V_IN– V_OUTvoltage drops across the device or from high inrush currents charging large

output capacitors. Under some conditions, the thermal shutdown protection disables the device before startup

completes.

For reliable operation, limit the junction temperature to the maximum listed in the Recommended Operating

Conditions table. Operation above this maximum temperature causes the device to exceed its operational

specifications. Although the internal protection circuitry of the device is designed to protect against thermal

overload conditions, this circuitry is not intended to replace proper heat sinking. Continuously running the device

into thermal shutdown or above the maximum recommended junction temperature reduces long-term reliability.

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7.3.7 Active Discharge

An internal pulldown MOSFET connects a resistor from OUT to ground when the device is disabled to actively

discharge the output capacitance. The active discharge circuit is activated by driving EN low or by the voltage on

IN falling below the undervoltage lockout (UVLO) threshold.

Do not rely on the active discharge circuit for discharging a large amount of output capacitance after the input

supply has collapsed because reverse current can possibly flow from the output to the input. This reverse current

flow can cause damage to the device. Limit reverse current to no more than 5% of the device rated current for a

short period of time.

7.4 Device Functional Modes

7.4.1 Device Functional Mode Comparison

The Device Functional Mode Comparison table shows the conditions that lead to the different modes of

operation. See the Electrical Characteristics table for parameter values.

Table 7-1. Device Functional Mode Comparison

PARAMETER

OPERATING MODE

V_IN

V_EN

I_OUT

T_J

Normal operation

Dropout operation

V_IN> V_OUT(nom)+ V_DOand V_IN> V_IN(min)

V_IN(min)< V_IN< V_OUT(nom)+ V_DO

V_EN> V_EN(HI)

I_OUT< I_OUT(max)

T_J< T_SD(shutdown)

Disabled

(any true condition

disables the device)

V_IN< V_UVLO

V_EN< V_EN(LOW)

Not applicable

T_J> T_SD(shutdown)

7.4.2 Normal Operation

The device regulates to the nominal output voltage when the following conditions are met:

•

The input voltage is greater than the nominal output voltage plus the dropout voltage (V_OUT(nom)+ V_DO)

The output current is less than the current limit (I_OUT< I_CL)

The device junction temperature is less than the thermal shutdown temperature (T_J< T_SD

)

•

The enable voltage has previously exceeded the enable rising threshold voltage and has not yet decreased

to less than the enable falling threshold

7.4.3 Dropout Operation

If the input voltage is lower than the nominal output voltage plus the specified dropout voltage, but all other

conditions are met for normal operation, the device operates in dropout mode. In this mode, the output voltage

tracks the input voltage. During this mode, the transient performance of the device becomes significantly

degraded because the pass transistor is in the ohmic or triode region, and acts as a switch. Line or load

transients in dropout can result in large output-voltage deviations.

When the device is in a steady dropout state (defined as when the device is in dropout, V_IN< V_OUT(NOM)+ V_DO

,

directly after being in a normal regulation state, but not during startup), the pass transistor is driven into the

ohmic or triode region. When the input voltage returns to a value greater than or equal to the nominal output

voltage plus the dropout voltage (V_OUT(NOM)+ V_DO), the output voltage can overshoot for a short period of time

while the device pulls the pass transistor back into the linear region.

7.4.4 Disabled

The output of the LDO can be shut down by driving EN to less than V_EN(LOW)(see the Electrical Characteristics

table). When disabled, the pass transistor is turned off, internal circuits are shut down, and the output voltage is

actively discharged to ground by an internal discharge circuit between OUT and ground.

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8 Application and Implementation

Note

Information in the following applications sections is not part of the TI component specification,

and TI does not warrant its accuracy or completeness. TI’s customers are responsible for

determining suitability of components for their purposes, as well as validating and testing their design

implementation to confirm system functionality.

8.1 Application Information

8.1.1 Recommended Capacitor Types

The device is designed to be stable using low equivalent series resistance (ESR) ceramic capacitors at the input

and output. Multilayer ceramic capacitors have become the industry standard for these types of applications and

are recommended, but must be used with good judgment. Ceramic capacitors that employ X7R-, X5R-, and

C0G-rated dielectric materials provide relatively good capacitive stability across temperature, whereas the use of

Y5V-rated capacitors is discouraged because of large variations in capacitance.

Regardless of the ceramic capacitor type selected, the effective capacitance varies with operating voltage and

temperature. As a rule of thumb, expect the effective capacitance to decrease by as much as 50%. The input

and output capacitors recommended in the Recommended Operating Conditions table account for an effective

capacitance of approximately 50% of the nominal value.

8.1.2 Input and Output Capacitor Requirements

Although the LDO itself is stable without an input capacitor, good analog design practice is to connect a

capacitor from IN to GND, with a value at least equal to the nominal value specified in the Recommended

Operating Conditions table. The input capacitor counteracts reactive input sources and improves transient

response, input ripple, and PSRR, and is recommended if the source impedance is greater than 0.5 Ω. When the

source resistance and inductance are sufficiently high, especially in the presence of load transients, the overall

system may be susceptible to instability (including ringing and sustained oscillation) and other performance

degradation if there is insufficient capacitance between IN and GND. A capacitor with a value greater than

the minimum may be necessary if large, fast-rise-time load or line transients are anticipated or if the device is

located more than a few centimeters from the input power source.

An output capacitor of an appropriate value helps ensure stability and improve dynamic performance. Use an

output capacitor within the range specified in the Recommended Operating Conditions table.

8.1.3 Load Transient Response

The load-step transient response is the output voltage response by the LDO to a step in load current, whereby

output voltage regulation is maintained. There are two key transitions during a load transient response: the

transition from a light to a heavy load and the transition from a heavy to a light load. The regions shown in Figure

8-1 are broken down as follows. Regions A, E, and H are where the output voltage is in steady-state.

tAt

tCt

tDt

tEt

tGt

tHt

B

F

Figure 8-1. Load Transient Waveform

During transitions from a light load to a heavy load, the:

•

Initial voltage dip is a result of the depletion of the output capacitor charge and parasitic impedance to the

output capacitor (region B)

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•

Recovery from the dip results from the LDO increasing its sourcing current, and leads to output voltage

regulation (region C)

During transitions from a heavy load to a light load, the:

•

Initial voltage rise results from the LDO sourcing a large current, and leads to the output capacitor charge to

increase (region F)

Recovery from the rise results from the LDO decreasing its sourcing current in combination with the load

discharging the output capacitor (region G)

A larger output capacitance reduces the peaks during a load transient but slows down the response time of the

device. A larger DC load also reduces the peaks because the amplitude of the transition is lowered and a higher

current discharge path is provided for the output capacitor.

8.1.4 Undervoltage Lockout (UVLO) Operation

The UVLO circuit ensures that the device stays disabled before its input supply reaches the minimum

operational voltage range, and ensures that the device shuts down when the input supply collapses. Figure

8-2 shows the UVLO circuit response to various input voltage events. The diagram can be separated into the

following parts:

•

Region A: The device does not start until the input reaches the UVLO rising threshold.

Region B: Normal operation, regulating device.

Region C: Brownout event above the UVLO falling threshold (UVLO rising threshold – UVLO hysteresis). The

output may fall out of regulation but the device remains enabled.

•

Region D: Normal operation, regulating device.

Region E: Brownout event below the UVLO falling threshold. The device is disabled in most cases and the

output falls because of the load and active discharge circuit. The device is reenabled when the UVLO rising

threshold is reached by the input voltage and a normal start-up follows.

•

Region F: Normal operation followed by the input falling to the UVLO falling threshold.

Region G: The device is disabled when the input voltage falls below the UVLO falling threshold to 0 V. The

output falls because of the load and active discharge circuit.

UVLO Rising Threshold

UVLO Hysteresis

V_IN

C

V_OUT

tAt

tBt

tDt

tEt

tFt

tGt

Figure 8-2. Typical UVLO Operation

8.1.5 Power Dissipation (P_D)

Circuit reliability demands that proper consideration be given to device power dissipation, location of the circuit

on the printed circuit board (PCB), and correct sizing of the thermal plane. The PCB area around the regulator

must be as free as possible of other heat-generating devices that cause added thermal stresses.

As a first-order approximation, power dissipation in the regulator depends on the input-to-output voltage

difference and load conditions. Use Equation 2 to approximate P_D:

P_D= (V_IN– V_OUT) × I_OUT

(2)

Power dissipation can be minimized, and thus greater efficiency achieved, by proper selection of the system

voltage rails. Proper selection allows the minimum input-to-output voltage differential to be obtained. The low

dropout of the TPS7A20 allows for maximum efficiency across a wide range of output voltages.

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The main heat conduction path for the device is through the thermal pad on the package. As such, the thermal

pad must be soldered to a copper pad area under the device. This pad area contains an array of plated vias that

conduct heat to any inner plane areas or to a bottom-side copper plane.

The maximum power dissipation determines the maximum allowable junction temperature (T_J) for the device.

According to Equation 3, power dissipation and junction temperature are most often related by the junction-to-

ambient thermal resistance (R_θJA) of the combined PCB and device package and the temperature of the ambient

air (T_A). Equation 4 rearranges Equation 3 for output current.

T_J= T_A+ (R_θJA× P_D)

(3)

(4)

I_OUT= (T_J– T_A) / [R_θJA× (V_IN– V_OUT)]

Unfortunately, this thermal resistance (R_θJA) is highly dependent on the heat-spreading capability built into the

particular PCB design, and therefore varies according to the total copper area, copper weight, and location of

the planes. The R_θJArecorded in the Thermal Information table is determined by the JEDEC standard, PCB,

and copper-spreading area, and is only used as a relative measure of package thermal performance. For a

well-designed thermal layout, R_θJAis actually the sum of the X2SON package junction-to-case (bottom) thermal

resistance (R_θJC(bot)) plus the thermal resistance contribution by the PCB copper.

8.1.5.1 Estimating Junction Temperature

The JEDEC standard now recommends the use of psi (Ψ) thermal metrics to estimate the junction temperatures

of the LDO when in-circuit on a typical PCB board application. These metrics are not strictly speaking thermal

resistances, but rather offer practical and relative means of estimating junction temperatures. These psi metrics

are determined to be significantly independent of the copper-spreading area. The key thermal metrics (Ψ_JTand

Ψ_JB) are used in accordance with Equation 5 and are given in the Thermal Information table.

Ψ_JT: T_J= T_T+ Ψ_JT× P_Dand Ψ_JB: T_J= T_B+ Ψ_JB× P_D

(5)

where:

•

P_Dis the power dissipated as explained in Equation 2

T_Tis the temperature at the center-top of the device package

T_Bis the PCB surface temperature measured 1 mm from the device package and centered on the package

edge

8.1.5.2 Recommended Area for Continuous Operation

The operational area of an LDO is limited by the dropout voltage, output current, junction temperature, and input

voltage. The recommended area for continuous operation for a linear regulator is given in Figure 8-3 and can be

separated into the following parts:

•

Dropout voltage limits the minimum differential voltage between the input and the output (V_IN– V_OUT) at a

given output current level. See the Dropout Operation section for more details.

The rated output currents limits the maximum recommended output current level. Exceeding this rating

causes the device to fall out of specification.

The rated junction temperature limits the maximum junction temperature of the device. Exceeding this rating

causes the device to fall out of specification and reduces long-term reliability.

– The shape of the slope is given by Equation 4. The slope is nonlinear because the maximum-rated

junction temperature of the LDO is controlled by the power dissipation across the LDO; thus when V_IN

V_OUTincreases the output current must decrease.

–

•

The rated input voltage range governs both the minimum and maximum of V_IN– V_OUT.

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SBVS338E – MARCH 2020 – REVISED DECEMBER 2021

Figure 8-3 shows the recommended area of operation for this device on a JEDEC-standard high-K board with a

R_θJAas given in the Thermal Information table.

Output current limited by

dropout

Rated output

current

Output current limited by thermals

Limited by

minimum V_IN

Limited by

maximum V_IN

V_INœ V_OUT(V)

Figure 8-3. Region Description of Continuous Operation Regime

30

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SBVS338E – MARCH 2020 – REVISED DECEMBER 2021

8.2 Typical Application

Figure 8-4 shows the typical application circuit for the TPS7A20. Input and output capacitances may need to be

increased above the 1 µF minimum for some applications.

V_OUT

V_IN

OUTPUT

1.0 µF

INPUT

1.0 µF

TPS7A20

V_EN

ENABLE

GND

SVA-30180501

Figure 8-4. TPS7A20 Typical Application

8.2.1 Design Requirements

Table 8-1 summarizes the design requirements for Figure 8-4.

Table 8-1. Design Parameters

DESIGN PARAMETER

EXAMPLE VALUE

3.1 V to 3.6 V

2.8 V

Input voltage range

Output voltage

Output current

200 mA

Maximum ambient temperature

85°C

8.2.2 Detailed Design Procedure

For this design example, the 2.8-V output version (TPS7A2028) is selected. A nominal 3.3-V input supply

is assumed. A minimum 1.0-μF input capacitor is recommended to minimize the effect of resistance and

inductance between the 3.3-V source and the LDO input. A minimum 1.0-μF output capacitor is also

recommended for stability and good load transient response. The dropout voltage (V_DO) is less than 140 mV

maximum at a 2.8-V output voltage and 300-mA output current, so there are no dropout issues with a minimum

input voltage of 3.0 V and a maximum output current of 200 mA.

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SBVS338E – MARCH 2020 – REVISED DECEMBER 2021

8.2.3 Application Curves

4.5

4

100

90

80

70

60

50

40

30

20

10

0

I_OUT

200 mA

3.5

3

2.5

2

1.5

1

0.5

0

V_IN/ V_EN

V_OUT

-0.5

0

200 400 600 800 1000 1200 1400 1600 1800 2000

Time (us)

10 20

100

1000

10000 100000 1000000 1E+7

Frequency (Hz)

D064

D065

Figure 8-5. Start-Up

Figure 8-6. PSRR

9 Power Supply Recommendations

This device is designed to operate from an input supply voltage range of 1.6 V to 6.0 V. The input supply must

be well regulated and free of spurious noise. To ensure that the output voltage is well regulated and dynamic

performance is optimum, the input supply must be at least V_OUT(nom)+ 0.3 V or 1.6 V, whichever is greater.

TI highly recommends using a 1-µF or greater input capacitor to reduce the impedance of the input supply,

especially during transients.

32

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10 Layout

10.1 Layout Guidelines

•

Place input and output capacitors as close to the device as possible.

Use copper planes for device connections to optimize thermal performance.

Place thermal vias around the device to distribute the heat.

Do not place a thermal via directly beneath the thermal pad of the DQN package. A via can wick solder or

solder paste away from the thermal pad joint during the soldering process, leading to a compromised solder

joint on the thermal pad.

10.2 Layout Examples

V

OUT

IN

C

IN

OUT

5

C

1

2

3

OUT

IN

GND

EN

Enable

4

N/C

Figure 10-1. DBV Package (SOT-23) Typical Layout

TPS7A20

V_OUT

V_IN

1

2

4

3

C_OUT

C_IN

Power Ground

V_EN

Figure 10-2. DQN Package (X2SON) Typical Layout

V_IN

V_OUT

TPS7A20

A1

A2

B2

C_OUT

C_IN

B1

Power Ground

V_EN

Figure 10-3. YCJ and YCK Package (DSBGA) Typical Layout

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SBVS338E – MARCH 2020 – REVISED DECEMBER 2021

11 Device and Documentation Support

11.1 Device Support

11.1.1 Device Nomenclature

Table 11-1. Device Nomenclature

PRODUCT ^{(1) (2)}

V_OUT

xx(x) is the nominal output voltage. For output voltages with a resolution of 100 mV, two digits are used

in the ordering number; otherwise, three digits are used (for example, 28 = 2.8 V; 125 = 1.25 V).

P indicates an active output discharge feature. All members of the TPS7A20 family actively discharge

the output when the device is disabled.

TPS7A20xx(x)Pyyyz

yyy is the package designator.

z is the package quantity. R is for reel (3000 pieces for DQN and DBV; 12000 pieces for YCJ and YCK).

(1) For the most current package and ordering information see the Package Option Addendum at the end of this document, or visit the

device product folder on www.ti.com.

(2) Output voltages from 0.8 V to 5.5 V in 25-mV increments are available. Contact the factory for details and availability.

11.2 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on

Subscribe to updates to register and receive a weekly digest of any product information that has changed. For

change details, review the revision history included in any revised document.

11.3 Support Resources

TI E2E^™support forums are an engineer's go-to source for fast, verified answers and design help — straight

from the experts. Search existing answers or ask your own question to get the quick design help you need.

Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do

not necessarily reflect TI's views; see TI's Terms of Use.

11.4 Trademarks

TI E2E^™is a trademark of Texas Instruments.

All trademarks are the property of their respective owners.

11.5 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled

with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may

be more susceptible to damage because very small parametric changes could cause the device not to meet its published

specifications.

11.6 Glossary

TI Glossary

This glossary lists and explains terms, acronyms, and definitions.

12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

34

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Product Folder Links: TPS7A20

PACKAGE MATERIALS INFORMATION

www.ti.com

29-Dec-2021

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

A0

B0

K0

P1

W

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

TPS7A2009PDBVR

TPS7A2009PDQNR

TPS7A20105PDQNR

TPS7A2012PDBVR

TPS7A2012PDQNR

TPS7A2015PDBVR

TPS7A2015PDQNR

TPS7A201825PDQNR

TPS7A20185PDBVR

TPS7A20185PDQNR

TPS7A2018PDBVR

SOT-23

X2SON

SOT-23

X2SON

SOT-23

X2SON

SOT-23

X2SON

SOT-23

DBV

DQN

DBV

DQN

DBV

DQN

DBV

DQN

DBV

5

4

5

4

5

4

5

4

5

3000

178.0

180.0

178.0

180.0

178.0

180.0

178.0

180.0

178.0

180.0

178.0

180.0

9.0

8.4

9.5

9.0

8.4

9.5

8.4

9.0

9.5

8.4

9.5

8.4

9.0

8.4

9.5

8.4

3.3

3.2

1.4

0.5

1.4

0.5

1.4

0.5

0.53

0.5

0.53

1.4

0.53

0.5

1.4

4.0

8.0

Q3

Q2

Q3

Q2

Q3

Q2

Q3

Q2

Q3

1.16

3.3

1.16

3.2

1.16

3.2

1.16

3.2

3.3

3.2

1.16

1.13

1.16

1.13

3.2

1.16

1.13

1.16

1.13

3.2

3.3

3.2

1.13

1.16

3.2

1.13

1.16

3.2

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

29-Dec-2021

Device

Package Package Pins

Type Drawing

SPQ

Reel

A0

B0

K0

P1

W

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

TPS7A2018PDBVR

TPS7A2018PDQNR

TPS7A2022PYCKR

TPS7A2024PDBVR

TPS7A2025PDBVR

TPS7A2025PDQNR

TPS7A2027PDQNR

TPS7A20285PDBVR

TPS7A20285PDQNR

TPS7A20285PYCKR

TPS7A2028PDBVR

TPS7A2028PDQNR

TPS7A2029PDQNR

TPS7A2030PDBVR

TPS7A2030PDQNR

TPS7A2031PDBVR

TPS7A2032PDBVR

TPS7A2033PDBVR

TPS7A2033PDQNR

TPS7A2033PYCJR

TPS7A2036PDBVR

TPS7A2036PDQNR

TPS7A2040PDQNR

TPS7A2042PDBVR

TPS7A2042PDQNR

TPS7A2045PDBVR

TPS7A2045PDQNR

TPS7A2050PDBVR

SOT-23

X2SON

DSBGA

SOT-23

X2SON

SOT-23

X2SON

DSBGA

SOT-23

X2SON

SOT-23

X2SON

SOT-23

X2SON

DSBGA

SOT-23

X2SON

SOT-23

X2SON

SOT-23

X2SON

SOT-23

DBV

DQN

YCK

DBV

DQN

DBV

DQN

YCK

DBV

DQN

DBV

DQN

DBV

DQN

YCJ

5

4

5

4

5

4

5

4

5

4

5

4

5

4

5

4

5

4

5

3000

12000

3000

12000

3000

12000

3000

178.0

180.0

178.0

180.0

178.0

180.0

178.0

180.0

178.0

180.0

178.0

180.0

178.0

180.0

178.0

180.0

178.0

180.0

178.0

180.0

178.0

180.0

178.0

9.0

8.4

9.5

8.4

9.0

8.4

9.5

9.0

8.4

9.5

8.4

9.0

8.4

9.5

8.4

9.0

9.5

8.4

9.0

8.4

9.0

8.4

9.5

8.4

9.0

8.4

9.5

8.4

9.0

9.5

9.0

8.4

9.5

8.4

9.0

3.3

1.13

1.16

0.71

3.2

1.13

1.16

0.71

3.2

1.4

0.53

0.5

0.42

1.4

0.5

1.4

0.5

0.42

1.4

0.53

0.5

1.4

0.5

1.4

0.5

0.53

0.42

1.4

0.5

1.4

0.5

1.4

0.5

1.4

4.0

2.0

4.0

2.0

4.0

2.0

4.0

8.0

Q3

Q2

Q1

Q3

Q2

Q3

Q2

Q1

Q3

Q2

Q3

Q2

Q3

Q2

Q1

Q3

Q2

Q3

Q2

Q3

Q2

Q3

3.3

3.2

3.3

3.2

1.16

3.3

1.16

3.2

1.16

0.71

3.2

1.16

0.71

3.2

3.3

3.2

1.13

1.16

3.2

1.13

1.16

3.2

3.3

3.2

1.16

3.2

1.16

3.2

3.3

3.2

3.3

3.2

3.3

3.2

1.16

1.13

0.71

3.3

1.16

1.13

0.71

3.2

DBV

DQN

DBV

DQN

DBV

DQN

DBV

3.2

1.16

3.2

1.16

3.2

3.3

3.2

1.16

3.3

1.16

3.2

1.16

3.2

1.16

3.2

3.3

3.2

Pack Materials-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

29-Dec-2021

Device

Package Package Pins

Type Drawing

SPQ

Reel

A0

B0

K0

P1

W

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

TPS7A2050PDQNR

TPS7A2055PDBVR

X2SON

SOT-23

DQN

DBV

4

5

3000

180.0

178.0

180.0

9.5

9.0

8.4

1.16

3.3

1.16

3.2

0.5

1.4

4.0

8.0

Q2

Q3

3.2

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

TPS7A2009PDBVR

TPS7A2009PDQNR

TPS7A20105PDQNR

TPS7A2012PDBVR

TPS7A2012PDQNR

TPS7A2015PDBVR

TPS7A2015PDQNR

TPS7A201825PDQNR

TPS7A20185PDBVR

SOT-23

X2SON

SOT-23

X2SON

SOT-23

X2SON

SOT-23

DBV

DQN

DBV

DQN

DBV

DQN

DBV

5

4

5

4

5

4

5

3000

180.0

210.0

184.0

180.0

210.0

184.0

210.0

180.0

184.0

205.0

184.0

205.0

210.0

180.0

185.0

184.0

180.0

185.0

184.0

185.0

180.0

184.0

200.0

184.0

200.0

185.0

18.0

35.0

19.0

18.0

35.0

19.0

35.0

18.0

19.0

33.0

19.0

33.0

35.0

Pack Materials-Page 3

PACKAGE MATERIALS INFORMATION

www.ti.com

29-Dec-2021

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

TPS7A20185PDBVR

TPS7A20185PDQNR

TPS7A2018PDBVR

TPS7A2018PDQNR

TPS7A2022PYCKR

TPS7A2024PDBVR

TPS7A2025PDBVR

TPS7A2025PDQNR

TPS7A2027PDQNR

TPS7A20285PDBVR

TPS7A20285PDQNR

TPS7A20285PYCKR

TPS7A2028PDBVR

TPS7A2028PDQNR

TPS7A2029PDQNR

TPS7A2030PDBVR

TPS7A2030PDQNR

TPS7A2031PDBVR

TPS7A2032PDBVR

TPS7A2033PDBVR

TPS7A2033PDQNR

TPS7A2033PYCJR

TPS7A2036PDBVR

TPS7A2036PDQNR

TPS7A2040PDQNR

TPS7A2042PDBVR

TPS7A2042PDQNR

TPS7A2045PDBVR

SOT-23

X2SON

SOT-23

X2SON

DSBGA

SOT-23

X2SON

SOT-23

X2SON

DSBGA

SOT-23

X2SON

SOT-23

X2SON

SOT-23

X2SON

DSBGA

SOT-23

X2SON

SOT-23

X2SON

SOT-23

DBV

DQN

DBV

DQN

YCK

DBV

DQN

DBV

DQN

YCK

DBV

DQN

DBV

DQN

DBV

DQN

YCJ

5

4

5

4

5

4

5

4

5

4

5

4

5

4

5

4

5

4

5

3000

12000

3000

12000

3000

12000

3000

180.0

205.0

184.0

210.0

180.0

205.0

184.0

182.0

210.0

180.0

210.0

184.0

180.0

210.0

184.0

182.0

210.0

180.0

205.0

184.0

210.0

180.0

184.0

210.0

180.0

210.0

180.0

210.0

184.0

205.0

182.0

180.0

210.0

184.0

210.0

180.0

184.0

180.0

210.0

180.0

200.0

184.0

185.0

180.0

200.0

184.0

182.0

185.0

180.0

185.0

184.0

180.0

185.0

184.0

182.0

185.0

180.0

200.0

184.0

185.0

180.0

184.0

185.0

180.0

185.0

180.0

185.0

184.0

200.0

182.0

180.0

185.0

184.0

185.0

180.0

184.0

180.0

185.0

18.0

33.0

19.0

35.0

18.0

33.0

19.0

20.0

35.0

18.0

35.0

19.0

18.0

35.0

19.0

20.0

35.0

18.0

33.0

19.0

35.0

18.0

19.0

35.0

18.0

35.0

18.0

35.0

19.0

33.0

20.0

18.0

35.0

19.0

35.0

18.0

19.0

18.0

35.0

DBV

DQN

DBV

DQN

DBV

Pack Materials-Page 4

PACKAGE MATERIALS INFORMATION

www.ti.com

29-Dec-2021

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

TPS7A2045PDQNR

TPS7A2050PDBVR

TPS7A2050PDQNR

TPS7A2055PDBVR

X2SON

SOT-23

X2SON

SOT-23

DQN

DBV

DQN

DBV

4

5

4

5

3000

184.0

210.0

180.0

184.0

180.0

210.0

184.0

185.0

180.0

184.0

180.0

185.0

19.0

35.0

18.0

19.0

18.0

35.0

Pack Materials-Page 5

PACKAGE OUTLINE

DBV0005A

SOT-23 - 1.45 mm max height

S

C

A

L

E

4

.

0

SMALL OUTLINE TRANSISTOR

C

3.0

2.6

0.1 C

1.75

1.45

0.90

B

A

PIN 1

INDEX AREA

1

2

5

2X 0.95

1.9

3.05

2.75

1.9

4

3

0.5

5X

0.3

0.15

0.00

(1.1)

TYP

0.2

C A B

0.25

GAGE PLANE

0.22

0.08

TYP

8

0

TYP

0.6

0.3

TYP

SEATING PLANE

4214839/F 06/2021

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. Refernce JEDEC MO-178.

4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not

exceed 0.25 mm per side.

www.ti.com

EXAMPLE BOARD LAYOUT

DBV0005A

SOT-23 - 1.45 mm max height

SMALL OUTLINE TRANSISTOR

PKG

5X (1.1)

1

5

5X (0.6)

SYMM

(1.9)

2

3

2X (0.95)

4

(R0.05) TYP

(2.6)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE:15X

SOLDER MASK

OPENING

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

METAL

EXPOSED METAL

0.07 MIN

ARROUND

0.07 MAX

ARROUND

NON SOLDER MASK

DEFINED

SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

4214839/F 06/2021

NOTES: (continued)

5. Publication IPC-7351 may have alternate designs.

6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com

EXAMPLE STENCIL DESIGN

DBV0005A

SOT-23 - 1.45 mm max height

SMALL OUTLINE TRANSISTOR

PKG

5X (1.1)

1

5

5X (0.6)

SYMM

(1.9)

2

3

2X(0.95)

4

(R0.05) TYP

(2.6)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

SCALE:15X

4214839/F 06/2021

NOTES: (continued)

7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

8. Board assembly site may have different recommendations for stencil design.

www.ti.com

PACKAGE OUTLINE

X2SON - 0.4 mm max height

DQN0004A

PLASTIC SMALL OUTLINE - NO LEAD

1.05

0.95

A

B

1

1.05

0.95

PIN 1

INDEX AREA

C

0.4 MAX

SEATING PLANE

0.08

NOTE 6

+0.12

-0.1

0.05

0.00

0.48

(0.05) TYP

NOTE 6

2

1

3

EXPOSED

THERMAL PAD

5

2X 0.65

(0.07) TYP

NOTE 5

4

0.28

PIN 1 ID

(OPTIONAL)

NOTE 4

4X

0.15

(0.11)

0.3

0.2

0.1

C A B

0.05

C

0.30

0.15

3X

4215302/E 12/2016

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.

4. Features may not exist. Recommend use of pin 1 marking on top of package for orientation purposes.

5. Shape of exposed side leads may differ.

6. Number and location of exposed tie bars may vary.

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EXAMPLE BOARD LAYOUT

X2SON - 0.4 mm max height

DQN0004A

PLASTIC SMALL OUTLINE - NO LEAD

(0.86)

SYMM

SEE DETAIL

4X

4X (0.36)

(0.03)

4

4X (0.21)

1

5

SYMM

(0.65)

4X (0.18)

2

3

(

0.48)

(0.22) TYP

EXPOSED METAL

CLEARANCE

LAND PATTERN EXAMPLE

SCALE: 40X

0.05 MIN

ALL AROUND

SOLDER MASK

OPENING

EXPOSED METAL

METAL UNDER

SOLDER MASK

DEFINED

SOLDER MASK DETAIL

4215302/E 12/2016

NOTES: (continued)

7. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

number SLUA271 (www.ti.com/lit/slua271)

.

8. If any vias are implemented, it is recommended that vias under paste be filled, plugged or tented.

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EXAMPLE STENCIL DESIGN

X2SON - 0.4 mm max height

DQN0004A

PLASTIC SMALL OUTLINE - NO LEAD

(0.9)

SYMM

4X (0.4)

4X (0.03)

4

1

4X (0.21)

5

SYMM

(0.65)

SOLDER MASK

EDGE

4X (0.22)

2

3

(

0.45)

4X (0.235)

SOLDER PASTE EXAMPLE

BASED ON 0.075 - 0.1mm THICK STENCIL

EXPOSED PAD

88% PRINTED SOLDER COVERAGE BY AREA

SCALE: 60X

4215302/E 12/2016

NOTES: (continued)

9. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

www.ti.com

IMPORTANT NOTICE AND DISCLAIMER

TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE

DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”

AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY

IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD

PARTY INTELLECTUAL PROPERTY RIGHTS.

These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate

TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable

standards, and any other safety, security, regulatory or other requirements.

These resources are subject to change without notice. TI grants you permission to use these resources only for development of an

application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license

is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you

will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these

resources.

TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with

such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for

TI products.

TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	TPS7A20285PDQNR
厂家：	TEXAS INSTRUMENTS
描述：	TPS7A20 300-mA, Ultra-Low-Noise, Low-IQ, High PSRR LDO
文件：	总51页 (文件大小：8881K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

TPS7A20285PDQNR [TI]

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