TPS7A4433DGQR [TI]
TPS7A44 50-mA, 65-V, Low IQ, Low-Dropout Linear Voltage Regulator With Power-Good and Selectable Mid-Output Rail;
| 型号： | TPS7A4433DGQR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | TPS7A44 50-mA, 65-V, Low IQ, Low-Dropout Linear Voltage Regulator With Power-Good and Selectable Mid-Output Rail |
| 文件： | 总37页 (文件大小：3000K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPS7A44
SBVS421 – NOVEMBER 2021
TPS7A44 50-mA, 65-V, Low IQ, Low-Dropout Linear Voltage Regulator
With Power-Good and Selectable Mid-Output Rail
1 Features
3 Description
•
•
Input voltage: 4 V to 65 V
The TPS7A44 low-dropout (LDO) linear voltage
regulator introduces a combination of a 4-V to 65-V
input voltage range with very-low quiescent current.
Wide output (OUT) voltage range:
– Adjustable: 1.24 V to 14.5 V
– Fixed: 1.25 V to 5.0 V
Selectable intermediate output (MID_OUT):
– 10 V, 12 V, 15 V
This device can support a wide range of input
voltages (for example, a 15-s battery and 24-V to
48-V line power) and withstand line transient voltages
up to 85 V. These features help modern applications
meet increasingly stringent energy requirements, and
help extend battery life in portable-power solutions.
•
•
Maximum output current:
– 50 mA (shared between OUT and MID_OUT)
1% accuracy over temperature
Ultra-low IQ: 5.5 μA
•
•
•
•
•
•
•
The TPS7A44 output (OUT) is available in both
fixed and adjustable output versions, which can
regulate from 1.24 V to 14.5 V at 1% accuracy. The
device also provides a second intermediate output
(MID_OUT) that can be set to 10 V, 12 V, and 15 V
using the MVSEL pins and can be used to bias gate
drivers in place of a discrete regulator.
Precision enable
Power-good (PG) output (open drain)
Thermal shutdown and overcurrent protection
Operating junction temperature: –40°C to +125°C
Package: HVSSOP-10 (RθJA = 53.7°C/W)
2 Applications
•
•
•
•
•
•
•
Cordless power tools
DC motors and fans
The TPS7A44 features a precision enable input that
helps enable or disable the LDO at a fixed and
accurate threshold voltage using a resistor divider
from the input.
Programmable logic controllers (PLCs)
Field transmitter and process sensors
Smoke and heat detectors
EV charging infrastructure
Battery packs
The power-good (PG) output is used to monitor the
voltage at the feedback pin to indicate the status of
the output voltage. The EN input and PG output can
be used for sequencing multiple power sources in the
system.
Device Information(1)
PART NUMBER
TPS7A44
PACKAGE
BODY SIZE (NOM)
HVSSOP (10)
3.00 mm × 3.00 mm
(1) For all available packages, see the package option
addendum at the end of the data sheet.
300
200
100
0
100
VIN
VOUT
COUT
IN
OUT
90
80
70
60
50
40
30
20
10
0
CIN
VEN
VMVSEL1
VMVSEL2
NC
EN
GND
GND
-100
-200
-300
-400
-500
-600
-700
TPS7A44
VMID_OUT
CMID_OUT
VMID_OUT
VOUT
VIN
MID_OUT
MVSEL1
MVSEL2
GND
GND
PG
GND
0
200
400
Time (ms)
600
800
1,000
Typical Application Circuit
Line Transient With VMID_OUT = 12 V, VOUT = 3.3 V,
IOUT = 50 mA
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS7A44
SBVS421 – NOVEMBER 2021
www.ti.com
Table of Contents
1 Features............................................................................1
2 Applications.....................................................................1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings........................................ 4
6.2 ESD Ratings............................................................... 4
6.3 Recommended Operating Conditions.........................5
6.4 Thermal Information....................................................5
6.5 Electrical Characteristics.............................................6
6.6 Typical Characteristics................................................8
7 Detailed Description......................................................15
7.1 Overview...................................................................15
7.2 Functional Block Diagrams....................................... 15
7.3 Feature Description...................................................16
7.4 Device Functional Modes..........................................20
8 Application and Implementation..................................21
8.1 Application Information............................................. 21
8.2 Typical Application.................................................... 23
9 Power Supply Recommendations................................25
10 Layout...........................................................................25
10.1 Layout Guidelines................................................... 25
10.2 Layout Examples.................................................... 26
11 Device and Documentation Support..........................27
11.1 Device Support........................................................27
11.2 Documentation Support.......................................... 27
11.3 Receiving Notification of Documentation Updates..27
11.4 Support Resources................................................. 27
11.5 Trademarks............................................................. 27
11.6 Electrostatic Discharge Caution..............................27
11.7 Glossary..................................................................28
12 Mechanical, Packaging, and Orderable
Information.................................................................... 28
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
DATE
REVISION
NOTES
November 2021
*
Initial Release
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5 Pin Configuration and Functions
OUT
FB
1
2
3
4
5
10
9
IN
OUT
NC
1
2
3
4
5
10
IN
NC
9
8
7
6
NC
Thermal pad
Thermal pad
PG
8
MID_OUT
MVSEL2
EN
PG
MID_OUT
MVSEL2
EN
MVSEL1
GND
7
MVSEL1
GND
6
Not to scale
Not to scale
Figure 5-1. DGQ Package (Adjustable),
10-Pin HVSSOP (Top View)
Figure 5-2. DGQ Package (Fixed), 10-Pin HVSSOP
(Top View)
Table 5-1. Pin Functions
PIN
TYPE
DESCRIPTION
DGQ
(Adjustable)
DGQ
(Fixed)
NAME
Precision enable pin. Driving this pin higher than VEN(HI) enables the device.
Driving this pin lower than VEN(LOW) disables the device. This pin can be left
floating to enable the device because the device features an internal pullup
current source. If this pin is tied to the IN pin then the input voltage must not
exceed 18 V; see the Recommended Operating Conditions table.
EN
FB
6
6
Input
Feedback pin. Input to the control-loop error amplifier for the (OUT) output.
This pin is used to set the output voltage of the device with the use of
external resistors. For adjustable-voltage version devices only. This pin must
not be left floating.
2
5
—
5
Input
—
GND
IN
Ground pin.
Input pin. For best transient response and to minimize input impedance, use
the recommended value or larger ceramic capacitor from IN to ground; see
the Recommended Operating Conditions table. Place the input capacitor as
close to the IN and GND pins of the device as possible.
10
10
Input
MID output pin. A capacitor is required from MID_OUT to ground for stability.
For best transient response, use the nominal recommended value or larger
capacitor from MID_OUT to ground. Follow the recommended capacitor
value as listed in the Recommended Operating Conditions table. Place the
MID output capacitor as close to the MID_OUT and GND pins of the device
as possible.
MID_OUT
8
8
Output
MID_OUT voltage-select pin. The MVSEL1 pin and MVSEL2 pin are used
to set the MID_OUT voltage; see Table 8-1 for details on how to set the
MID_OUT voltage using these pins. Do not float this pin, instead tie this pin
MVSEL1
MVSEL2
4
7
4
7
Input
Input
to GND if not used to set VMID_OUT
.
MID_OUT voltage-select pin. The MVSEL2 pin and MVSEL1 pin are used
to set the MID_OUT voltage; see Table 8-1 for details on how to set the
MID_OUT voltage using these pins. Do not float this pin, instead tie this pin
to GND if not used to set VMID_OUT
.
No internal connection. This pin must be left floating to observe high voltage
clearance between the IN and MID_OUT pins.
NC
NC
9
9
2
—
—
No internal connection. This pin can be left floating or tied to the GND plane
to improve thermal performance.
—
Output pin. A capacitor is required from OUT to ground for stability. For best
transient response, use the nominal recommended value or larger capacitor
from OUT to ground. Follow the recommended capacitor value as listed in
the Recommended Operating Conditions table. Place the output capacitor as
close to the OUT and GND pins of the device as possible.
OUT
1
1
Output
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Table 5-1. Pin Functions (continued)
PIN
TYPE
DESCRIPTION
DGQ
(Adjustable)
DGQ
(Fixed)
NAME
Power-good pin. An open-drain output indicates when the output voltage
reaches VIT(PG, RISING). If not used, this pin can be left floating or tied to the
GND plane to improve thermal performance.
PG
3
3
Output
—
Exposed pad of the package. Connect this pad to ground or leave floating.
Connect the thermal pad to a large-area GND plane for improved thermal
performance.
Thermal pad
Pad
Pad
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
MAX
UNIT
VIN
85(3)
VOUT (adjustable version)
VOUT (fixed version)
VMID_OUT
VMID + 0.3(4)
5.5
VIN + 0.3(5)
Voltage(2)
VFB
5.5
20
20
20
20
V
VEN
VMVSEL1
VMVSEL2
VPG
Maximum output
Maximum MID output
Operating junction, TJ
Storage, Tstg
Internally limited
Internally limited
–50
Current
A
150
150
Temperature
°C
–65
(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions.
If briefly operating outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not
sustain damage, but it may not be fully functional – this may affect device reliability, functionality, performance, and shorten the device
lifetime.
(2) All voltages with respect to GND.
(3) Absolute maximum voltage, withstand 85 V for 200 ms.
(4) VMID_OUT + 0.3 V or 20 V (whichever is smaller).
(5) VIN + 0.3 V or 20 V (whichever is smaller).
6.2 ESD Ratings
VALUE
±2000
±750
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
V(ESD)
Electrostatic discharge
V
Charged device model (CDM), per JEDEC specification JESD22-C101(2)
(1) JEDEC document JEP155 states that 2-kV HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 500-V CDM allows safe manufacturing with a standard ESD control process.
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6.3 Recommended Operating Conditions
MIN
4
NOM
MAX
65
UNIT
V
VIN
Input voltage
VMID_OUT
MID output voltage
10
15
V
VMID_OUT
VDO(OUT)
–
VOUT
Output voltage (adjustable version)
1.24
V
VOUT
Output voltage (fixed version)
Output current
1.25
0
5.5
V
mA
mA
V
IOUT
50 – IMID_OUT
IMID_OUT
VMVSEL1
VMVSEL2
VEN
MID rail output current
MID voltage select input voltage 1
MID voltage select input voltage 2
Enable voltage
0
50
18
18
18
18
0
0
V
0
V
(1)
VPG
Power-good voltage
0
V
(2)
CIN
Input capacitor
0.1
2.2
μF
μF
μF
°C
(2)
COUT
Output capacitor
1
3 × COUT
–40
100
125
(2) (3)
CMID_OUT
TJ
MID output capacitor
Operating junction temperature
(1) Select pullup resistor to limit PG pin sink current when PG output is driven low. See the Power Good section for details.
(2) All capacitor values are assumed to derate to 50% of the nominal capacitor value.
(3) Maintain a 3:1 ratio between CMID_OUT vs COUT for stability.
6.4 Thermal Information
TPS7A44
THERMAL METRIC(1)
HVSSOP (DGQ)
UNIT
8 PINS
53.7
76.6
26.8
3.6
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
ΨJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
ΨJB
26.7
9.6
RθJC(bot)
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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6.5 Electrical Characteristics
specified at TJ = –40°C to +125°C, VIN = VOUT(nom) + 1.5V or 4V, whichever is greater, FB tied to OUT (adjustable version
only), IOUT = 1 mA, IMID_OUT = 0mA, VEN = 2 V, VMVSEL1 = 0.9 V, VMVSEL2 = 0.9 V, CIN = 1 μF, CMID_OUT = 4.7 μF, and COUT
1 μF (unless otherwise noted); typical values are at TJ = 25°C
=
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
1.25
0.5
UNIT
ΔVOUT
ΔVOUT
VFB
Adjustable version, VOUT = VFB
1.23
1.24
V
Output voltage
accuracy
Fixed output version, TJ = 25℃
Fixed output version
–0.5
%
V
–0.75
0.75
Feedback voltage
Line regulation(1)
Adjustable version only
1.24
(VOUT(nom) + 1 V or 4 V) ≤ VIN ≤ 65 V
VMID_OUT(nom) + 1.5 V ≤ VIN ≤ 65 V
–0.05
–0.05
0.05
0.05
ΔVOUT(ΔVIN)
%
1 mA ≤ IOUT ≤ 50 mA,
IMID_OUT = 0 mA
ΔVOUT(ΔIOUT)
Load regulation
–0.15
14.4
0.10
15.6
%
V
VMVSEL1 ≤ VMVSEL1(LOW)
VMVSEL2 ≤ VMVSEL2(LOW)
,
15
12
10
VMVSEL1 ≤ VMVSEL1(LOW)
or VMVSEL1
VMVSEL1(HIGH)
MID output voltage
accuracy
≥
ΔVMID_OUT
VIN = VMID_OUT + 1.5 V
11.5
12.5
,
VMVSEL2 ≥ VMVSEL2(HIGH)
VMVSEL1 ≥ VMVSEL1(HIGH)
VMVSEL2 ≤ VMVSEL2(LOW)
,
9.6
10.4
0.1
Line regulation of
MID output(1)
(VMID_OUT(nom)) + 1.5 V ≤ VIN ≤ 65 V,
IMID_OUT = 1 mA, IOUT = 0 mA
ΔVMID_OUT(ΔVIN)
–0.1
%
%
1 mA ≤ IMID_OUT ≤ 50 mA
VIN = VMID_OUT + 1.5 V
IOUT = 0 mA
ΔVMID_OUT(Δ
Load regulation of
MID output
–0.2
0.1
IOUT)
Dropout voltage of
VIN to VOUT
VDO(OUT)
VDO(OUT)
VDO(MID_OUT)
ICL(OUT)
IOUT = 50 mA
800
200
mV
mV
(2)
Dropout voltage of
IOUT = 50 mA
(2)
VMID_OUT to VOUT
Dropout voltage of
IMID_OUT = 50 mA
600
145
165
mV
mA
mA
(3)
VIN to VMID_OUT
Output current limit VOUT = 0.9 × VOUT(nom)
MID output current VOUT = 0.9 × VMID_OUT(nom)
100
118
125
145
5.5
,
ICL(MID_OUT)
limit
VIN = VMID_OUT + 1.5 V
TJ = 25°C
7
9
IOUT = IMID_OUT = 0 mA,
VIN = VMID_OUT + 1.5 V
TJ = –40°C to +125°C
IGND
Ground pin current
µA
IOUT = 50 mA,
VIN = VMID_OUT + 1.5 V
185
710
VEN ≤ VEN(LOW)
VIN = VMID_OUT(nom) + 1.5
V
,
TJ = –40°C to +85°C
TJ = –40°C to +125°C
1600
2100
nA
nA
ISHUTDOWN
Shutdown current
IOUT = IMID_OUT = 0 mA
VEN ≤ VEN(LOW)
VIN =65 V
IOUT = IMID_OUT = 0 mA
,
TJ = –40°C to +85°C
TJ = –40°C to +125°C
710
1900
2500
ISHUTDOWN
Shutdown current
FB pin current
nA
IFB
10
10
10
10
nA
nA
nA
nA
IMVSEL1
IMVSEL2
IEN
MVSEL1 pin current VMVSEL1 = 18 V
MVSEL2 pin current VMVSEL2 = 18 V
EN pin current
VEN = 18 V
MVSEL1 pin high-
level input voltage
VMVSEL1(HIGH)
VMVSEL1(LOW)
0.9
V
V
MVSEL1 pin low-
level input voltage
0.3
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6.5 Electrical Characteristics (continued)
specified at TJ = –40°C to +125°C, VIN = VOUT(nom) + 1.5V or 4V, whichever is greater, FB tied to OUT (adjustable version
only), IOUT = 1 mA, IMID_OUT = 0mA, VEN = 2 V, VMVSEL1 = 0.9 V, VMVSEL2 = 0.9 V, CIN = 1 μF, CMID_OUT = 4.7 μF, and COUT
1 μF (unless otherwise noted); typical values are at TJ = 25°C
=
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
MVSEL2 pin high-
level input voltage
VMVSEL2(HIGH)
VMVSEL2(LOW)
VEN(HI)
0.9
V
MVSEL2 pin low-
level input voltage
0.3
1.35
1.28
V
V
Enable rising
threshold
Device enabled
Device disabled
1.15
1.11
1.24
1.19
50
Enable falling
threshold
VEN(LOW)
V
Enable pin
hysteresis
VEN(HYST)
VIT(PG,RISING)
VHYS(PG)
mV
PG pin threshold
rising
RPULLUP = 10 kΩ, VOUT rising,
VIN ≥ VUVLO(RISING)
88
84
93
96.5
RPULLUP = 10 kΩ, VOUT falling,
VIN ≥ VUVLO(RISING)
PG pin hysteresis
3
%VOUT
PG pin threshold
falling
RPULLUP = 10 kΩ, VOUT falling,
VIN ≥ VUVLO(RISING)
VIT(PG,FALLING)
VOL(PG)
90
94.5
0.4
PG pin low level
output voltage
VOUT < VIT(PG,FALLING), IPG-SINK = 500 µA
V
PG pin leakage
current
ILKG(PG)
VOUT > VIT(PG,RISING), VPG = 18 V
f = 10 Hz
5
130
nA
76
67
82
73
61
64
55
47
Power-supply
rejection ratio of
OUT rail
f = 100 Hz
IOUT = 20 mA
PSRR(OUT)
f = 1 kHz
f = 100 kHz
f = 10 Hz
dB
Power-supply
PSRR(MID_OUT) rejection ratio of
MID_OUT rail
f = 100 Hz
IMID_OUT = 20 mA
f = 1 kHz
f = 100 kHz
Output noise
voltage
Vn
BW = 10 Hz to 100 kHz, VOUT = 1.24 V
124
170
μVRMS
°C
Thermal shutdown
TSD(shutdown)
Shutdown, temperature increasing
temperature
(1) Line regulation from Input of the LDO to the final output of the LDO.
(2) VDO is measured with VIN = 0.95 × VOUT(nom) for fixed output voltage versions. VDO is not measured for fixed output voltage versions
when VOUT ≤ 3.1 V. For the adjustable output device, VDO is measured with VFB = 0.95 × VFB(nom).
(3) VDO(MID_OUT) is measured with VIN = 0.95 × VMID_OUT(nom) for Mid output voltages.
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6.6 Typical Characteristics
at operating temperature TJ = 25°C, IOUT = 1 mA, IMID_OUT = 0 mA, VEN = 2 V, VMVSEL1 = 0.9 V, VMVSEL2 = 0.9 V, CIN = 1 μF,
CMID_OUT = 4.7 μF, COUT = 1 μF, and VIN = VMID_OUT + 1.5 V (unless otherwise noted); typical values are at TJ = 25°C
0.5
0.4
0.3
0.2
0.1
0
0.5
0.4
0.3
0.2
0.1
0
TJ
25èC
85èC
TJ
25èC
85èC
-40èC
0èC
125èC
-40èC
0èC
125èC
-0.1
-0.2
-0.3
-0.4
-0.5
-0.1
-0.2
-0.3
-0.4
-0.5
0
0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1
Output Current (A)
0
10
20
30 40
Input Voltage (V)
50
60 65
VOUT = 1.24 V (adjustable)
VOUT = 1.24 V (adjustable)
Figure 6-1. VOUT Accuracy vs IOUT
Figure 6-2. VOUT Accuracy vs VIN
1
2
1.75
1.5
1.25
1
TJ
25èC
85èC
TJ
0.8
0.6
0.4
0.2
0
-40èC
0èC
125èC
-40èC
0èC
25èC
85èC
125èC
-0.2
-0.4
-0.6
-0.8
-1
0.75
0.5
0.25
0
13
23
33 43
Input Voltage (V)
53
63
0
0.02 0.04 0.06 0.08 0.1
Output Current Limit (A)
0.12 0.14 0.16
VMID_OUT = 12 V
VOUT = 1.24 V (adjustable)
Figure 6-3. VMID_OUT Accuracy vs VIN
Figure 6-4. VOUT vs ICL(OUT)
1000
700
18
16
14
12
10
8
TJ
25èC
85èC
-40èC
0èC
125èC
500
300
200
TJ
-40èC
0èC
25èC
85èC
125èC
100
70
6
50
4
30
20
2
0
0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1
Output Current (A)
0
0
0.02 0.04 0.06 0.08
0.1
MID_OUT Current Limit (A)
0.12 0.14 0.16
VIN = 11 V, VOUT = 1.24 V (adjustable)
VMID_OUT = 12 V
Figure 6-6. IGND vs IOUT (MID_OUT in Dropout)
Figure 6-5. VMID_OUT vs ICL(MID_OUT)
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6.6 Typical Characteristics (continued)
at operating temperature TJ = 25°C, IOUT = 1 mA, IMID_OUT = 0 mA, VEN = 2 V, VMVSEL1 = 0.9 V, VMVSEL2 = 0.9 V, CIN = 1 μF,
CMID_OUT = 4.7 μF, COUT = 1 μF, and VIN = VMID_OUT + 1.5 V (unless otherwise noted); typical values are at TJ = 25°C
270
240
210
180
150
120
90
30
25
20
15
10
5
TJ
25èC
85èC
TJ
25èC
85èC
-40èC
0èC
125èC
-40èC
0èC
125èC
60
30
0
0
0
0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1
Output Current (A)
0
10
20
30 40
Input Voltage (V)
50
60 65
VIN = 16.5 V, VMID_OUT = 15 V, VMVSEL1 = VMVSEL2 = 0 V,
VOUT = 1.24 V (adjustable)
IOUT = 0 mA
Figure 6-7. IGND vs IOUT
Figure 6-8. IGND vs VIN
8
0.3
0.27
0.24
0.21
0.18
0.15
0.12
0.09
0.06
0.03
0
TJ
25èC
85èC
TJ
-40èC
0èC
125èC
-40èC
0èC
25èC
85èC
125èC
6
4
2
0
0
10
20
30 40
Input Voltage (V)
50
60 65
0
0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1
Output Current (A)
VEN = 1 V
VOUT = 1.24 V (adjustable)
Figure 6-9. ISHUTDOWN vs VIN
Figure 6-10. VDO(OUT) vs IOUT
85
210
1.2
1
VIN
VOUT
VMID_OUT
IIN
TJ
25èC
85èC
75
65
55
45
35
25
15
5
180
150
120
90
-40èC
0èC
125èC
0.8
0.6
0.4
0.2
0
60
30
0
-30
-5
-60
1.4
0
0.2
0.4
0.6
0.8
1
1.2
0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1
MID_Output Current (A)
Time (ms)
CIN = 0 μF, VIN ramp rate = 10 V/μs, VOUT = 3.3 V,
IOUT = 0 mA
VMID_OUT = 15 V, VMVSEL1 = VMVSEL2 = 0 V, IOUT = 0 mA
Figure 6-12. Fast Start-Up (Inrush Current)
Figure 6-11. VDO(MID_OUT) vs IMID_OUT
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6.6 Typical Characteristics (continued)
at operating temperature TJ = 25°C, IOUT = 1 mA, IMID_OUT = 0 mA, VEN = 2 V, VMVSEL1 = 0.9 V, VMVSEL2 = 0.9 V, CIN = 1 μF,
CMID_OUT = 4.7 μF, COUT = 1 μF, and VIN = VMID_OUT + 1.5 V (unless otherwise noted); typical values are at TJ = 25°C
75
65
55
45
35
25
15
5
5.6
4.8
4
300
200
100
0
100
90
80
70
60
50
40
30
20
10
0
VIN
VOUT
VMID_OUT
3.2
2.4
1.6
0.8
0
-100
-200
-300
-400
-500
-600
-700
VMID_OUT
VOUT
VIN
-5
-0.8
0
0.2 0.4 0.6 0.8
1 1.2 1.4 1.6 1.8
Time (ms)
2
0
200
400
Time (ms)
600
800
1,000
CIN = 0 μF, VIN ramp rate = 40 V/ms,VOUT = 3.3 V,
IOUT = 1 mA
VIN = 15 V to 65 V, VIN ramp rate = 10 V/μs, VOUT = 3.3 V,
IOUT = 50 mA
Figure 6-13. Slow Start-Up
Figure 6-14. Line Transient
80
70
60
50
40
30
20
10
0
100
0
80
70
60
50
40
30
20
10
0
5
0
-100
-5
-200
VIN
VMID_OUT
-10
-15
-20
-25
-30
-35
VIN
VOUT
-300
-400
-500
-600
-700
0
200
400
600
800
1,000
0
200
400
600
800
1,000
Time (ms)
Time (ms)
VIN = 15 V to 65 V, VIN ramp rate = 10 V/μs, VOUT = 3.3 V,
IOUT = 50 mA
VIN = 15 V to 65 V, VIN ramp rate = 10 V/μs, VOUT = 3.3 V,
IOUT = 50 mA
Figure 6-15. Line Transient
Figure 6-16. Line Transient
80
70
60
50
40
30
20
10
0
100
0
80
70
60
50
40
30
20
10
0
5
0
-100
-200
-300
-400
-500
-600
-700
-5
VIN
VMID_OUT
VIN
VOUT
-10
-15
-20
-25
-30
-35
0
100 200 300 400 500 600 700 800 900 1000
Time (ms)
0
100
200
300
Time (ms)
400
500
600
700
VIN = 15 V to 65 V, VIN ramp rate = 5 V/μs, VOUT = 3.3 V,
IOUT = 1 mA
VIN = 15 V to 65 V, VIN ramp rate = 5 V/μs, VOUT = 3.3 V,
IOUT = 50 mA
Figure 6-17. Line Transient
Figure 6-18. Line Transient
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6.6 Typical Characteristics (continued)
at operating temperature TJ = 25°C, IOUT = 1 mA, IMID_OUT = 0 mA, VEN = 2 V, VMVSEL1 = 0.9 V, VMVSEL2 = 0.9 V, CIN = 1 μF,
CMID_OUT = 4.7 μF, COUT = 1 μF, and VIN = VMID_OUT + 1.5 V (unless otherwise noted); typical values are at TJ = 25°C
80
70
60
50
40
30
20
10
0
100
0
80
70
60
50
40
30
20
10
0
5
0
-100
-200
-300
-400
-500
-600
-700
-5
VIN
VMID_OUT
-10
-15
-20
-25
-30
-35
VIN
VOUT
0
200 400 600 800 1000 1200 1400 1600 1800
Time (ms)
0
200 400 600 800 1000 1200 1400 1600 1800
Time (ms)
VIN = 15 V to 65 V, VIN ramp rate = 5 V/μs, VOUT = 3.3 V,
IOUT = 1 mA
VIN = 15 V to 65 V, VIN ramp rate = 5 V/μs, VOUT = 3.3 V,
IOUT = 1 mA
Figure 6-19. Line Transient
Figure 6-20. Line Transient
80
70
60
50
40
30
20
10
0
100
0
80
70
60
50
40
30
20
10
0
5
0
-100
-200
-300
-400
-500
-600
-700
-5
VIN
VMID_OUT
VIN
VOUT
-10
-15
-20
-25
-30
-35
0
200 400 600 800 1000 1200 1400 1600 1800
Time (ms)
0
200 400 600 800 1000 1200 1400 1600 1800
Time (ms)
VIN = 15 V to 65 V, VIN ramp rate = 10 V/μs, VOUT = 3.3 V,
IOUT = 1 mA
VIN = 15 V to 65 V, VIN ramp rate = 10 V/μs, VOUT = 3.3 V,
IOUT = 1 mA
Figure 6-21. Line Transient
Figure 6-22. Line Transient
95
85
75
65
55
45
35
25
15
5
50
95
85
75
65
55
45
35
25
15
5
400
0
200
-50
0
-100
-150
-200
-250
-300
-350
-400
-450
-200
-400
-600
-800
-1,000
-1,200
-1,400
-1,600
VIN
VMID_OUT
VOUT
VIN
VMID_OUT
VOUT
-5
-5
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
Time (ms)
1
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
Time (ms)
1
VIN = 4 V to 65 V, VIN ramp rate = 1 V/μs, VOUT = 3.3 V,
IOUT = 1 mA
VIN = 4 V to 65 V, VIN ramp rate = 5 V/μs, VOUT = 3.3 V,
IOUT = 1 mA
Figure 6-23. Line Transient (VMID_OUT in Dropout)
Figure 6-24. Line Transient (VMID_OUT in Dropout)
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6.6 Typical Characteristics (continued)
at operating temperature TJ = 25°C, IOUT = 1 mA, IMID_OUT = 0 mA, VEN = 2 V, VMVSEL1 = 0.9 V, VMVSEL2 = 0.9 V, CIN = 1 μF,
CMID_OUT = 4.7 μF, COUT = 1 μF, and VIN = VMID_OUT + 1.5 V (unless otherwise noted); typical values are at TJ = 25°C
95
85
75
65
55
45
35
25
15
5
4
95
85
75
65
55
45
35
25
15
5
4
3
3
2
2
1
1
0
0
VIN
VMID_OUT
VOUT
VIN
VMID_OUT
VOUT
-1
-2
-3
-4
-5
-6
-1
-2
-3
-4
-5
-6
-5
-5
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
Time (ms)
1
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
Time (ms)
1
VIN = 4 V to 65 V, VIN ramp rate = 1 V/μs, VOUT = 3.3 V,
IOUT = 50 mA
VIN = 4 V to 65 V, VIN ramp rate = 5 V/μs, VOUT = 3.3 V,
IOUT = 50 mA
Figure 6-25. Line Transient (VMID_OUT in Dropout)
Figure 6-26. Line Transient (VMID_OUT in Dropout)
350
300
250
200
150
100
50
500
450
400
350
300
250
200
150
100
50
250
200
150
100
50
400
350
300
250
200
150
100
50
VOUT
VMID_OUT
IOUT
VOUT
VMID_OUT
IOUT
0
0
-50
-50
-100
-150
-200
-100
-150
-200
0
0
-50
-50
0
500 1000 1500 2000 2500 3000 3500 4000
Time (ms)
0
10
20
30
40
50
Time (ms)
60
70
80
90 100
VIN = 65 V, VOUT = 3.3 V, IOUT = 0 mA to 50 mA to 0 mA,
IOUT slew rate = 1 A/μs
VIN = 65 V, VOUT = 3.3 V, IOUT = 0 mA to 50 mA to 0 mA,
IOUT slew rate = 1 A/μs
Figure 6-27. Load Transient
Figure 6-28. Load Transient (Rising Edge)
350
300
250
200
150
100
50
500
450
400
350
300
250
200
150
100
50
250
200
150
100
50
400
350
300
250
200
150
100
50
VOUT
VMID_OUT
IOUT
VOUT
VMID_OUT
IOUT
0
0
-50
-50
-100
-150
-200
-100
-150
-200
0
0
-50
-50
0
500 1000 1500 2000 2500 3000 3500 4000
Time (ms)
0
10
20
30
40
50
Time (ms)
60
70
80
90 100
VIN = 65 V, VOUT = 3.3 V, IOUT = 1 mA to 50 mA to 1 mA,
IOUT slew rate = 1 A/μs
VIN = 65 V, VOUT = 3.3 V, IOUT = 1 mA to 50 mA to 1 mA,
IOUT slew rate = 1 A/μs
Figure 6-29. Load Transient
Figure 6-30. Load Transient (Rising Edge)
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6.6 Typical Characteristics (continued)
at operating temperature TJ = 25°C, IOUT = 1 mA, IMID_OUT = 0 mA, VEN = 2 V, VMVSEL1 = 0.9 V, VMVSEL2 = 0.9 V, CIN = 1 μF,
CMID_OUT = 4.7 μF, COUT = 1 μF, and VIN = VMID_OUT + 1.5 V (unless otherwise noted); typical values are at TJ = 25°C
100
250
200
150
100
50
5
250
200
150
100
50
VMID_OUT
IMID_OUT
50
0
0
-5
VOUT
IMID_OUT
-50
-100
-150
-200
-10
-15
-20
-25
0
0
-50
-50
0
1000 2000 3000 4000 5000 6000 7000 8000
Time (ms)
0
1000 2000 3000 4000 5000 6000 7000 8000
Time (ms)
VIN = 65 V, VMID_OUT = 12 V, IMID_OUT = 0 mA to 50 mA to
0 mA, IMID_OUT slew rate = 1 A/μs, IOUT = 0 mA
VIN = 65 V, VOUT = 3.3 V, IMID_OUT = 0 mA to 50 mA to 0 mA,
IMID_OUT slew rate = 1 A/μs, IOUT = 0 mA
Figure 6-31. Load Transient (MID_OUT)
Figure 6-32. Load Transient (MID_OUT)
100
50
250
200
150
100
50
5
0
250
200
150
100
50
VMID_OUT
IMID_OUT
0
-5
VOUT
IMID_OUT
-50
-100
-150
-200
-10
-15
-20
-25
0
0
-50
-50
0
1000 2000 3000 4000 5000 6000 7000 8000
Time (ms)
0
1000 2000 3000 4000 5000 6000 7000 8000
Time (ms)
VIN = 65 V, VMID_OUT = 12 V, IMID_OUT = 1 mA to 50 mA to
1 mA, IMID_OUT slew rate = 1 A/μs, IOUT = 0 mA
VIN = 65 V, VOUT = 3.3 V, IMID_OUT = 1 mA to 50 mA to 1 mA,
IMID_OUT slew rate = 1 A/μs, IOUT = 0 mA
Figure 6-33. Load Transient (MID_OUT)
Figure 6-34. Load Transient (MID_OUT)
200
100
IOUT = 0.1 mA, Vn = 235 mVRMS
IOUT = 1.0 mA, Vn = 320 mVRMS
IOUT = 20 mA, Vn = 385 mVRMS
IOUT = 50 mA, Vn = 398 mVRMS
COUT = 1.0 mF, Vn = 385 mVRMS
COUT = 100 mF, Vn = 317 mVRMS
100
50
50
20
20
10
5
10
5
2
1
2
1
0.5
0.5
0.2
0.1
0.2
0.1
0.05
0.05
0.02
0.01
0.02
0.01
0.005
0.005
10
100
1k
10k 100k
Frequency (Hz)
1M
10M
10
100
1k
10k 100k
Frequency (Hz)
1M
10M
VIN = 13 V, VOUT = 3.3 V, VRMS bandwidth = 10 Hz to 100 kHz
VIN = 13 V, VOUT = 3.3 V, IOUT = 20 mA,
VRMS bandwidth = 10 Hz to 100 kHz
Figure 6-35. Spectral Noise Density vs Frequency and IOUT
Figure 6-36. Spectral Noise Density vs Frequency and COUT
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6.6 Typical Characteristics (continued)
at operating temperature TJ = 25°C, IOUT = 1 mA, IMID_OUT = 0 mA, VEN = 2 V, VMVSEL1 = 0.9 V, VMVSEL2 = 0.9 V, CIN = 1 μF,
CMID_OUT = 4.7 μF, COUT = 1 μF, and VIN = VMID_OUT + 1.5 V (unless otherwise noted); typical values are at TJ = 25°C
120
100
80
60
40
20
0
120
100
80
60
40
20
0
IOUT = 1 mA
IOUT = 20 mA
IOUT = 50 mA
VIN - VMID_OUT = 1 V
VIN - VMID_OUT = 3 V
VIN - VMID_OUT = 6 V
10
100
1k
10k
Frequency (Hz)
100k
1M
10M
10M
10M
10
100
1k
10k
Frequency (Hz)
100k
1M
10M
VIN = 13 V, CIN = 0 μF, VOUT = 3.3 V
CIN = 0 μF,VOUT = 3.3 V, IOUT = 20 mA
Figure 6-37. OUT PSRR vs Frequency and IOUT
Figure 6-38. OUT PSRR vs Frequency and VIN
120
100
80
60
40
20
0
100
80
60
40
20
0
COUT = 1 mF
COUT = 100 mF
IMID_OUT = 1 mA
IMID_OUT = 20 mA
IMID_OUT = 50 mA
10
100
1k
10k
Frequency (Hz)
100k
1M
10
100
1k
10k
Frequency (Hz)
100k
1M
10M
VIN = 13 V, CIN = 0 μF, VOUT = 3.3 V, IOUT = 20 mA
Figure 6-39. OUT PSRR vs Frequency and COUT
100
VIN = 13 V, CIN = 0 μF, VOUT = 3.3 V, IOUT = 0 mA
Figure 6-40. MID_OUT PSRR vs Frequency and IMID_OUT
120
VIN - VMID_OUT = 1 V
VIN - VMID_OUT = 3 V
VIN - VMID_OUT = 6 V
CMID_OUT = 3.3 mF
CMID_OUT = 300 mF
100
80
60
40
20
0
80
60
40
20
0
10
100
1k
10k
Frequency (Hz)
100k
1M
10
100
1k
10k
Frequency (Hz)
100k
1M
10M
CIN = 0 μF, VOUT = 3.3 V, IMID_OUT = 20 mA, IOUT = 0 mA
VIN = 13 V, CIN = 0 μF, VOUT = 3.3 V, IMID_OUT = 20 mA,
IOUT = 0 mA
Figure 6-41. MID_OUT PSRR vs Frequency and VIN
Figure 6-42. MID_OUT PSRR vs Frequency and CMID_OUT
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7 Detailed Description
7.1 Overview
The TPS7A44 is a 65-V, low quiescent current, low-dropout (LDO) linear regulator. The very low IQ performance
makes the device an excellent choice for battery-powered or line-power applications that are expected to meet
increasingly stringent standby-power standards.
The high accuracy over temperature and power-good indication make this device an excellent choice for meeting
a broad range of microcontroller power requirements. The device features a selectable MID_OUT voltage pin to
provide a secondary voltage to serve as a bias rail for gate drivers.
For increased robustness, the TPS7A44 also incorporates precision enable, output current limit, active
discharge, and thermal shutdown protection. The operating junction temperature for this device is –40°C to
+125°C.
7.2 Functional Block Diagrams
OUT
IN
Current
limit
Current
limit
1.24-V
band gap
Band gap
MVSEL1
FB
Internal
controller
MVSEL2
PG
Thermal
shutdown
œ
0.9 x 1.24-V Band Gap
+
+
EN
œ
GND
MID_OUT
Band gap
GND
Figure 7-1. Adjustable Version
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OUT
IN
Current
limit
Current
limit
1.24-V
band gap
Band gap
MVSEL1
MVSEL2
NC
PG
550 kΩ
Internal
controller
GND
Thermal
Shutdown
œ
0.9 x 1.24-V Band Gap
+
+
EN
œ
GND
MID_OUT
Band Gap
GND
Figure 7-2. Fixed Version
7.3 Feature Description
7.3.1 MID_OUT Voltage Selection
The TPS7A44 features a MID_OUT voltage pin that provides a secondary output voltage supply in addition to
the OUT pin, which is the main output voltage supply. The MID_OUT voltage can be set using the MVSEL1 and
MVSEL2 pins; see the MID_OUT Voltage Setting section for more details.
7.3.2 Precision Enable
The TPS7A44 features a precision enable circuit. The enable pin (EN) is active high; thus, enable the device
by forcing the voltage of the enable pin to exceed the VEN(HI) voltage; see the Electrical Characteristics table.
Turn off the device by forcing the voltage of the enable pin to drop below the VEN(LOW) voltage; see the Electrical
Characteristics table. This device has an internal pullup resistor to the IN pin that enables the device when the
EN pin is left floating.
If this pin is tied to the IN pin, the input voltage must not exceed 18 V; see the Recommended Operating
Conditions table.
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As shown in Figure 7-3, an external resistor divider circuit can be used to enable the device using the input
voltage.
IN
Internal
controller
R1
+
EN
œ
R2
Band gap
GND
Figure 7-3. Enable the Device Using the Input Voltage
The VEN(HI) (maximum) and VEN(LOW) (minimum) thresholds along with the application input voltage can be used
to set the R1 to R2 resistor divider ratio. The values of the R2 and R1 resistors can also be optimized to minimize
the leakage current through the divider.
7.3.3 Dropout Voltage
Dropout voltage (VDO) is defined as the input voltage minus the output voltage (VIN – VOUT) at the rated output
current (IRATED), where the pass transistor is fully on. IRATED is the maximum IOUT listed in the Recommended
Operating Conditions table. The pass transistor is in the ohmic or triode region of operation, and acts as a
switch. The dropout voltage indirectly specifies a minimum input voltage greater than the nominal programmed
output voltage at which the output voltage is expected to stay in regulation. If the input voltage falls to less than
the nominal output regulation, then the output voltage falls as well.
For a CMOS regulator, the dropout voltage is determined by the drain-source on-state resistance (RDS(ON)) of the
pass transistor. Therefore, if the linear regulator operates at less than the rated current, the dropout voltage for
that current scales accordingly. The following equation calculates the RDS(ON) of the device.
VDO
RDS(ON)
=
IRATED
(1)
7.3.4 Current Limit
The device has internal current limit circuits for both MID_OUT and OUT rails. These circuits protect the
regulator during high-current load transient faults or shorting events on either rails. Both current limit circuits
are brick-wall schemes with ICL(MID_OUT) being higher than ICL(OUT); see the Electrical Characteristics table. In
a high-current load transient fault, the brick-wall scheme limits the output current to the respective current limit
(ICL(MID_OUT) or ICL(OUT)), both of which are listed in the Electrical Characteristics table.
When the device is in either current limit, the output voltages are not regulated. When a current limit event
occurs, the device begins to heat up because of the increase in power dissipation. When the device is in either
current limit, the corresponding pass transistor dissipates power. For instance, when the OUT rail is in current
limit, the power dissipation can be calculated as [(VIN – VOUT) × ICL(OUT)]. If thermal shutdown is triggered, the
device turns off. After the device cools down, the internal thermal shutdown circuit turns the device back on. If
the faulty output current condition continues, the device cycles between current limit and thermal shutdown with
approximately a 5-ms time constant. For more information on current limits, see the Know Your Limits application
report.
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Figure 7-4 shows a diagram of the current limit.
VOUT
Brick Wall
VOUT(NOM)
0 V
IOUT
IRATED
0 mA
ICL
Figure 7-4. Current Limit: Brick-Wall Scheme
7.3.5 Thermal Shutdown
The device contains a thermal shutdown protection circuit to disable the device when the junction temperature
(TJ) of the pass transistor rises to TSD(shutdown) (typical). Thermal shutdown hysteresis assures that the device
resets (turns on) when the temperature falls to TSD(reset) (typical).
The thermal time-constant of the semiconductor die is fairly short, thus the device may cycle on and off
when thermal shutdown is reached until power dissipation is reduced. Power dissipation during start up can
be high from large VIN – VOUT voltage drops across the device or from high inrush currents charging large
output capacitors. Under some conditions, the thermal shutdown protection disables the device before start up
completes.
When the thermal limit is triggered with the load current near the value of the current limit, the output may
oscillate prior to the output switching off.
For reliable operation, limit the junction temperature to the maximum listed in the Recommended Operating
Conditions table. Operation above this maximum temperature causes the device to exceed its operational
specifications. Although the internal protection circuitry of the device is designed to protect against thermal
overall conditions, this circuitry is not intended to replace proper heat sinking. Continuously running the device
into thermal shutdown or above the maximum recommended junction temperature reduces long-term reliability.
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7.3.6 Power Good
The power-good (PG) pin is an open-drain output and can be connected to a regulated supply through an
external pullup resistor. The maximum pullup voltage is listed as VPG in the Recommended Operating Conditions
table. For the PG pin to have a valid output, the voltage on the IN pin must be greater than 4 V. When VOUT
exceeds VIT(PG,RISING), the PG output is high impedance and the PG pin voltage pulls up to the connected
regulated supply. When the regulated output falls below VIT(PG,FALLING), the open-drain output turns on and pulls
the PG output low after a short deglitch time. If output voltage monitoring is not needed, the PG pin can be left
floating or connected to ground.
The recommended maximum PG pin sink current (IPG-SINK) and the leakage current into the PG pin (ILKG(PG)) are
listed in the Electrical Characteristics table.
The PG pullup voltage (VPG_PULLUP), the desired minimum power-good output voltage (VPG(MIN)), and ILKG(PG)
limit the maximum PG pin pullup resistor value (RPG_PULLUP). VPG_PULLUP, the PG pin low-level output voltage
(VOL(PG)), and IPG-SINK limit the minimum RPG_PULLUP. Maximum and minimum values for RPG_PULLUP can be
calculated from the following equations:
RPG_PULLUP(MAX) = (VPG_PULLUP – VPG(MIN)) / ILKG(PG)_MAX
RPG_PULLUP(MIN) = (VPG_PULLUP – VOL(PG)) / IPG-SINK
(2)
(3)
For example, if the PG pin is connected to a pullup resistor with a 3.3-V external supply, from the Electrical
Characteristics table, RPG_PULLUP(MAX) is 25 MΩ. From the Electrical Characteristics table, RPG_PULLUP(MIN) is 6.6
kΩ.
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7.4 Device Functional Modes
7.4.1 Device Functional Mode Comparison
Table 7-1 shows the conditions that lead to the different modes of operation. See the Electrical Characteristics
table for parameter values.
Table 7-1. Device Functional Mode Comparison
PARAMETER
IMID_OUT
IMID_OUT
IMID_OUT(max)
IMID_OUT
IMID_OUT(max)
IMID_OUT
IMID_OUT(max)
OPERATING
MODE
VIN
VEN
IOUT
TJ
VIN > VOUT(nom) + VDO and VIN
VIN(min)
>
<
Normal operation
VEN > VEN(HI)
IOUT < IOUT(max) TJ < TSD(shutdown)
Dropout operation
on MID_OUT
VIN(min) < VIN < VMID_OUT(nom)
VDO(MID_OUT)
+
<
VEN > VEN(HI)
VEN > VEN(HI)
IOUT < IOUT(max) TJ < TSD(shutdown)
IOUT < IOUT(max) TJ < TSD(shutdown)
Dropout operation
on OUT
VIN(min) < VIN < VOUT(nom) + VDO(OUT)
<
Disabled
(any true condition
disables the
device)
VIN < 4 V
VEN < VEN(LOW) Not applicable
Not applicable
TJ > TSD(reset)
7.4.2 Normal Operation
The device regulates to the nominal output voltages when the following conditions are met:
•
•
The input voltage is greater than the nominal output voltage plus the dropout voltage on either rails
(VMID_OUT(nom) + VDO(MID_OUT) and VOUT(nom) +VDO(OUT)
The current sourced from either MID_OUT and OUT is less than the respective current limit specified in the
)
Electrical Characteristics table for each rail
•
•
The device junction temperature is less than the thermal shutdown temperature (TJ < TSD(shutdown))
The enable voltage has previously exceeded the VEN(HI) (maximum) threshold and has not yet decreased to
less than the VEN(LOW) minimum threshold or VIN had exceeded 4 V if the EN pin is left floating
7.4.3 Dropout Operation
Because the TPS7A44 has two output rails (MID_OUT and OUT), the device can be in either VDO(MID_OUT) or
VDO(OUT), or in both depending on the input voltage level while all other conditions are met for normal operation.
When the input voltage drops to lower than VMID_OUT(nom) + VDO(MID_OUT), the device is in VDO(MID_OUT) dropout.
During this rail dropout, VMID_OUT tracks VIN and the transient performance of VMID_OUT becomes significantly
degraded because the pass transistor is in the ohmic or triode region, and acts as a switch. The MID_OUT
rail line or load transients in the VDO(MID_OUT) dropout can result in large VMID_OUT deviations. When the device
is still in VDO(MID_OUT) and when VIN is higher than VOUT(nom) + VDO(OUT), VOUT is in regulation and is not in
VDO(OUT) dropout. When VIN drops below VOUT(nom) + VDO(OUT), VOUT is no longer in regulation and its transient
performance becomes significantly degraded.
When the device is in a steady dropout state (when the device is in both VDO(MID_OUT) and VDO(OUT) dropout,
directly after being in a normal regulation state, but not during start up), the pass transistor is driven into the
ohmic or triode region. When the input voltage returns to a value greater than or equal to VMID_OUT(nom)
+
VDO(MID_OUT) and greater than VOUT(NOM) + VDO, the output voltage (OUT) can overshoot for a short period of
time while the device pulls the pass transistor back into the linear region.
7.4.4 Disabled
The outputs of the device can be shutdown by forcing the voltage of the enable pin to less than VEN(LOW)
(minimum); see the Electrical Characteristics table. When disabled, the pass transistor is turned off and internal
circuits are shutdown.
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8 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
8.1 Application Information
8.1.1 MID_OUT Voltage Setting
The MID_OUT voltage has three different output voltage levels (10 V, 12 V, and 15 V), as listed in Table 8-1,
depending on the MVSEL1 and MVSEL2 pin voltage settings.
Table 8-1. MID_OUT Voltage Setting
SET VMVSEL1
SET VMVSEL2
MID_OUT
15 V
VMVSEL1 ≤ VMVSEL1(LOW)
VMVSEL1 ≤ VMVSEL1(LOW)
VMVSEL1 ≥ VMVSEL1(HIGH)
VMVSEL1 ≥ VMVSEL1(HIGH)
VMVSEL2 ≤ VMVSEL2(LOW)
VMVSEL2 ≥ VMVSEL2(HIGH)
VMVSEL2 ≤ VMVSEL2(LOW)
VMVSEL2 ≥ VMVSEL2(HIGH)
12 V
10 V
12 V
For adjustable voltage options of the TPS7A44, and to maintain voltage regulation on the MID_OUT and OUT
pins, the input voltage must be kept ≥ MID_OUT + VDO(MID_OUT). Additionally, to maintain regulation on the OUT
pin, the MID_OUT voltage must be set ≥ VOUT(nom) + VDO(OUT)
.
Set the MVSEL1 and MVSEL2 voltages before enabling the device to set the MID_OUT voltage level; however,
the MID_OUT voltage setting can be changed to a different level after the device had powered up. Do not allow
these pins to float, instead tie them both to GND if not used to set VMID_OUT. When the device is powered while
either of these pins are floating, the MID_OUT voltage is not set properly and might switch levels and cause
damage to the device.
8.1.2 Adjustable Device Feedback Resistors
The adjustable-version device requires external feedback divider resistors to set the output voltage. VOUT is set
using the feedback divider resistors, R1 and R2, according to the following equation:
VOUT = VFB × (1 + R1 / R2)
(4)
To ignore the FB pin current error term in the VOUT equation, set the feedback divider current to 100x the FB pin
current listed in the Electrical Characteristics table. This setting provides the maximum feedback divider series
resistance, as shown in the following equation:
R1 + R2 ≤ VOUT / (IFB × 100)
(5)
8.1.3 Recommended Capacitor Types
The device is designed to be stable using low equivalent series resistance (ESR) capacitors at the input and
output. Multilayer ceramic capacitors have become the industry standard for these types of applications and
are recommended, but must be used with good judgment. Ceramic capacitors that employ X7R-, X5R-, and
C0G-rated dielectric materials provide relatively good capacitive stability across temperature, whereas the use of
Y5V-rated capacitors is discouraged because of large variations in capacitance.
Regardless of the ceramic capacitor type selected, the effective capacitance varies with operating voltage and
temperature. As a rule of thumb, expect the effective capacitance to decrease by as much as 50%. The input
and output capacitors recommended in the Recommended Operating Conditions table account for an effective
capacitance of approximately 50% of the nominal value.
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8.1.4 Input and Output Capacitor Requirements
An input capacitor is not required for stability except when the device maximum current is sourced from the
MID_OUT pin. However, adding an input capacitor is always good analog design practice to counteract reactive
input sources and improve transient response, input ripple, and PSRR. Starting with the nominal input capacitor
value is required if large, fast transient load or line transients are anticipated on the MID_OUT pin or if the device
is located several inches from the input power source.
A minimum of a 3:1 capacitor ratio between CMID_OUT and COUT is required for proper operation of the TPS7A44
LDO and a 4.7-μF capacitor can be connected from the MID_OUT pin to GND.
A minimum 1-μF output capacitor is required for VOUT stability. A maximum 100-μF output capacitor can be used
as long as the 3:1 ratio between CMID_OUT and COUT is maintained.
8.1.5 Power Dissipation (PD)
Circuit reliability requires consideration of the device power dissipation, location of the circuit on the printed
circuit board (PCB), and correct sizing of the thermal plane. The PCB area around the regulator must have few
or no other heat-generating devices that cause added thermal stress.
To first-order approximation, power dissipation in the regulator depends on the input-to-output voltage difference
and load conditions. The following equation calculates power dissipation (PD).
PD = (VIN – VOUT) × IOUT
(6)
Note
Power dissipation can be minimized, and therefore greater efficiency can be achieved, by correct
selection of the system voltage rails. For the lowest power dissipation use the minimum input voltage
required for correct output regulation.
For devices with a thermal pad, the primary heat conduction path for the device package is through the thermal
pad to the PCB. Solder the thermal pad to a copper pad area under the device. This pad area must contain an
array of plated vias that conduct heat to additional copper planes for increased heat dissipation.
The maximum power dissipation determines the maximum allowable ambient temperature (TA) for the device.
According to the following equation, power dissipation and junction temperature are most often related by the
junction-to-ambient thermal resistance (RθJA) of the combined PCB and device package and the temperature of
the ambient air (TA).
TJ = TA + (RθJA × PD)
(7)
Thermal resistance (RθJA) is highly dependent on the heat-spreading capability built into the particular PCB
design, and therefore varies according to the total copper area, copper weight, and location of the planes.
The junction-to-ambient thermal resistance listed in the Thermal Information table is determined by the JEDEC
standard PCB and copper-spreading area, and is used as a relative measure of package thermal performance.
8.1.6 Estimating Junction Temperature
The JEDEC standard now recommends the use of psi (Ψ) thermal metrics to estimate the junction temperatures
of the linear regulator when in-circuit on a typical PCB board application. These metrics are not thermal
resistance parameters and instead offer a practical and relative way to estimate junction temperature. These
psi metrics are determined to be significantly independent of the copper area available for heat-spreading.
The Thermal Information table lists the primary thermal metrics, which are the junction-to-top characterization
parameter (ψJT) and junction-to-board characterization parameter (ψJB). These parameters provide two methods
for calculating the junction temperature (TJ), as described in Equation 8 and Equation 9. Use the junction-to-top
characterization parameter (ψJT) with the temperature at the center-top of device package (TT) to calculate
the junction temperature. Use the junction-to-board characterization parameter (ψJB) with the PCB surface
temperature 1 mm from the device package (TB) to calculate the junction temperature.
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TJ = TT + ψJT × PD
(8)
where:
•
•
PD is the dissipated power
TT is the temperature at the center-top of the device package
TJ = TB + ψJB × PD
(9)
where:
•
TB is the PCB surface temperature measured 1 mm from the device package and centered on the package
edge
For detailed information on the thermal metrics and how to use them, see the Semiconductor and IC Package
Thermal Metrics application report.
8.2 Typical Application
This section discusses the implementation of the TPS7A44 in a cordless power tools application. Figure 8-1
shows a typical circuit diagram for this application.
VIN
R1
VOUT
COUT
IN
OUT
VCC
VSS
CIN
GND
GND
MCU
NC
EN
GND
GND
GND
R2
TPS7A4433
VMID_OUT
MID_OUT
MVSEL1
MVSEL2
CMOID_OUT
VIN
GND
Gate
Driver
R3
PG
R4
GND
GND
Figure 8-1. Powering Cordless Power Tools
8.2.1 Design Requirements
Table 8-2 summarizes the design requirements for Figure 8-1.
Table 8-2. Design Parameters
PARAMETER
DESIGN VALUES
VIN
15 V (min), 65 V (transient max)
3.3 V ± 2 %
0 V
VOUT
VMVSEL1
VMVSEL2
≥ 0.9 V
VMID_OUT
12 V ± 5 %
I(IN) (no load)
IOUT (typical), (max)
IMID_OUT (typical), (max)
TA
< 9 μA
20 mA, 50 mA
0 mA , 1 mA
60 °C (max)
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8.2.2 Detailed Design Procedure
A fixed 3.3-V output voltage device is used for this application. The MID_OUT voltage is set to 12 V by tying the
VMVSEL1 pin to GND and setting VMVSEL2 to ≥ 0.9 V using the R3 and R4 resistor divider. The value of the R3 and
R4 divider ratio must ensure that VMVSEL2 is set to ≥ 0.9 V when VIN ≥ 15 V. To limit the current burned through
this divider to 5 μA, R3 can be calculated using Equation 10, and the calculated value then can be rounded to
the nearest standard value. When VIN goes all the way up to 65 V during a transient, the VMSEL2 voltage goes
up to 3.9 V (which is still lower than maximum recommended value for this pin as specified in the Recommended
Operating Conditions table).
R3 = (15 V – 0.9 V) / 5 μA = 2.82 MΩ
(10)
R4 then can be calculated with Equation 11 by using the VMVSEL2 value of the same current value.
R3 = 0.9 V / 5 μA = 180 kΩ
(11)
The enable precision circuit is also used to turn off the device when VIN drops below 15 V. The R1 and R2
resistor divider is used to set VEN to lower than VEN(LOW) of 1.15 V when VIN drops below 15 V. R1 can be
calculated using Equation 12 to limit the burned current through this divider to 5 μA, similar to the above divider.
R1 = (15 V – 1.15 V) / 5 μA = 2.77 MΩ
(12)
Equation 13 can then be used to calculate R2. The calculated R1 and R2 values can then rounded to the
nearest standard values.
R2 = 1.15 V / 5 μA = 230 kΩ
(13)
8.2.3 Application Curves
80
70
60
50
40
30
20
10
0
100
0
80
70
60
50
40
30
20
10
0
5
0
-100
-200
-300
-400
-500
-600
-700
-5
-10
-15
-20
-25
-30
-35
VIN
VMID_OUT
VIN
VOUT
0
200
400
600
800
1,000
0
200
400
600
800
1,000
Time (ms)
Time (ms)
VIN = 15 V to 65 V, VIN ramp rate = 10 V/μs, VMVSEL1 = 0 V,
VMVSEL2 = 0.9 V, IOUT = 50 mA, IMID_OUT = open
VIN = 15 V to 65 V, VIN ramp rate = 10 V/μs, VMVSEL1 = 0 V,
VMVSEL2 = 0.9 V, IOUT = 50 mA, IMID_OUT = open
Figure 8-2. TPS7A43 Line Transient: 15 V to 65 V
Figure 8-3. TPS7A43 Line Transient: 15 V to 65 V
(Zoom on VOUT
)
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9 Power Supply Recommendations
The device is designed to operate from an input supply voltage range of 4 V to 65 V. To ensure that the
output voltages are well regulated and dynamic performance is optimum, the input supply must be at least
VMID_OUT(nom) + 1.5 V. Connect a low output impedance power supply directly to the input pin of the TPS7A44.
10 Layout
10.1 Layout Guidelines
•
•
•
•
Place input and output capacitors as close to the device pins as possible.
Use copper planes for device connections to optimize thermal performance.
Place thermal vias around the device and under the thermal pad to distribute heat.
Only place tented thermal vias directly beneath the thermal pad of the DGQ package. An untented via
can wick solder or solder paste away from the thermal pad joint during the soldering process, leading to a
compromised solder joint on the thermal pad.
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10.2 Layout Examples
CIN
COUT
OUT
IN
GND Plane
OUT
FB
1
2
3
4
10
9
IN
R1
NC
8
PG
MID_OUT
MVSEL2
EN
Thermal Pad
R2
R2
CMID_
OUT
R PG
MVSEL1
GND
7
PG
5
6
GND Plane
Routing Via
Thermal Via
Figure 10-1. Adjustable Version Layout Example
CIN
COUT
OUT
IN
GND Plane
OUT
NC
1
2
3
4
10
9
IN
NC
R PG
8
PG
MID_OUT
MVSEL2
EN
Thermal Pad
CMID_
OUT
MVSEL1
GND
7
5
6
GND Plane
Routing Via
Thermal Via
Figure 10-2. Fixed Version Layout Example
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Development Support
11.1.1.1 Evaluation Modules
An evaluation module (EVM) for a similar P2P device, the TPS7A43, is available to assist in the initial
circuit performance evaluation for the TPS7A44. The TPS7A43EVM-047 Evaluation Module user guide can
be requested at the Texas Instruments website through the product folders or purchased directly from the TI
Store.
11.1.1.2 Spice Models
SPICE models for the TPS7A44 are available through the product folder under Tools & software.
11.1.2 Device Nomenclature
Table 11-1. Device Nomenclature(1)
PRODUCT
VOUT
xx(x) is the nominal output voltage. For output voltages with a resolution of 100 mV, two
digits are used in the ordering number; for output voltages with a resolution of 50 mV, three
digits are used (for example, 28 = 2.8 V; 125 = 1.25 V). 01 indicates adjustable output
version.
TPS7A44xx(x) yyy z
yyy is the package designator.
z is the package quantity. R is for large quantity reel, T is for small quantity reel.
(1) For the most current package and ordering information see the Package Option Addendum at the end of this document, or visit the
device product folder at www.ti.com.
11.2 Documentation Support
11.2.1 Related Documentation
For related documentation see the following:
•
•
•
Texas Instruments, TPS7A43EVM-047 Evaluation Module user guide
Texas Instruments, LDO Basics: Preventing reverse current blog
Texas Instruments, LDO basics: capacitor vs. capacitance blog
11.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
11.4 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
11.5 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
11.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
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11.7 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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11-Dec-2021
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPS7A4401DGQR
TPS7A4433DGQR
TPS7A4450DGQR
ACTIVE
ACTIVE
ACTIVE
HVSSOP
HVSSOP
HVSSOP
DGQ
DGQ
DGQ
10
10
10
2500 RoHS & Green
2500 RoHS & Green
2500 RoHS & Green
NIPDAUAG
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 125
-40 to 125
-40 to 125
4401
4433
4450
NIPDAUAG
NIPDAUAG
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
11-Dec-2021
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
12-Dec-2021
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS7A4401DGQR
TPS7A4433DGQR
TPS7A4450DGQR
HVSSOP DGQ
HVSSOP DGQ
HVSSOP DGQ
10
10
10
2500
2500
2500
330.0
330.0
330.0
12.4
12.4
12.4
5.3
5.3
5.3
3.4
3.4
3.4
1.4
1.4
1.4
8.0
8.0
8.0
12.0
12.0
12.0
Q1
Q1
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
12-Dec-2021
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TPS7A4401DGQR
TPS7A4433DGQR
TPS7A4450DGQR
HVSSOP
HVSSOP
HVSSOP
DGQ
DGQ
DGQ
10
10
10
2500
2500
2500
366.0
366.0
366.0
364.0
364.0
364.0
50.0
50.0
50.0
Pack Materials-Page 2
GENERIC PACKAGE VIEW
DGQ 10
3 x 3, 0.5 mm pitch
PowerPADTM HVSSOP - 1.1 mm max height
PLASTIC SMALL OUTLINE
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224775/A
www.ti.com
PACKAGE OUTLINE
DGQ0010D
PowerPADTM - 1.1 mm max height
S
C
A
L
E
3
.
7
0
0
PLASTIC SMALL OUTLINE
C
5.05
4.75
TYP
SEATING PLANE
PIN 1 ID
AREA
A
0.1 C
8X 0.5
10
1
3.1
2.9
NOTE 3
2X
2
5
6
0.27
0.17
10X
3.1
2.9
1.1 MAX
0.08
C A B
B
NOTE 4
0.23
0.13
TYP
SEE DETAIL A
EXPOSED
THERMAL PAD
4
5
0.25
GAGE PLANE
1.89
1.69
0.15
0.05
0.7
0.4
8
0 - 8
1
DETAIL A
TYPICAL
1.83
1.63
4218842/A 01/2019
PowerPAD is a trademark of Texas Instruments.
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-187, variation BA-T.
www.ti.com
EXAMPLE BOARD LAYOUT
DGQ0010D
PowerPADTM - 1.1 mm max height
PLASTIC SMALL OUTLINE
(2.2)
NOTE 9
(1.83)
SOLDER MASK
OPENING
SOLDER MASK
DEFINED PAD
SEE DETAILS
10X (1.45)
10X (0.3)
1
10
(1.3)
TYP
(1.89)
SOLDER MASK
OPENING
SYMM
(3.1)
NOTE 9
8X (0.5)
6
5
(R0.05) TYP
SYMM
METAL COVERED
BY SOLDER MASK
(
0.2) TYP
VIA
(1.3) TYP
(4.4)
LAND PATTERN EXAMPLE
SCALE:15X
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
METAL
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4218842/A 01/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
8. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
numbers SLMA002 (www.ti.com/lit/slma002) and SLMA004 (www.ti.com/lit/slma004).
9. Size of metal pad may vary due to creepage requirement.
www.ti.com
EXAMPLE STENCIL DESIGN
DGQ0010D
PowerPADTM - 1.1 mm max height
PLASTIC SMALL OUTLINE
(1.83)
BASED ON
0.125 THICK
STENCIL
10X (1.45)
10X (0.3)
1
10
(1.89)
SYMM
BASED ON
0.125 THICK
STENCIL
8X (0.5)
5
6
(R0.05) TYP
SEE TABLE FOR
SYMM
(4.4)
DIFFERENT OPENINGS
FOR OTHER STENCIL
THICKNESSES
METAL COVERED
BY SOLDER MASK
SOLDER PASTE EXAMPLE
EXPOSED PAD
100% PRINTED SOLDER COVERAGE BY AREA
SCALE:15X
STENCIL
THICKNESS
SOLDER STENCIL
OPENING
0.1
2.05 X 2.11
1.83 X 1.89 (SHOWN)
1.67 X 1.73
0.125
0.150
0.175
1.55 X 1.60
4218842/A 01/2019
NOTES: (continued)
10. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
11. Board assembly site may have different recommendations for stencil design.
www.ti.com
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