TPS7A53A-Q1 [TI]

汽车类 3A、低 VIN、5.6µVRMS、低噪声、高精度、超低压降稳压器;


型号：	TPS7A53A-Q1
厂家：	TEXAS INSTRUMENTS
描述：	汽车类 3A、低 VIN、5.6µVRMS、低噪声、高精度、超低压降稳压器稳压器
文件：	总37页 (文件大小：2682K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

TPS7A53A-Q1

ZHCSR69A –NOVEMBER 2022 –REVISED DECEMBER 2022

TPS7A53A-Q1 3A 高精度汽车级低噪声LDO 稳压器

1 特性

3 说明

• 符合面向汽车应用的AEC-Q100 标准：

TPS7A53A-Q1 是一款低噪声 (5.6µV_RMS)、低压降线

性稳压器 (LDO)，可提供 3A 拉电流，压降仅为

130mV。

– 温度等级1：–40°C ≤T_A≤+125°C

– HBM ESD 分类等级2

– CDM ESD 分类等级C4A

• 扩展结温(T_J) 范围：

– –40°C 至+150°C

• 输入电压范围：

– IN: V_IN+ V_DO至6.0V

– BIAS：V_OUT+ V_DO(BIAS)至6.0V

• 低压降：130 mV (3 A)

• 输出电压噪声：5.6µV_RMS

• 整个线路、负载和温度范围内的精度：

– 1.3%（最大值）

• 电源纹波抑制：

– 500kHz 时为40dB

• 可调软启动浪涌控制

• 开漏电源正常(PG) 输出

• 封装：

TPS7A53A-Q1 集低噪声 (5.6µV_RMS)、高 PSRR 和高

输出电流能力等特性于一体，设计用于为雷达电源和信

息娱乐等应用中的噪声敏感型组件供电。此器件的优秀

性能可抑制电源产生的相位噪声和时钟抖动，适合为射

频放大器、雷达传感器和芯片组供电。具体而言，信号

链元件将受益于器件的高性能。TPS7A53A-Q1 还提供

可湿侧面选项，方便进行光学检查。

对于需要以低输入和低输出 (LILO) 电压运行的数字负

载（例如应用特定集成电路 (ASIC)、现场可编程门阵

列 (FPGA) 和数字信号处理器 (DSP)），TPS7A53A-

Q1 所具备的出色精度（在负载和温度范围内可达

1.3%）、遥感功能、出色的瞬态性能和软启动功能可

实现出色的系统性能。

TPS7A53A-Q1 器件的多功能性使其适用于许多严苛应

用。

– 具有可湿侧面和高CTE (12ppm/°C) 塑封料的

4mm × 4mm 20 引脚WQFN

封装信息⁽¹⁾

封装尺寸（标称值）

器件型号

封装

2 应用

具有可湿侧面的

RTJ (WQFN、20)

TPS7A53A-Q1

4.00mm × 4.00mm

• 远程信息处理控制单元

• 信息娱乐系统与仪表组

• 成像雷达

(1) 如需了解所有可用封装，请参阅数据表末尾的封装选项附录。

Bias Supply

BIAS

Input Supply

TPS7A53A-Q1

OUT

EN Signal

V_CC

Radar

Sensor System

频谱噪声密度与频率和输出电流

为射频组件供电

本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问

www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: SBVS412

TPS7A53A-Q1

ZHCSR69A –NOVEMBER 2022 –REVISED DECEMBER 2022

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Table of Contents

7.4 Device Functional Modes..........................................17

8 Application and Implementation..................................18

8.1 Application Information............................................. 18

8.2 Typical Application.................................................... 22

8.3 Power Supply Recommendations.............................23

8.4 Layout....................................................................... 23

9 Device and Documentation Support............................25

9.1 Documentation Support............................................ 25

9.2 接收文档更新通知..................................................... 25

9.3 支持资源....................................................................25

9.4 Trademarks...............................................................25

9.5 Electrostatic Discharge Caution................................25

9.6 术语表....................................................................... 25

10 Mechanical, Packaging, and Orderable

1 特性................................................................................... 1

2 应用................................................................................... 1

3 说明................................................................................... 1

4 Revision History.............................................................. 2

5 Pin Configuration and Functions...................................3

6 Specifications.................................................................. 4

6.1 Absolute Maximum Ratings........................................ 4

6.2 ESD Ratings............................................................... 4

6.3 Recommended Operating Conditions.........................4

6.4 Thermal Information....................................................5

6.5 Electrical Characteristics.............................................5

6.6 Typical Characteristics................................................7

7 Detailed Description......................................................13

7.1 Overview...................................................................13

7.2 Functional Block Diagram.........................................13

7.3 Feature Description...................................................14

Information.................................................................... 25

10.1 Mechanical Data..................................................... 26

4 Revision History

Changes from Revision * (November 2022) to Revision A (December 2022)

Page

• 将文档状态从预告信息更改为量产数据.............................................................................................................1

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5 Pin Configuration and Functions

OUT

SNS

Thermal

Pad

NR/SS

BIAS

Not to scale

图5-1. RTJ Package (Fixed), 4-mm × 4-mm, 20-Pin WQFN (Top View)

表5-1. Pin Functions

RTJ

(Fixed) TYPE

NAME

DESCRIPTION

BIAS supply voltage. This pin enables the use of low-input voltage, low-output (LILO) voltage conditions

(that is, V_IN= 1.3 V, V_OUT= 1 V) to reduce power dissipation across the die. Using a BIAS voltage improves

dc and ac performance for V_IN≤2.2 V. A 0.1-µF capacitor or larger must be connected between this pin

and ground.

BIAS

Enable pin. Driving this pin to logic high enables the device; driving this pin to logic low disables the device.

If enable functionality is not required, this pin must be connected to IN or BIAS.

Feedback pin connected to the error amplifier. Although not required, a 10-nF, feed-forward capacitor from

FB to OUT (as close to the device as possible) maximizes ac performance. Using a feed-forward capacitor

can disrupt PG (power-good) functionality.

—

GND

Ground pin. This pin must be connected to ground and the thermal pad with a low-impedance connection.

—

Input supply voltage pin. A 1-µF or larger ceramic capacitor (0.5 µF or greater of capacitance) from IN to

ground reduces the impedance of the input supply. Place the input capacitor as close to the input as

possible.

15-17

3, 5, 6, 7,

9, 10,11,

No internal connection.

—

Noise-reduction and soft-start pin. Connecting an external capacitor between this pin and ground enables

the soft-start function.

Regulated output pin. A 10-µF or larger ceramic capacitor (5 µF or greater of capacitance) from OUT to

ground is required for stability and must be placed as close to the output as possible. Minimize the

impedance from the OUT pin to the load.

OUT

1, 19, 20

Active-high, power-good pin. An open-drain output indicates when the output voltage reaches V_IT(PG)of the

target. The use of a feed-forward capacitor can disrupt PG (power-good) functionality.

SNS

Sense pin connected to the error amplifier.

Thermal pad

Connect the thermal pad to a large-area ground plane. The thermal pad is internally connected to GND.

—

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6 Specifications

6.1 Absolute Maximum Ratings

over operating temperature range (unless otherwise noted)⁽¹⁾

MIN

–0.3

MAX

6.5

UNIT

IN, BIAS, PG, EN

Voltage

OUT

V_IN+ 0.3

6.5

SS, FB

OUT

Internally limited

Current

PG (sink current into device)

Junction, T_J

Storage, T_stg

–40

–55

1.5

150

Temperature

°C

(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply

functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If

used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully

functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.

6.2 ESD Ratings

VALUE

±2000

±500

UNIT

Human body model (HBM), per AEC Q100-002⁽¹⁾

V_(ESD)

Electrostatic discharge

Charged device model (CDM), per AEC specification Q100-011

(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN

NOM

MAX

6.0

UNIT

V_OUT+ V_DO

(IN)

V_IN

Input supply voltage

Enable supply voltage

BIAS supply voltage

V_EN

V_BIAS

6.0

V_OUT+ V_DO

(BIAS)⁽¹⁾

6.0

V_OUT

I_OUT

C_OUT

C_IN

Output voltage

0.8

V_IN- V_DO

Output current

Output capacitor ⁽³⁾

Input capacitor ^{(1) (2)}

Bias capacitor

µF

C_BIAS

C_SS

T_J

0.1

Soft-start capacitor

Operating junction temperature

100

150

–40

℃

(1) V_BIAShas a minimum voltage of 1.7 V or V_OUT+ V_DO(V_BIAS), whichever is higher.

(2) If V_INand V_BIASare connected to the same supply, the recommended minimum capacitor for the supply is 4.7 μF.

(3) A maximum capacitor derating of 25% is considered for minimum capacitance.

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6.4 Thermal Information

TPS7A53A-Q1

THERMAL METRIC⁽¹⁾

RTJ (VQFN)

20 PINS

42.5

UNIT

R_θJA

Junction-to-ambient thermal resistance

Junction-to-case (top) thermal resistance

°C/W

R_θJC(top)

R_θJB

35.2

Junction-to-board thermal resistance

18.8

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

1.7

ψ_JT

18.7

ψ_JB

R_θJC(bot)

2.9

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC package thermal metrics application

report.

6.5 Electrical Characteristics

at V_EN= 1.1 V, V_IN= V_OUT+ 0.3 V, C_BIAS= 0.1 μF, C_IN= C_OUT= 10 μF, C_NR= 1 nF, I_OUT= 50 mA, V_BIAS= 5.0 V ⁽⁵⁾, and T_J

= –40°C to 150°C (unless otherwise noted); typical values are at T_J= 25°C

PARAMETER

TEST CONDITIONS

MIN

TYP

1.0

MAX

UNIT

V_REF

Internal reference

NR/SS pin voltage

Rising bias supply UVLO

Fixed 1 V only

V_NR/SS

Fixed 1 V only ⁽⁴⁾

V_BIAS(UVLO)

1.4

1.8

V_{BIAS(UVLO),HY}Bias supply UVLO

hysteresis

V_OUT+ 2.5 V ≤V_BIAS≤5.5 V, 50 mA ≤I_OUT≤3

A, -40°C ≤T_J≤125°C

±0.5

–1

Accuracy ^{(1) (6)}

ΔV_{OUT (ΔVIN)}

±0.5

0.025

1.3

V_OUT+ 2.5 V ≤V_BIAS≤5.5 V, 50 mA ≤I_OUT≤3 A

V_OUT(nom)+ 0.3 V ≤V_IN≤6.0 V

50 mA ≤I_OUT≤3 A

–1.3

Line regulation

Load regulation

%/V

%/A

ΔV_{OUT (ΔIOUT)}

V_OUT

I_OUT= 3 A, V_BIAS–V_OUT(nom)≥3.25 V⁽³⁾, -40°C ≤

T_J≤125°C

130

275

V_DO(IN)

V_INdropout voltage⁽²⁾

I_OUT= 3 A, V_BIAS–V_OUT(nom)≥3.25 V⁽³⁾

130

1.4

285

1.9

V_DO(BIAS)

I_CL(Fixed

V_BIASdropout voltage⁽²⁾

I_OUT= 3 A, V_IN= V_BIAS

Fixed V_OUT, output

current limit

V_OUT= 80% × V_OUT(nom)

I_OUT= 50 mA

4.0

4.7

0.7

5.5

1.2

V_OUT

)

I_BIAS

BIAS pin current

µA

Shutdown supply current

I_SHDN

V_EN≤0.4 V, V_IN= 1.25 V, V_BIAS= 6 V

(I_GND

)

Feedback/sense pin

current

I_FB/SNS

0.12

0.3

µA

–0.3

1 kHz, I_OUT= 2 A, V_IN= 1.25 V, V_OUT= 1.0 V

3 MHz, I_OUT= 2 A, V_IN= 1.25 V, V_OUT= 1.0 V

1 kHz, I_OUT= 2 A, V_IN= 1.25 V, V_OUT= 1.0 V

3 MHz, I_OUT= 2 A, V_IN= 1.25 V, V_OUT= 1.0 V

BW = 10 Hz to 100 kHz, I_OUT= 2 A, C_SS= 1 nF

C_SS= 10 nF, V_OUT= 1.0 V

Power-supply rejection

(V_INto V_OUT

)

PSRR

Power-supply rejection

(V_BIASto V_OUT

)

V_n

Output noise voltage

Minimum startup time

μVrms

t_STR

Soft-start charging

current

I_SS

t_SS= 4.8 x V_OUT(NOM)/ 0.8 V, V_OUT= 1.0 V

µA

V_EN(hi)

V_EN(lo)

V_EN(hys)

Enable input high level

Enable input low level

Enable pin hysteresis

1.1

5.5

0.4

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6.5 Electrical Characteristics (continued)

at V_EN= 1.1 V, V_IN= V_OUT+ 0.3 V, C_BIAS= 0.1 μF, C_IN= C_OUT= 10 μF, C_NR= 1 nF, I_OUT= 50 mA, V_BIAS= 5.0 V ⁽⁵⁾, and T_J

= –40°C to 150°C (unless otherwise noted); typical values are at T_J= 25°C

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

V_EN(dg)

I_EN

Enable pin deglitch time

Enable pin current

PG trip threshold

µs

V_EN= 5 V

0.1

0.25

µA

V_IT

V_OUTdecreasing

94 %V_OUT

%V_OUT

V_HYS

PG trip hysteresis

PG output low voltage

PG leakage current

2.5

V_PG(lo)

I_PG(lkg)

R_PULLDOWN

I_PG= 1 mA (sinking), V_OUT< V_IT

V_PG= 5.25 V, V_OUT> V_IT

0.3

0.001

0.5

0.05

µA

kΩ

Output Pulldown resistor V_BIAS= 5 V, V_EN= 0 V

Shutdown, temperature increasing

Reset, temperature decreasing

165

140

Thermal shutdown

temperature

T_SD

℃

(1) Adjustable devices tested at 0.8 V; resistor tolerance is not taken into account.

(2) Dropout is defined as the voltage from V_INto V_OUTwhen V_OUTis 3% below nominal.

(3) 3.25 V is a test condition of this device and can be adjusted by referring to Figure 6.

(4) For fixed voltage, NR/SS voltage is equal to output voltage.

(5) V_BIAS= V_{DO_MAX(BIAS)}+ V_OUTfor V_OUT≥3.1V.

(6) The device is not tested under conditions where V_IN> V_OUT+ 0.85 V and I_OUT= 3 A, because the power dissipation is higher than the

maximum rating of the package. Also, this accuracy specification does not apply on any application condition that exceeds the power

dissipation limit of the package under test.

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6.6 Typical Characteristics

at T_A= 25°C, V_IN= 1.4 V or V_IN= V_OUT(NOM)+ 0.3 V (whichever is greater), V_BIAS= open, V_OUT(NOM)= 0.8 V, V_EN= 1.1 V,

C_OUT= 47 µF, C_NR/SS= 0 nF, C_FF= 0 nF, and PG pin pulled up to V_INwith 100 kΩ(unless otherwise noted)

V_IN= 1.3 V, V_BIAS= 5 V, V_OUT= 1.0 V, C_OUT= 10 µF,

I_OUT= 1 A, V_BIAS= 5 V, V_OUT= 1.0 V, C_OUT= 10 µF,

C_BIAS= 0.1 μF, C_SS= 10 nF

图6-1. PSRR vs Frequency and I_OUT

图6-2. PSRR vs Frequency and V_INfor I_OUT= 1 A

I_OUT= 2 A, V_BIAS= 5 V, V_OUT= 1.0 V, C_OUT= 10 µF,

I_OUT= 3 A, V_BIAS= 5 V, V_OUT= 1.0 V, C_OUT= 10 µF,

C_BIAS= 0.1 μF, C_SS= 10 nF

图6-3. PSRR vs Frequency and V_INfor I_OUT= 2 A

图6-4. PSRR vs Frequency and V_INfor I_OUT= 3 A

I_OUT= 3 A, V_BIAS= 5 V, V_OUT= 1.0 V, C_BIAS= 0.1 μF,

C_OUT= 10 μF

C_SS= 10 nF

图6-5. PSRR vs Frequency and C_OUT

图6-6. PSRR vs Frequency and C_SS

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6.6 Typical Characteristics (continued)

at T_A= 25°C, V_IN= 1.4 V or V_IN= V_OUT(NOM)+ 0.3 V (whichever is greater), V_BIAS= open, V_OUT(NOM)= 0.8 V, V_EN= 1.1 V,

C_OUT= 47 µF, C_NR/SS= 0 nF, C_FF= 0 nF, and PG pin pulled up to V_INwith 100 kΩ(unless otherwise noted)

V_IN= V_EN= 1.3 V, V_BIAS= 5 V, V_OUT= 1.0 V, C_IN= 10 μF,

C_OUT= 10 μF, C_SS= 10 nF

V_IN= V_EN= 1.3 V, V_OUT= 1.0 V, C_IN= 10 μF, C_OUT= 10 μF,

C_SS= 10 nF

图6-8. BIAS PSRR vs Frequency and V_BIAS

图6-7. BIAS PSRR vs Frequency and I_OUT

V_IN= 1.3 V, V_OUT= 1.0 V, V_BIAS= 5 V, C_OUT= 10 µF, C_SS

V_IN= 1.3 V, V_OUT= 1.0 V, C_OUT= 10 µF, C_SS= 10 nF,

10 nF, C_BIAS= 0.1 μF, RMS noise BW = 10 Hz to 100 kHz

C_BIAS= 0.1 μF, RMS noise BW = 10 Hz to 100 kHz

图6-9. Spectral Noise Density vs Frequency and I_OUT

图6-10. Spectral Noise Density vs Frequency and V_BIAS

V_IN= 1.3 V, V_OUT= 1.0 V, V_BIAS= 5 V, C_SS= 10 nF,

V_IN= 1.3 V, V_OUT= 1.0 V, V_BIAS= 5 V, C_OUT= 10 μF,

C_BIAS= 0.1 μF, RMS noise BW = 10 Hz to 100 kHz

图6-11. Spectral Noise Density vs Frequency and C_OUT

图6-12. Spectral Noise Density vs Frequency and C_SS

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6.6 Typical Characteristics (continued)

at T_A= 25°C, V_IN= 1.4 V or V_IN= V_OUT(NOM)+ 0.3 V (whichever is greater), V_BIAS= open, V_OUT(NOM)= 0.8 V, V_EN= 1.1 V,

C_OUT= 47 µF, C_NR/SS= 0 nF, C_FF= 0 nF, and PG pin pulled up to V_INwith 100 kΩ(unless otherwise noted)

V_IN= 1.3 V, V_OUT= 1.0 V, V_BIAS= 5.0 V, I_OUT= 3 A,

C_OUT= 10 µF, C_SS= 1 nF

V_IN= 1.3 V, V_OUT= 1.0 V, V_BIAS= 5.0 V, I_OUT= 3 A,

C_OUT= 10 µF, C_SS= 10 nF

图6-13. Start-Up Waveform for C_SS= 1 nF

图6-14. Start-Up Waveform vs Time for C_SS= 10 nF

V_IN= V_OUT+ 0.3 V, V_BIAS= V_EN= 5 V, I_{OUT, DC}= 10 mA,

slew rate = 1 A/µs, C_SS= 10 nF, C_OUT= 10 µF

V_IN= 1.3 V, V_OUT= 1.0 V, V_BIAS= 5.0 V, I_OUT= 3 A,

C_OUT= 10 µF, C_SS= 22 nF

图6-16. Load Transient for V_OUTWith Bias

图6-15. Start-Up Waveform for C_SS= 22 nF

I_{OUT, DC}= 1.5 A, C_OUT= 10 µF,

V_BIAS= 5 V, I_OUT= 3 A, C_OUT= 10 µF, C_SS= 10 nF

C_SS= C_FF= 10 nF, slew rate = 1 A/µs

图6-17. Line Transient for V_OUTWith Bias

图6-18. Input Ramp Response

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6.6 Typical Characteristics (continued)

at T_A= 25°C, V_IN= 1.4 V or V_IN= V_OUT(NOM)+ 0.3 V (whichever is greater), V_BIAS= open, V_OUT(NOM)= 0.8 V, V_EN= 1.1 V,

C_OUT= 47 µF, C_NR/SS= 0 nF, C_FF= 0 nF, and PG pin pulled up to V_INwith 100 kΩ(unless otherwise noted)

V_BIAS= 5 V, V_OUT= 1.0 V

V_IN= 1.25 V, V_OUT= 1 V

图6-19. IN-to-OUT Dropout Voltage vs Output Current

图6-20. BIAS-to-OUT Dropout Voltage vs Output Current

V_IN= 1.25 V, V_BIAS= 5 V, V_OUT= 1.0 V

V_IN= 1.25 V, V_OUT= 1.0 V, V_BIAS= 5 V

图6-21. Load Regulation vs 0-mA to 50-mA Output Current

图6-22. Load Regulation vs ≥50-mA Output Current

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6.6 Typical Characteristics (continued)

at T_A= 25°C, V_IN= 1.4 V or V_IN= V_OUT(NOM)+ 0.3 V (whichever is greater), V_BIAS= open, V_OUT(NOM)= 0.8 V, V_EN= 1.1 V,

C_OUT= 47 µF, C_NR/SS= 0 nF, C_FF= 0 nF, and PG pin pulled up to V_INwith 100 kΩ(unless otherwise noted)

V_IN= 5 V, V_OUT= 1.0 V, I_OUT= 50 mA

V_OUT= 1.0 V, V_BIAS= 5 V, I_OUT= 50 mA

图6-24. Output Voltage vs Bias Voltage

图6-23. Line Regulation vs Input Voltage

V_OUT= 1.0 V, V_BIAS= 5.0 V, I_OUT= 50 mA

V_OUT= 1.0 V, V_BIAS= 5.0 V

图6-25. IN Pin Quiescent Current vs

图6-26. IN Pin Quiescent Current vs

Input Voltage

Output Current

V_OUT= 1.0 V, V_BIAS= 5.0 V, I_OUT= 3 A

V_IN= 1.25 V, V_BIAS= 5.0 V, V_OUT= 1.0 V

图6-27. BIAS Pin Quiescent Current vs

图6-28. BIAS Pin Quiescent Current vs

Input Voltage

Output Current

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6.6 Typical Characteristics (continued)

at T_A= 25°C, V_IN= 1.4 V or V_IN= V_OUT(NOM)+ 0.3 V (whichever is greater), V_BIAS= open, V_OUT(NOM)= 0.8 V, V_EN= 1.1 V,

C_OUT= 47 µF, C_NR/SS= 0 nF, C_FF= 0 nF, and PG pin pulled up to V_INwith 100 kΩ(unless otherwise noted)

V_BIAS= 5 V, V_EN= 0 V

V_IN= 1.25 V, V_EN= 0 V

图6-29. Shutdown Current (GND Pin) vs

图6-30. Shutdown Current (GND Pin) vs

Input Voltage

Bias Voltage

Temperature limited because of power dissipation

图6-31. Current Limit vs Output Voltage

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7 Detailed Description

7.1 Overview

The TPS7A53A-Q1 is a low-input, low-output (LILO), low-quiescent-current linear regulator optimized to support

excellent transient performance. This regulator uses a low-current bias rail to power all internal control circuitry,

allowing the n-type field effect transistor (NMOS) pass transistor to regulate very-low input and output voltages.

Using an NMOS-pass transistor offers several critical advantages for many applications. Unlike a p-channel

metal-oxide-semiconductor field effect transistor (PMOS) topology device, the output capacitor has little effect on

loop stability. This architecture allows the TPS7A53A-Q1 to be stable with any ceramic capacitor 10 μF or

greater. Transient response is also superior to PMOS topologies, particularly for low V_INapplications.

The TPS7A53A-Q1 features a programmable, voltage-controlled, soft-start circuit that provides a smooth,

monotonic start-up and limits start-up inrush currents that can be caused by large capacitive loads. An enable

(EN) pin with hysteresis and deglitch allows slow-ramping signals to be used for sequencing the device. The low

V_INand V_OUTcapability allows for inexpensive, easy-to-design, and efficient linear regulation between the

multiple supply voltages often required by processor-intensive systems.

7.2 Functional Block Diagram

OUT

V_OUT

500 ꢀ

BIAS

UVLO

Thermal &

Current

Limit

20 µA

C_SS

Soft-Start

Discharge

1-V

Reference

SNS

Hysteresis

and Deglitch

V_OUT

Delay^(B)

10 kꢀ

0.9 x

V_REF

GND

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7.3 Feature Description

7.3.1 Enable and Shutdown

The enable (EN) pin is active high and compatible with standard digital-signaling levels. Setting V_ENbelow 0.4 V

turns the regulator off, and setting V_ENabove 1.1 V turns the regulator on. Unlike many regulators, the enable

circuitry has hysteresis and deglitching for use with relatively slowly ramping analog signals. This configuration

allows the device to be enabled by connecting the output of another supply to the EN pin. The enable circuitry

typically has 70 mV of hysteresis and a deglitch circuit to help avoid on-off cycling as a result of small glitches in

the V_ENsignal.

The enable threshold is typically 0.75 V and varies with temperature and process variations. Temperature

variation is approximately –1.2 mV/°C; process variation accounts for most of the remaining variation to the 0.4-

V and 1.1-V limits. If precise turn-on timing is required, a fast rise-time signal must be used.

If not used, EN can be connected to BIAS. Place the connection as close as possible to the bias capacitor.

7.3.2 Active Discharge

The TPS7A53A-Q1 has an internal active pulldown circuits on the OUT pin.

This active discharge function uses an internal metal-oxide-semiconductor field-effect transistor (MOSFET) that

connects a resistor (R_PULLDOWN) to ground when the low-dropout resistor (LDO) is disabled in order to actively

discharge the output voltage. The active discharge circuit is activated when the device is disabled by driving EN

to logic low, when the voltage at IN or BIAS is below the UVLO threshold, or when the regulator is in thermal

shutdown.

The discharge time after disabling the device depends on the output capacitance (C_OUT) and the load resistance

(R_L) in parallel with the pulldown resistor.

The active pulldown circuit connects the output to GND through a 500-Ωresistor when the device is disabled.

τ_OUT= (500 × R_L/ (500 + R_L) × C_OUT

(1)

Do not rely on the active discharge circuit for discharging a large amount of output capacitance after the input

supply has collapsed because reverse current can flow from the output to the input and can cause damage to

the device. Limit reverse current to no more than 5% of the device-rated current.

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7.3.3 Power-Good Output (PG)

The PG signal provides an easy solution to meet demanding sequencing requirements because PG signals

when the output nears the nominal value. PG can be used to signal other devices in a system when the output

voltage is near, at, or above the set output voltage (V_OUT(nom)). 图7-1 shows a simplified schematic.

The PG signal is an open-drain digital output that requires a pullup resistor to a voltage source and is active

high. The PG circuit sets the PG pin into a high-impedance state to indicate that the power is good.

Using a large feed-forward capacitor (C_FF) delays the output voltage and, because the PG circuit monitors the

FB pin, the PG signal can indicate a false positive.

V_PG

V_BG

V_IN

V_FB

GND

UVLO_BIAS

GND

图7-1. Simplified PG Circuit

7.3.4 Internal Current Limit

The device has an internal current-limit circuit that protects the regulator during transient high-load current faults

or shorting events. The current limit is a hybrid brick-wall foldback scheme. The current limit transitions from a

brick-wall scheme to a foldback scheme at the foldback voltage (V_FOLDBACK). In a high-load current fault with the

output voltage above V_FOLDBACK, the brick-wall scheme limits the output current to the current limit (I_CL). When

the voltage drops below V_FOLDBACK, a foldback current limit activates that scales back the current when the

output voltage approaches GND. When the output is shorted, the device supplies a typical current called the

short-circuit current limit (I_SC). I_CLand I_SCare listed in the Electrical Characteristics table.

For this device, V_FOLDBACKis approximately 60% × V_OUT(nom)

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The output voltage is not regulated when the device is in current limit. When a current-limit event occurs, the

device begins to heat up because of the increase in power dissipation. When the device is in a brick-wall current

limit, the pass transistor dissipates power [(V_IN–V_OUT) × I_CL]. When the device output is shorted and the output

is below V_FOLDBACK, the pass transistor dissipates power [(V_IN– V_OUT) × I_SC]. If thermal shutdown is triggered,

the device turns off. When the device sufficiently cools down, the internal thermal shutdown circuit turns the

device back on. If the output current fault condition continues, the device cycles between current limit and

thermal shutdown. For more information on current limits, see the Know Your Limits application note. 图 7-2

shows a diagram of the foldback current limit.

V_OUT

Brickwall

V_OUT(NOM)

V_FOLDBACK

Foldback

0 V

I_OUT

I_RATED

0 mA

I_SC

I_CL

图7-2. Foldback Current Limit

7.3.5 Thermal Shutdown Protection (T_SD

)

The internal thermal shutdown protection circuit disables the output when the thermal junction temperature (T_J)

of the pass transistor rises to the thermal shutdown temperature threshold, T_{SD(shutdown) (typical)}. The thermal

shutdown circuit hysteresis makes sure that the LDO resets (turns on) when the temperature falls to

T_{SD(reset) (typical)}

The thermal time constant of the semiconductor die is fairly short; thus, the device can cycle on and off when

thermal shutdown is reached until the power dissipation is reduced. Power dissipation during start up can be

high from large V_IN– V_OUTvoltage drops across the device or from high inrush currents charging large output

capacitors. Under some conditions, the thermal shutdown protection disables the device before start up

completes.

For reliable operation, limit the junction temperature to the maximum listed in the Recommended Operating

Conditions table. Operation above this maximum temperature causes the device to exceed operational

specifications. Although the internal protection circuitry is designed to protect against thermal overload

conditions, this circuitry is not intended to replace proper heat sinking. Continuously running the regulator into

thermal shutdown, or above the maximum recommended junction temperature, reduces long-term reliability.

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7.4 Device Functional Modes

表 7-1 shows the conditions that lead to the different modes of operation. See the Electrical Characteristics table

for parameter values.

表7-1. Device Functional Mode Comparison

PARAMETER

OPERATING MODE

V_IN

V_BIAS

V_EN

I_OUT

T_J

V_IN≥V_{OUT (nom)}

V_DO(IN)and V_IN≥

T_J< T_SDfor

shutdown

_BIAS≥V_OUT+

V_DO(BIAS)

Normal mode

Dropout mode

I_OUT< I_CL

V_EN≥V_HI(EN)

V_IN(min)

V_IN(min)< V_IN< V_OUT

_(nom)+ V_DO(IN)

T_J< T_SDfor

shutdown

V_BIAS< V_OUT+ V_DO(BIAS)

V_EN> V_HI(EN)

I_OUT< I_CL

Disabled mode

(any true condition

disables the device)

T_J≥T_SDfor

shutdown

V_IN< V_UVLO(IN)

V_BIAS< V_BIAS(UVLO)

V_EN< V_LO(EN)

—

7.4.1 Normal Operation

The device regulates to the nominal output voltage when the following conditions are met:

• The input voltage is greater than the nominal output voltage plus the dropout voltage (V_OUT(nom)+ V_DO(IN)

)

• The bias voltage is greater than the nominal output voltage plus the dropout voltage (V_OUT(nom)+ V_DO(BIAS)

• The output current is less than the current limit (I_OUT< I_CL)

)

• The device junction temperature is less than the thermal shutdown temperature ( T_J< T_SD(shutdown)

)

• The enable voltage has previously exceeded the enable rising threshold voltage and has not yet decreased

to less than the enable falling threshold

7.4.2 Dropout Operation

If the input voltage is lower than the nominal output voltage plus the specified dropout voltage, but all other

conditions are met for normal operation, the device operates in dropout mode. Similarly, if the bias voltage is

lower than the nominal output voltage plus the specified dropout voltage, but all other conditions are met for

normal operation, the device operates in dropout mode as well. In this mode, the output voltage tracks the input

voltage. During this mode, the transient performance of the device becomes significantly degraded because the

pass transistor is in the ohmic or triode region, and functions as a switch. Line or load transients in dropout can

result in large output voltage deviations.

When the device is in a steady dropout state, defined as when the device is in dropout (V_IN< V_OUT+ V_DO(IN)or

V_BIAS< V_OUT+ V_DO(BIAS)directly after being in normal regulation state, but not during start up), the pass

transistor is driven into the ohmic or triode region. When the input voltage returns to a value greater than or

equal to the nominal output voltage plus the dropout voltage (V_OUT(NOM)+ V_DO(IN)), the output voltage can

overshoot for a short time when the device pulls the pass transistor back into the linear region.

7.4.3 Disabled

The output of the device can be shutdown by forcing the voltage of the enable pin to less than V_IL(EN)(see the

Electrical Characteristics table). When disabled, the pass transistor is turned off, internal circuits are shutdown,

and the output voltage is actively discharged to ground by an internal discharge circuit from the output to ground.

The device is disabled under the following conditions:

• The input or bias voltages are below the respective minimum specifications

• The enable voltage is less than the enable falling threshold voltage or has not yet exceeded the enable rising

threshold

• The device junction temperature is greater than the thermal shutdown temperature

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8 Application and Implementation

备注

Information in the following applications sections is not part of the TI component specification, and TI

does not warrant its accuracy or completeness. TI’s customers are responsible for determining

suitability of components for their purposes, as well as validating and testing their design

implementation to confirm system functionality.

8.1 Application Information

The TPS7A53A-Q1 is a low-input, low-output (LILO), low-dropout regulator (LDO) that features soft-start

capability. This regulator uses a low-current bias input to power all internal control circuitry, allowing the NMOS

pass transistor to regulate very low input and output voltages.

Using an NMOS pass transistor offers several critical advantages for many applications. Unlike a PMOS

topology device, the output capacitor has little effect on loop stability. This architecture allows stability with

ceramic capacitors of 10 μF or greater. Transient response is also superior to PMOS topologies, particularly for

low V_INapplications.

A programmable voltage-controlled, soft-start circuit provides a smooth, monotonic start-up and limits start-up

inrush currents that can be caused by large capacitive loads. An enable (EN) pin with hysteresis and deglitch

allows slow-ramping signals to be used for sequencing the device. The low V_INand V_OUTcapability allows for

inexpensive, easy-to-design, and efficient linear regulation between the multiple supply voltages often required

by processor-intensive systems.

8.1.1 Input, Output, and Bias Capacitor Requirements

The device is designed to be stable for ceramic capacitor of values ≥ 10 μF. The device is also stable with

multiple capacitors in parallel, which can be of any type or value.

The capacitance required on the IN and BIAS pins strongly depends on the input supply source impedance. To

counteract any inductance in the input, the minimum recommended capacitor for V_INis 1 μF and the minimum

recommended capacitor for V_BIASis 0.1 µF. If V_INand V_BIASare connected to the same supply, the

recommended minimum capacitor for V_BIASis 4.7 μF. Use good quality, low equivalent series resistance (ESR)

and equivalent series inductance (ESL) capacitors on the input; ceramic X5R and X7R capacitors are preferred.

Place these capacitors as close the pins as possible for optimum performance.

Low ESR and ESL capacitors improve high-frequency PSRR.

8.1.2 Dropout Voltage

The TPS7A53A-Q1 offers very low dropout performance, making the device designed for high-current, low V_IN

and low V_OUTapplications. The low dropout allows the device to be used in place of a dc/dc converter and still

achieve good efficiency. 方程式2 provides a quick estimate of the efficiency.

_OUT´ I_OUT

V_OUT

V_IN

at I_OUT>> I_Q

Efficiency »

V_IN´ (I_IN+ I_Q)

(2)

This efficiency provides designers with the power architecture for applications to achieve the smallest, simplest,

and lowest cost solutions.

For this architecture, there are two different specifications for dropout voltage. The first specification (see 图

6-19) is referred to as V_INdropout and is used when an external bias voltage is applied to achieve low dropout.

This specification assumes that V_BIASis at least 2.8 V above V_OUT, which is the case for V_BIASwhen powered by

a 5.0-V rail with 5% tolerance and with V_OUT= 1.5 V. If V_BIASis higher than V_OUT+ 2.8 V, the V_INdropout is less

than specified.

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备注

2.8 V is a test condition of this device and can be adjusted by referring to the Electrical Characteristics

table.

The second specification (illustrated in 图 6-20) is referred to as V_BIASdropout and applies to applications where

IN and BIAS are tied together. This option allows the device to be used in applications where an auxiliary bias

voltage is not available or low dropout is not required. Dropout is limited by BIAS in these applications because

V_BIASprovides the gate drive to the pass transistor; therefore, V_BIASmust be 1.9 V above V_OUT. Because of this

usage, having IN and BIAS tied together become a highly inefficient solution that can consume large amounts of

power. Pay attention not to exceed the power rating of the device package.

8.1.3 Output Noise

The TPS7A53A-Q1 provides low output noise when a soft-start capacitor is used. When the device reaches the

end of the soft-start cycle, the soft-start capacitor serves as a filter for the internal reference. By using a 10-nF,

soft-start capacitor, the output noise is reduced by half and is typically 7.1 μV_RMSfor a 1-V output (10 Hz to

100 kHz). Further increasing C_SShas little effect on noise. Because most of the output noise is generated by the

internal reference, the noise is a function of the set output voltage. 方程式 3 gives the RMS noise with a 10-nF,

soft-start capacitor:

ꢀV

≈

∆

’

◊

RMS

V ( ꢀV_RMS) = 7.1∂

∂V_OUT(V)

(3)

The low output noise makes this LDO a good choice for powering transceivers, phase-locked loops (PLLs), or

other noise-sensitive circuitry.

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8.1.4 Estimating Junction Temperature

By using the thermal metrics Ψ_JTand Ψ_JB, as shown in the Thermal Information table, the junction temperature

can be estimated with corresponding formulas (given in 方程式 4). For backwards compatibility, an older θ_JC(top)

parameter is listed as well.

Y_JT: T_J= T_T+ Y_JT· P_D

Y_JB: T_J= T_B+ Y_JB· P_D

(4)

where:

• P_Dis the power dissipation

• T_Tis the temperature at the center-top of the package

• T_Bis the PCB temperature measured 1 mm away from the package on the PCB surface

备注

Both T_Tand T_Bcan be measured on actual application boards using a thermo-gun (an infrared

thermometer).

For more information about measuring T_Tand T_B, see the Using New Thermal Metrics application note,

available for download at www.ti.com.

For a more detailed discussion of why TI does not recommend using θ_JC(top)to determine thermal

characteristics, see the Using New Thermal Metrics application note, available for download at www.ti.com. For

further information, see the Semiconductor and IC Package Thermal Metrics application note, also available on

the TI website.

8.1.5 Soft Start, Sequencing, and Inrush Current

Soft-start refers to the ramp-up characteristic of the output voltage during LDO turn-on after EN and UVLO

achieve threshold voltage. The soft start current is fixed for fixed output voltage versions.

Although the device does not have any sequencing requirement, following the sequencing order of BIAS, IN, and

EN makes sure that the soft start starts from zero.

图 8-1 shows an example of the device behavior when the EN pin is enabled prior to having either power supply

up. Under this condition, the output jumps from 0 V to approximately 0.3 V almost instantly when the IN voltage

is sufficient to power the circuit.

图8-1. Sequencing and Soft-Start Behavior

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As shown in 图 8-2, connecting EN to IN, in conjunction with a slow input or output voltage ramp, can have

undesired behavior in the application. For a smooth IN and OUT ramp, consider using the EN pin separate from

the IN voltage.

图8-2. V_EN= V_INBehavior

Inrush current is defined as the current into the LDO at the IN pin during start-up. Inrush current then consists

primarily of the sum of load current and the current used to charge the output capacitor. This current is difficult to

measure because the input capacitor must be removed, which is not recommended. However, 方程式 5 can

estimate this soft-start current:

_OUT´ dV_OUT(t)

V_OUT(t)

R_LOAD

I_OUT(t)

(5)

where:

• V_OUT(t) is the instantaneous output voltage of the turn-on ramp

• dV_OUT(t) / dt is the slope of the V_OUTramp

• R_LOADis the resistive load impedance

8.1.6 Power-Good Operation

For proper operation of the power-good circuit, the pullup resistor value must be between 10 kΩ and 100 kΩ.

The lower limit of 10 kΩ results from the maximum pulldown strength of the power-good transistor, and the

upper limit of 100 kΩresults from the maximum leakage current at the power-good node. If the pullup resistor is

outside of this range, then the power-good signal can possibly not read a valid digital logic level.

The state of PG is only valid when the device operates above the minimum supply voltage. During short UVLO

events and at light loads, power-good does not assert because the output voltage is sustained by the output

capacitance.

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8.2 Typical Application

This section discusses the implementation of the fixed 1.0-V TPS7A53A-Q1 to regulate a 3-A load requiring

good PSRR at high frequency with low noise. 图8-3 provides a schematic for this typical application circuit.

V_IN

OUT

V_OUT

C_OUT

V_BIAS

C_IN

SNS

TPS7A53A-Q1

R_PG

C_SS

V_BIAS

C_BIAS

BIAS

GND

图8-3. Typical Fixed Voltage Application

8.2.1 Design Requirements

For this design example, use the parameters listed in 表8-1 as the input parameters.

表8-1. Design Parameters

PARAMETER

Input voltage

DESIGN REQUIREMENT

1.3 V, ±3%, provided by the dc/dc converter switching at 500 kHz

Bias voltage

5.0 V

Output voltage

1.0 V, ±1%

Output current

3.0 A (maximum), 10 mA (minimum)

RMS noise, 10 Hz to 100 kHz

PSRR at 500 kHz

Start-up time

< 10 µV_RMS

> 40 dB

< 25 ms

8.2.2 Detailed Design Procedure

At 3.0 A and 1.0 V_OUT, the dropout of the TPS7A53A-Q1 has a 285-mV maximum dropout over temperature;

thus, a 300-mV headroom is sufficient for operation over both input and output voltage accuracy. At full load and

high temperature on some devices, the TPS7A53A-Q1 can enter dropout if both the input and output supply are

beyond the edges of the respective accuracy specification.

To satisfy the required start-up time and still maintain low noise performance, a 10-nF C_SSis selected. 方程式 6

calculates this value.

t_SS= (V_SS× C_SS) / I_SS

(6)

At the 3.0-A maximum load, the internal power dissipation is 0.9 W and corresponds to a 38.3°C junction

temperature rise for the RTJ package on a standard JEDEC board. With an 55°C maximum ambient

temperature, the junction temperature is at 93.3°C.

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8.2.3 Application Curve

图8-4. PSRR vs Frequency for

V_OUT= 1.0 V and I_OUT= 3 A

8.3 Power Supply Recommendations

The TPS7A53A-Q1 is designed to operate from an input voltage up to 6.0 V, provided the bias rail is at least

1.3 V higher than the input supply and dropout requirements are met. The bias rail and the input supply must

both provide adequate headroom and current for the device to operate normally. Connect a low output

impedance power supply directly to the IN pin. This supply must have at least 1 μF of capacitance near the IN

pin for optimal performance. A supply with similar requirements must also be connected directly to the BIAS rail

with a separate 0.1 μF or larger capacitor. If the IN pin is tied to the BIAS pin, a minimum 4.7-μF capacitor is

required for performance. To increase the overall PSRR of the solution at higher frequencies, use a pi-filter or

ferrite bead before the input capacitor.

8.4 Layout

8.4.1 Layout Guidelines

8.4.1.1 Board Layout

For best overall performance, place all circuit components on the same side of the circuit board and as near as

practical to the respective LDO pin connections. Place ground return connections to the input and output

capacitor, and to the LDO ground pin as close to each other as possible, connected by a wide, component-side,

copper surface. To avoid negative system performance, do not use of vias and long traces to the input and

output capacitors. The grounding and layout scheme illustrated in 图 8-5 minimizes inductive parasitics, and

thereby reduces load-current transients, minimizes noise, and increases circuit stability.

To improve performance, use a ground reference plane, either embedded in the PCB or placed on the bottom

side of the PCB opposite the components. This reference plane serves to provide accuracy of the output

voltage, shield noise, and behaves similar to a thermal plane to spread (or sink) heat from the LDO device when

connected to the thermal pad. In most applications, this ground plane is necessary to meet thermal

requirements.

8.4.1.2 RTJ Package —High CTE Mold Compound

The RTJ package uses a mold compound with a high coefficient of thermal expansion (CTE) of 12 ppm/°C. This

mold compound allows for the CTE of the packaged device to more closely match the CTE of a conventional

FR4 PCB (approximately 14 ppm/°C to 17 ppm/°C). This CTE match is important when considering the effects

that temperature swings can induce on a board with large differences in CTE values. Package and board

combinations with widely dissimilar CTEs can experience mechanical cracking or fracturing of the solder joints

caused by frequent changes in temperature, and the corresponding differences in expansion. Devices with

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normal mold compounds in similar packages typically have CTE values that are 25% lower than values found

with the RTJ package.

8.4.2 Layout Example

Ground Plane for Thermal Relief and Signal

Ground

To PG Pullup Supply

PG Output

NC 11

C_BIAS

R_PG

To Bias Supply

To Signal Ground

Enable Signal

BIAS

Thermal Pad

SS 13

SNS

C_NR/SS

EN 14

To Load

OUT

Input Power Plane

Output Power Plane

C_IN

C_OUT

Power Ground Plane

Vias used for application purposes.

图8-5. Example Layout

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9 Device and Documentation Support

9.1 Documentation Support

9.1.1 Related Documentation

For related documentation, see the following:

• Texas Instruments, TPS3702 High-Accuracy, Overvoltage and Undervoltage Monitor data sheet

• Texas Instruments, Pros and Cons of Using a Feed-Forward Capacitor with a Low Dropout Regulator

application note

• Texas Instruments, 6 A Current-Sharing Dual LDO design guide

9.2 接收文档更新通知

要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新进行注册，即可每周接收产品信息更

改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。

9.3 支持资源

TI E2E^™支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解

答或提出自己的问题可获得所需的快速设计帮助。

链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅

TI 的《使用条款》。

9.4 Trademarks

TI E2E^™is a trademark of Texas Instruments.

所有商标均为其各自所有者的财产。

9.5 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled

with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may

be more susceptible to damage because very small parametric changes could cause the device not to meet its published

specifications.

9.6 术语表

TI 术语表

本术语表列出并解释了术语、首字母缩略词和定义。

10 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

Submit Document Feedback

Product Folder Links: TPS7A53A-Q1

TPS7A53A-Q1

ZHCSR69A –NOVEMBER 2022 –REVISED DECEMBER 2022

www.ti.com.cn

10.1 Mechanical Data

PACKAGE OUTLINE

RTJ0020L

WQFN - 0.8 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

4.15

3.85

PIN 1 INDEX AREA

4.15

3.85

0.07 MIN

(0.13)

SECTION A-A

TYPICAL

0.8

0.7

SEATING PLANE

0.08 C

0.05

0.00

2.2 0.1

SYMM

(0.2) TYP

EXPOSED

THERMAL PAD

(0.16) TYP

SYMM

16X 0.5

PIN 1 ID

0.3

0.2

20X

0.1

C A B

0.5

0.05

20X

0.3

4228235/A 12/2021

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

www.ti.com

Submit Document Feedback

Product Folder Links: TPS7A53A-Q1

TPS7A53A-Q1

ZHCSR69A –NOVEMBER 2022 –REVISED DECEMBER 2022

www.ti.com.cn

EXAMPLE BOARD LAYOUT

RTJ0020L

WQFN - 0.8 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

(

2.2)

SYMM

SEE SOLDER MASK

DETAIL

20X (0.6)

20X (0.25)

16X (0.5)

(0.85)

SYMM

(3.8)

(R0.05) TYP

(

0.2) TYP

VIA

(0.85)

(3.8)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE: 20X

0.07 MIN

ALL AROUND

0.07 MAX

ALL AROUND

METAL UNDER

SOLDER MASK

METAL EDGE

EXPOSED METAL

SOLDER MASK

OPENING

EXPOSED

METAL

SOLDER MASK

OPENING

NON SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DEFINED

SOLDER MASK DETAILS

4228235/A 12/2021

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

number SLUA271 (www.ti.com/lit/slua271).

5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown

on this view. It is recommended that vias under paste be ﬁlled, plugged or tented.

www.ti.com

Submit Document Feedback

Product Folder Links: TPS7A53A-Q1

TPS7A53A-Q1

ZHCSR69A –NOVEMBER 2022 –REVISED DECEMBER 2022

www.ti.com.cn

EXAMPLE STENCIL DESIGN

RTJ0020L

WQFN - 0.8 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

(0.59) TYP

20X (0.6)

20X (0.25)

16X (0.5)

(0.59) TYP

(3.8)

SYMM

4X ( 0.98)

(R0.05) TYP

SYMM

(3.8)

SOLDER PASTE EXAMPLE

BASED ON 0.125 MM THICK STENCIL

SCALE: 20X

EXPOSED PAD 21

79% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE

4228235/A 12/2021

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may oﬀer better paste release. IPC-7525 may have alternate

design recommendations.

www.ti.com

Submit Document Feedback

Product Folder Links: TPS7A53A-Q1

PACKAGE OPTION ADDENDUM

www.ti.com

28-May-2023

PACKAGING INFORMATION

Orderable Device

Status Package Type Package Pins Package

Eco Plan

Lead finish/

Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

(1)

(2)

(3)

(4/5)

(6)

PTPS7A5310AQWRTJQ1

TPS7A5310AQWRTJRQ1

ACTIVE

QFN

RTJ

3000 RoHS & Green

NIPDAU

Level-2-260C-1 YEAR

-40 to 150

P7A5310

7A5310A

Samples

NIPDAU

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

⁽³⁾MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

⁽⁵⁾Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6)

Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

28-May-2023

Addendum-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

12-Mar-2023

TAPE AND REEL INFORMATION

REEL DIMENSIONS

TAPE DIMENSIONS

Reel

Diameter

Cavity

A0 Dimension designed to accommodate the component width

B0 Dimension designed to accommodate the component length

K0 Dimension designed to accommodate the component thickness

Overall width of the carrier tape

P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2

Q3 Q4

Q1 Q2

Q3 Q4

User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

TPS7A5310AQWRTJRQ1 QFN

RTJ

3000

330.0

12.4

4.25

1.15

8.0

12.0

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

12-Mar-2023

TAPE AND REEL BOX DIMENSIONS

Width (mm)

*All dimensions are nominal

Device

Package Type Package Drawing Pins

QFN RTJ 20

SPQ

Length (mm) Width (mm) Height (mm)

360.0 360.0 36.0

TPS7A5310AQWRTJRQ1

3000

Pack Materials-Page 2

GENERIC PACKAGE VIEW

RTJ 20

4 x 4, 0.5 mm pitch

WQFN - 0.8 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

This image is a representation of the package family, actual package may vary.

Refer to the product data sheet for package details.

4224842/A

www.ti.com

PACKAGE OUTLINE

RTJ0020L

WQFN - 0.8 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

4.15

3.85

PIN 1 INDEX AREA

4.15

3.85

0.07 MIN

(0.13)

SECTION A-A

TYPICAL

0.8

0.7

SEATING PLANE

0.08 C

0.05

0.00

2.2 0.1

2X 2

SYMM

(0.2) TYP

EXPOSED

THERMAL PAD

(0.16) TYP

SYMM

2X 2

16X 0.5

0.3

0.2

20X

PIN 1 ID

0.1

C A B

0.5

0.05

20X

0.3

4228235/A 12/2021

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

www.ti.com

EXAMPLE BOARD LAYOUT

RTJ0020L

WQFN - 0.8 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

(

2.2)

SYMM

SEE SOLDER MASK

DETAIL

20X (0.6)

20X (0.25)

16X (0.5)

(0.85)

SYMM

(3.8)

(R0.05) TYP

(

0.2) TYP

VIA

(0.85)

(3.8)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE: 20X

0.07 MIN

ALL AROUND

0.07 MAX

ALL AROUND

METAL UNDER

SOLDER MASK

METAL EDGE

EXPOSED METAL

SOLDER MASK

OPENING

EXPOSED

METAL

SOLDER MASK

OPENING

NON SOLDER MASK

SOLDER MASK DEFINED

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

4228235/A 12/2021

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

number SLUA271 (www.ti.com/lit/slua271).

5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown

on this view. It is recommended that vias under paste be filled, plugged or tented.

www.ti.com

EXAMPLE STENCIL DESIGN

RTJ0020L

WQFN - 0.8 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

(0.59) TYP

20X (0.6)

20X (0.25)

16X (0.5)

(0.59) TYP

(3.8)

SYMM

4X ( 0.98)

(R0.05) TYP

SYMM

(3.8)

SOLDER PASTE EXAMPLE

BASED ON 0.125 MM THICK STENCIL

SCALE: 20X

EXPOSED PAD 21

79% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE

4228235/A 12/2021

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

www.ti.com

重要声明和免责声明

TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，

不保证没有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担

保。

这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验

证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。

这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。

您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成

本、损失和债务，TI 对此概不负责。

TI 提供的产品受 TI 的销售条款或 ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI 提供这些资源并不会扩展或以其他方式更改

TI 针对 TI 产品发布的适用的担保或担保免责声明。

TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE

邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

TPS7A53A-Q1 [TI]

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