TPS7A7002 [TI]
具有使能功能的 3A、低输入电压 (1.4V)、可调节超低压降稳压器;
| 型号： | TPS7A7002 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有使能功能的 3A、低输入电压 (1.4V)、可调节超低压降稳压器 稳压器 |
| 文件： | 总23页 (文件大小：1784K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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TPS7A7002
ZHCSBT7D –MAY 2013–REVISED APRIL 2017
TPS7A7002 具有使能端的极低输入、极低压降 3A 稳压器
1 特性
3 说明
1
•
输入电压低至 1.425V
2A 时，最大压降 380mV
TPS7A7002 是一款高性能、正电压、低压降 (LDO)
稳压器，针对 要求 在高达 3A 的电流下拥有超低输入
电压和超低压降的应用而设计。该器件支持低至
1.425V 的单输入电压，输出电压最低可通过编程设置
为 0.5V。输出电压可使用外部分压器进行设置。
•
•
•
•
•
•
•
•
3A 时，最大压降 600mV
从 0.5V 开始的可调输出
保护：电流限制和热关断
启用引脚
TPS7A7002 具有 超低压降，非常 适用于 VOUT 与 VIN
极为接近的应用。此外， TPS7A7002 还有使能引脚以
便在关断模式下进一步减少功率耗散。TPS7A7002 在
线路、负载和温度变化时提供出色的稳压功能。
关断模式下的接地电流为 1µA
完整工业温度范围
采用小外型尺寸集成电路 (SOIC)-8，完全 RoHS
标准兼容封装
TPS7A7002 提供 8 引脚小型 PowerPAD™封装选
项。
2 应用
•
•
•
•
•
•
•
•
电信和网卡
器件信息(1)
主板和外设卡
工业应用
器件型号
封装
封装尺寸（标称值）
TPS7A7002
SO PowerPAD (8)
3.90mm x 4.89mm
无线基础设施
机顶盒
(1) 要了解所有可用封装，请参见数据表末尾的封装选项附录。
医疗设备
笔记本电脑
电池供电系统
典型应用
压降与输出电流间的关系
(VOUT = 3.3V)
400
NC
NC
−40°C
25°C
125°C
TPS7A7002
350
300
250
200
150
100
50
Input Voltage
CIN
Output Voltage
IN
OUT
FB
COUT
R1
R2
Enable
EN
NC
GND
R1
VOUT = 0.5 ´ 1 +
R2
0
0
500m
1
1.5
2
Output Current (A)
G003
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SBVS209
TPS7A7002
ZHCSBT7D –MAY 2013–REVISED APRIL 2017
www.ti.com.cn
目录
1
2
3
4
5
6
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ..................................... 4
6.2 ESD Ratings.............................................................. 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information.................................................. 4
6.5 Electrical Characteristics........................................... 5
6.6 Typical Characteristics.............................................. 6
Detailed Description .............................................. 7
7.1 Overview ................................................................... 7
7.2 Functional Block Diagram ......................................... 7
7.3 Feature Description................................................... 7
7.4 Device Functional Modes.......................................... 8
8
9
Application and Implementation .......................... 9
8.1 Application Information.............................................. 9
8.2 Typical Application .................................................. 10
Power Supply Recommendations...................... 11
10 Layout................................................................... 11
10.1 Layout Guidelines ................................................. 11
10.2 Layout Example .................................................... 12
10.3 Thermal Consideration.......................................... 12
10.4 Power Dissipation ................................................. 12
11 器件和文档支持 ..................................................... 13
11.1 器件支持................................................................ 13
11.2 文档支持................................................................ 13
11.3 接收文档更新通知 ................................................. 13
11.4 社区资源................................................................ 13
11.5 商标....................................................................... 13
11.6 静电放电警告......................................................... 13
11.7 Glossary................................................................ 13
12 机械、封装和可订购信息....................................... 13
7
4 修订历史记录
注：之前版本的页码可能与当前版本有所不同。
Changes from Revision C (July 2015) to Revision D
Page
•
Changed OUT pin description text from "TI recommends using at least a 4.7-μF ceramic capacitor, and up to 10 μF
for a good transient response." to " A 4.7-μF or larger capacitor of any type is required for stability." for clarity.................. 3
•
•
Changed "operating free-air" to "junction" in Absolute Maximum Ratings table condition line ............................................. 4
Added rows for enable pin voltage, input capacitor, output capacitor, and feedforward capacitance to
Recommended Operating Conditions table............................................................................................................................ 4
•
•
•
Added min value of 0 to output current in Recommended Operating Conditions table ......................................................... 4
Changed note (1) in Electrical Characteristics table; deleted initial reference to R1 and updated R2 resistor range............. 5
Changed Output Capacitor (OUT) section; reworded for clarity............................................................................................. 9
Changes from Revision B (November 2013) to Revision C
Page
•
已添加 ESD 额定值表，特性 描述部分，器件功能模式，应用和实施部分，电源相关建议部分，布局部分，器件和文
档支持部分以及机械、封装和可订购信息部分。 .................................................................................................................... 1
Changes from Revision A (September 2013) to Revision B
Page
•
•
将数据表状态从产品预览改为生产数据................................................................................................................................... 1
Added pin 1 identifier (black bar) to pinout diagram............................................................................................................... 3
Changes from Original (May 2013) to Revision A
Page
•
Changed product preview data sheet..................................................................................................................................... 7
2
Copyright © 2013–2017, Texas Instruments Incorporated
TPS7A7002
www.ti.com.cn
ZHCSBT7D –MAY 2013–REVISED APRIL 2017
5 Pin Configuration and Functions
DDA Package
8-Pin SO PowerPAD
Top View
NC
EN
IN
GND
FB
1
2
3
4
8
7
6
5
PowerPAD
OUT
NC
NC
Pin Functions
PIN
I/O
DESCRIPTION
NAME
NO.
Enable input. Pulling this pin to less than 0.5 V turns the regulator off. Connect to VIN if not
being used.
EN
2
I
This pin is the output voltage feedback input through voltage dividers. See Table 2 for more
details.
FB
7
8
3
I
—
I
GND
IN
Ground pin
Input pin. Although it is not required for stability, TI recommends connecting a 1-μF to 10-μF
capacitor with low equivalent series resistance (ESR) across this pin and GND.
Not internally connected. The NC pins are not connected to any electrical node. TI
recommends connecting the NC pins to large-area planes.
NC
1, 4, 5
6
—
O
OUT
Regulated output pin. A 4.7-μF or larger capacitor of any type is required for stability.
TI strongly recommends connecting the thermal pad to a large-area ground plane. If an
electrically floating, dedicated thermal plane is available, the thermal pad can also be
connected to it.
PowerPAD
—
—
Copyright © 2013–2017, Texas Instruments Incorporated
3
TPS7A7002
ZHCSBT7D –MAY 2013–REVISED APRIL 2017
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6 Specifications
6.1 Absolute Maximum Ratings
over junction temperature range (unless otherwise noted)(1)
MIN
–0.3
–0.3
MAX
7
VIN + 0.3(2)
UNIT
V
IN
Voltage
EN, FB, OUT
Current
OUT
Internally limited
A
Operating virtual junction, TJ
Storage temperature, Tstg
–55
–55
150
150
Temperature
°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The absolute maximum rating is VIN + 0.3 V or 7 V, whichever is smaller.
6.2 ESD Ratings
VALUE
±2000
±500
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
V(ESD)
Electrostatic discharge
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
MIN
1.425
0
NOM
MAX
6.5
VIN
10
UNIT
VIN
Input voltage
V
V
VEN
CIN
Enable pin voltage
Input capacitor
1
µF
µF
nF
A
COUT
CFB
IOUT
TJ
Output capacitor(1)(2)
Feedforward capacitance
Output current
4.7
0
10
200
100
3
0
Junction temperature
–40
125
°C
(1) See Figure 1 and Figure 2 for additional output capacitor ESR requirements.
(2) For output capacitors larger than 47 µF, a feedforward capacitor of at least 220 pF must be used.
6.4 Thermal Information
TPS7A7002
DDA (SO
PowerPAD)
THERMAL METRIC(1)
UNIT
8 PINS
46.4
54.2
29.9
10.2
29.8
6.8
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
ψJB
RθJC(bot)
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
4
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TPS7A7002
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ZHCSBT7D –MAY 2013–REVISED APRIL 2017
6.5 Electrical Characteristics
Over the full operating temperature range (see Recommended Operating Conditions), VEN = 1.1 V, VFB = VOUT(1), 1.425 V ≤
VIN ≤ 6.5 V, 10 µA ≤ IOUT ≤ 3 A, COUT = 10 μF (unless otherwise noted). Typical values are at TJ = 25°C.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
INPUT VOLTAGE
VIN = 3.3 V,
50-Ω load resistor between OUT and GND
GND pin current
3
5
mA
µA
IGND
Shutdown GND pin current
VIN = 6.5 V, VEN = 0 V
OUTPUT VOLTAGE
VIN = VOUT + 0.5 V(4), IOUT = 10 mA
VIN = 1.8 V, IOUT = 0.8 A, 0°C ≤ TJ = TA ≤ 85°C
IOUT = 10 mA
–2%
–2%
–3%
2%
2%
VOUT
Output voltage accuracy(2)(3)
3%
ΔVO(ΔVI)
ΔVO(ΔIO)
Line regulation
IOUT = 10 mA
0.2
0.4
%/V
%/A
Load regulation(3)
10 mA ≤ IOUT ≤ 3 A
0.25
0.75
200
380
600
IOUT = 1 A, 0.5 V ≤ VOUT ≤ 5 V
IOUT = 2 A, 0.5 V ≤ VOUT ≤ 5 V
IOUT = 3 A, 0.5 V ≤ VOUT ≤ 4.8 V
VIN = 1.425 V, VOUT = 0.9 × VOUT(NOM)
(5)
VDO
Dropout voltage
mV
A
ICL
Output current limit
3.36
0.49
FEEDBACK
VREF
Reference voltage accuracy
FB pin current
VIN = 3.3 V, IOUT = 10 mA
VFB = 0.5 V
0.5
0.51
1
V
IFB
µA
ENABLE
IEN
EN pin current
VEN = 0 V, VIN = 3.3 V
VIN = 3.3 V
0.2
0.5
VIN
µA
V
VEN(LO)
EN pin input low (disable)
EN pin input high (enable)
0
VEN(HI)
VIN = 3.3 V
1.1
V
TEMPERATURE
Shutdown, temperature increasing
Reset, temperature decreasing
160
140
TSD
Thermal shutdown temperature
°C
(1) When setting VOUT to a value other than 0.5 V, connect R2 to the FB pin using 27-kΩ ≤ R2 ≤ 33-kΩ resistors. See Figure 7 for details of
R1 and R2.
(2) Accuracy does not include error on feedback resistors R1 and R2.
(3) TPS7A7002 is not tested at VOUT = 0.5 V, 2.3 V ≤ VIN ≤ 6.5 V, and 500 mA ≤ IOUT ≤ 3 A because the power dissipation is higher than
the maximum rating of the package. Also, this accuracy specification does not apply to any application condition that exceeds the power
dissipation limit of the package.
(4) VIN = VOUT + 0.5 V or 1.425 V, whichever is greater.
(5) VDO = VIN – VOUT with VFB = GND configuration.
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6.6 Typical Characteristics
for all fixed voltage versions and an adjustable version at TJ = 25°C, VEN = VIN, CIN = 10 μF, COUT = 10 μF, and using the
component values in Table 2 (unless otherwise noted)
10
1
10
1
Region of Instability
Region of Instability
100m
10m
1m
100m
10m
1m
Stable Region
Stable Region
Region of Instability
Region of Instability
100u
100u
0
500m
1
Output Current (A)
1.5
2
0
500m
1
Output Current (A)
1.5
2
G000
G001
COUT = 10 µF
COUT = 100 µF
Figure 1. Stability Curve
Figure 2. Stability Curve
70
60
50
40
30
20
10
400
350
300
250
200
150
100
50
IOUT = 0.1 A
IOUT = 1 A
−40°C
25°C
125°C
0
0
0
10
100
1k
10k
100k
1M
10M
500m
1
1.5
2
Frequency (Hz)
Output Current (A)
G002
G003
VIN = 5 V, VOUT = 3.3 V
VOUT = 3.3 V
Figure 3. Power-Supply Ripple Rejection vs Frequency
Figure 4. Dropout Voltage vs Output Current
400
400
350
300
250
200
150
100
50
−40°C
25°C
125°C
−40°C
25°C
125°C
350
300
250
200
150
100
50
0
0
0
500m
1
1.5
2
0
500m
1
1.5
2
Output Current (A)
Output Current (A)
G004
G005
VOUT = 1.6 V
Figure 5. Dropout Voltage vs Output Current
VOUT = 1.4 V
Figure 6. Dropout Voltage vs Output Current
6
Copyright © 2013–2017, Texas Instruments Incorporated
TPS7A7002
www.ti.com.cn
ZHCSBT7D –MAY 2013–REVISED APRIL 2017
7 Detailed Description
7.1 Overview
The TPS7A7002 offers a high current supply with very-low dropout voltage. The TPS7A7002 is designed to
minimize the required component count for a simple, small-size, and low-cost solution.
7.2 Functional Block Diagram
OUT
Current
Limit
VOUT
IN
R1
R2
VOUT = 0.5 x (1 +
)
UVLO
Thermal
Charge
Pump
Protection
R1
R2
0.5V Reference
FB
Hysteresis
EN
GND
Figure 7. Adjustable Output Voltage Version
7.3 Feature Description
7.3.1 Internal Current Limit
The TPS7A7002 internal current limit helps protect the regulator during fault conditions. During a current limit
condition, the output sources a fixed amount of current largely independent of output voltage. For reliable
operation, do not operate the device in a current limit state for an extended period of time.
Powering on the device with the enable pin, or increasing the input voltage above the minimum operating voltage
while a low-impedance short exists on the output of the device, may result in a sequence of high-current pulses
from the input to the output of the device. The energy consumed by the device is minimal during these events;
therefore, there is no failure risk. Additional input capacitance helps to mitigate the load transient requirement of
the upstream supply during these events.
7.3.2 Enable (EN)
The enable pin (EN) is an active-high logic input. When it is logic low, the device turns off, and the consumption
current is less than 1 µA. When it is logic high, the device turns on. The EN pin must be connected to a logic
high or logic low level.
When the enable function is not required, connect EN to IN.
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TPS7A7002
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7.4 Device Functional Modes
Table 1 provides a quick comparison between the normal, dropout, and disabled modes of operation.
Table 1. Device Functional Mode Comparison
PARAMETER
OPERATING MODE
VIN
EN
IOUT
IOUT < ICL
IOUT < ICL
—
TJ
TJ < TSD
Normal
Dropout
Disabled
VIN > VOUT(nom) + VDO
VIN < VOUT(nom) + VDO
—
VEN > VEN(HI)
VEN > VEN(HI)
VEN < VEN(LO)
TJ < TSD
TJ > TSD
7.4.1 Normal Operation
The device regulates to the nominal output voltage under the following conditions:
•
•
The input voltage is greater than the nominal output voltage plus the dropout voltage (VOUT(nom) + VDO).
The enable voltage has previously exceeded the enable rising threshold voltage and not yet decreased below
the enable falling threshold.
•
•
The output current is less than the current limit (IOUT < ICL).
The device junction temperature is less than the thermal shutdown temperature (TJ < TSD).
7.4.2 Dropout Operation
If the input voltage is lower than the nominal output voltage plus the specified dropout voltage, but all other
conditions are met for normal operation, the device operates in dropout mode. In this mode, the output voltage
tracks the input voltage. During this mode, the transient performance of the device becomes significantly
degraded because the pass device is in a triode state and no longer controls the current through the LDO. Line
or load transients in dropout can result in large output-voltage deviations.
8
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TPS7A7002
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ZHCSBT7D –MAY 2013–REVISED APRIL 2017
8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The TPS7A7002 offers a high current supply with very-low dropout voltage, and it is designed to minimize the
required component count for a simple, small-size, and low-cost solution. This section discusses the
implementation of the TPS7A7002 LDO.
8.1.1 Input Capacitor (IN)
An input capacitor is not required for stability; however, TI recommends connecting a 1-µF to 10-µF low
equivalent series resistance (ESR) capacitor across IN and GND as close as possible to the device.
8.1.2 Output Capacitor (OUT)
The TPS7A7002 is stable with standard ceramic capacitors with capacitance values from 4.7 μF to 47 μF without
a feedforward capacitor. For output capacitors from 47 μF to 200 μF, a feedforward capacitor of at least 220 pF
must be used. The TPS7A7002 is evaluated using an X5R-type, 10-μF ceramic capacitor. X5R- and X7R-type
capacitors are recommended because of minimal variation in value and ESR over temperature. Maximum ESR
must be less than 1 Ω.
As with any regulator, increasing the size of the output capacitor reduces overshoot and undershoot magnitude,
but increases duration of the transient response.
8.1.3 Feedback Resistors (FB)
The voltage on the FB pin sets the output voltage and is determined by the values of R1 and R2. Use Equation 1
to calculate the values of R1 and R2 for any voltage.
æ
ö
R1
VOUT = VREF ´ 1+
ç
÷
R2 ø
è
(1)
Table 2 shows the recommended resistor values for the best performance of the TPS7A7002. If the values in
Table 2 are not used, keep the value of R2 from 27 kΩ to 33 kΩ. In Table 2, E96 series resistors are used. For
the actual design, pay attention to any resistor error factors.
Table 2. Sample Resistor Values for Common Output Voltages
VOUT
1
R1 (kΩ)
30.1
42.2
60.4
78.7
121
R2 (kΩ)
30.1
30.1
30.1
30.1
30.1
30.1
30.1
30.1
1.2
1.5
1.8
2.5
3
150
3.3
5
169
274
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8.2 Typical Application
This section describes the implementation of the TPS7A7002, using the feedback pin to configure the output
voltage and regulate a 2-A load at 1.4 V using a 1.6-V input voltage, operating in a temperature range of 25°C to
85°C. Figure 8 shows the schematic for this typical application circuit.
NC
IN
NC
OUT
FB
TPS7A7002
Input Voltage
CIN
Output Voltage
COUT
R1
R2
Enable
EN
NC
GND
R1
VOUT = 0.5 ´ 1 +
R2
Figure 8. Typical Application Schematic
8.2.1 Design Requirements
For this design example, use the parameters listed in Table 3 as the input parameters.
Table 3. Design Parameters
PARAMETER
Input voltage
DESIGN REQUIREMENT
1.6 V ±3%
Output voltage
1.4 V ±3%
Maximum output current
Ambient temperature
2 A
25°C ≤ TA ≤ 75°C
8.2.2 Detailed Design Procedure
At IOUT = 2 A, the TPS7A7002 has a maximum dropout of less than 150 mV over temperature, as seen in
Figure 9; thus, a 200-mV headroom is sufficient for operation over both input and output voltage accuracy.
To achieve 1.2 V on the output, choose the correct feedback resistors. The Feedback Resistors (FB) section
suggests keeping the value of R2 in the range of 27 kΩ to 33 kΩ, so select R2 to be 30.1 kΩ, a standard resistor
in the E96 series. Using Equation 1 to achieve a 1.4-V output, determine the size for R1 using Equation 2.
R1 = ((2 × VOUT) – 1) × R2
(2)
Given that R2 = 30.1 kΩ and VOUT = 1.4 V, R1 = 54.2 kΩ. The closest resistor in the E96 series is 53.6 kΩ, giving
an output voltage within the output design requirements.
With a headroom voltage of 200 mV and a 2-A maximum load, the internal power dissipation is 400 mW, and
corresponds to a 18.56°C junction temperature rise for the DDA package.
With a 75°C maximum ambient temperature as per design constraints, the junction temperature is at 93.56°C,
and satisfies the recommended operating junction temperature range.
10
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8.2.3 Application Curve
400
350
300
250
200
150
100
50
−40°C
25°C
125°C
0
0
500m
1
1.5
2
Output Current (A)
G005
VOUT = 1.4 V
Figure 9. Dropout Voltage vs Output Current
9 Power Supply Recommendations
These devices are designed to operate from an input voltage supply range from 1.425 V to 6.5 V. The input
voltage range provides adequate headroom for the device to have a regulated output. This input supply is well
regulated and stable. If the input supply is noisy, additional input capacitors with low ESR can help improve the
output noise performance.
10 Layout
10.1 Layout Guidelines
For best performance, place all circuit components on the same side of the circuit board, and place the external
components as close to the device as practically possible. The use of vias and long traces is strongly
discouraged because of parasitics that might affect performance; follow these guidelines to minimize parasitics.
Also, embed a ground reference plane to maintain accuracy of the output voltage and shield noise. Make sure
that this plane is connected to the PowerPAD in order to help spread (or sink) heat from the device; be aware
that NC pins might be connected to this plane. The recommended layout is shown in Figure 10.
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10.2 Layout Example
R2
TPS7A7002
R1
1
2
3
4
8
7
6
5
NC
EN
IN
GND
FB
VEN
CIN
VIN
OUT
NC
VOUT
NC
COUT
GND PLANE
Figure 10. Layout Recommendation
10.3 Thermal Consideration
Thermal protection disables the output when the junction temperature rises to approximately 160°C, allowing the
device to cool. When the junction temperature cools to approximately 140°C, the output circuitry is re-enabled.
The internal protection circuitry of the TPS7A7002 is designed to protect against overload conditions. The
protection circuitry is not intended to replace proper heat sinking. Continuously running the TPS7A7002 into
thermal shutdown degrades device reliability.
10.4 Power Dissipation
Power dissipation (PD) of the device depends on the input voltage and load conditions, and is calculated using
Equation 3.
P = VIN - VOUT ìI
D
OUT
(3)
In order to minimize power dissipation and achieve greater efficiency, use the lowest possible input voltage
necessary to achieve the required output voltage regulation
On the SOIC (DDA) package, the primary conduction path for heat is through the exposed pad to the PCB. The
pad can either be connected to ground or left floating; however, attach the pad to an appropriate amount of
copper PCB area to prevent the device from overheating. The maximum junction-to-ambient thermal resistance
depends on the maximum ambient temperature, maximum device junction temperature, and power dissipation of
the device, and is calculated using Equation 4:
+125°C - TA
RqJA
=
PD
(4)
12
版权 © 2013–2017, Texas Instruments Incorporated
TPS7A7002
www.ti.com.cn
ZHCSBT7D –MAY 2013–REVISED APRIL 2017
11 器件和文档支持
11.1 器件支持
11.1.1 器件命名规则
产品(1)
TPS7A7002yyyz
说明
YYY 为封装标识符。
Z 为封装数量。
(1) 要获得最新的封装和订货信息，请参阅本文档末尾的封装选项附录，或者访问器件产品文件夹，此文件夹位于www.ti.com内。
11.2 文档支持
11.2.1 相关文档ꢀ
相关文档如下：
•
•
TI LDO 应用手册的主题索引
半导体和集成电路 (IC) 封装热度量
11.3 接收文档更新通知
如需接收文档更新通知，请访问 www.ti.com.cn 网站上的器件产品文件夹。点击右上角的提醒我 (Alert me) 注册
后，即可每周定期收到已更改的产品信息。有关更改的详细信息，请查阅已修订文档中包含的修订历史记录。
11.4 社区资源
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.5 商标
PowerPAD, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
11.6 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
11.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 机械、封装和可订购信息
以下页中包括机械、封装和可订购信息。这些信息是针对指定器件可提供的最新数据。这些数据会在无通知且不对
本文档进行修订的情况下发生改变。欲获得该数据表的浏览器版本，请查阅左侧的导航栏。
版权 © 2013–2017, Texas Instruments Incorporated
13
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPS7A7002DDA
TPS7A7002DDAR
ACTIVE SO PowerPAD
ACTIVE SO PowerPAD
DDA
DDA
8
8
75
RoHS & Green
NIPDAUAG
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 125
-40 to 125
SJA
SJA
2500 RoHS & Green
NIPDAUAG
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2022
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS7A7002DDAR
SO
Power
PAD
DDA
8
2500
330.0
12.8
6.4
5.2
2.1
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2022
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SO PowerPAD DDA
SPQ
Length (mm) Width (mm) Height (mm)
366.0 364.0 50.0
TPS7A7002DDAR
8
2500
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2022
TUBE
*All dimensions are nominal
Device
Package Name Package Type
DDA HSOIC
Pins
SPQ
L (mm)
W (mm)
T (µm)
B (mm)
TPS7A7002DDA
8
75
517
7.87
635
4.25
Pack Materials-Page 3
GENERIC PACKAGE VIEW
DDA 8
PowerPADTM SOIC - 1.7 mm max height
PLASTIC SMALL OUTLINE
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4202561/G
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