TPS7A7850PWPT [TI]

120mA 智能电容降压型低压降 (LDO) 线性稳压器 | PWP | 14 | -40 to 125;


型号：	TPS7A7850PWPT
厂家：	TEXAS INSTRUMENTS
描述：	120mA 智能电容降压型低压降 (LDO) 线性稳压器 \| PWP \| 14 \| -40 to 125 光电二极管稳压器
文件：	总40页 (文件大小：2035K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

Support &

Community

Reference

Design

Product

Folder

Order

Now

Tools &

Software

Technical

Documents

TPS7A78

ZHCSJG2A –MARCH 2019–REVISED SEPTEMBER 2019

TPS7A78 120mA 智能交流/直流线性稳压器

1 特性

3 说明

•

适用于交流电压 ≥ 18V_{AC RMS}的非隔离式电源解决

方案：

TPS7A78 提高了电源的整体效率并改进了待机功耗，

实现了简单易用的非磁性交流/直流转换方案。

TPS7A78 采用了电容降压架构，可在主动钳制整流电

压前降低交流电源电压。该器件还可将此整流电压降至

应用特定的工作电压。由于器件采用独特的架构，因而

可将待机功耗降至仅几十毫瓦。TPS7A78 开关电容器

级按照 P_IN≅ P_OUT以及 V_IN≅ V_OUT× 4 将整流输入电

压降低至原来的四分之一，并以相同的比例提升输出到

输入电流，从而降低功率损耗。相较于传统的电容压降

级，此类降压能减小输入电流，从而最大限度降低所需

的电容值。

–

效率高达 75%

待机功耗：15mW（典型值）

线路电压、电容压降电容器的大小仅为线性解决

方案大小的四分之一

•

可提供固定输出电压：

1.3V 至 5V（50mV 阶跃）

–

•

电源故障检测

电源正常指示

典型精度为 1%

封装：

电量计量应用中的电源必须可靠且可防范磁篡改，由

于 TPS7A78 无需外部磁体，因此采用该器件可为此类

应用带来优势。借助此特性，您可以更轻松地达到 IEC

61000-4-8 标准，同时最大限度地降低磁屏蔽成本。

–

5mm × 6.5mm HTSSOP-14 (PWP)

2 应用

•

键盘

车库门系统

小型家用电器

电表

此外，TPS7A78 还具有用户可编程的电源故障检测阈

值，可对电源故障进行早期预警，并可在系统完全断电

之前执行关断。器件还配备了电源正常指示器 (PG)，

可用于定序或对微控制器进行复位。

烟雾和热量探测器

恒温器

TPS7A78 采用 14 引脚 HTSSOP (PWP) 封装。

器件信息⁽¹⁾

器件型号

TPS7A78

封装

封装尺寸（标称值）

HTSSOP (14)

5.00mm × 6.50mm

(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附

录。

半桥配置典型原理图

全桥配置典型原理图

SC1-

SC2-

C_SC1

C_SC2

SC1+

SC2+

SC1+

SC2+

C_SCIN

Optional

SCIN

PFD

GND

SCIN

PFD

GND

Optional

V_PG

TPS7A78

V_PF

C_S

R_S

AC+

GND

ACœ

AC+

GND

ACœ

Connect AC- to

device GND for

Half-Bridge

V_AC

LDO_IN

TVS

C_{LDO_IN}

Configuration

V_{LDO_OUT}

LDO_OUT

C_{LDO_OUT}

本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确

性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: SBVS343

TPS7A78

ZHCSJG2A –MARCH 2019–REVISED SEPTEMBER 2019

www.ti.com.cn

7.4 Device Functional Modes........................................ 14

Application and Implementation ........................ 15

8.1 Application Information............................................ 15

8.2 Typical Application .................................................. 23

Power Supply Recommendations...................... 29

特性.......................................................................... 1

应用.......................................................................... 1

说明.......................................................................... 1

修订历史记录 ........................................................... 2

Pin Configuration and Functions......................... 3

Specifications......................................................... 4

6.1 Absolute Maximum Ratings ...................................... 4

6.2 ESD Ratings.............................................................. 4

6.3 Recommended Operating Conditions....................... 5

6.4 Thermal Information.................................................. 5

6.5 Electrical Characteristics........................................... 6

6.6 Timing Requirements................................................ 6

6.7 Typical Characteristics.............................................. 7

Detailed Description ............................................ 10

7.1 Overview ................................................................. 10

7.2 Functional Block Diagram ....................................... 10

7.3 Feature Description ................................................ 11

10 Layout................................................................... 29

10.1 Layout Guidelines ................................................. 29

10.2 Layout Example .................................................... 29

11 器件和文档支持 ..................................................... 30

11.1 器件支持................................................................ 30

11.2 文档支持................................................................ 30

11.3 接收文档更新通知 ................................................. 30

11.4 社区资源................................................................ 30

11.5 商标....................................................................... 30

11.6 静电放电警告......................................................... 30

11.7 Glossary................................................................ 31

12 机械、封装和可订购信息....................................... 31

4 修订历史记录

注：之前版本的页码可能与当前版本有所不同。

Changes from Original (March 2019) to Revision A

Page

•

已更改将器件状态从 APL 更改为生产数据 ............................................................................................................................ 1

TPS7A78

www.ti.com.cn

ZHCSJG2A –MARCH 2019–REVISED SEPTEMBER 2019

5 Pin Configuration and Functions

PWP Package

14-Pin HTSSOP

Top View

SC1œ

SC1+

SCIN

PFD

SC2œ

SC2+

GND

Thermal

Pad

AC+

GND

ACœ

LDO_IN

LDO_OUT

Not to scale

Pin Functions

NAME

TYPE

DESCRIPTION

NO.

Negative terminal of the switched-capacitor, voltage-reduction stage pin. Connect a minimum 1-

µF, X5R (or better) dielectric, 16-V-rated capacitor between this pin and the SC1+ pin. Place the

capacitor as close to the device as possible; see the Recommended Operating Conditions table

for details.

SC1–

—

Positive terminal of the switched-capacitor, voltage-reduction stage pin. Connect a minimum 1-

µF, X5R (or better) dielectric, 16-V-rated capacitor between this pin and the SC1– pin. Place the

capacitor as close to the device as possible; see the Recommended Operating Conditions table

for details.

SC1+

SCIN

PFD

—

Rectified DC-voltage pin. Place the capacitor as close to the device as possible; see the Device

Functional Modes section for the dual-input power-supply capability and the Calculating the Bulk

Capacitor section for the proper capacitor calculation.

Power-failure detect pin. An analog voltage input compares the reference voltage to a resistor-

divided V_SCINvoltage to detect a V_ACpower-failure; see the Recommended Operating Conditions

table and the Calculating the PFD Pin Resistor Dividers for Power-Fail Detection section for

details.

Input

AC-supply line or neutral input to the device after the capacitive-drop (cap-drop) capacitor and

surge resistor. Either this pin or the AC– pin must have the cap-drop capacitor and surge resistor

in series with the line. See the Full-Bridge (FB) and Half-Bridge (HB) Configurations section for

details.

AC+

Power

Ground pin. All device ground pins must be referenced to the same ground. Connect this pin to

the thermal pad at the bottom of the device; see the Layout section for details.

GND

AC–

Ground

Power

AC-supply line or neutral input to the device pin after the cap-drop capacitor and surge resistor.

Either this pin or the AC+ pin must have the cap-drop capacitor and surge resistor in series with

the line. See the Full-Bridge (FB) and Half-Bridge (HB) Configurations section for details.

Regulated DC output pin. Connect a minimum 0.68-µF, X5R (or better) dielectric capacitor

between this pin and the device GND pins. Place the capacitor as close to the device as possible;

see the Recommended Operating Conditions table for the maximum capacitor value.

LDO_OUT

LDO_IN

Output

—

Charge-pump output pin. Connect a minimum 0.68-µF, X5R (or better) dielectric capacitor

between this pin and the device GND pins. This pin is internally driven and must not be driven

externally. For optimal performance, connect a capacitor that is 10x the value of C_{LDO_OUT}placed

as close to the device as possible. See the Recommended Operating Conditions table for the

maximum capacitor value.

Power-fail indicator pin. An open-drain indicator signal indicates if the V_ACsupply has failed.

Pullup this pin through an external resistor to V_{LDO_IN}or to a DC-rail that shares the same GND

as the device. The PF pin goes low when V_PFDis less than the V_{IT(PFD,FALLING)}threshold, as

specified in the Electrical Characteristics table. See the Recommended Operating Conditions

table for proper selection of the pullup resistor.

Output

TPS7A78

ZHCSJG2A –MARCH 2019–REVISED SEPTEMBER 2019

www.ti.com.cn

Pin Functions (continued)

TYPE

DESCRIPTION

NO.

NAME

Power-good indication pin. An open-drain indicator signal indicates if the V_{LDO_OUT}surpassed the

V_{IT(PG,RISING)}threshold, as specified in the Electrical Characteristics table. Pullup this pin through

an external resistor to V_{LDO_OUT}or to a DC rail that shares the same GND as the device. See the

Recommended Operating Conditions table for proper selection of the pullup resistor.

Output

Ground

—

Ground pin. All device ground pins must be referenced to the same ground. Connect this pin to

the thermal pad at the bottom of the device; see the Layout section for details.

GND

Positive terminal of the switched-capacitor, voltage-reduction stage pin. Connect a minimum 1-

µF, X5R (or a better) dielectric, 10-V-rated capacitor between this pin and the SC2– pin. Place

the capacitor as close to the device as possible; see the Recommended Operating Conditions

table for details.

SC2+

Negative terminal of the switched-capacitor, voltage-reduction stage pin. Connect a minimum 1-

µF, X5R (or a better) dielectric, 10-V-rated capacitor between this pin and the SC2+ pin. Place

the capacitor as close to the device as possible; see the Recommended Operating Conditions

table for details.

SC2–

—

Exposed pad of the package. Connect this pad to device ground pins. Connect the thermal pad to

a large-area ground plane for best thermal performance.

Thermal pad

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾⁽²⁾

MIN

–1.5

– 0.3

–0.3

MAX

5.5

UNIT

AC+, AC– (V_ACsupply mode only)

SCIN (V_ACsupply mode only, internally driven)

SCIN (DC supply mode only, voltage directly applied on SCIN pin)

Voltage

LDO_OUT

PF, PG

PFD

LDO_OUT pin reverse current⁽³⁾

Current

Maximum output

I_PF, I_PG

Internally limited

– 65

Temperature

Storage, T_STG

150

℃

(1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltages are with respect to the device GND pins (not Earth GND); see the Full Bridge (FB) and Half Bridge (HB)

Configurations section for details.

(3) Exceeding the maximum reverse current into the LDO_OUT pin can cause damage to the device; see the Reverse Current section for

details.

6.2 ESD Ratings

VALUE

UNIT

Human body model (HBM), per

±2000

ANSI/ESDA/JEDEC JS-001, all pins⁽¹⁾

V_(ESD)

Electrostatic discharge

Charged device model (CDM), per JEDEC

specification JESD22-C101, all pins⁽²⁾

±1000

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

TPS7A78

www.ti.com.cn

ZHCSJG2A –MARCH 2019–REVISED SEPTEMBER 2019

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

MIN

18⁽⁵⁾

NOM

MAX

UNIT

V_RMS

(2)

V_AC

f_AC

Connected via C_S⁽³⁾and R_S⁽³⁾⁽⁴⁾on either AC+ or AC–

Line frequency

20,000

2.5

Peak transient current into or out of either the AC+ or AC– pins (during hot

plug for ≤ 100 µs)

I_SURGE

I_SHUNT

V_SCIN

mA_RMS

AC current during shunt event on either AC+ or AC- pins

200

DC supply mode, voltage applied to the SCIN pin for devices with

17⁽⁶⁾

V_{LDO_OUT}≤ 3.4 V

C_SCIN

C_SC1

Bulk capacitor for V_ACsupply mode

Bulk capacitor for DC-supply mode

Switched-capacitor stage 1

Switched-capacitor stage 2

LDO_IN capacitor

1.0

µF

4.7⁽⁷⁾

1000

100

µF

kΩ

℃

C_SC2

C_{LDO_IN}

0.68

C_{LDO_OUT}LDO_OUT capacitor

R₁

PFD top resistor divider

200

R₃& R₄

I_OUT

T_J

Power-good and power-fail pullup resistors

Output current

100

120

Operating junction temperature

–40

125

(1) All voltages are with respect to the device GND pins (not Earth GND); see the Full Bridge (FB) and Half Bridge (HB) Configurations

section for details.

(2) Theoretically there is no upper limit to the V_ACsupply voltage because this voltage is dropped across the C_Scapacitor; see

the Calculating the Cap-Drop Capacitor section for details.

(3) The voltage ratings for the cap-drop capacitor C_Sand the surge resistor R_Smust be able to handle the peak V_ACsupply voltage; see

the Typical Application section for details.

(4) The surge resistor R_Sis required to limit the inrush current into or out off either AC+ or AC– pins during hot-plug or surge current events;

see the Calculating the Surge Resistor section for details.

(5) Only available for devices with ≤ 3.3-V output voltage options.

(6) DC-supply mode is also availabe for 3.6-V devices but with a minmum required V_SCINsupply voltage of 18 V.

(7) A 16 V or higher voltage rating is recommended for the C_SC1capacitor, and a 10 V or higher voltage rating is recommeded for the C_SC2

capacitor.

6.4 Thermal Information

TPS7A78

THERMAL METRIC⁽¹⁾⁽²⁾

PWP (TSSOP)

14 PINS

48.0

UNIT

R_θJA

Junction-to-ambient thermal resistance

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

°C/W

R_θJC(top)

R_θJB

44.0

24.2

Ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

1.6

Ψ_JB

24.1

R_θJC(bot)

7.2

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

(2) Thermal metrics were modeled on a JEDEC Hi-K board in order to provide a standardized layout and measurement technique for

comparison purposes.The An empirical analysis of the impact of board layout on LDO thermal performance application report goes into

detail on how board layout impacts the thermal performance of linear regulators.

TPS7A78

ZHCSJG2A –MARCH 2019–REVISED SEPTEMBER 2019

www.ti.com.cn

6.5 Electrical Characteristics

V_SCIN⁽¹⁾= 4 (V_{LDO_OUT (nom)}+ 0.6 V) + 1 V or 17 V (whichever is greater), C_SCIN= 10 µF, C_S1= 1.0 µF, C_S2= 2.2 µF , C_{LDO_IN}

10 µF, C_{LDO_OUT}= 1.0 µF, and I_OUT= 1 mA (unless otherwise noted);typical values are at T_J= 25°C⁽²⁾

PARAMETER

UVLO_SCIN threshold

TEST CONDITIONS

MIN

TYP

MAX

UNIT

V_{UVLO_SCIN}

V_SCINrising, V_{LDO_OUT(nom)}≤ 3.4 V

rising

UVLO_LDO_IN threshold

rising

V_SCINrising

3.9

V_{UVLO_LDO_IN}

UVLO_LDO_IN threshold

falling

V_SCINfalling

3.5

0.21

ΔV_{LDO_OUT(ΔIOUT)}Load regulation

V_{LDO_OUT}Output voltage accuracy

I_CL

0 mA ≤ I_OUT≤ 120 mA

V_SCIN⁽¹⁾⁽³⁾= 4 (V_{LDO_OUT (nom)}+ 0.6 V) + 3 V,

mV/mA

–2

215

280

0 mA ≤ I_OUT≤ 120 mA

Output current limit

V_{LDO_OUT}= 0.9 x V_{LDO_OUT(nom)}

145

300

SCIN pin quiescent

current

I_{DD_SCIN}

V_{LDO_OUT(nom)}= 3.3 V, I_OUT= 0 mA, no R_3,R₄

µA

V_AC= 120 V, 60 Hz, FB, C_S= 1.0 µF, C_SCIN= 180

µF, V_{LDO_OUT(nom) =}5 V, I_OUT= 10 mA,

scope BW = 10 MHz

V_Ripple

Output voltage ripple

V_{IT(PFD,RISING)}

V_{IT(PFD,FALLING)}

V_HYS(PFD)

PFD pin rising threshold

PFD pin falling threshold

PFD pin hysteresis

V_PFDrising, R₄= 100 kΩ

V_PFDfalling, R₄= 100 kΩ

1.24

1.17

1.42

1.25

110

V_{IT(PG,RISING)}

V_{IT(PG,FALLING)}

V_HYS(PG)

PG pin rising threshold

PG pin falling threshold

PG pin hysteresis

R₃= 100 kΩ, V_SCINrising

R₃= 100 kΩ

90.16

88.5

92 93.84

91.5 %V_{LDO_OUT}

PF and PG pins low-level

ouput voltage

V_OL(PF),(PG)

I_LKG(PF),(PG)

T_SD(Shutdown)

T_SD(Reset)

I_PF,PG= 500 µA

0.2

PF and PG pins open-

drain leakage current

V_PF,PG= 5 V

Thermal shutdown

temperature

Shutdown, temperature increasing

Reset, temperature decreasing

162

135

℃

Thermal shutdown reset

temperature

(1) For V_{LDO_OUT}> 4.4 V, V_SCINis limited to 24 V for testing purposes only.

(2) Electrcial characterestic data tested in DC supply mode equivalent to V_SCINvoltage under AC supply mode.

(3) _SCIN≥ 19 V.

6.6 Timing Requirements

MIN

NOM

MAX

UNIT

µs

t_PF(HL)

t_PG(LH)

f_SC

PF pin going from high to low

PG pin going from low to high

µs

Switched capacitor stage operating frequency

200

kHz

TPS7A78

www.ti.com.cn

ZHCSJG2A –MARCH 2019–REVISED SEPTEMBER 2019

6.7 Typical Characteristics

at operating temperature T_J= 25°C, V_ACsupply = 120 V_RMSper 60 Hz, full-bridge (FB) bridge configuration, C_S= 1.0 µF,

C_SCIN= 220 µF, C_SC1= 1.0 µF, C_SC2= 2.2 µF, C_{LDO_IN}= 10 µF, C_{LDO_OUT}= 1.0 µF, and I_OUT= 1 mA (unless otherwise noted)

0.8

0.6

0.4

0.2

0.8

0.6

0.4

0.2

-40èC

0èC

25èC

85èC

125èC

-40èC

0èC

25èC

85èC

125èC

-0.2

-0.4

-0.6

-0.8

-1

-0.2

-0.4

-0.6

-0.8

-1

Output Current (mA)

100

120

90 110 130 150 170 190 210 230 250 270

V_{AC RMS}

V_{LDO_OUT}= 5.0 V, I_OUT= 0 mA to 120 mA

V_AC= 70 V_RMSto 270 V_RMS, V_{LDO_OUT}= 5.0 V

图 2. V_{LDO_OUT}Accuracy vs I_OUT

图 1. V_{LDO_OUT}Accuracy vs V_ACSupply

0.8

0.6

0.4

0.2

0.8

0.6

0.4

0.2

-40èC

0èC

25èC

85èC

125èC

-40èC

0èC

25èC

85èC

125èC

-0.2

-0.4

-0.6

-0.8

-1

-0.2

-0.4

-0.6

-0.8

-1

DC Supply Voltage on the SCIN Pin (V)

Output Current (mA)

100

120

V_SCIN= 17 V, V_{LDO_OUT}≤ 3.4 V

V_SCIN= 19 V, V_{LDO_OUT}≤ 3.4 V

图 3. V_{LDO_OUT}Accuracy vs DC Supply on the SCIN Pin

图 4. V_{LDO_OUT}Accuracy vs I_OUTDC Supply on the SCIN Pin

3.312

-40èC

0èC

25èC

85èC

-40èC

0èC

25èC

85èC

125èC

3.308

3.304

3.3

3.308

3.304

3.3

3.296

3.292

3.288

3.296

3.292

3.288

Output Current (mA)

100

120

Output Current (mA)

100

120

V_SCIN= 17 V, V_{LDO_OUT}= 3.3 V

图 5. V_{LDO_OUT}vs I_OUTDC Supply on the SCIN Pin

V_SCIN= 19 V, V_{LDO_OUT}= 3.3 V

图 6. V_{LDO_OUT}vs I_OUTDC Supply on the SCIN Pin

TPS7A78

ZHCSJG2A –MARCH 2019–REVISED SEPTEMBER 2019

www.ti.com.cn

Typical Characteristics (接下页)

at operating temperature T_J= 25°C, V_ACsupply = 120 V_RMSper 60 Hz, full-bridge (FB) bridge configuration, C_S= 1.0 µF,

C_SCIN= 220 µF, C_SC1= 1.0 µF, C_SC2= 2.2 µF, C_{LDO_IN}= 10 µF, C_{LDO_OUT}= 1.0 µF, and I_OUT= 1 mA (unless otherwise noted)

1.2076

V_{IT(PG,FALLING)}

V_{IT(PG,RISING)}

1.2074

1.2072

1.207

1.2068

1.2066

1.2064

-40

-20

100 120 140

-40 -25 -10

20 35 50 65 80 95 110 125

Temperature (èC)

图 7. V_{IT(PFD,FALLING)}Threshold vs Temperature

图 8. V_{IT(PG,FALLING)}and V_{IT(PG,RISING)}Thresholds vs

Temperature

-1

-2

-1

-2

Time (ms)

FB configuration, scope bandwidth = 10 MHz,

I_OUT= 1 mA

FB configuration, scope bandwidth = 10 MHz,

I_OUT= 120 mA

图 9. V_{LDO_OUT}Ripple for FB Configuration

图 10. V_{LDO_OUT}Ripple for FB Configuration

200

-200

-400

-600

-800

-1000

-1200

-1400

-1600

-200

-400

-600

-800

-1000

-1200

-1400

-1600

V_{LDO_IN}

V_PG

V_{LDO_OUT}

V_AC

V_{LDO_IN}

V_PG

V_{LDO_OUT}

V_AC

-1

Time (ms)

50 100 150 200 250 300 350 400 450 500

Time (ms)

C_S= 2.2 µF, C_SCIN= 22 µF, C_{LDO_IN}= 1.0 µF, I_OUT= 10 mA

C_S= 100 nF, C_SCIN= 22 µF, C_{LDO_IN}= 1.0 µF, I_OUT= 10 mA

图 11. Fast Startup With Larger Than the Required Cap-Drop

图 12. Slow Startup With the Minimum Required Cap-Drop

Capacitor for 10-mA I_OUT

TPS7A78

www.ti.com.cn

ZHCSJG2A –MARCH 2019–REVISED SEPTEMBER 2019

Typical Characteristics (接下页)

at operating temperature T_J= 25°C, V_ACsupply = 120 V_RMSper 60 Hz, full-bridge (FB) bridge configuration, C_S= 1.0 µF,

C_SCIN= 220 µF, C_SC1= 1.0 µF, C_SC2= 2.2 µF, C_{LDO_IN}= 10 µF, C_{LDO_OUT}= 1.0 µF, and I_OUT= 1 mA (unless otherwise noted)

220

210

200

190

180

-40

-20

100 120 140

Temperature (èC)

V_SCIN= 19 V, V_{LDO_OUT}≤ 3.4 V

图 13. I_OUTCurrent Limit

TPS7A78

ZHCSJG2A –MARCH 2019–REVISED SEPTEMBER 2019

www.ti.com.cn

7 Detailed Description

7.1 Overview

The TPS7A78 features an internally controlled, active bridge rectifier that can be configured either as full bridge

(FB) or a half bridge (HB), a 4:1 switched-capacitor stage (charge pump), an internally controlled low-dropout

(LDO) linear-voltage regulator, as well as current-limit, thermal-shutdown, programmable power-fail detection,

and power-good detection.

The TPS7A78 is a non-isolated, smart linear-voltage regulator that uses an external high-voltage, capacitor-drop

(cap-drop) capacitor (C_S) and an internally controlled, active bridge-rectifier to create a regulated DC output

voltage. The device incorporates a switched-capacitor charge pump stage that transforms the voltage and

current characteristics of the rectifier stage to the voltage and current needs of the LDO stage, providing a 4-

times reduction in input power for a given load power. This feature also reduces the size of the required C_Sby a

factor of 4. The external surge resistor R_Sis used to limit the inrush-current to the device. Unlike typical AC-to-

DC power solutions, the TPS7A78 does not require external magnetic components, thus making the device an

excellent choice for electricity-metering applications by improving tamper resistance. This unique design allows

the TPS7A78 to reduce standby power to approximately 15 mW for light-load applications while maintaining high

efficiency.

For applications with output voltages of 3.6 V or less, the TPS7A78 can be powered from a DC supply connected

directly to the SCIN pin. This supply mode can provide DC-only operation or DC-powered backup in case of AC

supply failure. When a DC supply is used to power the device, the internally controlled dropout voltage regulation

is affected as explained in the Dropout Voltage Regulation section. The AC+ and AC– pins must be grounded

when only a DC power source is used.

7.2 Functional Block Diagram

SC1-

SC1+

SC2-

SC2+

SCIN

LDO_IN

Switch Capacitor Stage

Overvoltage

Protection

UVLO_SCIN

UVLO_LDO_IN

AC+

LDO_OUT

Current

Limit

Control

Logic

AC-

LDO

Thermal Shutdown

PFD

VIT(PFD,FALLING)

GND

TPS7A78

www.ti.com.cn

ZHCSJG2A –MARCH 2019–REVISED SEPTEMBER 2019

7.3 Feature Description

7.3.1 Active Bridge Control

The TPS7A78 has an internally controlled, actively clamped, full-bridge rectifier between the AC+ and AC– pins

that requires one of these pins to be connected in series with the high-voltage capacitor C_Sand the surge

resistor R_S. The active clamp for the bridge is designed to stabilize the rectified DC voltage at the SCIN pin to

optimize performance given the LDO output voltage. The clamp circulates any excess AC charging current from

the cap-drop capacitor C_Sand surge resistor R_Sthrough the AC+ or the AC– pins to the GND pins when the

SCIN pin voltage surpasses its UVLO_SCIN rising threshold during startup. The clamp maintains the SCIN pin

voltage higher than this threshold to support the targeted output voltage. This excess AC charging current is also

referred to as the shunt current, I_SHUNT; see the Standby Power and Output Efficiency section for details on the

shunt current.

A DC supply can also be used to provide power directly to the SCIN pin, which completely bypasses the bridge

active-clamp circuit; see 表 1 for details on the DC supply mode.

7.3.2 Full-Bridge (FB) and Half-Bridge (HB) Configurations

The TPS7A78 can be configured to operate either in full-bridge (FB) or half-bridge (HB) configurations. HB

configuration ties the AC input pin without the series C_Sand R_Scomponents to the device GND pins. See 图 14

and 图 15 for the HB and FB configurations.

SC1-

SC2-

C_SC1

C_SC2

SC1+

SC2+

SC1+

SC2+

C_SCIN

Optional

SCIN

PFD

SCIN

PFD

GND

Optional

V_PG

TPS7A78

V_PF

C_S

R_S

AC+

GND

ACœ

AC+

GND

ACœ

Connect AC- to

device GND for

Half-Bridge

V_AC

LDO_IN

TVS

C_{LDO_IN}

Configuration

V_{LDO_OUT}

LDO_OUT

C_{LDO_OUT}

图 14. Typical Schematic Half-Bridge Configuration

图 15. Typical Schematic Full-Bridge Configuration

注

When FB configuration is used, do not tie the device GNDs to earth GND neither

schematically nor accidentally via an earth-grounded oscilloscope or measurement

equipment because the device GNDs and earth GND are at different voltage potentials.

Doing so and can cause damage to the device and external equipment. Tying the device

GND pins to earth GND when FB configuration is used is only acceptable if a second

surge resistor R_Sis used on the AC input pin side without the series C_Sand first R_S, as

illustrated in 图 16 with floating device GND pins and 图 17 with non-floating (earth

grounded) device GND pins.

TPS7A78

ZHCSJG2A –MARCH 2019–REVISED SEPTEMBER 2019

www.ti.com.cn

Feature Description (接下页)

SC1-

SC2-

SC1-

SC2-

C_SC1

C_SC2

C_SC1

C_SC2

SC1+

SCIN

SC2+

GND

SC1+

SC2+

Differential Measurement

Equipment is required

Non-Floating

Device GND

SCIN

PFD

GND

C_SCIN

Floating

Device

GND

C_SCIN

PFD

TPS7A78

Earth-GND

C_S

R_S

C_S

R_S1

AC+

GND

ACœ

AC+

GND

ACœ

C_{LDO_IN}

V_AC

LDO_IN

TVS

V_AC

LDO_IN

TVS

R_S2

V_{LDO_OUT}

LDO_OUT

V_{LDO_OUT}

C_{LDO_OUT}

LDO_OUT

C_{LDO_OUT}

图 16. Full-Bridge Floating Device GND

图 17. Full-Bridge Non-Floating Device GND

7.3.3 4:1 Switched-Capacitor Voltage Reduction

The TPS7A78 uses a switched-capacitor charge pump to reduce the rectified DC voltage at the SCIN pin by four

times, providing the LDO block with an input voltage above its dropout voltage that is then regulated to the target

output voltage. The DC voltage at the SCIN pin can be provided either by the active clamp for the bridge

rectifying the input V_ACsupply or by a direct DC supply connection to the SCIN pin.

7.3.4 Undervoltage Lockout Circuits (V_{UVLO_SCIN}) and (V_{UVLO_LDO_IN}

)

The TPS7A78 incorporates two undervoltage lockout (UVLO) circuits; the UVLO_SCIN circuit and the

UVLO_LDO_IN circuit. UVLO_SCIN is used to make sure that the active clamp for the bridge has charged the

C_SCINcapacitor to a voltage level that surpasses the UVLO_SCIN rising threshold to start the switched-capacitor

stage. The UVLO_SCIN rising threshold voltage is a function of the LDO output voltage, V_{LDO_OUT(nom)}, as

indicated in the Electrical Characteristics table.

The UVLO_LDO_IN circuit is used to ensure that the switched-capacitor stage has charged the C_{LDO_IN}capacitor

to a voltage level that surpasses the UVLO_LDO_IN rising threshold to enable the LDO circuit to begin regulation

at the specified LDO output voltage. See the Startup Behavior section for details.

注

The LDO_IN pin must not be driven externally and must not be used as a supply rail to an

external load.

7.3.5 Dropout Voltage Regulation

This LDO functional block follows the conventional definition of dropout voltage (V_DO) between V_{LDO_IN}and

V_{LDO_OUT}. However, the supply mode can have an effect on the dropout voltage.

When the AC input is used as the supply, a fixed dropout (V_DO) of 600 mV (typical) between V_{LDO_IN}and

V_{LDO_OUT}is maintained for output voltages between 5.0 V and 3.4 V. For output voltages below 3.4 V, the V_{LDO_IN}

voltage is maintained at 4.0 V regardless of the output voltage.

A DC supply via the SCIN pin can only be used for output voltages of 3.6 V or less. Under a load condition

approaching maximum output current and at high ambient temperature, the LDO can be driven into dropout; see

the Switched-Capacitor Stage Output Impedance section for details.

7.3.6 Current Limit

The LDO block has an internal current-limit circuit that protects the output during overcurrent events or short-

circuit faults. The current-limit circuit limits the output current to (I_CL), as specified in the Electrical Characteristics

table.

TPS7A78

www.ti.com.cn

ZHCSJG2A –MARCH 2019–REVISED SEPTEMBER 2019

Feature Description (接下页)

When in current limit, the output voltage cannot be regulated and the device heats up because of the increase in

power dissipation. When in current limit, the LDO pass transistor dissipates power equal to V_DO× I_CL, where V_DO

is equal in the worst case to V_{LDO_IN}. The heat generated when operating at current limit, in conjunction with the

ambient temperature, can trigger the internal thermal shutdown. During thermal shutdown, both V_{LDO_OUT}and the

switched-capacitor stage are shut down to prevent further heating; see the Load Transient section for more

details.

7.3.7 Programmable Power-Fail Detection

The TPS7A78 can monitor the rectified DC voltage at the SCIN pin to provide the application with an early

warning via the power-fail (PF) pin if the main power fails. An external resistor-divider network connected to the

VSCIN pin provides the input to the power-fail detect (PFD) analog input pin to monitor for an AC line supply

failure. When the AC supply falls below its minimum level programmed by the resistor divider R₁and R₂, as

illustrated in 图 14 and in 图 15, the PF output is pulled low. If this feature is not used, omit R₁and R₂and

connect PFD and PF pins to the device GND pins reference.

注

The PFD pin can also be used to monitor another DC rail within the application to provide

an early warning via the PF pin. However, this DC rail must share the same GND

reference with the TPS7A78 GND and the absolute maximum voltage of the PF pin must

not be exceeded.

7.3.8 Power-Good (PG) Detection

The power-good (PG) circuit monitors the V_{LDO_OUT}voltage to indicate the status of the LDO output voltage. PG

is pulled low until V_{LDO_OUT}reaches its proper regulate voltage level, then PG is released and allowed to be

pulled high. If V_{LDO_OUT}falls below the V_{IT(PG_FALLING)}threshold, PG is asserted low to indicate the LDO output

voltage is not in regulation. PG pin low assertion can happen during an overcurrent event or a short-circuit fault.

PG can be used to release the reset pin of a microcontroller. The PG pin must be pulled up to a DC rail such as

V_{LDO_OUT}

Use the recommended pullup resistor value specified in the Electrical Characteristics table for the PG pin. The

functionality of the power-good detection pin has no effect on the internal control logic other than to indicate the

state of the output voltage. If this function is not used, connect the PG pin to the device GND pins reference.

注

An external DC rail can also be used to pull up the PG pin signal via a pullup resistor only

when the external DC rail shares the same reference GND with the TPS7A78 GND and

the absolute maximum voltage of the PG pin is not exceeded.

7.3.9 Thermal Shutdown

A thermal shutdown protection circuit is included to disable V_{LDO_OUT}and to stop the switched-capacitor stage

from switching when the junction temperature T_Jof the pass-transistor rises to T_SD(SHUTDOWN). Thermal shutdown

hysteresis assures that the device resets, resumes normal operation, and that V_{LDO_OUT}turns back on when T_J

falls to T_SD(RESET). Based on the thermal time constant of the die and the device startup time, the device output

can cycle on and off until power dissipation is reduced and the junction temperature remains below T_SD(RESET)

For reliable operation, limit the junction temperature to the maximum listed in the Recommended Operating

Conditions table. Operating above this maximum temperature causes the device to exceed its operational

specifications. Although the internal protection circuitry is designed to protect against thermal overload

conditions, this circuitry is not intended to replace proper heat sinking. Continuously running the device into

thermal shutdown or above the maximum recommended junction temperature reduces long-term reliability.

TPS7A78

ZHCSJG2A –MARCH 2019–REVISED SEPTEMBER 2019

www.ti.com.cn

7.4 Device Functional Modes

The unique features of the TPS7A78, along with its dual-input power-supply capability, enables the device to be

used in a vast array applications. 表 1 gives a general overview of the conditions that lead to different modes of

operation, given that the requirements in the Typical Application section are met.

表 1. Device Functional Mode Comparison

PARAMETER

OPERATING

MODE

DEVICE POWER-SUPPLY

I_OUT

T_J

I_OUT< I_CLused in the Calculating the Cap-Drop Capacitor

C_Ssection

Normal operation

Dropout mode⁽³⁾

V_ACsupply⁽¹⁾/ DC supply⁽²⁾

T_J< T_{SD (Shutdown)}

C_Sor C_SCINcapacitors are not sufficient to support I_OUT(V_ACI_OUT< I_CLused in the Calculating the Cap-Drop Capacitor

supply) C_Ssection

T_J< T_{SD (Shutdown)}

_SCIN≤ V_{UVLO SCIN}rising threshold and V_{LDO_IN}> V_{UVLO LDO_IN}I_OUT< I_CLused in the Calculating the Cap-Drop Capacitor

rising threshold (DC supply)⁽⁴⁾

C_Ssection

V_{LDO_IN}< V_{UVLO LDO_IN}falling threshold (V_ACsupply)

V_{LDO_IN}< V_{UVLO LDO_IN}falling threshold (DC supply)

Disabled mode⁽⁵⁾

Not applicable

T_J> T_{SD (Shutdown)}

(1) The device can function with the V_ACsupply down to 18 V_RMS; see the Typical Application section for details.

(2) The DC supply applied on the SCIN pin must be bounded by the V_{SCIN (MAX)}> V_SCIN> V_{UVLO_SCIN}(RISING) threshold as specified in

the Recommended Operating Conditions and Electrical Characteristics tables.

(3) The device can be in dropout when powered by V_ACor DC supplies; see the Dropout Voltage Regulation section for details.

(4) This condition applies after device has started up.

(5) Any true condition disables the device V_{LDO_OUT}and stops the switched-capacitor stage from switching; see the Disabled Mode section

for details.

7.4.1 Normal Operation

The device is mainly designed to be powered by the AC supply; however, a DC supply can also be used to

power the TPS7A78. See the Active Bridge Control and Application and Implementation sections for proper

operation.

7.4.2 Dropout Mode

During dropout mode and when V_{LDO_OUT}tracks V_{LDO_IN}, the transient performance becomes significantly

degraded because the pass-transistor is operating in the ohmic or triode region.

7.4.3 Disabled Mode

There is no disable pin and disable mode simply means that the output, V_{LDO_OUT}, is turned off and the switched

capacitor (see the 4:1 Switched-Capacitor Voltage Reduction section) is not switching. However, when V_SCINis

less than the V_{UVLO_SCIN}rising threshold and V_{LDO_IN}is greater than the V_{UVLO_LDO_IN}falling threshold, the internal

blocks resume normal operation when either the AC or the DC supply is restored.

注

When the device is in disabled mode and powered by an AC supply, the bridge active

control (see the Active Bridge Control section) continues to run until the AC supply powers

off.

TPS7A78

www.ti.com.cn

ZHCSJG2A –MARCH 2019–REVISED SEPTEMBER 2019

8 Application and Implementation

注

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

8.1 Application Information

The TPS7A78 is a non-isolated smart AC/DC linear-voltage regulator capable of providing a maximum 120-mA

load current; see 图 14 and 图 15 for the HB and FB configurations, respectively.

Being highly customizable, the TPS7A78 can be used in many low-power AC-to-DC or DC-to-DC applications,

such as electricity meters, appliances, and thermostat controls. 图 18 shows an example configuration for a

single-phase AC supply.

SC1-

SC2-

C_SC1

C_SC2

SC1+

SC2+

SCIN

PFD

GND

C_SCIN

TPS7A78

C_S

R_S

AC+

GND

ACœ

C_{LDO_IN}

V_AC

LDO_IN

TVS

V_{LDO_OUT}

LDO_OUT

C_{LDO_OUT}

图 18. Implementation Example for the TPS7A78 Single-Phase AC Supply

8.1.1 Recommended Capacitor Types

The choice of capacitor types is flexible as long as the minimum derated capacitor values and capacitor voltage

ratings are met.

Based on the system design requirements, TI recommends that greater than the minimum capacitor values and

voltage ratings, as well as better than minimum-required dielectric materials for all device capacitors, be specified

to ensure optimal performance. Chose the correct high-voltage, safety-rated cap-drop capacitor, C_S, as required

by the application. Regardless of the capacitor types selected, the effective capacitance varies with operating

voltage, temperature, and time. Follow the manufacturer recommendations for component derating.

8.1.2 Input and Output Capacitors Requirements

All the capacitors illustrated in 图 14 or 图 15 are required for proper operation. The value of C_Srequired to

support the application current is obtained from the Calculating the Cap-Drop Capacitor C_Ssection. The chosen

C_Scapacitor must tolerate the peak V_ACsupply voltage of the application and meet the required safety

requirements.

TPS7A78

ZHCSJG2A –MARCH 2019–REVISED SEPTEMBER 2019

www.ti.com.cn

Application Information (接下页)

Choosing an a larger value of the C_Scapacitor than required has an adverse effect on the standby power

consumption; however, capacitance reduction over long-term service is inevitable and must be considered when

selecting the value of C_S. A ceramic capacitor can be used as C_Sin designs for lower AC supply voltages, but

the capacitor voltage rating must be appropriate to the application.

For switching capacitors C_SC1and C_SC2, select the minimum-required capacitor values and voltage ratings

specified in the Recommended Operating Conditions table. Using too large of a capacitor for the switching

capacitors is not recommended because a large capacitor lengthens the start-up time and load transient

recovery time of the entire solution. Keep the switching capacitors as close to the device as possible to eliminate

any unwanted trace inductance.

For the bulk capacitor C_SCIN, use the minimum required capacitor value obtained from the Calculating the Bulk

Capacitor C_SCINsection and increase that value based on the expected capacitor degradation resulting from

aging and operating conditions. Accounting for capacitor degradation is especially important if a relatively low life

expectancy of the capacitor is expected when an electrolytic capacitor is used. If the application requires an

extended hold-up time, the values of the C_SCINor C_{LDO_IN}capacitors can be increased as long as the maximum

capacitor values specified in the Recommended Operating Conditions table are not exceeded. Using a

significantly larger values of C_SCINor C_{LDO_IN}has an adverse effect on the startup time of the solution.

For the C_{LDO_OUT}capacitor, maintain a 10:1 ratio between C_{LDO_IN}and C_{LDO_OUT}for applications using the

maximum load current. For lesser load currents, the minimum required C_{LDO_OUT}and C_{LDOU_IN}capacitors are

sufficient. For optimum performance, place all capacitors as close as possible to the device.

8.1.3 Startup Behavior

The device startup time is dependent on the circuit topology (FB versus HB configuration), AC supply voltage

and frequency, input capacitors values, and output voltage. The FB configuration has a faster startup time

compared to the HB configuration. Having a larger than minimum C_Scapacitor value shortens the startup time

without exceeding the maximum I_SHUNTcurrent specified in the Recommended Operating Conditions table.

However, startup behavior depends on which C_SCINand C_{LDO_IN}capacitor values are used. 图 19 illustrates the

startup behavior with the minimum required C_SCINcapacitor and a typical C_{LDO_IN}capacitor to support 30 mA of

load current with the FB configuration. 图 20 illustrates the startup behavior with the minimum required C_SCIN

capacitor and a large C_{LDO_IN}capacitor in the same configuration.

Although the load current has no effect on startup time or startup behavior, the bulk capacitor C_SCINand input

capacitor C_{LDO_IN}have a significant effect on the time and behavior; see 图 19 and 图 20. For some applications,

larger C_SCINor C_{LDO_IN}capacitors are used to hold-up the output voltage on for a longer period of time after the

input collapses.

TPS7A78

www.ti.com.cn

ZHCSJG2A –MARCH 2019–REVISED SEPTEMBER 2019

Application Information (接下页)

V_SCIN

V_{LDO_IN}

V_{LDO_OUT}

V_PG

V_SCIN

V_{LDO_IN}

V_{LDO_OUT}

V_PG

-2

80 100 120 140 160 180 200

Time (ms)

50 100 150 200 250 300 350 400 450 500

Time (ms)

V_AC= 120 V_RMSat 60 Hz, FB, C_S= 220 nF,

V_{LDO_OUT}= 3.3 V, C_SCIN= 47 µF, C_{LDO_IN}= 1 µF, I_OUT= 30 mA

V_AC= 120 V_RMSat 60 Hz, FB, C_S= 220 nF,

V_{LDO_OUT}= 3.3 V, C_SCIN= 47 µF, C_{LDO_IN}= 330 µF,

I_OUT= 30 mA

图 20. Startup Behavior With a Minimum C_SCINCapacitor

图 19. Startup Behavior With a Minimum C_SCINCapacitor

and a Large C_{LDO_IN}Capacitor for a 30-mA Load

and a Typical C_{LDO_IN}Capacitor for a 30-mA Load

8.1.4 Load Transient

A load-transient event can trigger the internal overcharge protection circuit on the LDO_IN pin. This condition

prevents C_{LDO_IN}from overcharging when a heavy load is abruptly removed. The overvoltage protection circuit

engages and prevents the switched capacitors from switching until the excess charge on C_{LDO_IN}is discharged

into the load. This protection behavior occurs most often during heavy load-transient events on devices with

higher output voltages. The value of the C_{LDO_IN}capacitor and the load current determine how long the

overvoltage protection circuit remains engaged. 图 21 shows the overvoltage protection circuit behavior after the

load is removed without tripping the PG signal.

1600

1200

800

400

480

400

320

240

160

V_{LDO_IN}

V_PG

V_{LDO_OUT}

I_OUT

-400

-800

200 400 600 800 1000 1200 1400 1600 1800 2000

Time (ms)

图 21. Overvoltage Protection Circuit Behavior for a 5.0-V Output Voltage Device During Load Transient

As illustrated in 图 22, a load-transient event that exceeds the maximum output current can disable the output

when the heavy load pulls down the V_{LDO_IN}voltage below the V_{UVLO_LDO_IN}falling threshold. If the application is

prone to heavy load-transient events as illustrated in 图 22, increase the C_{LDO_IN}capacitor value as necessary.

However, as illustrated in 图 20, too large of a C_{LDO_IN}leads to a longer startup time.

TPS7A78

ZHCSJG2A –MARCH 2019–REVISED SEPTEMBER 2019

www.ti.com.cn

Application Information (接下页)

1200

1000

800

600

400

200

1200

1000

800

V_{LDO_IN}

V_PG

V_{LDO_OUT}

I_OUT

V_{LDO_IN}

V_PG

V_{LDO_OUT}

I_OUT

600

400

200

-2

0.5

1.5

Time (ms)

2.5

3.5

0.5

1.5

Time (ms)

2.5

3.5

V_AC= 120 V_RMSat 60 Hz, FB, C_{LDO_IN}= 10 µF,

V_{LDO_OUT}= 3.3 V, I_OUT= 1 mA to 600 mA,

current slew = 1 A/µs

V_AC= 120 V_RMSat 60 Hz, FB, C_{LDO_IN}= 56 µF,

V_{LDO_OUT}= 3.3 V, I_OUT= 1 mA to 600 mA, current slew = 1 A/µs

图 22. Heavy Load-Transient Event Triggering a Restart

图 23. Heavy Load-Transient Event Without Triggering a

Restart

8.1.5 Standby Power and Output Efficiency

The AC input current cannot be directly calculated because of the active bridge control; see the Active Bridge

Control section. The AC input current through the AC+ and AC– pins is a combination of two current

components, as shown in 图 24: I_SHUNTand I_PEAK. The I_SHUNTcurrent component is identified by its wave profile

because this component is the AC charging current supplied by the cap-drop capacitor C_S. The I_PEAKcurrent

component is identified by its instantaneous peak current profile.

400

200

V_AC-

I_AC+

V_AC+

I_AC-

-200

-400

-600

Time (ms)

图 24. The Device V_ACInput Current With its Two Components

公式 1 calculates the shunt current I_SHUNT, and 公式 2 calculates the peak current I_PEAK

I_SHUNT= V_{AC (MAX)}/ XC_S= V_{AC (MAX)}× 2 × π × ƒ × C_S

I_PEAK= V_SCIN/ R_S

(1)

(2)

V_SCIN= 4 × (V_{LDO_OUT (nom)}+ 0.6 V)

where

•

V_{AC (MAX)}is the maximum V_ACsupply RMS voltage

XC_Sis the impedance of the standard C_Scapacitor to be used in the application

V_SCINis the rectified DC voltage on the SCIN pin

R_Sis the standard R_Sresistor to be used in the application

(3)

TPS7A78

www.ti.com.cn

ZHCSJG2A –MARCH 2019–REVISED SEPTEMBER 2019

Application Information (接下页)

The frequency of the shunt activity is uncorrelated to the AC input frequency. Therefore, the standby power must

be measured with a power analyzer. Fortunately, using a power analyzer is relatively simple and the

measurement setup shown in 图 25 and 图 26 can be used to measure the standby power and the output

efficiency.

If the application has an upstream current-limit circuit that limits any high-transient input currents, such as surge

or hot-plug currents, the requirement for the surge resistor R_Scan be relaxed. The input transient current-limit

circuit allows the R_Sresistor to be removed, thus significantly improving the standby power and output efficiency

because no power loss is dissipated in R_S.

Analyzer Current

Measurement

C_S

R_S

AC+

Power

Analyzer

Analyzer Voltage

Measurement

V_AC

TPS7A78

ACœ

图 25. Standby Power and Output Efficiency Measurement Setup

Analyzer Current

Measurement

C_S

AC+

Power

Analyzer

Current

Limit Circuit

Analyzer Voltage

Measurement

TPS7A78

ACœ

图 26. Standby Power and Output Efficiency Measurement Setup With an Upstream Current-Limit Circuit

TPS7A78

ZHCSJG2A –MARCH 2019–REVISED SEPTEMBER 2019

www.ti.com.cn

Application Information (接下页)

The standby power and output efficiency measurements shown in 图 27 to 图 29 were created with the

measurement setup in 图 25.

1200

1000

800

600

400

200

R_S= 280 W

R_S= 560 W

R_S= 280 W

R_S= 560 W

100 200 300 400 500 600 700 800 900 1000

Cap-Drop Capacitor C_S(nF)

I_OUT(mA)

V_AC= 120 V_RMSat 60 Hz, FB, V_{LDO_OUT}= 5.0 V,

I_OUT= 0 mA

V_AC= 120 V_RMSat 60 Hz, FB, C_S= 150 nF, V_{LDO_OUT}= 5.0 V

图 28. Efficiency vs I_OUTFB Configuration

图 27. Standby Power vs Cap-Drop Capacitor (C_S)

R_S= 280 W

R_S= 560 W

5 6

I_OUT(mA)

V_AC= 120 V_RMSat 60 Hz, HB, C_S= 150 nF, V_{LDO_OUT}= 5.0 V

图 29. Efficiency vs I_OUTHB Configuration

8.1.6 Reverse Current

Excessive reverse current can damage the TPS7A78. Reverse current flows through the intrinsic body diode of

the pass-transistor instead of the normal conducting channel. At high magnitudes, this current flow degrades the

long-term reliability of the device.

Conditions where reverse current can occur are:

•

If the device has a large C_{LDO_OUT}and the input supply collapses with little or no load current

The LDO_OUT pin is biased when the input supply is not present

The LDO_OUT pin is biased above the voltage of the LDO_IN pin

If reverse current flow is expected in the application, external protection is recommended to provide protect.

Reverse current is not limited within the device, so external limiting is required, as illustrated in 图 30 and 图 31,

if extended reverse-voltage operation is anticipated.

TPS7A78

www.ti.com.cn

ZHCSJG2A –MARCH 2019–REVISED SEPTEMBER 2019

Application Information (接下页)

SC1-

SC2-

C_SC1

C_SC2

SC1+

SC2+

SCIN

GND

C_SCIN

PFD

TPS7A78

AC+

GND

ACœ

C_{LDO_IN}

LDO_IN

V_{LDO_OUT}

LDO_OUT

C_{LDO_OUT}

图 30. Example Circuit for Reverse Current Protection Using a Schottky Diode

SC1-

SC2-

C_SC1

C_SC2

SC1+

SC2+

SCIN

PFD

GND

C_SCIN

TPS7A78

AC+

GND

ACœ

C_{LDO_IN}

LDO_IN

V_{LDO_OUT}

LDO_OUT

C_{LDO_OUT}

图 31. Example Circuit for Reverse Current Protection Using a P-Channel FET

TPS7A78

ZHCSJG2A –MARCH 2019–REVISED SEPTEMBER 2019

www.ti.com.cn

Application Information (接下页)

8.1.7 Switched-Capacitor Stage Output Impedance

To ensure a low output impedance of the device switched-capacitor stage (charge pump), connect a 1-µF X5R or

a better dielectric capacitor in parallel with the bulk capacitor C_SCIN. 图 32 shows the switched-capacitor stage

output impedance versus temperature at the maximum output current of 120 mA. When a DC supply power

source is used to power the device under heavy loading conditions close to the maximum current rating at high

temperature, the load can run the LDO into dropout because of the degradation in the charge pump output

impedance. To enhance performance with a DC supply, apply the DC supply voltage to the SCIN pin equal to 4

(VLDO_OUT (nom) + 0.6 V) + 2 V to ensure optimal performance. See 图 5 and 图 6 for a 3.3-V output voltage

example.

V_{LDO_OUT}3.3 V

V_{LDO_OUT}5.0 V

5.5

4.5

3.5

-40

-20

100 120 140

Temperature (èC)

图 32. Switched-Capacitor Stage Output Impedance vs Temperature at a 120-mA Load Current

8.1.8 Power Dissipation (P_D)

To ensure proper thermal design, the printed circuit board (PCB) area around the TPS7A78 must include a

minimal of heat-generating devices to avoid added thermal stress. The three internal sources that dissipate

power are: the bridge rectifier conduction losses, the switched-capacitor stage, and the LDO. For devices with an

output voltage greater 3.3 V, the maximum power dissipation under a maximum load current of 120 mA is

estimated to be between 160 mW and 190 mW, assuming a nominal C_Scapacitor value for the given load

current. For applications with less than a 3.3-V output , the power dissipated in the LDO is the dominant power

and can be calculated using 公式 4 because the dropout voltage between V_{LDO_IN}and V_{LDO_OUT}can be as high

as 2.7 V for the 1.3-V output option. See the Dropout Voltage Regulation section for details on dropout voltage.

P_{D_LDO}= (V_{LDO_IN}– V_{LDO_OUT}) × I_OUT

(4)

The higher dropout for less than 2.0-V output voltage options may run the device into thermal limitations at the

startup ramp for higher temperatures, especially with the large LDO_OUT pin capacitor or when close to the

maximum load. The thermal pad under the TPS7A78 must contain an array of filled vias that conduct heat to

additional copper planes for increased heat dissipation. The amount of thermal dissipation determines the

maximum allowable ambient temperature (T_A) for the device. According to 公式 5, power dissipation and junction

temperature are determined by the junction-to-ambient thermal resistance (R_θJA) of the combined PCB and

device package as well as the temperature of the ambient air (T_A).

T_J= T_A+ (R_θJA× P_D)

(5)

Thermal resistance (R_θJA) is highly dependent on the heat-spreading capability built into the particular PCB

design, and therefore varies according to the total copper area, copper weight, and location of the planes. The

junction-to-ambient thermal resistance listed in the Thermal Information table is determined by the JEDEC

standard PCB and copper-spreading area, and is used as a relative measure of package thermal performance,

but not indicative of performance in any particular implementation.

TPS7A78

www.ti.com.cn

ZHCSJG2A –MARCH 2019–REVISED SEPTEMBER 2019

Application Information (接下页)

8.1.9 Estimating Junction Temperature

The JEDEC standard recommends the use of psi (Ψ) thermal metrics to estimate the junction temperatures of

the linear regulator when in circuit on a typical PCB board application. These metrics are not thermal resistance

parameters and instead offer a practical and relative way to estimate junction temperature. These psi metrics are

determined to be significantly independent of the copper area available for heat spreading. The Thermal

Information table lists the primary thermal metrics, which are the junction-to-top characterization parameter (ψ_JT)

and junction-to-board characterization parameter (ψ_JB). These parameters provide two methods for calculating

the junction temperature (T_J). As described in the Semiconductor and IC Package Thermal Metrics application

report, use the junction-to-top characterization parameter (ψ_JT) with the temperature at the center-top of device

package (T_T) to calculate the junction temperature. As described in the Semiconductor and IC Package Thermal

Metrics application report, use the junction-to-board characterization parameter (ψ_JB) with the PCB surface

temperature 1 mm from the device package (T_B) to estimate the junction temperature.

T_J= T_T+ ψJT × P_{D_Total}

where

•

P_{D_Total}is the total dissipated power in the device

T_Tis the temperature at the center-top of the device package

(6)

T_J= T_B+ ψJB × P_D

where

•

T_Bis the PCB surface temperature measured 1 mm from the device package and centered on the package

edge

(7)

For detailed information on the thermal metrics and how to use them, see the Semiconductor and IC Package

Thermal Metrics application report.

8.2 Typical Application

This section demonstrates the design process for a typical application of the TPS7A78, including the calculation

of the values of the external components required for proper operation. 图 33 shows an optimized electricity

meter application using an HB configuration. For this design, the AC supply line voltage is referenced to the

TPS7A78 GND pins to share the same GND as the system microcontroller.

SC1-

SC2-

C_SC1

C_SC2

SC1+

SC2+

C_SCIN

SCIN

PFD

GND

V_PG

V_PF

TPS7A78

AC+

GND

ACœ

V_AC

LDO_IN

TVS

C_{LDO_IN}

C_S

R_S

V_{LDO_OUT}

LDO_OUT

C_{LDO_OUT}

图 33. Example for a Single-Phase Electricity Meter Configuration

TPS7A78

ZHCSJG2A –MARCH 2019–REVISED SEPTEMBER 2019

www.ti.com.cn

Typical Application (接下页)

8.2.1 Design Requirements

表 2 summarizes the design requirement for this example.

表 2. Design Parameters

PARAMETER

V_ACsupply voltage

DESIGN REQUIREMENT

85 V_{AC RMS}to 265 V_{AC RMS}

50 Hz (±3 Hz)

V_ACsupply frequency

Bridge configuration

HB, AC+ pin is tied to the device GND pins

Device GND pins reference

Output voltage

Floating device GND, AC supply line voltage is referenced to the device GND pins

3.3 V

12 mA

Output current

Electrical fast transient immunity (EFT)

(IEC 61000-4-4) level 2 (1 kV)

8.2.2 Detailed Design Procedure

This section discusses how to calculate the external components required for this design example.

8.2.2.1 Calculating the Cap-Drop Capacitor C_S

Use 公式 8 to calculate the minimum required cap-drop capacitance needed to support the application current.

For common application conditions, 表 3 can be used to select the minimum standard cap-drop capacitor

required to support the application current. However, neither 公式 8 nor 表 3 account for capacitance derating

under biasing voltage and operating temperature conditions. Follow the manufacturer recommendation and

guidelines on capacitor derating and degradation to ensure the minimum-required capacitance needed for the

application under various operating conditions. Do not use a load current less than 10 mA to calculate the C_S

capacitor because the device current is a larger fraction of the load current. 公式 8 and 表 3 can also be used to

calculate the value of C_Sdepending on the application V_{AC (MIN)}voltage and frequency and then use the highest

value for the application.

C_S= I_OUT/ (16 × ƒ × [√2 × V_{AC (MIN)}– 4 × (V_{LDO_OUT (nom)}+ 0.6 V)])

where

•

the C_Svalue is the minimum cap-drop capacitance value in farads needed to support I_OUT

I_OUTis the application nominal load current, but the application peak current must be considered if this current

cannot be supported by the LDO output capacitor

•

V_{LDO_OUT}is the targeted LDO output voltage

V_{AC (MIN)}is the minimum RMS V_ACsupply voltage

ƒ is the minimum V_ACline frequency

(8)

表 3. The Minimum Required Cap-Drop Capacitor C_S

V_{AC (MIN)}(ƒ)

I_OUT(mA)

C_SFOR FB (nF)

C_SFOR HB (nF)

100

330

560

820

1000

220

470

120 (60)

1000

1500

2200

100

120

150

330

470

560

330

240 (50)

560

820

120

1200

TPS7A78

www.ti.com.cn

ZHCSJG2A –MARCH 2019–REVISED SEPTEMBER 2019

The capacitance value of C_Sfrom 公式 8 is for the FB configuration. For the HB configuration, double the

calculated capacitance value, then approximate the value up to the nearest standard capacitor value after taking

capacitance degradation into account. Similarly, the capacitor value of C_Sfrom 表 3 represents the minimum

required capacitor value and is already approximated to the nearest standard value but capacitor degradation is

not accounted for.

8.2.2.1.1 C_SCalculations for the Typical Design

公式 8 yields a capacitance value of 153 nF, as given by 公式 9, which results from the V_{AC (MIN)}voltage and

frequency of this application. This value is for the FB configuration. For the HB configuration, doubling the

calculated capacitance value yields 306 nF, and approximate this value up to the nearest standard capacitor

value, which yields a C_Svalue of 330 nF.

C_S= (0.012 ) / (16 × 47 × [√2 × 85 – 4(3.3 + 0.6)]) = 153 n F

(9)

As mentioned in the Calculating the Cap-Drop Capacitor C_Sand Input and Output Capacitors Requirements

sections, capacitance loss under long-term service is inevitable and must be considered in the design. Follow the

manufacturer recommendations and guidelines for capacitor derating and degradation over time.

8.2.2.2 Calculating the Surge Resistor R_S

The device requires a surge resistor or resistors in series with the AC+ and or AC– pins, depending

configuration; see the Full-Bridge (FB) and Half-Bridge (HB) Configurations section for details. The purpose of

the surge resistor is to limit the hot-plug AC current into the AC+ and AC– pins when the AC supply voltage is

applied. 公式 10 calculates the value of the minimum surge resistor R_{S (MIN)}required for the application.

R_{S (MIN)}= V_{AC (PEAK)}/ I _{Surge (MAX)}

where

•

V_{AC (PEAK)}is the peak V_ACsupply voltage for the application

I_{Surge (MAX)}is the maximum V_ACcurrent into or out of out the AC+ or AC– pins for a duration of ≤100 µs, as

specified in the Recommended Operating Conditions table.

(10)

If the solution requires the use of a transient voltage surge suppressor (TVS) or a metal-oxide varistor (MOV),

then use the maximum clamping voltage of the TVS or MOV instead of the peak V_ACvoltage in 公式 10. After

calculating R_{S (MIN)}, select the next-higher standard resistor value.

8.2.2.2.1 R_SCalculations for the Typical Design

The peak AC supply voltage for this example is equal to 375 V (√2 × 265) and the electrical fast transient

immunity (EFT) requirement is given as 1 kV. Thus, a TVS with a maximum clamping voltage of 1000 V can be

used. 公式 11 shows the calculated R_{S (MIN)}value.

R_{S (MIN)}= 1000 / 2.5 = 400 Ω

(11)

Because both the device I_PEAKcurrent and the device maximum I_SHUNTcurrent flow through R_S, the power rating

of R_Smust be able to handle these currents values. See the Checking for the Device Maximum I_SHUNTCurrent

section for the I_SHUNTcurrent calculation and R_Spower rating for this application.

If the application already has an upstream hot-plug current-limit circuit, then the requirement for the surge

resistor can be relaxed to significantly improve the solution standby-power; see the Standby Power and Output

Efficiency section for details.

8.2.2.3 Checking for the Device Maximum I_SHUNTCurrent

After determining the cap-drop capacitor value, a check must be performed to confirm that the maximum I_SHUNT

current specified in the Recommended Operating Conditions table is not exceeded by the standard capacitor

value of C_S. Other factors that affect the I_SHUNTcurrent are the maximum AC supply RMS voltage and the

maximum line frequency.

TPS7A78

ZHCSJG2A –MARCH 2019–REVISED SEPTEMBER 2019

www.ti.com.cn

8.2.2.3.1 I_SHUNTCalculations for the Typical Design

Given the maximum AC supply voltage and the minimum frequency for this application example, the calculated

I_SHUNTcurrent using 公式 1 from the Standby Power and Output Efficiency section yields:

I_SHUNT= 265 × 2 × π × 53 × 330 × 10^-9= 0.02912 A

(12)

注

The Recommended Operating Conditions table does not specify the maximum AC voltage

that can be used because the maximum V_ACvoltage is bound by the maximum I_SHUNT

current and the availability of the high-voltage cap-drop capacitor.

The RMS power given in 公式 13 and the peak power given in 公式 14 must be used to determine the power

rating of the surge resistor R_S.

P_RMS= (I_SHUNT

P_PEAK= [I_SHUNT× R_S+ 4(V_{LDO_OUT (nom)}+ 0.6 V)]²/ R_S

)

²× R_S

(13)

(14)

Using 公式 13 and 公式 14 yields the following R_Spower ratings:

P_RMS= (0.02912)²× 400 = 0.34 W

P_PEAK= [0.02912 × 400 + 4(3.3 + 0.6 )]²/ 400 = 1.86 W

(15)

(16)

Use the power rating resulting from 公式 14 because this equation yields a higher power requirement.

Furthermore, additional margin is always a good design practice.

8.2.2.4 Calculating the Bulk Capacitor C_SCIN

The TPS7A78 uses a bulk capacitor C_SCINto smooth the rectified DC voltage ripple on the SCIN pin and to

supply charge to the switched capacitor stage; see the 4:1 Switched-Capacitor Voltage Reduction section. The

C_SCINcapacitor also functions as a charge reservoir to hold-up the device output voltage for a period of time if

the supply collapses. The minimum value of the C_SCINcapacitor required can be calculated using 公式 17

through 公式 20, however these equations make the following assumptions to simplify the C_SCINcapacitor

calculation:

•

The AC supply frequency is within ±5% of the nominal standard frequencies of 50 Hz and 60 Hz

The voltage ripple on the SCIN pin is around from 0.5 V to 0.8 V.

The AC impedance of the cap-drop capacitor C_Sis at least ten times lower than that of the bulk capacitor

C_SCINand the surge resistor R_S

Use 公式 17 for the FB 60-Hz V_ACsupply and 公式 18 for the HB 60-Hz V_ACsupply.

C_SCIN= 0.0014 × I_OUT

C_SCIN= 0.0035 × I_OUT

(17)

(18)

Use 公式 19 for the FB 50-Hz V_ACsupply and 公式 20 for the HB 50-Hz V_ACsupply.

C_SCIN= 0.0017 × I_OUT

C_SCIN= 0.0041 × I_OUT

where

(19)

•

I_OUTis the application load current

(20)

The calculated C_SCINcapacitor from 公式 17 through 公式 20 represents the minimum value required for the

application example. However, 公式 17 through 公式 20 do not account for capacitance derating for all operating

conditions. Follow the manufacturer recommendation and guidelines to ensure the minimum required

capacitance needed for the application. See the Input and Output Capacitors Requirements section for more

details.

TPS7A78

www.ti.com.cn

ZHCSJG2A –MARCH 2019–REVISED SEPTEMBER 2019

8.2.2.4.1 C_SCINCalculations for the Typical Design

公式 21 shows the use of 公式 20 to calculate the C_SCINcapacitor value for the requirements of this application

example.

C_SCIN= 0.0041 × 0.012 = 49.2 µF

(21)

The calculated C_SCINcapacitor from the equations in the Calculating the Bulk Capacitor C_SCINsection represents

the minimum value required for the respective device configuration. Choose the nearest standard capacitor

value; see the Input and Output Capacitors Requirements section for more details.

8.2.2.5 Calculating the PFD Pin Resistor Dividers for a Power-Fail Detection

Using the device power-fail detection feature is optional as indicated in 图 14 and 图 15. The PFD pin is an

analog voltage input to an internal comparator that drives the open-drain PF output. The resistor divider

consisting of R₁and R₂can be used to set the minimum V_SCINvoltage that triggers the PF output. Regardless of

whether an AC or DC supply is used, the PF output triggers when the supply fails to maintain the V_SCINvoltage

above V_{SCIN (MIN)}. 公式 22 gives the calculation of the R₁– R₂resistor divider that sets the PF pin trigger point.

V_{IT(PFD,FALLING)}threshold = (V_{SCIN (MIN)}– V_rippleon the SCIN pin) × [R₂/ (R₁+ R₂)]

where

•

V_Rippleis the peak-to-peak voltage ripple on the SCIN pin and is in the range of 0.5 V to 0.8 V

(22)

(23)

公式 23 calculates the V_{SCIN (MIN)}voltage.

V_{SCIN (MIN)}= 4 (V_{LDO_OUT (nom)}+ 0.6 V) – 1.5 V

Set R₁as close as possible to the maximum value specified in the Recommended Operating Conditions table.

This high R₁value limits the power used by the resistors, then calculates the value of R₂. Choose the closest

standard resistor value for R₂. Optionally, because the PFD pin is a high-impedance node, add a 10-pF capacitor

in parallel with the R₂resistors to reduce noise coupling into V_PFD

Pull up the PF pin to a DC rail, such as V_{LDO_IN}, so that a microcontroller can monitor the PF signal as an early

power-fail warning to trigger the switch to a backup power solution or to perform a controlled system shutdown.

Pulling up the PF pin to V_{LDO_IN}rather than V_{LDO_OUT}ensures that the PF signal is continuously monitored even if

V_{LDO_OUT}is down because of a load-transient event or a short-circuit fault.

注

An external DC rail can also be used to pullup the PF pin signal via a pullup resistor only if

the external DC rail shares a common ground with the device GND pins and the absolute

maximum of the PF pin voltage is not exceeded.

8.2.2.5.1 PFD Pin Resistor Divider Calculations for the Typical Design

Using 公式 23 and then solving 公式 22 for R₂yields an R₂value of 18.3 kΩ.

V_{SCIN (MIN)}= 4 (3.3 + 0.6) – 1.5 V = 14.1 V

(24)

(25)

(26)

R₂= (V_{IT(PFD,FALLING)}× R₁) / (V_{SCIN (MIN)}– V_rippleon the SCIN pin – V_{IT(PFD,FALLING)}

)

R₂= (1.17 × 200) / (14.1 – 0.5 – 1.17)

TPS7A78

ZHCSJG2A –MARCH 2019–REVISED SEPTEMBER 2019

www.ti.com.cn

8.2.2.6 Summary of the Typical Application Design Components

表 4 summarizes the component values chosen through the design process for this application example.

表 4. Typical Application Design Example Components

COMPONENT

C_S

CALCULATED VALUE

330 nF, capacitance loss under long-term service is inevitable and must be considered in the design.

400 Ω, see the Checking for the Device Maximum I_SHUNTCurrent section for the R_Spower-rating calculation.

47 µF, approximate the 49.2-µF capacitor value resulting from the Calculating the Bulk Capacitor C_SCINsection.

1 µF, select the minimum capacitor value specified in the Recommended Operating Conditions table.

1 µF, select the typical capacitor value specified in the Recommended Operating Conditions table.

200 kΩ, select the maximum resistor value specified in the Recommended Operating Conditions table.

R_S

C_SCIN

C_SC1

C_SC2

C_{LDO_IN}

C_{LDO_OUT}

R₁

18.7 kΩ, approximate the 18.3-kΩ resistor value from the PFD Pin Resistor Divider Calculations for the Typical

Design section.

R₂

R₃and R₄

100 kΩ, select the maximum resistor values specified in the Recommended Operating Conditions table.

8.2.3 Application Curves

300

-300

-600

-900

-1200

-1500

-1800

-300

-600

-900

-1200

-1500

V_PF

V_{LDO_IN}

V_SCIN

V_PG

V_{LDO_OUT}

V_AC

V_{LDO_IN}

V_PG

V_{LDO_OUT}

V_AC

-1

50 100 150 200 250 300 350 400 450 500

Time (ms)

90 100

C_S= 330 nF, C_SCIN= 47 µF, C_SC1= C_SC2= 1.0 µF,

C_{LDO_IN}= C_{LDO_OUT}= 1.0 µF, I_OUT= 12 mA

C_S= 330 nF, C_SCIN= 47 µF, C_SC1= C_SC2= 1.0 µF,

C_{LDO_IN}= C_{LDO_OUT}= 1.0 µF, I_OUT= 12 mA

图 34. Startup Time

图 35. Shutdown Hold-Up Time With a 47-µF C_SCIN

Capacitor

300

-300

-600

V_PF

V_{LDO_IN}

V_SCIN

V_PG

V_{LDO_OUT}

V_AC

-900

-1200

-1500

-1

80 100 120 140 160 180 200

Time (ms)

C_S= 330 nF, C_SCIN= 120 µF, C_SC1= C_SC2= 1.0 µF,

C_{LDO_IN}= C_{LDO_OUT}= 1.0 µF, I_OUT= 12 mA

图 36. Shutdown Hold-Up Time With a 120-µF C_SCINCapacitor

TPS7A78

www.ti.com.cn

ZHCSJG2A –MARCH 2019–REVISED SEPTEMBER 2019

9 Power Supply Recommendations

The TPS7A78 is designed primarily to operate from an AC supply voltage ≥ 18 V_ACand an input line frequency

up to 20 kHz. To ensure that the output voltage is well regulated and that dynamic performance is optimum, the

procedures and examples in the Typical Application section must be followed.

The TPS7A78 can also operate from a DC supply voltage from 17 V to 23 V depending on the output voltage. To

ensure proper operation and ensure that the DC output voltage is well regulated, the DC supply voltage applied

to the SCIN pin must be well regulated and greater than or equal to the minimum V_{UVLO_SCIN}rising threshold

specified in the Electrical Characteristics table.

10 Layout

10.1 Layout Guidelines

•

Place the input and output capacitors as close to the TPS7A78 as possible

Place the PFD resistor divider, if used, away from the AC+, AC– pins, and the switched-capacitor stage pins;

if not used, tie the PFD pin to the common ground with the device GND pins

•

Pull up the PG pin, if used, to the LDO_OUT pin via a pullup resistor; otherwise, tie the PG pin to the

common ground with the device GND pins

Pull up the PF pin, if used, to the LDO_IN pin via a pullup resistor; otherwise, tie the PF pin to the common

ground with the device GND pins

Follow the recommended creepage distance between the AC+ and AC– pin traces, and between these traces

and other circuit traces

•

Tie the AC+ and AC– pins to the device GND pins if only the DC input supply is used

Place thermal vias around the device to distribute heat

10.2 Layout Example

SC2-

SC2+

GND

SC1-

SC1+

SCIN

Thermal Pad

(GND)

PFD

AC+

GND

AC-

LDO_IN

LDO_OUT

Represents via used for application-

specific connections

图 37. Example Layout

TPS7A78

ZHCSJG2A –MARCH 2019–REVISED SEPTEMBER 2019

www.ti.com.cn

11 器件和文档支持

11.1 器件支持

11.1.1 开发支持

11.1.1.1 评估模块

我们为您提供了评估模块 (EVM)，您可以借此对使用 TPS7A78 的电路性能进行初始评估。《TPS7A78EVM-011

评估模块》用户指南可在德州仪器 (TI) 网站的产品文件夹中获取，也可直接从 TI 网上商店购买。

11.1.1.2 SIMPLIS 模型

可以通过 TPS7A78 产品文件夹的工具与软件选项卡获取该器件的 SIMPLIS 模型。

11.1.2 器件命名规则

表 5. 器件命名规则⁽¹⁾⁽²⁾

产品

V_{LDO_OUT}

xx(x) 是标称输出电压。对于分辨率为 50mV 的输出电压，订购编号中使用两位数字；否则，使用三位数

字（例如，33 = 3.3V；135 = 1.35V）。

yyy 为封装标识符。

TPS7A78xx(x)yyyz

z 为封装数量。R 表示大数量卷带，T 表示小数量卷带。

(1) 要获得最新的封装和订货信息，请参阅本文档末尾的封装选项附录，或者访问器件产品文件夹（www.ti.com.cn）。

(2) 可提供 1.3V 至 5.0V 范围内的输出电压（以 50mV 为单位增量）。有关器件的详细信息和供货情况，请联系制造商。

11.2 文档支持

11.2.1 相关文档

请参阅如下相关文档：

•

德州仪器 (TI)，《TPS7A78EVM-011 评估模块》用户指南

德州仪器 (TI)，《使用独立 ADC 的单相并联电表参考设计》设计指南

德州仪器 (TI)，《适用于电网应用的离线（非隔离式）交流/直流电源架构参考设计》设计指南

11.3 接收文档更新通知

要接收文档更新通知，请导航至 TI.com.cn 上的器件产品文件夹。单击右上角的通知我进行注册，即可每周接收产

品信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。

11.4 社区资源

TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight

from the experts. Search existing answers or ask your own question to get the quick design help you need.

Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do

not necessarily reflect TI's views; see TI's Terms of Use.

11.5 商标

E2E is a trademark of Texas Instruments.

All other trademarks are the property of their respective owners.

11.6 静电放电警告

ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可

能会损坏集成电路。

ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可

能会导致器件与其发布的规格不相符。

TPS7A78

www.ti.com.cn

ZHCSJG2A –MARCH 2019–REVISED SEPTEMBER 2019

11.7 Glossary

SLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

12 机械、封装和可订购信息

以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且

不会对此文档进行修订。如需获取此数据表的浏览器版本，请查阅左侧的导航栏。

PACKAGE OPTION ADDENDUM

www.ti.com

10-Dec-2020

PACKAGING INFORMATION

Orderable Device

Status Package Type Package Pins Package

Eco Plan

Lead finish/

Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

(1)

(2)

(3)

(4/5)

(6)

TPS7A7833PWPR

TPS7A7833PWPT

TPS7A7836PWPR

TPS7A7836PWPT

TPS7A7850PWPR

TPS7A7850PWPT

ACTIVE

HTSSOP

PWP

3000 RoHS & Green

250 RoHS & Green

3000 RoHS & Green

250 RoHS & Green

3000 RoHS & Green

250 RoHS & Green

NIPDAU

Level-3-260C-168 HR

-40 to 125

S7A7833

NIPDAU

S7A7833

S7A7836

S7A7850

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

⁽³⁾MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

⁽⁵⁾Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6)

Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

10-Dec-2020

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

3-Jun-2022

TAPE AND REEL INFORMATION

REEL DIMENSIONS

TAPE DIMENSIONS

Reel

Diameter

Cavity

A0 Dimension designed to accommodate the component width

B0 Dimension designed to accommodate the component length

K0 Dimension designed to accommodate the component thickness

Overall width of the carrier tape

P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2

Q3 Q4

Q1 Q2

Q3 Q4

User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

TPS7A7833PWPR

TPS7A7833PWPT

TPS7A7836PWPR

TPS7A7836PWPT

TPS7A7850PWPR

TPS7A7850PWPT

HTSSOP PWP

3000

250

330.0

12.4

6.9

5.6

1.6

8.0

12.0

3000

250

3000

250

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

3-Jun-2022

TAPE AND REEL BOX DIMENSIONS

Width (mm)

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

TPS7A7833PWPR

TPS7A7833PWPT

TPS7A7836PWPR

TPS7A7836PWPT

TPS7A7850PWPR

TPS7A7850PWPT

HTSSOP

PWP

3000

250

356.0

35.0

3000

250

3000

250

Pack Materials-Page 2

GENERIC PACKAGE VIEW

PWP 14

4.4 x 5.0, 0.65 mm pitch

PowerPAD TSSOP - 1.2 mm max height

PLASTIC SMALL OUTLINE

This image is a representation of the package family, actual package may vary.

Refer to the product data sheet for package details.

4224995/A

www.ti.com

重要声明和免责声明

TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，

不保证没有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担

保。

这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验

证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。

这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。

您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成

本、损失和债务，TI 对此概不负责。

TI 提供的产品受 TI 的销售条款或 ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI 提供这些资源并不会扩展或以其他方式更改

TI 针对 TI 产品发布的适用的担保或担保免责声明。

TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE

邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

TPS7A7850PWPT [TI]

相关型号：

TPS7A80

TPS7A8001

TPS7A8001DRBR

TPS7A8001DRBT

TPS7A8001_13

TPS7A8008

TPS7A8010

TPS7A8012

TPS7A8012DRBR

TPS7A8012DRBT

TPS7A8015

TPS7A8018