TPS7A8300ARGRR_技术文档

TPS7A83A

SBVS304B – JUNE 2017 – REVISED OCTOBER 2021

TPS7A83A 2-A, High-Accuracy (0.75%), Low-Noise (4.4 μV_RMS) LDO Regulator

1 Features

3 Description

•

Low dropout: 200 mV (max) at 2 A

Accuracy over line, load, and temperature with

BIAS: 0.75% (max)

Output voltage noise:

– 4.4 μV_RMSat 0.8-V output

Input voltage range:

– Without BIAS: 1.4 V to 6.5 V

– With BIAS: 1.1 V to 6.5 V

TPS7A8300A output voltage range:

– Adjustable operation: 0.8 V to 5.2 V

– ANY-OUT^™operation: 0.8 V to 3.95 V

TPS7A8301A output voltage range:

– Adjustable operation: 0.5 V to 5.2 V

– ANY-OUT^™operation: 0.5 V to 2.075 V

Power-supply ripple rejection:

– 40 dB at 500 kHz

The TPS7A83A is a low-noise (4.4 μV_RMS), low-

dropout, linear regulator (LDO) capable of sourcing

2 A with only 200 mV of maximum dropout. The

TPS7A8300A output voltage is pin programmable

from 0.8 V to 3.95 V with a 50-mV resolution, and

adjustable from 0.8 V to 5.2 V using an external

resistor divider. The TPS7A8301A output voltage is

pin programmable from 0.5 V to 2.075 V with a 25-mV

resolution, and adjustable from 0.5 V to 5.2 V using

an external resistor divider.

•

The combination of low noise

, high PSRR,

and high output current capability makes the

TPS7A83A an excellent choice to power noise-

sensitive components such as those found in high-

speed communications, video, medical, or test

and measurement applications. This device is

designed for powering high-performance serializer

and deserializer (SerDes), analog-to-digital converters

(ADCs), digital-to-analog converters (DACs), and

RF components because the high performance of

the TPS7A83A limits power-supply-generated phase

noise and clock jitter. Specifically, RF amplifiers

benefit from the high-performance and 5.2-V output

capability of the device.

•

Excellent load transient response

Adjustable soft-start inrush control

Open-drain power-good (PG) output

2 Applications

•

Macro remote radio units (RRU)

Outdoor backhaul units

Active antenna system mMIMO (AAS)

Ultrasound scanners

Lab and field instrumentation

Sensor, imaging, and radar

Device Information⁽¹⁾

PART NUMBER

PACKAGE

BODY SIZE (nom)

3.50 mm × 3.50 mm

5.00 mm × 5.00 mm

TPS7A83A

VQFN (20)

(1) For all available packages, see the orderable addendum at

the end of the data sheet.

C_BIAS

Bias

Supply

1.2 V_IN

BIAS

IN

C_IN

TPS7A8300A: 0.9 V_OUT

TPS7A8301A: 0.55 V_OUT

PG

OUT

SNS

FB

EN

R_PG

To Digital

Load

C_OUT

NR/SS

C_NR/SS

TPS7A8300(01)A

1.6 V (0.8 V)

C_FF

800 mV(400 mV)

400 mV (200 mV)

200 mV (100 mV)

100 mV (50 mV)

50 mV (25 mV)

ANYOUT

Used to set

voltage

GND

Typical Application Circuit

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

TPS7A83A

SBVS304B – JUNE 2017 – REVISED OCTOBER 2021

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Table of Contents

1 Features............................................................................1

2 Applications.....................................................................1

3 Description.......................................................................1

4 Revision History.............................................................. 2

5 Description (continued).................................................. 3

6 Pin Configuration and Functions...................................4

7 Specifications.................................................................. 6

7.1 Absolute Maximum Ratings ....................................... 6

7.2 ESD Ratings .............................................................. 6

7.3 Recommended Operating Conditions ........................6

7.4 Thermal Information ...................................................7

7.5 Electrical Characteristics: General .............................7

7.6 Electrical Characteristics: TPS7A8300A ....................8

7.7 Electrical Characteristics: TPS7A8301A ....................9

7.8 Typical Characteristics: TPS7A8300A...................... 10

7.9 Typical Characteristics: TPS7A8301A...................... 17

8 Detailed Description......................................................22

8.1 Overview...................................................................22

8.2 Functional Block Diagram.........................................22

8.3 Feature Description...................................................23

8.4 Device Functional Modes..........................................26

9 Application and Implementation..................................27

9.1 Application Information............................................. 27

9.2 Typical Application.................................................... 44

10 Power Supply Recommendations..............................45

11 Layout...........................................................................46

11.1 Layout Guidelines................................................... 46

11.2 Layout Example...................................................... 46

12 Device and Documentation Support..........................47

12.1 Device Support....................................................... 47

12.2 Documentation Support.......................................... 47

12.3 Receiving Notification of Documentation Updates..47

12.4 Support Resources................................................. 47

12.5 Trademarks.............................................................47

12.6 Electrostatic Discharge Caution..............................48

12.7 Glossary..................................................................48

13 Mechanical, Packaging, and Orderable

Information.................................................................... 48

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision A (November 2017) to Revision B (October 2021)

Page

•

Updated the numbering format for tables and figures throughout the document .............................................. 1

Added TPS7A8301A to document......................................................................................................................1

Changed Features section..................................................................................................................................1

Changes from Revision * (June 2017) to Revision A (November 2017)

Page

•

Added RGW package to document.................................................................................................................... 1

Changed Packages Features bullet to include and differentiate RGW package ...............................................1

Changed Applications section............................................................................................................................ 1

Changed Description section..............................................................................................................................1

Added RGW thermal data to Thermal Information table.....................................................................................6

Added Typical Characteristics: TPS7A8301A section...................................................................................... 17

2

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5 Description (continued)

For digital loads [such as application-specific integrated circuits (ASICs), field-programmable gate arrays

(FPGAs), and digital signal processors (DSPs)] requiring low-input voltage, low-output (LILO) voltage operation,

the exceptional accuracy (0.75% over load and temperature), remote sensing, excellent transient performance,

and soft-start capabilities of the TPS7A83A ensure optimal system performance.

The versatility of the TPS7A83A makes the device a component of choice for many demanding applications.

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6 Pin Configuration and Functions

OUT

SNS

FB

1

2

3

4

5

15

14

13

12

11

IN

OUT

SNS

FB

1

2

3

4

5

15

14

13

12

11

IN

EN

Thermal

Pad

Thermal

Pad

NR/SS

BIAS

1.6V

NR/SS

BIAS

800mV

PG

50mV

25mV

Not to scale

Figure 6-1. TPS7A8300A RGW and RGR Package,

20-Pin VQFN (Top View)

Figure 6-2. TPS7A8301A RGW and RGR Package,

20-Pin VQFN (Top View)

Table 6-1. Pin Functions

I/O

DESCRIPTION

NAME

25mV

TPS7A8300A TPS7A8301A

—

5

6

50mV

ANY-OUT voltage setting pins. These pins connect to an internal feedback network.

Connect these pins to ground, SNS, or leave floating. Connecting these pins

to ground increases the output voltage, whereas connecting these pins to SNS

increases the resolution of the ANY-OUT network but decreases the range of the

network; multiple pins can be simultaneously connected to GND or SNS to select the

desired output voltage. Leave these pins floating (open) when not in use; see the

ANY-OUT Programmable Output Voltage section for additional details.

100mV

200mV

400mV

6

7

I

7

9

10

800mV

1.6V

10

11

—

BIAS supply voltage. This pin enables the use of low-input voltage, low-output (LILO)

voltage conditions (that is, V_IN= 1.2 V, V_OUT= 1 V) to reduce power dissipation

BIAS

EN

12

14

3

12

14

3

I

across the die. The use of a BIAS voltage improves dc and ac performance for V_IN≤

2.2 V. A 1-µF capacitor (0.47-µF capacitance) or larger must be connected between

this pin and ground. If not used, this pin must be left floating or tied to ground.

Enable pin. Driving this pin to logic high enables the device; driving this pin to logic

low disables the device. If enable functionality is not required, this pin must be

connected to IN or BIAS.

Feedback pin connected to the error amplifier. Although not required, placing a

10-nF feed-forward capacitor from FB to OUT (as close to the device as possible)

maximizes ac performance. Using a feed-forward capacitor may disrupt power-good

(PG) functionality; see the ANY-OUT Programmable Output Voltage and Adjustable

Operation sections for more details.

FB

Ground pin. These pins must be connected to ground, the thermal pad, and each

other with a low-impedance connection.

GND

IN

8, 18

—

I

Input supply voltage pin. A 10-μF or larger ceramic capacitor (5 μF of capacitance or

greater) from IN to ground is required to reduce the impedance of the input supply.

Place the input capacitor as close as possible to the input; see the Input and Output

Capacitor Requirements (C_INand C_OUT) section for more details.

15-17

4

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Table 6-1. Pin Functions (continued)

I/O

DESCRIPTION

NAME

TPS7A8300A TPS7A8301A

Noise-reduction and soft-start pin. Connecting an external capacitor between this pin

and ground reduces reference voltage noise and also enables the soft-start function.

Although not required, connecting a 10-nF or larger capacitor from NR/SS to GND

(as close as possible to the pin) maximizes ac performance; see the Input and

Output Capacitor Requirements (C_INand C_OUT) section for more details.

NR/SS

13

—

Regulated output pin. A 47-μF or larger ceramic capacitor (25 μF of capacitance or

greater) from OUT to ground is required for stability and must be placed as close

as possible to the output. Minimize the impedance from the OUT pin to the load;

see the Input and Output Capacitor Requirements (C_INand C_OUT) section for more

details.

OUT

PG

1, 19, 20

O

Active-high, PG pin. An open-drain output indicates when the output voltage reaches

V_IT(PG)of the target. Using a feed-forward capacitor may disrupt PG functionality;

see the Input and Output Capacitor Requirements (C_INand C_OUT) section for more

details.

4

2

4

2

Output voltage sense input pin. This pin connects the internal R₁resistor to the

output. Connect this pin to the load side of the output trace only if the ANY-OUT

feature is used. If the ANY-OUT feature is not used, leave this pin floating; see

the ANY-OUT Programmable Output Voltage and Adjustable Operation sections for

more details.

SNS

I

Connect the thermal pad to a large-area ground plane. The thermal pad is internally

connected to GND.

Thermal pad

—

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7 Specifications

7.1 Absolute Maximum Ratings

over junction temperature range (unless otherwise noted)⁽¹⁾

MIN

–0.3

MAX

7.0

UNIT

IN, BIAS, PG, EN

IN, BIAS, PG, EN (5% duty cycle, pulse duration = 200 µs)

SNS, OUT

7.5

Voltage

V_IN+ 0.3⁽²⁾

3.6

V

NR/SS, FB

50mV, 100mV, 200mV, 400mV, 800mV, 1.6V

OUT

V_OUT+ 0.3

Internally limited

A

Current

PG (sink current into device)

Operating junction, T_J

Storage, T_stg

5

150

mA

–55

Temperature

°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress

ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under

Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device

reliability.

(2) The absolute maximum rating is V_IN+ 0.3 V or 7.0 V, whichever is smaller.

7.2 ESD Ratings

VALUE

±2000

±500

UNIT

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾

V_(ESD)

Electrostatic discharge

V

Charged-device model (CDM), per JEDEC specification JESD22-C101⁽²⁾

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

over junction temperature range (unless otherwise noted)

MIN

1.1

3.0

0.8

0.5

0

NOM

MAX

6.5

5.2

V_IN

2

UNIT

V

V_IN

Input supply voltage range

Bias supply voltage range⁽¹⁾

Output voltage range (TPS7A8400A)⁽²⁾

Output voltage range (TPS7A8401A)⁽²⁾

Enable voltage range

V_BIAS

V

V_OUT

V

V_EN

V

I_OUT

C_IN

Output current

0

A

Input capacitor

10

22

1

22

10

µF

kΩ

nF

C_OUT

C_BIAS

R_PG

Output capacitor

Bias pin capacitor

Power-good pullup resistance

NR/SS capacitor

10

100

C_NR/SS

C_FF

10

Feed-forward capacitor

Top resistor value in feedback network for adjustable

operation

R₁

12.1⁽³⁾

kΩ

Bottom resistor value in feedback network for adjustable

operation

R₂

T_J

160⁽⁴⁾

125

kΩ

°C

Operating junction temperature

–40

(1) BIAS supply is required when the V_INsupply is below 1.4 V. Conversely, no BIAS supply is required when the V_INsupply is higher than

or equal to 1.4 V. A BIAS supply helps improve dc and ac performance for V_IN≤ 2.2 V.

(2) This output voltage range does not include device accuracy or accuracy of the feedback resistors.

(3) The 12.1-kΩ resistor is selected to optimize PSRR and noise by matching the internal R₁value.

(4) The upper limit for the R₂resistor is to ensure accuracy by making the current through the feedback network much larger than the

leakage current into the feedback node.

6

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7.4 Thermal Information

TPS7A83A

THERMAL METRIC⁽¹⁾

RGR (VQFN)

20 PINS

43.4

RGW (VQFN)

20 PINS

33.4

UNIT

R_θJA

Junction-to-ambient thermal resistance

°C/W

R_θJC(top)

R_θJB

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

36.8

24.9

17.6

13.0

ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

0.8

0.4

ψ_JB

17.6

13.0

R_θJC(bot)

3.4

3.9

(1) For more information about traditional and new thermalmetrics, see the Semiconductor and ICPackage Thermal Metrics application

report.

7.5 Electrical Characteristics: General

over operating junction temperature range (T_J= –40°C to +125°C), V_IN= 1.4 V or V_IN= V_OUT(nom)+ 0.4 V (whichever is

greater), V_BIAS= open, V_OUT(nom)= 0.8 V for TPS7A8300A or 0.5 V for TPS7A8301A⁽¹⁾, OUT connected to 50 Ω to GND⁽²⁾

V_EN= 1.1 V, C_IN= 10 μF, C_OUT= 22 μF, C_NR/SS= 0 nF, without C_FF, and PG pin pulled up to V_INwith 100 kΩ (unless

otherwise noted); typical values are at T_J= 25°C

,

PARAMETER

TEST CONDITIONS

MIN

TYP

1.02

320

1.31

253

2.83

290

MAX UNIT

V_UVLO1(IN)

V_HYS1(IN)

V_UVLO2(IN)

V_HYS2(IN)

V_UVLO(BIAS)

V_HYS(BIAS)

I_EN

Input supply UVLO with BIAS

V_UVLO1(IN)hysteresis

Input supply UVLO without BIAS

V_UVLO2(IN)hysteresis

Bias supply UVLO

V_INrising with V_BIAS= 3.0 V

1.085

1.39

2.9

V

V_BIAS= 3.0 V

V_INrising

mV

V

mV

V

V_BIASrising, V_IN= 1.1 V

V_IN= 1.1 V

V_UVLO(BIAS)hysteresis

EN pin current

mV

µA

V_IN= 6.5 V, V_EN= 0 V and 6.5 V

–0.1

0.1

3.5

V_IN= 1.1 V, V_BIAS= 6.5 V,

V_{OUT(nom) =}V_{OUT_MIN}, I_OUT= 2 A

I_BIAS

BIAS pin current

2.3

mA

V

EN pin low-level input voltage

(disable device)

V_IL(EN)

V_IH(EN)

V_OL(PG)

0

0.5

6.5

0.4

EN pin high-level input voltage

(enable device)

1.1

V

V_OUT< V_IT(PG), I_PG= –1 mA

(current into device)

PG pin low-level output voltage

V

I_lkg(PG)

I_NR/SS

I_FB

PG pin leakage current

NR/SS pin charging current

FB pin leakage current

V_OUT> V_IT(PG), V_PG= 6.5 V

V_NR/SS= GND, V_IN= 6.5 V

V_IN= 6.5 V

1

9.0

µA

nA

4.0

6.6

–100

100

Shutdown, temperature increasing

Reset, temperature decreasing

160

140

T_sd

T_J

Thermal shutdown temperature

Operating junction temperature

°C

–40

125

(1) V_OUT(nom)is the calculated V_OUTtarget value from the ANY-OUT in a fixed configuration. In an adjustable configuration, V_OUT(nom)is the

expected V_OUTvalue set by the external feedback resistors.

(2) This 50-Ω load is disconnected when the test conditions specify an I_OUTvalue.

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7.6 Electrical Characteristics: TPS7A8300A

over operating junction temperature range (T_J= –40°C to +125°C), V_IN= 1.4 V or V_IN= V_OUT(nom)+ 0.4 V (whichever is

greater), V_BIAS= open, V_OUT(nom)= 0.8 V⁽¹⁾, OUT connected to 50 Ω to GND⁽²⁾, V_EN= 1.1 V, C_IN= 10 μF, C_OUT= 47 μF,

C_NR/SS=0 nF, without C_FF, and PG pin pulled up to V_INwith 100 kohm, unless otherwise noted; Typical values are at T_J=

25°C

PARAMETER

Feedback voltage

NR/SS pin voltage

TEST CONDITIONS

MIN

TYP

MAX UNIT

V_FB

0.8

V

V_NR/SS

0.8

Using the ANY-OUT pins

0.8 – 1.0%

3.95 + 1.0%

Range

V

Using external resistors⁽³⁾

5.2 + 1.0%

1.0%

0.8 V ≤ V_OUT≤ 5.2⁽⁵⁾V,

5 mA ≤ I_OUT≤ 2 A, over V_IN

Accuracy^{(3) (4)}

–1.0%

V_OUT

Output voltage

Accuracy with

BIAS

1.1V ≤ V_IN≤ 2.2 V, 5 mA ≤ I_OUT≤ 2 A,

3.0 V ≤ V_BIAS≤ 6.5 V

–0.75%

0.75%

ΔV_OUT

ΔV_IN

/

Line regulation

Load regulation

I_OUT= 5 mA, 1.4 V ≤ V_IN≤ 6.5 V

0.03

0.07

mV/V

mV/A

5 mA ≤ I_OUT≤ 2 A, 3.0 V ≤ V_BIAS≤ 6.5 V,

V_IN= 1.1 V

ΔV_OUT

ΔI_OUT

/

5 mA ≤ I_OUT≤ 2 A

0.08

0.04

5 mA ≤ I_OUT≤ 2 A, V_OUT= 5.15 V

V_IN= 1.4 V, I_OUT= 2 A, V_FB= 0.8 V – 3%

V_IN= 5.3 V, I_OUT= 2 A, V_FB= 0.8 V – 3%

V_IN= 5.5 V, I_OUT= 2 A, V_FB= 0.8 V – 3%

200

300

V_DO

Dropout voltage

mV

V_IN= 1.1 V, V_BIAS= 5 V,

I_OUT= 2 A, V_FB= 0.8 V – 3%

125

3.8

V_OUTforced at 0.9 × V_OUT(nom)

V_IN= V_OUT(nom)+ 0.4 V

,

I_LIM

I_SC

Output current limit

2.8

3.3

1.0

A

Short-circuit current limit

R_LOAD= 20 mΩ, under foldback operation

f = 10 kHz,

V_OUT= 0.8 V,

V_BIAS= 5.0 V

42

39

f = 500 kHz, V_OUT

= 0.8 V, V_BIAS

5.0 V

V_IN– V_OUT= 0.4 V,

I_OUT= 2 A, C_NR/SS= 100 nF,

C_FF= 10 nF,

=

PSRR

Power-supply ripple rejection

dB

C_OUT= 22 μF

f = 10 kHz,

V_OUT= 5.0 V

40

25

f = 500 kHz, V_OUT

= 5.0 V

BW = 10 Hz to 100 kHz, V_IN= 1.1 V,

V_OUT= 0.8 V, V_BIAS= 5.0 V, I_OUT= 2 A,

C_NR/SS= 100 nF, C_FF= 10 nF,

C_OUT= 22 μF

4.4

7.7

V_n

Output noise voltage

GND pin current

μV_RMS

BW = 10 Hz to 100 kHz,

V_OUT= 5.0 V, I_OUT= 2 A, C_NR/SS= 100 nF,

C_FF= 10 nF, C_OUT= 22 μF

V_IN= 6.5 V, I_OUT= 5 mA

V_IN= 1.4 V, I_OUT= 2 A

2.8

3.7

1.2

4

5

mA

I_GND

Shutdown, PG = open, V_IN= 6.5 V, V_EN= 0.5 V

For falling V_OUT

25

μA

V

V_IT(PG)

PG pin threshold

PG pin hysteresis

82% . V_OUT88% . V_OUT93% . V_OUT

2% . V_OUT

V_HYS(PG)

For rising V_OUT

V

(1) V_OUT(nom)is the calculated V_OUTtarget value from the ANY-OUT in a fixed configuration. In an adjustable configuration, V_OUT(nom)is the

expected V_OUTvalue set by the external feedback resistors.

(2) This 50-Ω load is disconnected when the test conditions specify an I_OUTvalue.

(3) When the device is connected to external feedback resistors at the FB pin, external resistor tolerances are not included.

(4) The device is not tested under conditions where V_IN> V_OUT+ 1.7 V and I_OUT= 3 A, because the power dissipation is higher than the

maximum rating of the package.

(5) For V_OUT≤ 5 V, V_IN= V_OUT+ 0.4 V; for V_OUT> 5 V, V_IN= V_OUT+ 0.45 V.

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7.7 Electrical Characteristics: TPS7A8301A

over operating junction temperature range (T_J= –40°C to +125°C), V_IN= 1.4 V or V_IN= V_OUT(nom)+ 0.4 V (whichever is

greater), V_BIAS= open, V_OUT(nom)= 0.5 V⁽¹⁾, OUT connected to 50 Ω to GND⁽²⁾, V_EN= 1.1 V, C_IN= 10 μF, C_OUT= 47 μF,

C_NR/SS= 0 nF, without C_FF, and PG pin pulled up to V_INwith 100 kΩ (unless otherwise noted); typical values are at T_J= 25°C

PARAMETER

Feedback voltage

NR/SS pin voltage

TEST CONDITIONS

MIN

TYP

MAX UNIT

V_FB

0.5

V

V_NR/SS

0.5

2.075 +

1.0%

Using the ANY-OUT pins

0.5 – 1.2%

–1.25%

Range

V

Using external resistors⁽³⁾

5.2 + 1.0%

0.5 V ≤ V_OUT≤ 5.2⁽⁵⁾V,

5 mA ≤ I_OUT≤ 2 A, over V_IN

V_OUT

Output voltage

Accuracy^{(3) (4)}

1.25%

1.1%

Accuracy with

BIAS

V_IN= 1.1 V, V_OUT= 0.5 V,

5 mA ≤ I_OUT≤ 2 A, 3.0 V ≤ V_BIAS≤ 6.5 V

–1.0%

ΔV_OUT

ΔV_IN

/

Line regulation

Load regulation

I_OUT= 5 mA, 1.4 V ≤ V_IN≤ 6.5 V

0.03

0.07

mV/V

mV/A

5 mA ≤ I_OUT≤ 2 A, 3.0 V ≤ V_BIAS≤ 6.5 V,

V_IN= 1.1 V

ΔV_OUT

ΔI_OUT

/

5 mA ≤ I_OUT≤ 2 A

0.08

0.04

5 mA ≤ I_OUT≤ 2 A, V_OUT= 5.2 V

V_IN= 1.4 V, I_OUT= 2 A, V_FB= 0.5 V – 3%

V_IN= 5.3 V, I_OUT= 2 A, V_FB= 0.5 V – 3%

V_IN= 5.5 V, I_OUT= 2 A, V_FB= 0.5 V – 3%

210

215

300

V_DO

Dropout voltage

mV

V_IN= 1.1 V, V_BIAS= 5 V,

I_OUT= 2 A, V_FB= 0.5 V – 3%

125

3.8

V_OUTforced at 0.9 × V_OUT(nom)

V_IN= V_OUT(nom)+ 0.4 V

,

I_LIM

I_SC

Output current limit

2.8

3.3

1

A

Short-circuit current limit

R_LOAD= 20 mΩ, under foldback operation

f = 10 kHz,

V_OUT= 0.5 V,

V_BIAS= 5.0 V

42

39

V_IN– V_OUT= 0.4 V,

I_OUT= 2 A,

f = 500 kHz, V_OUT

= 0.5 V, V_BIAS

5.0 V

=

PSRR

Power-supply ripple rejection

C_NR/SS= 100 nF,

C_FF= 10 nF,

C_OUT= 22 μF

dB

f = 10 kHz,

V_OUT= 5.0 V

40

25

f = 500 kHz, V_OUT

= 5.0 V

BW = 10 Hz to 100 kHz, V_IN= 1.1 V,

V_OUT= 0.5 V, V_BIAS= 5.0 V, I_OUT= 2 A,

C_NR/SS= 100 nF, C_FF= 10 nF,

C_OUT= 22 μF

4.4

7.7

V_n

Output noise voltage

GND pin current

μV_RMS

BW = 10 Hz to 100 kHz,

V_OUT= 5.0 V, I_OUT= 2 A,

C_NR/SS= 100 nF,

C_FF= 10 nF, C_OUT= 22 μF

V_IN= 6.5 V, I_OUT= 5 mA

2.3

3.7

1.2

4.3

5

mA

I_GND

V_IN= 1.4 V, I_OUT= 2 A

Shutdown, PG = open, V_IN= 6.5 V, V_EN= 0.5 V

25

μA

V

80% .

V_OUT

86% .

V_OUT

91% .

V_OUT

V_IT(PG)

PG pin threshold

PG pin hysteresis

For falling V_OUT

For rising V_OUT

V_HYS(PG)

5% . V_OUT

V

(1) V_OUT(nom)is the calculated V_OUTtarget value from the ANY-OUT in a fixed configuration. In an adjustable configuration, V_OUT(nom)is the

expected V_OUTvalue set by the external feedback resistors.

(2) This 50-Ω load is disconnected when the test conditions specify an I_OUTvalue.

(3) When the device is connected to external feedback resistors at the FB pin, external resistor tolerances are not included.

(4) The device is not tested under conditions where V_IN> V_OUT+ 1.7 V and I_OUT= 3 A, because the power dissipation is higher than the

maximum rating of the package.

(5) For V_OUT≤ 5 V, V_IN= V_OUT+ 0.4 V; for V_OUT> 5 V, V_IN= V_OUT+ 0.45 V.

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7.8 Typical Characteristics: TPS7A8300A

at T_A= 25°C, V_IN= 1.4 V or V_IN= V_OUT(nom)+ 0.3 V (whichever is greater), V_BIAS= open, V_OUT(nom)= 0.8 V, V_EN= 1.1 V, C_IN

= 10 μF, C_OUT= 22 μF, C_NR/SS= 0 nF, C_FF= 0 nF, and PG pin pulled up to V_INwith 100 kΩ (unless otherwise noted)

80

60

40

20

0

70

60

50

40

30

20

10

0

I_OUT= 100mA

I_OUT= 250mA

I_OUT= 500mA

I_OUT= 750mA

I_OUT= 1A

V_IN= 1.4V

V_IN= 1.35V

V_IN= 1.3V

V_IN= 1.25V

V_IN= 1.2V

V_IN= 1.15V

V_IN= 1.1V

I_OUT= 1.5A

I_OUT= 2A

10

100

1k

10k

Frequency (Hz)

100k

1M

10M

10

100

1k

10k

Frequency (Hz)

100k

1M

10M

Fig1

Fig2

V_IN= 1.1 V, V_BIAS= 5 V, C_OUT= 22 μF, C_NR/SS= 10 nF,

C_FF= 10 nF

I_OUT= 2 A, V_BIAS= 5 V, C_OUT= 22 μF, C_NR/SS= 10 nF,

C_FF= 10 nF

Figure 7-1. PSRR vs Frequency and I_OUT

Figure 7-2. PSRR vs Frequency and V_INWith BIAS

70

60

50

40

30

60

50

40

30

20

V_IN= 1.1V, V_BIAS= 5V

V_IN= 1.2V, V_BIAS= 5V

V_IN= 1.4V, V_BIAS= 0V

V_IN= 2.3V, V_BIAS= 0V

V_BIAS= 0V

V_BIAS= 3V

V_BIAS= 5V

10

0

10

0

10

100

1k

10k

Frequency (Hz)

100k

1M

10M

100

1k

10k

Frequency (Hz)

100k

1M

10M

Fig2

Fig4

V_IN= 1.4 V, I_OUT= 1 A, C_OUT= 22 μF, C_NR/SS= 10 nF,

C_FF= 10 nF

I_OUT= 1 A, C_OUT= 22 μF, C_NR/SS= 10 nF, C_FF= 10 nF

Figure 7-3. PSRR vs Frequency and V_BIAS

Figure 7-4. PSRR vs Frequency and V_IN

70

80

70

60

50

40

60

50

40

30

20

10

0

30

V_IN= 4V

V_IN= 3.85V

V_IN= 3.8V

V_IN= 3.75V

V_IN= 3.7V

V_IN= 3.65V

V_IN= 3.6V

20

10

0

V_OUT= 0.8V

V_OUT= 2.5V

-10

-20

10

100

1k

10k

Frequency (Hz)

100k

1M

10M

10

100

1k

10k

Frequency (Hz)

100k

1M

10M

Fig4

Fig6

V_IN= V_OUT+ 0.3 V, V_BIAS= 5 V, I_OUT= 2 A, C_OUT= 22 μF,

C_NR/SS= 10 nF, C_FF= 10 nF

I_OUT= 2 A, C_OUT= 22 μF, C_NR/SS= 10 nF, C_FF= 10 nF

Figure 7-5. PSRR vs Frequency and V_OUTWith BIAS

Figure 7-6. PSRR vs Frequency and V_INfor V_OUT= 3.3 V

10

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7.8 Typical Characteristics: TPS7A8300A (continued)

at T_A= 25°C, V_IN= 1.4 V or V_IN= V_OUT(nom)+ 0.3 V (whichever is greater), V_BIAS= open, V_OUT(nom)= 0.8 V, V_EN= 1.1 V, C_IN

= 10 μF, C_OUT= 22 μF, C_NR/SS= 0 nF, C_FF= 0 nF, and PG pin pulled up to V_INwith 100 kΩ (unless otherwise noted)

80

70

60

50

40

30

20

10

0

100

80

60

40

20

0

V_BIAS= 3.0 V

V_BIAS= 5.0 V

V_BIAS= 6.5 V

C_OUT= 22uF

C_OUT= 100uF

-10

-20

1x10¹

1x10²

1x10³

Frequency (Hz)

1x10⁴

1x10⁵

1x10⁶

1x10⁷

10

100

1k

10k

Frequency (Hz)

100k

1M

10M

Fig7

V_IN= V_OUT+ 0.3 V, V_OUT= 1 V, I_OUT= 2 A,

V_IN= V_OUT+ 0.3 V, V_OUT= 1 V, V_BIAS= 5 V, I_OUT= 2 A,

C_NR/SS= 10 nF, C_FF= 10 nF

C_OUT= 47 μF || 10 μF || 10 μF, C_NR/SS= 10 nF, C_FF= 10 nF

Figure 7-8. V_BIASPSRR vs Frequency

Figure 7-7. PSRR vs Frequency and C_OUT

12

2

1

I_OUT= 2A

11

10

9

0.1

8

7

0.01

6

V_OUT= 0.8 V

V_OUT= 1.5 V

V_OUT= 3.3 V

V_OUT= 5 V

0.001

5

4

0.6

1.2

1.8

2.4

Output Voltage (V)

3

3.6

4.2

4.8

5.4

10

100

1k

10k 100k

Frequency (Hz)

1M

10M

Fig9

Fig1

V_IN= V_OUT+ 0.3 V and V_BIAS= 5 V for V_OUT≤ 2.2 V,

C_OUT= 22 μF, C_BIAS= 10 μF, C_NR/SS= 10 nF, C_FF= 10 nF,

RMS noise BW = 10 Hz to 100 kHz

V_IN= V_OUT+ 0.3 V and V_BIAS= 5 V for V_OUT≤ 2.2 V,

I_OUT= 2 A, C_OUT= 22 μF, C_BIAS= 10 μF, C_NR/SS= 10 nF,

C_FF= 10 nF, RMS noise BW = 10 Hz to 100 kHz

Figure 7-9. Output Voltage Noise vs Output Voltage

Figure 7-10. Output Noise vs Frequency and Output Voltage

2

0.5

V_IN= 1.4 V, V_BIAS= 5 V, 4.7 mV_RMS

V_IN= 1.4 V, 6.2 mV_RMS

1

V_IN= 1.5 V, 4.7 mV_RMS

V_IN= 2.5 V, 4.7 mV_RMS

V_IN= 5.3 V, 4.7 mV_RMS

0.1

0.01

C_NR/SS= 0 nF, 8.4 mV_RMS

C_NR/SS= 0.1 nF, 7.3 mV_RMS

C_NR/SS= 10 nF, 4.5 mV_RMS

C_NR/SS= 100 nF, 4.3 mV_RMS

C_NR/SS= 1 mF, 4.28 mV_RMS

0.001

10

100

1k

10k 100k

Frequency (Hz)

1M

10M

10

100

1k

10k 100k

Frequency (Hz)

1M

10M

Fig1

I_OUT= 2 A, C_OUT= 22 μF, C_NR/SS= 10 nF, C_FF= 10 nF,

RMS noise BW = 10 Hz to 100 kHz

V_IN= 1.1 V, V_OUT= 0.8 V, V_BIAS= 5 V, I_OUT= 2 A,

C_OUT= 22 μF, C_BIAS= 10 μF, C_FF= 10 nF,

RMS noise BW = 10 Hz to 100 kHz

Figure 7-11. Output Noise vs Frequency and Input Voltage

Figure 7-12. Output Noise vs Frequency and C_NR/SS

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7.8 Typical Characteristics: TPS7A8300A (continued)

at T_A= 25°C, V_IN= 1.4 V or V_IN= V_OUT(nom)+ 0.3 V (whichever is greater), V_BIAS= open, V_OUT(nom)= 0.8 V, V_EN= 1.1 V, C_IN

= 10 μF, C_OUT= 22 μF, C_NR/SS= 0 nF, C_FF= 0 nF, and PG pin pulled up to V_INwith 100 kΩ (unless otherwise noted)

2

1

2

1

0.1

0.01

0.1

0.01

C_FF= 0 nF, 22 mV_RMS

C_NR/SS= 10 nF, C_FF= 10 nF, 11.8 mV_RMS

C_NR/SS= 10 nF, C_FF= 100 nF, 10.2 mV_RMS

C_NR/SS= 100 nF, C_FF= 100 nF, 6.3 mV_RMS

C_FF= 1 nF, 15.7 mV_RMS

C_FF= 10 nF, 11.8 mV_RMS

C_FF= 100 nF, 10.2 mV_RMS

0.001

10

100

1k

10k 100k

Frequency (Hz)

1M

10M

10

100

1k

10k 100k

Frequency (Hz)

1M

10M

Fig1

V_IN= 5.3 V, V_OUT= 5 V, V_BIAS= 5 V, I_OUT= 2 A, C_OUT= 22 μF,

C_BIAS= 10 μF, C_NR/SS= 10 nF,

I_OUT= 2 A, C_OUT= 22 μF, C_FF= 10 nF,

RMS noise BW = 10 Hz to 100 kHz

Figure 7-13. Output Noise vs Frequency and C_FF

Figure 7-14. Output Noise at 5-V Output

1.2

10

50

Output Current

V_IN= 1.4V

V_IN= 1.1V, V_BIAS= 5V

9

8

7

6

5

4

3

2

1

0

40

30

20

10

0

1

0.8

0.6

0.4

-10

-20

-30

-40

-50

V_EN

0.2

0

V_OUT, C_NR/SS= 0 nF

V_OUT, C_NR/SS= 10 nF

V_OUT, C_NR/SS= 47 nF

V_OUT, C_NR/SS= 100 nF

-0.2

0

0.1

0.2

0.3 0.4

Time (ms)

0.5

0.6

0.7

0

5

10

15

20

25

Time (ms)

30

35

40

45

50

Fig1

V_IN= 1.2 V, V_OUT= 0.9 V, V_BIAS= 5 V, I_OUT= 2 A,

C_OUT= 22 μF, C_BIAS= 10 μF, C_FF= 10 nF

I_{OUT, DC}= 100 mA, slew rate = 1 A/μs, C_NR/SS= 10 nF,

C_OUT= 22 μF, C_BIAS= 10 μF

Figure 7-15. Start-Up Waveform vs Time and C_NR/SS

Figure 7-16. Load Transient vs Time for V_OUT= 0.8 V

10

9

8

7

6

5

4

3

2

1

0

50

40

30

20

10

0

50

Output Current

V_OUT= 5V

2A/us

1A/us

0.5A/us

40

30

20

10

0

-10

-20

-30

-40

-50

-10

-20

-30

-40

-50

0

50

100

150

Time (ms)

200

250

300

0

50

100

150

Time (ms)

200

250

300

Fig1

I_{OUT, DC}= 100 mA, C_OUT= 22 μF, C_NR/SS= C_FF= 10 nF,

slew rate = 1 A/μs

V_OUT= 5 V, I_{OUT, DC}= 100 mA, I_OUT= 100 mA to 2 A,

C_OUT= 22 μF, C_NR/SS= C_FF= 10 nF

Figure 7-17. Load Transient vs Time for V_OUT= 5 V

Figure 7-18. Load Transient vs Time and Slew Rate

12

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7.8 Typical Characteristics: TPS7A8300A (continued)

at T_A= 25°C, V_IN= 1.4 V or V_IN= V_OUT(nom)+ 0.3 V (whichever is greater), V_BIAS= open, V_OUT(nom)= 0.8 V, V_EN= 1.1 V, C_IN

= 10 μF, C_OUT= 22 μF, C_NR/SS= 0 nF, C_FF= 0 nF, and PG pin pulled up to V_INwith 100 kΩ (unless otherwise noted)

50

40

700

600

500

400

300

200

100

0

V_OUT, 100mA to 2A

V_OUT, 500mA to 2A

-40èC

0èC

25èC

85èC

125èC

30

20

10

0

-10

-20

-30

-40

-50

0

50

100

150

Time (ms)

200

250

300

1

1.5

2

2.5

3

3.5

4

Input Voltage (V)

4.5

5

5.5

6

6.5

Fig1

D023

I_OUT= 2 A

V_IN= 5.3 V, V_BIAS= 5 V, C_OUT= 22 μF, C_BIAS= 10 μF,

V_OUT= 5 V, C_NR/SS= C_FF= 10 nF, slew rate = 1 A/μs

Figure 7-20. Dropout Voltage vs Input Voltage Without BIAS

Figure 7-19. Load Transient vs Time and DC Load

700

140

-40°C

0°C

25°C

85°C

125°C

-40èC

0èC

25èC

85èC

125èC

120

100

80

60

40

20

0

600

500

400

300

200

100

0

-20

1

1.5

2

2.5

3

3.5

4

Input Voltage (V)

4.5

5

5.5

6

6.5

0

0.2 0.4 0.6 0.8

1

Output Current (A)

1.2 1.4 1.6 1.8

2

D024

D025

I_OUT= 2 A, V_BIAS= 6.5 V

V_IN= 1.4 V

Figure 7-21. Dropout Voltage vs Input Voltage With BIAS

Figure 7-22. Dropout Voltage vs Output Current Without BIAS

150

180

-40°C

0°C

25°C

-40èC

0èC

25èC

85èC

125èC

125

150

120

90

60

30

0

85°C

125°C

100

75

50

25

0

0.25

0.5

0.75

1

1.25

Output Current (A)

1.5

1.75

2

0

0.2 0.4 0.6 0.8

1

Output Current (A)

1.2 1.4 1.6 1.8

2

D026

D027

V_IN= 1.1 V, V_BIAS= 3 V

V_IN= 5.5 V

Figure 7-23. Dropout Voltage vs Output Current With BIAS

Figure 7-24. Dropout Voltage vs Output Current (High V_IN)

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7.8 Typical Characteristics: TPS7A8300A (continued)

at T_A= 25°C, V_IN= 1.4 V or V_IN= V_OUT(nom)+ 0.3 V (whichever is greater), V_BIAS= open, V_OUT(nom)= 0.8 V, V_EN= 1.1 V, C_IN

= 10 μF, C_OUT= 22 μF, C_NR/SS= 0 nF, C_FF= 0 nF, and PG pin pulled up to V_INwith 100 kΩ (unless otherwise noted)

0.35

0.3

0.05

0.025

0

0.25

0.2

0.15

0.1

-40èC

0èC

25èC

85èC

125èC

-0.025

-0.05

-0.075

-0.1

0.05

0

-0.05

-0.1

-0.15

-0.2

-40°C

0°C

25°C

85°C

125°C

0

0.25

0.5

0.75

1

1.25

Output Current (A)

1.5

1.75

2

0.5

1

1.5

2

2.5

3

Output Voltage (V)

3.5

4

4.5

5

D026

D025

V_IN= 1.4 V

I_OUT= 100 mA to 2 A

Figure 7-26. Load Regulation

Figure 7-25. Load Regulation vs Output Voltage

0.05

0.025

0

0.025

0

-0.025

-0.05

-0.075

-0.1

-0.025

-0.05

-0.075

-0.1

-40èC

0èC

25èC

85èC

125èC

-40èC

0èC

25èC

85èC

125èC

0

0.25

0.5

0.75

Output Current (A)

1

1.25

1.5

1.75

2

0

0.25

0.5

0.75

Output Current (A)

1

1.25

1.5

1.75

2

D027

D028

V_IN= 3.8 V

V_IN= 5.5 V

Figure 7-27. Load Regulation (3.3-V Output)

Figure 7-28. Load Regulation (5-V Output)

0

-0.025

-0.05

25

0

-25

-50

-75

-100

-0.075

-0.1

-40°C

0°C

25°C

85°C

125°C

-40°C

0°C

25°C

85°C

125°C

-0.125

1

1.5

2

2.5

3

3.5

4

Input Voltage (V)

4.5

5

5.5

6

6.5

3

3.5

4

4.5 5

Bias Voltage (V)

5.5

6

6.5

V_OUT= 0.8 V, I_OUT= 5 mA

Figure 7-29. Line Regulation

V_OUT= 0.8 V, V_IN= 1.1 V, I_OUT= 5 mA, V_BIAS= 5 V

Figure 7-30. Line Regulation With BIAS

14

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7.8 Typical Characteristics: TPS7A8300A (continued)

at T_A= 25°C, V_IN= 1.4 V or V_IN= V_OUT(nom)+ 0.3 V (whichever is greater), V_BIAS= open, V_OUT(nom)= 0.8 V, V_EN= 1.1 V, C_IN

= 10 μF, C_OUT= 22 μF, C_NR/SS= 0 nF, C_FF= 0 nF, and PG pin pulled up to V_INwith 100 kΩ (unless otherwise noted)

0

-20

-40

-60

3.3

3

2.7

2.4

2.1

1.8

1.5

-40°C

0°C

25°C

85°C

125°C

-40°C

0°C

25°C

85°C

125°C

5.25

5.5

5.75

Input Voltage (V)

6

6.25

6.5

1

2

3

4

Input Voltage (V)

5

6

7

I_OUT= 5 mA

V_BIAS= 0 V, I_OUT= 5 mA

Figure 7-32. Ground Pin Current vs Input Voltage

Figure 7-31. Line Regulation (5-V Output)

2.4

2

5

-40°C

0°C

25°C

85°C

125°C

4

3

2

1

0

1.6

1.2

0.8

-40°C

0°C

25°C

85°C

125°C

3

3.5

4

4.5

Bias Voltage (V)

5

5.5

6

6.5

1

1.5

2

2.5

3

3.5

Input Voltage (V)

4

4.5

5

5.5

6

6.5

V_IN= 1.1 V, I_OUT= 5 mA

V_BIAS= 0 V

Figure 7-33. BIAS Pin Current vs Bias Voltage

Figure 7-34. Shutdown Current vs Input Voltage

6

5

4

3

2

1

0

7.5

-40°C

0°C

25°C

85°C

125°C

7

6.5

6

5.5

5

-40°C

0°C

25°C

85°C

125°C

4.5

3

3.5

4

4.5

Bias Voltage (V)

5

5.5

6

6.5

1

1.5

2

2.5

3

3.5

Input Voltage (V)

4

4.5

5

5.5

6

6.5

V_IN= 1.1 V

V_BIAS= 0 V

Figure 7-35. Shutdown Current vs Bias Voltage

Figure 7-36. I_NR/SSCurrent vs Input Voltage

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7.8 Typical Characteristics: TPS7A8300A (continued)

at T_A= 25°C, V_IN= 1.4 V or V_IN= V_OUT(nom)+ 0.3 V (whichever is greater), V_BIAS= open, V_OUT(nom)= 0.8 V, V_EN= 1.1 V, C_IN

= 10 μF, C_OUT= 22 μF, C_NR/SS= 0 nF, C_FF= 0 nF, and PG pin pulled up to V_INwith 100 kΩ (unless otherwise noted)

1.4

1.2

1

3

2.9

2.8

2.7

2.6

2.5

V_UVLO(BIAS), Rising

V_UVLO(BIAS), Falling

0.8

0.6

0.4

0.2

V_UVLO2(IN)w/o BIAS, Rising

V_UVLO2(IN)w/o BIAS, Falling

V_UVLO1(IN)w/ BIAS, Rising

V_UVLO1(IN)w/ BIAS, Falling

-40

-20

0

20

40 60

Temperature (°C)

80

100 120 140

-60

-30

0

30 60

Temperature (°C)

90

120

150

UVLO

V_IN= 1.1 V

Figure 7-38. V_BIASUVLO vs Temperature

Figure 7-37. V_INUVLO vs Temperature

0.85

0.8

0.75

0.6

0.45

0.3

0.15

0

-40°C

0°C

25°C

85°C

125°C

0.75

0.7

0.65

0.6

V_IH(EN), V_IN= 1.4 V

V_IH(EN), V_IN= 6.5 V

V_IL(EN), V_IN= 1.4 V

V_IL(EN), V_IN= 6.5 V

0.55

-40

-20

0

20

40 60

Temperature (°C)

80

100 120 140

0

0.5

1

PG Current Sink (mA)

1.5

2

2.5

3

V_IN= 1.4 V, 6.5 V

Figure 7-39. Enable Threshold vs Temperature

0.4

Figure 7-40. PG Voltage vs PG Current Sink

90.25

90

-40°C

0°C

V_IT(PG)Rising, V_IN= 1.4 V

V_IT(PG)Rising, V_IN= 6.5 V

V_IT(PG)Falling, V_IN= 1.4V

V_IT(PG)Falling, V_IN= 6.5 V

25°C

85°C

125°C

89.75

89.5

89.25

89

0.32

0.24

0.16

0.08

0

88.75

88.5

88.25

88

87.75

-50

-25

0

25 50

Temperature (°C)

75

100

125

0

0.5

1

1.5

2

PG Current Sink (mA)

2.5

3

V_IN= 6.5 V

Figure 7-42. PG Threshold vs Temperature

Figure 7-41. PG Voltage vs PG Current Sink

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7.9 Typical Characteristics: TPS7A8301A

at T_A= 25°C, V_IN= 1.4 V or V_IN= V_OUT(nom)+ 0.3 V (whichever is greater), V_BIAS= open, V_OUT(nom)= 0.8 V, V_EN= 1.1 V, C_IN

= 10 μF, C_OUT= 22 μF, C_NR/SS= 0 nF, C_FF= 0 nF, and PG pin pulled up to V_INwith 100 kΩ (unless otherwise noted)

100

V_BIAS

0 V

3 V

5 V

6.5 V

90

80

70

60

50

40

30

20

10

0

10

100

1k

10k

Frequency (Hz)

100k

1M

10M

V_IN= 1.4 V, I_OUT= 1 A, C_OUT= 22 μF, C_NR/SS= 10 nF,

C_FF= 10 nF

V_IN= 1.1 V, V_BIAS= 5 V, C_OUT= 22 μF, C_NR/SS= 10 nF,

C_FF= 10 nF

Figure 7-44. PSRR vs Frequency and V_BIAS

Figure 7-43. PSRR vs Frequency and I_OUT

100

90

80

70

60

50

40

30

20

10

0

V_IN

1.10 V ( V_BIAS= 5V )

1.20 V ( V_BIAS= 5V )

1.40 V ( V_BIAS= 0V )

1.40 V ( V_BIAS= 5V )

2.50 V ( V_BIAS= 0V )

5.0 V ( V_BIAS= 0V )

10

100

1k

10k

Frequency (Hz)

100k

1M

10M

I_OUT= 1 A, C_OUT= 22 μF, C_NR/SS= 10 nF, C_FF= 10 nF

V_IN= 5.5 V, V_OUT= 5 V, C_OUT= 47 μF || 10 μF || 10μF,

C_NR/SS= 10 nF, C_FF= 10 nF

Figure 7-45. PSRR vs Frequency and V_IN

Figure 7-46. PSRR vs Frequency and I_OUT(V_OUT= 5 V)

140

-40èC

0èC

25èC

85èC

125èC

120

100

80

60

40

20

0

-20

0

0.2 0.4 0.6 0.8

1

Output Current (A)

1.2 1.4 1.6 1.8

2

D025

V_IN= V_OUT+ 0.3 V or V_IN= 1.1 V (whichever is greater) and

V_BIAS= 5 V for V_OUT≤ 2.2 V,

V_IN= 1.4 V

C_OUT= 47 μF || 10μF || 10μF, C_NR/SS= 10 nF, C_FF= 10 nF,

RMS noise BW = 10 Hz to 100 kHz

Figure 7-47. Output Voltage Noise vs V_OUT

Figure 7-48. Dropout Voltage vs Output Current Without BIAS

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7.9 Typical Characteristics: TPS7A8301A (continued)

at T_A= 25°C, V_IN= 1.4 V or V_IN= V_OUT(nom)+ 0.3 V (whichever is greater), V_BIAS= open, V_OUT(nom)= 0.8 V, V_EN= 1.1 V, C_IN

= 10 μF, C_OUT= 22 μF, C_NR/SS= 0 nF, C_FF= 0 nF, and PG pin pulled up to V_INwith 100 kΩ (unless otherwise noted)

150

125

100

75

180

150

120

90

-40°C

0°C

25°C

85°C

125°C

-40èC

0èC

25èC

85èC

125èC

50

60

25

30

0

0.25

0.5

0.75

1

1.25

Output Current (A)

1.5

1.75

2

0

0.2 0.4 0.6 0.8

1

Output Current (A)

1.2 1.4 1.6 1.8

2

D026

D027

V_IN= 1.1 V, V_BIAS= 3 V

V_IN= 5.5 V

Figure 7-49. Dropout Voltage vs Output Current With BIAS

Figure 7-50. Dropout Voltage vs Output Current (High V_IN)

V_IN= 1.4 V

V_IN= 3.8 V

Figure 7-51. Load Regulation

Figure 7-52. Load Regulation (3.3-V Output)

0

-0.05

-0.1

-0.15

-0.2

-0.25

-0.3

T_J

-0.35

-0.4

-55°C

-40°C

0°C

25°C

85°C

125°C

150°C

6

1

1.5

2

2.5

3 4

Input Voltage (V)

3.5

4.5

5

5.5

6.5

V_OUT= 0.5 V, I_OUT= 5 mA

V_IN= 5.55 V, V_OUT= 5.15 V

Figure 7-53. Load Regulation (5-V Output)

Figure 7-54. Line Regulation vs V_IN

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7.9 Typical Characteristics: TPS7A8301A (continued)

at T_A= 25°C, V_IN= 1.4 V or V_IN= V_OUT(nom)+ 0.3 V (whichever is greater), V_BIAS= open, V_OUT(nom)= 0.8 V, V_EN= 1.1 V, C_IN

= 10 μF, C_OUT= 22 μF, C_NR/SS= 0 nF, C_FF= 0 nF, and PG pin pulled up to V_INwith 100 kΩ (unless otherwise noted)

0

-20

20

T_J

-55°C

-40°C

0°C

10

-40

25°C

85°C

125°C

150°C

0

-60

-80

-10

-20

-30

-40

T_J

-55°C

-40°C

0°C

25°C

85°C

125°C

150°C

-100

-120

-140

-160

3

3.5

4

4.5 5

Bias Voltage (V)

5.5

6

6.5

5.25

5.5

5.75 6

Input Voltage (V)

6.25

6.5

V_OUT= 0.5 V, V_IN= 1.1 V, I_OUT= 5 mA, V_BIAS= 5 V

I_OUT= 5 mA

Figure 7-55. Line Regulation With BIAS

Figure 7-56. Line Regulation vs V_IN(5.2-V Output)

3.2

4

3.5

3

2.8

2.4

2

2.5

2

1.6

1.2

0.8

T_J

5

-55°C

-40°C

0°C

25°C

85°C

125°C

150°C

6

-55°C

-40°C

0°C

25°C

85°C

125°C

150°C

1.5

1

1.5

2

2.5

3 4

Input Voltage (V)

3.5

4.5

5

5.5

3

3.5

4

4.5

5.5

6

6.5

Bias Voltage (V)

V_BIAS= 0 V, I_OUT= 5 mA

Figure 7-57. Ground Pin Current vs Input Voltage

10

V_IN= 1.1 V, I_OUT= 5 mA

Figure 7-58. BIAS Pin Current vs Bias Voltage

8

7

6

5

4

3

2

1

T_J

9

8

7

6

5

4

3

2

1

0

-55°C

-40°C

0°C

25°C

85°C

125°C

150°C

-55°C

-40°C

0°C

25°C

85°C

125°C

150°C

0

3

1

1.5

2

2.5

3

3.5

4

Input Voltage (V)

4.5

5

5.5

6

3.5

4

4.5 5

Input Voltage (V)

5.5

6

6.5

V_BIAS= 0 V

V_IN= 1.1 V

Figure 7-59. Shutdown Current vs Input Voltage

Figure 7-60. Shutdown Current vs Bias Voltage

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7.9 Typical Characteristics: TPS7A8301A (continued)

at T_A= 25°C, V_IN= 1.4 V or V_IN= V_OUT(nom)+ 0.3 V (whichever is greater), V_BIAS= open, V_OUT(nom)= 0.8 V, V_EN= 1.1 V, C_IN

= 10 μF, C_OUT= 22 μF, C_NR/SS= 0 nF, C_FF= 0 nF, and PG pin pulled up to V_INwith 100 kΩ (unless otherwise noted)

8

7

6

5

4

1.4

1.2

1

0.8

0.6

0.4

0.2

V_UVLO2w/o BIAS (V_INrising)

V_UVLO2w/o BIAS (V_INfalling)

V_UVLO1w/ BIAS (V_INfalling)

V_UVLO1w/ BIAS (V_INrising)

T_J

-55°C

-40°C

0°C

25°C

85°C

125°C

150°C

6

-60

-30

0

30

60

90

120

150

1

1.5

2

2.5

3

3.5

4

Input Voltage (V)

4.5

5

5.5

6.5

Temperature (èC)

V_BIAS= 0 V

Figure 7-62. V_INUVLO vs Temperature

Figure 7-61. I_NR/SSCurrent vs Input Voltage

3

0.9

V

V_UVLO(BIAS)(V_INrising)

V_UVLO(BIAS)(V_INfalling)

IH(EN) V_IN= 1.4V

IL(EN) V_IN= 1.4V

V

IL(EN) V_IN= 6.5V

V

IH(EN) V_IN= 6.5V

0.85

0.8

2.9

2.8

2.7

2.6

2.5

0.75

0.7

0.65

0.6

0.55

-60

-30

0

30

60

90

120

150

-60

-30

0

30

60

90

120

150

Temperature (èC)

V_IN= 1.4 V, 6.5 V

V_IN= 1.1 V

Figure 7-64. Enable Threshold vs Temperature

Figure 7-63. V_BIASUVLO vs Temperature

0.4

T_J

-55°C

-40°C

0°C

25°C

85°C

125°C

150°C

-55°C

-40°C

0°C

25°C

85°C

125°C

150°C

0.32

0.24

0.16

0.08

0

0.32

0.24

0.16

0.08

0

0.25

0.5

0.75

PG Sink Current (mA)

1

1.25

1.5

1.75

2

0

0.25

0.5

0.75

PG Sink Current (mA)

1

1.25

1.5

1.75

2

V_IN= 6.5 V

Figure 7-65. PG Voltage vs PG Current Sink

Figure 7-66. PG Voltage vs PG Current Sink

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7.9 Typical Characteristics: TPS7A8301A (continued)

at T_A= 25°C, V_IN= 1.4 V or V_IN= V_OUT(nom)+ 0.3 V (whichever is greater), V_BIAS= open, V_OUT(nom)= 0.8 V, V_EN= 1.1 V, C_IN

= 10 μF, C_OUT= 22 μF, C_NR/SS= 0 nF, C_FF= 0 nF, and PG pin pulled up to V_INwith 100 kΩ (unless otherwise noted)

92

91

90

89

V_IT(PG)+Rising, V_IN= 1.4 V

88

87

86

85

84

83

82

V_IT(PG)+Rising, V_IN= 6.5 V

V_IT(PG)+Falling, V_IN= 1.4 V

V_IT(PG)+Falling, V_IN= 6.5 V

-50

-25

0

25

50

75

100

125

150

Temperature (èC)

Figure 7-67. PG Threshold vs Temperature

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8 Detailed Description

8.1 Overview

The TPS7A83A is a high-current (2 A), low-noise (4.4 µV_RMS), high-accuracy (0.75%), low-dropout linear voltage

regulator (LDO). These features make the device a robust solution to solve many challenging problems in

generating a clean, accurate power supply.

The TPS7A83A has several features that make the device useful in a variety of applications. Table 8-1

categorizes the functionalities shown in the Functional Block Diagram section.

Table 8-1. Features

VOLTAGE REGULATION

SYSTEM START-UP

INTERNAL PROTECTION

High accuracy

Programmable soft-start

Foldback current limit

No sequencing requirement between BIAS,

IN, and EN

Low-noise, high-PSRR output

Fast transient response

Thermal shutdown

Power-good output

Start-up with negative bias on OUT

Overall, these features make the TPS7A83A the component of choice because of the versatility and ability of the

device to generate a supply for most applications.

8.2 Functional Block Diagram

PSRR

Boost

Current

Limit

IN

OUT

Charge

Pump

BIAS

Active

Discharge

R_NR/SS= 250 kW

0.8-V

V_REF

+

Error

Amp

œ

I_NR/SS

SNS

FB

NR/SS

200 pF

R₁= 2×R = 12.1 kW

1×R = 6.05 kW

2×R = 12.1 kW

4×R = 24.2 kW

8×R = 48.4 kW

16×R = 96.8 kW

32×R = 193.6 kW

1.6 V

Internal

Controller

800 mV

400 mV

200 mV

100 mV

50 mV

UVLO

Circuits

ANY-OUT Network

Thermal

Shutdown

PG

œ

0.88 x V_REF

+

EN

GND

NOTE: For the ANY-OUT network, the ratios between the values are highly accurate as a result of matching, but the actual resistance

can vary significantly from the numbers listed.

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8.3 Feature Description

8.3.1 Voltage Regulation Features

8.3.1.1 DC Regulation

As Figure 8-1 shows, an LDO functions as a class-B amplifier in which the input signal is the internal reference

voltage (V_REF). V_REFis designed to have a very low bandwidth at the input to the error amplifier through the use

of a low-pass filter (V_NR/SS).

As such, the reference can be considered as a pure dc input signal. The low output impedance of an LDO

comes from the combination of the output capacitor and pass element. The pass element also presents a high

input impedance to the source voltage when operating as a current source. A positive LDO can only source

current because of the class-B architecture.

This device achieves a maximum of 0.75% output voltage accuracy primarily because of the high-precision

band-gap voltage (V_BG) that creates V_REF. The low dropout voltage (V_DO) reduces the thermal power dissipation

required by the device to regulate the output voltage at a given current level, thereby improving system

efficiency. These features combine to make this device a good approximation of an ideal voltage source.

V_IN

To Load

R₁

V_REF

R₂

GND

V_OUT= V_REF× (1 + R₁/ R₂).

Figure 8-1. Simplified Regulation Circuit

8.3.1.2 AC and Transient Response

The LDO responds quickly to a transient (large-signal response) on the input supply (line transient) or the

output current (load transient) resulting from the LDO high-input impedance and low output-impedance across

frequency. This same capability also means that the LDO has a high power-supply rejection ratio (PSRR)

and, when coupled with a low internal noise-floor (e_n), the LDO approximates an ideal power supply in ac

(small-signal) and large-signal conditions.

The choice of external component values optimizes the small- and large-signal response. The NR/SS capacitor

(C_NR/SS) and feed-forward capacitor (C_FF) easily reduce the device noise floor and improve PSRR; see the

Optimizing Noise and PSRR section for more information on optimizing the noise and PSRR performance.

8.3.2 System Start-Up Features

In many different applications, the power-supply output must turn on within a specific window of time to either

ensure proper operation of the load or to minimize the loading on the input supply or other sequencing

requirements. The LDO start up is well controlled and user adjustable, solving the demanding requirements

faced by many power-supply design engineers in a simple fashion.

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8.3.2.1 Programmable Soft-Start (NR/SS)

Soft-start directly controls the output start-up time and indirectly controls the output current during start up

(inrush current).

Figure 8-2 shows that the external capacitor at the NR/SS pin (C_NR/SS) sets the output start-up time by setting

the rise time of the internal reference (V_NR/SS).

SW

I_NR/SS

R_NR

V_REF

+

C_NR/SS

œ

V_FB

GND

Figure 8-2. Simplified Soft-Start Circuit

8.3.2.2 Internal Sequencing

Controlling when a single power supply turns on can be difficult in a power distribution network (PDN) because

of the high power levels inherent in a PDN, and the variations between the supplies. Figure 8-3 and Table 8-2

show how the LDO turn-on and turn-off times are set by the enable circuit (EN) and undervoltage lockout circuits

(UVLO_1,2(IN)and UVLO_BIAS).

EN

UVLO_BIAS

UVLO_1,2(IN)

Internal Enable

Control

Figure 8-3. Simplified Turn-On Control

Table 8-2. Internal Sequencing Functionality Table

ENABLE

STATUS

ACTIVE

DISCHARGE

INPUT VOLTAGE

BIAS VOLTAGE

LDO STATUS

POWER GOOD

EN = 1

EN = 0

On

Off

On

PG = 1 when V_OUT≥ V_IT(PG)

V_BIAS≥ V_UVLO(BIAS)

V_IN≥ V_{UVLO_1,2(IN)}

V_BIAS< V_UVLO(BIAS)

V_HYS(BIAS)

+

Off

PG = 0

EN = don't

care

V_IN< V_{UVLO_1,2(IN)}

V_HYS1,2(IN)

–

On ⁽¹⁾

BIAS = don't care

V_BIAS≥ V_UVLO(BIAS)

Off

IN = don't care

(1) The active discharge remains on as long as V_INor V_BIASprovide enough headroom for the discharge circuit to function.

8.3.2.2.1 Enable (EN)

The enable signal (V_EN) is an active-high digital control that enables the LDO when the enable voltage is past

the rising threshold (V_EN≥ V_IH(EN)) and disables the LDO when the enable voltage is below the falling threshold

(V_EN≤ V_IL(EN)). The exact enable threshold is between V_IH(EN)and V_IL(EN)because EN is a digital control.

Connect EN to V_INor V_BIASif enable functionality is not desired.

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8.3.2.2.2 Undervoltage Lockout (UVLO) Control

The UVLO circuits respond quickly to glitches on IN or BIAS and attempts to disable the output of the device if

either of these rails collapse.

The local input capacitance prevents severe brownouts in most applications; see the Undervoltage Lockout

(UVLO) section for more details.

8.3.2.2.3 Active Discharge

When either EN or UVLO is low, the device connects a resistor of several hundred ohms from V_OUTto GND,

discharging the output capacitance.

Do not rely on the active discharge circuit for discharging large output capacitors when the input voltage drops

below the targeted output voltage. Current flows from the output to the input (reverse current) when V_OUT> V_IN,

which can cause damage to the device (when V_OUT> V_IN+ 0.3 V); see the Reverse Current section for more

details.

8.3.2.3 Power-Good Output (PG)

The PG signal provides an easy solution to meet demanding sequencing requirements because PG signals

when the output nears the nominal value. PG can be used to signal other devices in a system when the output

voltage is near, at, or above the set output voltage (V_OUT(nom)). Figure 8-4 shows a simplified schematic.

The PG signal is an open-drain digital output that requires a pullup resistor to a voltage source and is active

high. The PG circuit sets the PG pin into a high-impedance state to indicate that the power is good.

Using a large feed-forward capacitor (C_FF) delays the output voltage and, because the PG circuit monitors the

FB pin, the PG signal can indicate a false positive. A simple solution to this scenario is to use an external voltage

detector device, such as the TPS3890; see the Feed-Forward Capacitor (C_FF) section for more information.

V_PG

V_BG

V_IN

œ

V_FB

+

GND

UVLO_BIAS

UVLO_IN

EN

GND

Figure 8-4. Simplified PG Circuit

8.3.3 Internal Protection Features

In many applications, fault events can occur that damage devices in the system. Short circuits and excessive

heat are the most common fault events for power supplies. The TPS7A83A implements circuitry to protect the

device and its load during these events. Continuously operating in these fault conditions or above a junction

temperature of 125°C is not recommended because the long-term reliability of the device is reduced.

8.3.3.1 Foldback Current Limit (I_CL

)

The internal current limit circuit is used to protect the LDO against high load-current faults or shorting events.

During a current-limit event, the LDO sources constant current; therefore, the output voltage falls with decreased

load impedance. Thermal shutdown can activate during a current limit event because of the high power

dissipation typically found in these conditions. To ensure proper operation of the current limit, minimize the

inductances to the input and load. Continuous operation in current limit is not recommended.

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8.3.3.2 Thermal Protection (T_sd)

The thermal shutdown circuit protects the LDO against excessive heat in the system, either resulting from

current limit or high ambient temperature.

The output of the LDO turns off when the LDO temperature (junction temperature, T_J) exceeds the rising

thermal shutdown temperature. The output turns on again after T_Jdecreases below the falling thermal shutdown

temperature.

A high power dissipation across the device, combined with a high ambient temperature (T_A), can cause T_Jto be

greater than or equal to T_sd, triggering the thermal shutdown and causing the output to fall to 0 V. The LDO can

cycle on and off when thermal shutdown is reached under these conditions.

Continuously triggering thermal shutdown can degrade long-term reliability.

8.4 Device Functional Modes

Table 8-3 provides a quick comparison between the regulation and disabled operation.

Table 8-3. Device Functional Modes Comparison

PARAMETER

OPERATING MODE

V_IN

V_BIAS

EN

I_OUT

T_J

T_J≤ T_J(maximum)

T_J> T_sd

—

V_IN> V_OUT(nom)

V_DO

+

Regulation⁽¹⁾

Disabled⁽²⁾

V_BIAS≥ V_UVLO(BIAS)

V_EN> V_IH(EN)

V_EN< V_IL(EN)

—

I_OUT< I_CL

(3)

V_IN< V_{UVLO_1,2(IN)}

—

V_BIAS< V_UVLO(BIAS)

—

Current-limit

operation

I_OUT≥ I_CL

(1) All table conditions must be met.

(2) The device is disabled when any condition is met.

(3) V_BIASis only required for V_IN< 1.4 V.

8.4.1 Regulation

The device regulates the output to the nominal output voltage when all the conditions in Table 8-3 are met.

8.4.2 Disabled

When disabled, the pass device is turned off, the internal circuits are shut down, and the output voltage is

actively discharged to ground by an internal resistor from the output to ground. See the Active Discharge section

for additional information.

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9 Application and Implementation

Note

Information in the following applications sections is not part of the TI component specification,

and TI does not warrant its accuracy or completeness. TI’s customers are responsible for

determining suitability of components for their purposes, as well as validating and testing their design

implementation to confirm system functionality.

9.1 Application Information

Successfully implementing an LDO in an application depends on the application requirements. This section

discusses key device features and how to best implement them to achieve a reliable design.

9.1.1 External Component Selection

9.1.1.1 Adjustable Operation

The TPS7A83A can be used either with the internal ANY-OUT network or by using external resistors. Using the

ANY-OUT network allows the TPS7A83A to be programmed from 0.8 V to 3.95 V. For an output voltage range

greater than 3.95 V and up to 5.2 V, external resistors must be used. This configuration is referred to as the

adjustable configuration of the TPS7A83A throughout this document. Figure 9-1 shows that the output voltage is

set by two resistors. 0.75% accuracy can be achieved with an external BIAS for V_INlower than 2.2 V.

C_BIAS

Optional

Bias

Supply

Input

Supply

BIAS

IN

C_IN

PG

OUT

SNS

FB

EN

R_PG

NR/SS

To Load

C_OUT

C_NR/SS

TPS7A83A

1.6 V

C_FF

R₁

800 mV

400 mV

200 mV

100 mV

50 mV

R₂

GND

Figure 9-1. Adjustable Operation

Use Equation 1 to calculate R₁and R₂for any output voltage range. This resistive network must provide a

current equal to or greater than 5 μA for dc accuracy. Use an R₁of approximately 12 kΩ to optimize the noise

and PSRR.

V_OUT= V_NR/SS× (1 + R₁/ R₂)

(1)

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Table 9-1 shows the resistor combinations required to achieve several common rails using standard 1%-

tolerance resistors.

Table 9-1. Recommended Feedback-Resistor Values⁽¹⁾

FEEDBACK RESISTOR VALUES

CALCULATED OUTPUT

NOMINAL OUTPUT VOLTAGE

(V)

VOLTAGE

(V)

R₁(kΩ)

R₂(kΩ)

0.90

0.95

1.00

1.10

1.20

1.50

1.80

1.90

2.50

2.85

3.00

3.30

3.60

4.50

5.00

12.4

12.1

12.4

12.1

11.8

12.1

11.8

12.4

100

66.5

49.9

33.2

24.9

14.3

10

0.899

0.949

0.999

1.099

1.198

1.494

1.798

1.890

2.480

2.838

2.990

3.324

3.582

4.502

4.985

8.87

5.9

4.75

4.42

3.74

3.48

2.55

2.37

(1) R₁is connected from OUT to FB; R₂is connected from FB to GND.

9.1.1.2 ANY-OUT Programmable Output Voltage

The TPS7A83A can use either external resistors or the internally matched ANY-OUT feedback resistor network

to set output voltage. The ANY-OUT resistors are accessible via pin 2 and pins 5 to 11 and are used to program

the regulated output voltage. Each pin is can be connected to ground (active) or left open (floating), or connected

to SNS. ANY-OUT programming is set by Equation 2 as the sum of the internal reference voltage (V_NR/SS

=

0.8 V) plus the accumulated sum of the respective voltages assigned to each active pin; that is, 50mV (pin 5),

100mV (pin 6), 200mV (pin 7), 400mV (pin 9), 800mV (pin 10), or 1.6V (pin 11). Table 9-2 summarizes these

voltage values associated with each active pin setting for reference. By leaving all program pins open or floating,

the output is thereby programmed to the minimum possible output voltage equal to V_FB.

V_OUT= V_NR/SS+ (Σ ANY-OUT Pins to Ground)

(2)

Table 9-2. ANY-OUT Programmable Output Voltage (RGR Package)

ANY-OUT PROGRAM PINS (Active Low)

ADDITIVE OUTPUT VOLTAGE LEVEL

Pin 5 (50mV)

50 mV

100 mV

200 mV

400 mV

800 mV

1.6 V

Pin 6 (100mV)

Pin 7 (200mV)

Pin 9 (400mV)

Pin 10 (800mV)

Pin 11 (1.6V)

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Table 9-3 provides a full list of target output voltages and corresponding pin settings when the ANY-OUT pins

are only tied to ground or left floating. The voltage setting pins have a binary weight; therefore, the output

voltage can be programmed to any value from 0.8 V to 3.95 V in 50-mV steps when tying these pins to ground.

There are several alternative ways to set the output voltage. The program pins can be driven using external

general-purpose input/output pins (GPIOs), manually connected using 0-Ω resistors (or left open), or hardwired

by the given layout of the printed circuit board (PCB) to set the ANY-OUT voltage. As with the adjustable

operation, the output voltage is set according to Equation 3 except that R₁and R₂are internally integrated and

matched for higher accuracy. Tying any of the ANY-OUT pins to SNS can increase the resolution of the internal

feedback network by lowering the value of R₁; see the Increasing ANY-OUT Resolution for LILO Conditions

section for additional information.

V_OUT= V_NR/SS× (1 + R₁/ R₂)

(3)

Note

For output voltages greater than 3.95 V, use a traditional adjustable configuration (see the Adjustable

Operation section).

Table 9-3. User-Configurable Output Voltage Settings

V_OUT(NOM)

(V)

50 mV

100 mV 200 mV 400 mV 800 mV

1.6 V

50 mV

100 mV 200 mV 400 mV 800 mV

1.6 V

(V)

0.80

0.85

0.90

0.95

1.00

1.05

1.10

1.15

1.20

1.25

1.30

1.35

1.40

1.45

1.50

1.55

1.60

1.65

1.70

1.75

1.80

1.85

1.90

1.95

2.00

2.05

2.10

2.15

2.20

2.25

2.30

2.35

Open

GND

Open

GND

Open

GND

Open

GND

Open

GND

Open

GND

Open

GND

Open

GND

Open

GND

Open

GND

Open

GND

Open

GND

Open

GND

Open

GND

Open

GND

Open

GND

Open

GND

Open

GND

Open

GND

Open

GND

Open

GND

Open

GND

Open

GND

Open

GND

Open

GND

Open

GND

Open

GND

Open

GND

Open

GND

Open

GND

Open

GND

Open

2.40

2.45

2.50

2.55

2.60

2.65

2.70

2.75

2.80

2.85

2.90

2.95

3.00

3.05

3.10

3.15

3.20

3.25

3.30

3.35

3.40

3.45

3.50

3.55

3.60

3.65

3.70

3.75

3.80

3.85

3.90

3.95

Open

GND

Open

GND

Open

GND

Open

GND

Open

GND

Open

GND

Open

GND

Open

GND

Open

GND

Open

GND

Open

GND

Open

GND

Open

GND

Open

GND

Open

GND

Open

GND

Open

GND

Open

GND

Open

GND

Open

GND

Open

GND

Open

GND

Open

GND

Open

GND

Open

GND

Open

GND

Open

GND

Open

GND

Open

GND

Open

GND

Open

GND

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9.1.1.3 ANY-OUT Operation

Considering the use of the ANY-OUT internal network (where the unit resistance of 1R is equal to 6.05 kΩ)

the output voltage is set as shown in Figure 9-2 by grounding the appropriate control pins. When grounded, all

control pins add a specific voltage on top of the internal reference voltage (V_NR/SS= 0.8 V). Use Equation 4 and

Equation 5 to calculate the output voltage. Figure 9-2 and Figure 9-3 show a 0.9-V output voltage, respectively,

that provides an example of the circuit usage with and without BIAS voltage.

C_BIAS

Bias

Supply

EN

V_IN

BIAS

IN

C_IN

PG

OUT

SNS

FB

R_PG

3.3 V_OUT

To Load

NR/SS

C_OUT

C_NR/SS

TPS7A83A

1.6 V

C_FF

800 mV

400 mV

200 mV

100 mV

50 mV

GND

Figure 9-2. ANY-OUT Configuration Circuit (3.3-V Output, No External BIAS)

V_OUT(nom)= V_NR/SS+ 1.6 V + 0.8 V + 0.1 V = 0.8 V + 1.6 V + 0.8 V + 0.1 V = 3.3 V

(4)

C_BIAS

Bias

Supply

1.2 V_IN

BIAS

IN

C_IN

PG

OUT

SNS

FB

EN

R_PG

0.9 V_OUT

To Digital

Load

NR/SS

C_OUT

C_NR/SS

TPS7A83A

1.6 V

C_FF

800 mV

400 mV

200 mV

100 mV

50 mV

ANYOUT

Used to set

voltage

GND

Figure 9-3. ANY-OUT Configuration Circuit (0.9-V Output With BIAS)

V_OUT(nom)= V_NR/SS+ 0.1 V = 0.8 V + 0.1 V = 0.9 V

(5)

9.1.1.4 Increasing ANY-OUT Resolution for LILO Conditions

As with the adjustable operation, the output voltage is set according to Equation 3, except that R₁and R₂are

internally integrated and matched for higher accuracy. Tying any of the ANY-OUT pins to SNS can increase the

resolution of the internal feedback network by lowering the value of R₁. One of the more useful pin combinations

is to tie the 800mV pin to SNS, which reduces the resolution by 50% to 25 mV but limits the range. The new

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ANY-OUT ranges are 0.8 V to 1.175 V and 1.6 V to 1.975 V. Table 9-4 lists the new additive output voltage

levels.

Table 9-4. ANY-OUT Programmable Output Voltage With 800mV Tied to SNS (RGR Package)

ANY-OUT PROGRAM PINS (Active Low)

ADDITIVE OUTPUT VOLTAGE LEVEL

Pin 5 (50mV)

25 mV

50 mV

Pin 6 (100mV)

Pin 7 (200mV)

100 mV

200 mV

800 mV

Pin 9 (400mV)

Pin 11 (1.6V)

9.1.1.5 Recommended Capacitor Types

The TPS7A83A is designed to be stable using low equivalent series resistance (ESR) ceramic capacitors at the

input, output, and noise-reduction pin (NR/SS). Multilayer ceramic capacitors have become the industry standard

for these types of applications and are recommended, but must be used with good judgment. Ceramic capacitors

that employ X7R-, X5R-, and COG-rated dielectric materials provide relatively good capacitive stability across

temperature, whereas the use of Y5V-rated capacitors is discouraged because of large variations in capacitance.

Regardless of the ceramic capacitor type selected, ceramic capacitance varies with operating voltage and

temperature; derate ceramic capacitors by at least 50%. The input and output capacitors recommended herein

account for a capacitance derating of approximately 50%, but at high V_INand V_OUTconditions (for example, V_IN

= 5.6 V to V_OUT= 5.2 V) the derating can be greater than 50% and must be taken into consideration.

9.1.1.6 Input and Output Capacitor Requirements (C_INand C_OUT

)

The TPS7A83A is designed and characterized for operation with ceramic capacitors of 22 µF or greater (10 μF

or greater of capacitance) at the output and 10 µF or greater (5 μF or greater of capacitance) at the input. Using

at least a 22-µF capacitor is highly recommended at the input to minimize input impedance. Place the input

and output capacitors as near as practical to the respective input and output pins to minimize trace parasitic.

If the trace inductance from the input supply to the TPS7A83A is high, a fast current transient can cause V_IN

to ring above the absolute maximum voltage rating and damage the device. This situation can be mitigated by

additional input capacitors to dampen the ringing and to keep the ringing below the device absolute maximum

ratings.

9.1.1.7 Feed-Forward Capacitor (C_FF)

Although a feed-forward capacitor (C_FF) from the FB pin to the OUT pin is not required to achieve stability, a

10-nF external feed-forward capacitor optimizes the transient, noise, and PSRR performance. A higher

capacitance C_FFcan be used; however, the start-up time is longer, and the PG signal can incorrectly indicate

that the output voltage is settled. For a detailed description, see the Pros and Cons of Using a Feed-Forward

Capacitor with a Low Dropout Regulator application report.

9.1.1.8 Noise-Reduction and Soft-Start Capacitor (C_NR/SS

)

The TPS7A83A features a programmable, monotonic, voltage-controlled soft-start that is set with an external

capacitor (C_NR/SS).The use of an external C_NR/SSis highly recommended, especially to minimize in-rush

current into the output capacitors. This soft-start eliminates power-up initialization problems when powering

field-programmable gate arrays (FPGAs), digital signal processors (DSPs), or other processors. The controlled

voltage ramp of the output also reduces peak in-rush current during start up, minimizing start-up transients to the

input power bus.

To achieve a monotonic start-up, the TPS7A83A error amplifier tracks the voltage ramp of the external soft-start

capacitor until the voltage approaches the internal reference. The soft-start ramp time depends on the soft-start

charging current (I_NR/SS), the soft-start capacitance (C_NR/SS), and the internal reference (V_NR/SS). Use Equation 6

to calculate the soft-start ramp time:

t_SS= (V_NR/SS× C_NR/SS) / I_NR/SS

(6)

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The noise-reduction capacitor, in conjunction with the noise-reduction resistor, forms a low-pass filter (LPF) that

filters out the noise from the reference before being gained up with the error amplifier, thereby reducing the

device noise floor. The LPF is a single-pole filter and Equation 7 to calculates the cutoff frequency. The typical

value of R_NR/SSis 250 kΩ. Increasing the C_NR/SScapacitor has a greater affect because the output voltage

increases when the noise from the reference is gained up even more at higher output voltages. For low-noise

applications, a 10-nF to 1-µF C_NR/SSis recommended. When a C_NR/SScapacitor gets larger, the capacitor

leakage increases, causing a longer than expected start-up time.

f_cutoff= 1/ (2 × π × R_NR/SS× C_NR/SS

)

(7)

9.1.2 Start Up

9.1.2.1 Soft-Start (NR/SS)

The output of the device features a user-adjustable, monotonic, voltage-controlled soft-start that is set with an

external capacitor (C_NR/SS). This soft-start eliminates power-up initialization problems when powering FPGAs,

DSPs, or other processors. The controlled voltage ramp of the output also reduces peak inrush current during

start-up, thus minimizing start-up transients to the input power bus.

The output voltage (V_OUT) rises proportionally to V_NR/SSduring start-up as the LDO regulates so that the

feedback voltage equals the NR/SS voltage (V_FB= V_NR/SS). As such, the time required for V_NR/SSto reach

its nominal value determines the rise time of V_OUT(start-up time).

Not using a noise-reduction capacitor on the NR/SS pin can result in output voltage overshoot of approximately

10%. Using a capacitor on the NR/SS pin minimizes the overshoot.

9.1.2.1.1 Inrush Current

Inrush current is defined as the current into the LDO at the IN pin during start-up. Inrush current then consists

primarily of the sum of load current and the current used to charge the output capacitor. This current is difficult

to measure because the input capacitor must be removed, which is not recommended. However, Equation 8 can

estimate this soft-start current:

≈

∆

«

’

÷

◊

C

ì dV_OUT(t)

dt

V_OUT(t)

R_LOAD

≈

’

OUT

I_OUT(t) =

+

∆

«

÷

◊

(8)

where:

•

V_OUT(t) is the instantaneous output voltage of the turn-on ramp

dV_OUT(t) / dt is the slope of the V_OUTramp

R_LOADis the resistive load impedance

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9.1.2.2 Undervoltage Lockout (UVLO)

The UVLO circuits ensure that the device stays disabled before the input or bias supplies reach the minimum

operational voltage range, and ensures that the device properly shuts down when either the input or BIAS supply

collapses.

Figure 9-4 and Table 9-5 show one of the UVLO circuits being triggered to various input voltage events,

assuming V_EN≥ V_IH(EN)

.

UVLO Rising Threshold

UVLO Hysteresis

V_IN

C

V_OUT

tAt

tBt

tDt

tEt

tFt

tGt

Figure 9-4. Typical UVLO Operation

Table 9-5. Typical UVLO Operation Description

REGION

EVENT

V_OUTSTATUS

COMMENT

Turn on, V_IN≥ V_{UVLO_1,2(IN)}, and

V_BIAS≥ V_UVLO(BIAS)

A

B

Off

On

Start up

Regulation

Regulates to target V_OUT

Brownout, V_IN≥ V_{UVLO_1,2(IN)}

V_{HYS_1,2(IN)}

or V_BIAS≥ V_UVLO(BIAS)– V_HYS(BIAS)

–

C

D

On

The output can fall out of regulation but the device is still enabled

Regulation

Regulates to target V_OUT

The device is disabled and the output falls because of the load and

active discharge circuit. The device is re-enabled when the UVLO

fault is removed when either the IN or BIAS UVLO rising threshold

is reached by the input or bias voltage and a normal start up then

follows.

Brownout, V_IN< V_{UVLO_1,2(IN)}

V_{HYS_1,2(IN)}

or V_BIAS≥ V_UVLO(BIAS)– V_HYS(BIAS)

–

E

Off

F

Regulation

On

Off

Regulates to target V_OUT

Turn off, V_IN< V_{UVLO_1,2(IN)}

V_{HYS_1,2(IN)}

–

G

The output falls because of the load and active discharge circuit

or V_BIAS< V_UVLO(BIAS)– V_HYS(BIAS)

Similar to many other LDOs with this feature, the UVLO circuits take a few microseconds to fully assert. During

this time, a downward line transient below approximately 0.8 V causes the UVLO to assert for a short time;

however, the UVLO circuits do not have enough stored energy to fully discharge the internal circuits inside the

device. When the UVLO circuits are not given enough time to fully discharge the internal nodes, the outputs are

not fully disabled.

The effect of the downward line transient can be mitigated by using a larger input capacitor to increase the fall

time of the input supply when operating near the minimum V_IN.

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9.1.2.3 Power-Good (PG) Function

The PG circuit monitors the voltage at the feedback pin to indicate the status of the output voltage. The PG

circuit asserts whenever FB, V_IN, or EN are below their thresholds. Figure 9-5 and Table 9-6 describe the PG

operation versus the output voltage.

PG Rising Threshold

PG Falling Threshold

V_OUT

E

C

PG

tAt

tBt

tDt

tFt

tGt

Figure 9-5. Typical PG Operation

Table 9-6. Typical PG Operation Description

REGION

EVENT

PG STATUS

FB VOLTAGE

A

B

C

D

E

F

Turnon

Regulation

0

V_FB< V_IT(PG)+ V_HYS(PG)

Hi-Z

0

Output voltage dip

Regulation

V_FB≥ V_IT(PG)

Output voltage dip

Regulation

V_FB< V_IT(PG)

V_FB≥ V_IT(PG)

V_FB< V_IT(PG)

Hi-Z

0

G

Turnoff

The PG pin is open-drain, and connecting a pullup resistor to an external supply enables others devices to

receive power-good as a logic signal that can be used for sequencing. Make sure that the external pullup supply

voltage results in a valid logic signal for the receiving device or devices.

To ensure proper operation of the PG circuit, the pullup resistor value must be from 10 kΩ and 100 kΩ. The

lower limit of 10 kΩ results from the maximum pulldown strength of the PG transistor, and the upper limit of 100

kΩ results from the maximum leakage current at the PG node. If the pullup resistor is outside of this range, then

the PG signal may not read a valid digital logic level.

Using a large C_FFwith a small C_NR/SScauses the PG signal to incorrectly indicate that the output voltage has

settled during turnon. The C_FFtime constant must be greater than the soft-start time constant to ensure proper

operation of the PG during start-up. For a detailed description, see the Pros and Cons of Using a Feed-Forward

Capacitor with a Low Dropout Regulator application report.

The state of PG is only valid when the device operates above the minimum supply voltage. During short

brownout events and at light loads, PG does not assert because the output voltage (therefore V_FB) is sustained

by the output capacitance.

9.1.3 AC and Transient Performance

LDO ac performance includes power-supply rejection ratio, output-current transient response, and output noise.

These metrics are primarily a function of open-loop gain, bandwidth, and phase margin that control the closed-

loop input and output impedance of the LDO. The output noise is primarily a result of the reference and error

amplifier noise.

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9.1.3.1 Power-Supply Rejection Ratio (PSRR)

PSRR is a measure of how well the LDO control loop rejects signals from V_INto V_OUTacross the frequency

spectrum (usually 10 Hz to 10 MHz). Equation 9 gives the PSRR calculation as a function of frequency for the

input signal [V_IN(f)] and output signal [V_OUT(f)].

≈

’

V

ƒ

_IN( )

PSRR dB = 20Log

(

)

∆

÷

10

V_OUT

ƒ

( )

«

◊

(9)

Even though PSRR is a loss in signal amplitude, PSRR is shown as positive values in decibels (dB) for

convenience.

Figure 9-6 shows a simplified diagram of PSRR versus frequency.

PSRR Boost Circuit Improves PSRR in This Region

Band-Gap

RC Filter

Error Amplifier,

Flat-Gain Region

Error Amplifier,

Gain Roll-Off

Output Capacitor

|Z_COUT| Decreasing

Output Capacitor

|Z_COUT| Increasing

Band Gap

Sub 10 Hz

10 Hzœ1 MHz

100 kHz +

Frequency (Hz)

Figure 9-6. Power-Supply Rejection Ratio Diagram

An LDO is often employed not only as a dc/dc regulator, but also to provide exceptionally clean power-supply

voltages that exhibit ultra-low noise and ripple to sensitive system components. This usage is especially true for

the TPS7A83A.

The TPS7A83A features an innovative circuit to boost the PSRR from 200 kHz to 1 MHz; see Figure 7-1. To

achieve the maximum benefit of this PSRR boost circuit, use a capacitor with a minimum impedance in the

100-kHz to 1-MHz band.

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9.1.3.2 Output Voltage Noise

The TPS7A83A is designed for system applications where minimizing noise on the power-supply rail is critical

to system performance. For example, the TPS7A83A can be used in a phase-locked loop (PLL)-based clocking

circuit and can be used for minimum phase noise, or in test and measurement systems where even small

power-supply noise fluctuations reduce system dynamic range.

LDO noise is defined as the internally-generated intrinsic noise created by the semiconductor circuits alone. This

noise is the sum of various types of noise (such as shot noise associated with current-through-pin junctions,

thermal noise caused by thermal agitation of charge carriers, flicker noise, or 1/f noise and dominates at

lower frequencies as a function of 1/f). Figure 9-7 shows a simplified output voltage noise density plot versus

frequency.

Charge Pump Spurs

1

/

f

N

o

i

se

Wide-Band Noise

Integrated Noise

From Band-Gap and Error Amplifier

N

o

i

se

G

a

i

n

R

o

l

-

O

f

Measurement Noise Floor

Frequency (Hz)

Figure 9-7. Output Voltage Noise Diagram

For further details, see the How to Measure LDO Noise white paper.

9.1.3.3 Optimizing Noise and PSRR

Table 9-7 describes several ways how the ultra-low noise floor and PSRR of the device can be improved.

Table 9-7. Effect of Various Parameters on AC Performance^{(1) (2)}

NOISE

PSRR

PARAMETER

LOW-

MID-

HIGH-

LOW-

MID-

HIGH-

FREQUENCY

C_NR/SS

C_FF

+++

++

No effect

+++

++

+

No effect

+

+++

+

+++

+

+++

+

C_OUT

No effect

+

No effect

+++

++

V_IN– V_OUT

PCB layout

+

+++

++

+

+++

(1) The number of +'s indicates the improvement in noise or PSRR performance by increasing the parameter value.

(2) Shaded cells indicate the easiest improvement to noise or PSRR performance.

The noise-reduction capacitor, in conjunction with the noise-reduction resistor, forms a low-pass filter (LPF)

that filters out the noise from the reference before being gained up with the error amplifier, thereby minimizing

the output voltage noise floor. The LPF is a single-pole filter, and Equation 10 calculates the cutoff frequency.

The typical value of R_NR/SSis 250 kΩ. The effect of the C_NR/SScapacitor increases when V_OUT(nom)increases

because the noise from the reference is gained up when the output voltage increases. For low-noise

applications, use a 10-nF to 1-µF C_NR/SS

.

f_cutoff= 1 / (2 × π × R_NR/SS× C_NR/SS

)

(10)

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The feed-forward capacitor reduces output voltage noise by filtering out the mid-band frequency noise. The

feed-forward capacitor can be optimized by placing a pole-zero pair near the edge of the loop bandwidth and

pushing out the loop bandwidth, thus improving mid-band PSRR.

A larger C_OUTor multiple output capacitors reduces high-frequency output voltage noise and PSRR by reducing

the high-frequency output impedance of the power supply.

Additionally, a higher input voltage improves the noise and PSRR because greater headroom is provided for the

internal circuits. However, a high-power dissipation across the die increases the output noise because of the

increase in junction temperature.

Good PCB layout improves the PSRR and noise performance by providing heat sinking at low frequencies and

isolating V_OUTat high frequencies.

Table 9-8 lists the output voltage noise for the 10-Hz to 100-kHz band at a 5-V output for a variety of conditions

with an input voltage of 5.5 V and a load current of 2 A. The 5-V output was chosen as a worst-case nominal

operation for output voltage noise.

Table 9-8. Output Noise Voltage at a 5-V Output

OUTPUT VOLTAGE NOISE

C_NR/SS(nF)

C_FF(nF)

C_OUT(µF)

(μV_RMS

11.7

7.7

)

10

22

100

6

100

10

22

7.4

1000

5.8

100

9.1.3.3.1 Charge Pump Noise

Figure 9-8 shows that the device internal charge pump generates a minimal amount of noise.

Using a BIAS rail minimizes the internal charge-pump noise when the internal voltage is clamped, thereby

reducing the overall output noise floor.

The high-frequency components of the output voltage noise density curve are filtered out in most applications by

using 10-nF to 100-nF bypass capacitors close to the load. Using a ferrite bead between the LDO output and the

load input capacitors forms a pi-filter, further reducing the high-frequency noise contribution.

0.5

V_IN= 1.5 V, 4.5 mV_RMS

V_IN= 1.4 V, V_BIAS= 5.0 V, 4.5 mV_RMS

0.3

0.2

0.1

0.07

0.05

0.03

0.02

0.01

0.007

0.005

0.003

0.002

0.001

1000000

2000000

3000000

4000000

5000000

6000000

7000000

8000000

9000000

1E+7

Frequency (Hz)

Figure 9-8. Charge Pump Noise

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9.1.3.4 Load Transient Response

The load-step transient response is the output voltage response by the LDO to a step in load current, whereby

output voltage regulation is maintained. There are two key transitions during a load transient response: the

transition from a light to a heavy load and the transition from a heavy to a light load. The regions shown in

Figure 9-9 and described in Table 9-9 are broken down in this section. Regions A, E, and H are where the output

voltage is in steady-state.

V_OUTx

B

F

A

C

D

E

G

H

I_OUTx

Figure 9-9. Load Transient Waveform

Table 9-9. Load Transient Waveform Description

REGION

DESCRIPTION

COMMENT

A

B

Regulation

Output current ramping

Initial voltage dip is a result of the depletion of the output capacitor charge

Recovery from the dip results from the LDO increasing its sourcing current, and leads

to output voltage regulation

C

LDO responding to transient

At high load currents the LDO takes some time to heat up. During this time the output

voltage changes slightly.

D

E

F

Reaching thermal equilibrium

Regulation

Initial voltage rise results from the LDO sourcing a large current, and leads to the

output capacitor charge to increase

Output current ramping

Recovery from the rise results from the LDO decreasing its sourcing current in

combination with the load discharging the output capacitor

G

H

LDO responding to transient

Regulation

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The transient response peaks (V_OUT(max)and V_OUT(min)) are improved by using more output capacitance;

however, doing so slows down the recovery time (W_riseand W_fall). Figure 9-10 shows these parameters during a

load transient, with a given pulse duration (PW) and current levels (I_OUT(LO)and I_OUT(HI)).

V_OUT(max)

W_rise

V_OUT

W_fall

V_OUT(min)

I_OUT(HI)

PW

I_OUT

I_OUT(LO)

t_rise

t_fall

Figure 9-10. Simplified Load Transient Waveform

9.1.4 DC Performance

9.1.4.1 Output Voltage Accuracy (V_OUT

)

The device features an output voltage accuracy of 0.75% maximum, with BIAS, that includes the errors

introduced by the internal reference, load regulation, line regulation, and operating temperature. Output voltage

accuracy specifies minimum and maximum output voltage error, relative to the expected nominal output voltage

stated as a percent.

9.1.4.2 Dropout Voltage (V_DO

)

Generally speaking, dropout voltage often refers to the minimum voltage difference between the input and output

voltage (V_DO= V_IN– V_OUT) that is required for regulation. When V_INdrops below the required V_DOfor the given

load current, the device functions as a resistive switch and does not regulate output voltage. Figure 9-11 shows

that dropout voltage is proportional to the output current because the device is operating as a resistive switch.

V_DO

I_OUT

Figure 9-11. Dropout Voltage versus Output Current

Dropout voltage is affected by the drive strength for the gate of the pass element, which is nonlinear with respect

to V_INon this device because of the internal charge pump. Dropout voltage increases exponentially when the

input voltage nears its maximum operating voltage.

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9.1.4.2.1 Behavior When Transitioning From Dropout Into Regulation

Some applications can have transients that place the LDO into dropout, such as slower ramps on V_INfor start-up

or load transients. As with many other LDOs, the output can overshoot on recovery from these conditions.

Figure 9-12 shows that a ramping input supply can cause an LDO to overshoot on start-up when the slew rate

and voltage levels are in the right range. This condition is easily avoided through either the use of an enable

signal, or by increasing the soft-start time with C_SS/NR

.

Input Voltage

Response time for

LDO to get back into

regulation.

Load current discharges

output voltage.

V_IN= V_OUT(nom)+ V_DO

Output Voltage

Dropout

V_OUT= V_IN- V_DO

Output Voltage in

normal regulation.

Time

Figure 9-12. Start-Up Into Dropout

9.1.5 Sequencing Requirements

There is no sequencing requirement between the BIAS, IN, and EN pins in the TPS7A83A.

9.1.6 Negatively Biased Output

The TPS7A83A output can be negatively biased to the absolute maximum rating, without affecting the start-up

condition.

9.1.7 Reverse Current

As with most LDOs, this device can be damaged by excessive reverse current.

Reverse current is current that flows through the body diode on the pass element instead of the normal

conducting channel. This current flow, at high enough magnitudes, degrades long-term reliability of the device

resulting from risks of electro-migration and excess heat being dissipated across the device. If the current flow

gets high enough, a latch-up condition can be entered.

Conditions where excessive reverse current can occur are outlined in this section, all of which can exceed the

absolute maximum rating of V_OUT> V_IN+ 0.3 V:

•

If the device has a large C_OUTand the input supply collapses quickly with little or no load current

The output is biased when the input supply is not established

The output is biased above the input supply

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If excessive reverse current flow is expected in the application, then external protection must be used to protect

the device. Figure 9-13 shows one approach of protecting the device.

Schottky Diode

Internal Body Diode

IN

OUT

TI Device

GND

C_OUT

C_IN

Figure 9-13. Example Circuit for Reverse Current Protection Using a Schottky Diode

9.1.8 Power Dissipation (P_D)

Circuit reliability demands that proper consideration is given to device power dissipation, location of the circuit on

the printed circuit board (PCB), and correct sizing of the thermal plane. The PCB area around the regulator must

be as free as possible of other heat-generating devices that cause added thermal stresses.

As a first-order approximation, power dissipation in the regulator depends on the input-to-output voltage

difference and load conditions. Use Equation 11 to approximate P_D:

P_D= (V_IN– V_OUT) × I_OUT

(11)

An important note is that power dissipation can be minimized, and thus greater efficiency achieved, by proper

selection of the system voltage rails. Proper selection allows the minimum input-to-output voltage differential

to be obtained. The low dropout of the device allows for maximum efficiency across a wide range of output

voltages.

The main heat conduction path for the device is through the thermal pad on the package. As such, the thermal

pad must be soldered to a copper pad area under the device. This pad area contains an array of plated vias that

conduct heat to any inner plane areas or to a bottom-side copper plane.

The maximum power dissipation determines the maximum allowable junction temperature (T_J) for the device.

According to Equation 12, power dissipation and junction temperature are most often related by the junction-to-

ambient thermal resistance (R_θJA) of the combined PCB, device package, and the temperature of the ambient air

(T_A). Equation 13 rewrites Equation 12 for output current.

T_J= T_A+ R_θJA× P_D

(12)

(13)

I_OUT= (T_J– T_A) / [R_θJA× (V_IN– V_OUT)]

Unfortunately, this thermal resistance (R_θJA) is highly dependent on the heat-spreading capability built into the

particular PCB design, and therefore varies according to the total copper area, copper weight, and location of

the planes. The R_θJArecorded in the Thermal Information table is determined by the JEDEC standard, PCB,

and copper-spreading area, and is only used as a relative measure of package thermal performance. For a

well-designed thermal layout, R_θJAis actually the sum of the VQFN package junction-to-case (bottom) thermal

resistance (R_θJCbot) plus the thermal resistance contribution by the PCB copper.

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9.1.8.1 Estimating Junction Temperature

The JEDEC standard now recommends the use of psi (Ψ) thermal metrics to estimate the junction temperatures

of the LDO when in-circuit on a typical PCB board application. These metrics are not strictly speaking thermal

resistances, but rather offer practical and relative means of estimating junction temperatures. These psi metrics

are determined to be significantly independent of the copper-spreading area. The key thermal metrics (Ψ_JTand

Ψ_JB) are used in accordance with Equation 14.

Y_JT: T_J= T_T+ Y_JT´ P_D

Y_JB: T_J= T_B+ Y_JB´ P_D

(14)

where:

•

P_Dis the power dissipated as explained in Equation 11

T_Tis the temperature at the center-top of the device package, and

T_Bis the PCB surface temperature measured 1 mm from the device package and centered on the package

edge

9.1.8.2 Recommended Area for Continuous Operation (RACO)

The operational area of an LDO is limited by the dropout voltage, output current, junction temperature, and input

voltage. As shown in Figure 9-14, the recommended area for continuous operation for a linear regulator can be

separated into the following parts:

•

Limited by dropout: Dropout voltage limits the minimum differential voltage between the input and the output

(V_IN– V_OUT) at a given output current level; see the Dropout Voltage (V_DO) section for more details.

Limited by rated output current: The rated output current limits the maximum recommended output current

level. Exceeding this rating causes the device to fall out of specification.

Limited by thermals: The shape of the slope is given by Equation 13. The slope is nonlinear because the

junction temperature of the LDO is controlled by the power dissipation across the LDO; therefore, when

V_IN– V_OUTincreases, the output current must decrease in order to ensure that the rated junction temperature

of the device is not exceeded. Exceeding this rating can cause the device to fall out of specifications and

reduces long-term reliability.

•

Limited by V_INrange: The rated input voltage range governs both the minimum and maximum of V_IN– V_OUT.

Output Current Limited

by Dropout

Rated Output

Current

Output Current Limited by Thermals

Limited by

Minimum V_IN

Limited by

Maximum V_IN

V_INœ V_OUT(V)

Figure 9-14. Continuous Operation Slope Region Description

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Figure 9-15 to Figure 9-20 show the recommended area of operation curves for this device on a JEDEC-

standard, high-K board with a R_θJA= 43.4°C/W.

3

2.5

2

3

2.5

2

T_A= +40°C

T_A= +55°C

T_A= +70°C

T_A= +85°C

RACO at T_A= +85°C

T_A= +40°C

T_A= +55°C

T_A= +70°C

T_A= +85°C

RACO at T_A= +85°C

1.5

1

1.5

1

0.5

0

0.5

0

0.2

0.4

0.6 0.8

V_IN- V_OUT(V)

1

1.2

1.4

1.6

0

0.2

0.4

0.6 0.8

V_IN- V_OUT(V)

1

1.2

1.4

1.6

D0012

D001

Figure 9-16. Recommended Area for Continuous

Operation for V_OUT= 1.2 V

Figure 9-15. Recommended Area for Continuous

Operation for V_OUT= 0.9 V

3

T_A= +40°C

T_A= +55°C

T_A= +70°C

T_A= +85°C

RACO at T_A= +85°C

T_A= +40°C

T_A= +55°C

T_A= +70°C

T_A= +85°C

RACO at T_A= +85°C

2.5

2

2.5

2

1.5

1

1.5

1

0.5

0

0.5

0

0.2

0.4

0.6 0.8

V_IN- V_OUT(V)

1

1.2

1.4

1.6

0

0.2

0.4

0.6 0.8

V_IN- V_OUT(V)

1

1.2

1.4

1.6

D0013

D0014

Figure 9-17. Recommended Area for Continuous

Operation for V_OUT= 1.8 V

Figure 9-18. Recommended Area for Continuous

Operation for V_OUT= 2.5 V

3

T_A= +40°C

T_A= +55°C

T_A= +70°C

T_A= +85°C

RACO at T_A= +85°C

T_A= +40°C

T_A= +55°C

T_A= +70°C

T_A= +85°C

RACO at T_A= +85°C

2.5

2

2.5

2

1.5

1

1.5

1

0.5

0

0.5

0

0.2

0.4

0.6 0.8

V_IN- V_OUT(V)

1

1.2

1.4

1.6

0

0.2

0.4

0.6 0.8

V_IN- V_OUT(V)

1

1.2

1.4

1.6

D0015

D0016

Figure 9-19. Recommended Area for Continuous

Operation for V_OUT= 3.3 V

Figure 9-20. Recommended Area for Continuous

Operation for V_OUT= 5 V

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9.2 Typical Application

The TPS7A83A uses the ANY-OUT configuration to regulate a 2-A load requiring good PSRR at high frequency

with low-noise at 0.9 V using a 1.2-V input voltage and a 5-V bias supply. Figure 9-21 provides a schematic for

this typical application circuit.

C_BIAS

Bias

Supply

1.2 V_IN

BIAS

IN

C_IN

PG

OUT

SNS

FB

EN

R_PG

0.9 V_OUT

To Digital

Load

NR/SS

C_OUT

C_NR/SS

TPS7A83A

1.6 V

C_FF

800 mV

400 mV

200 mV

100 mV

50 mV

ANYOUT

Used to set

voltage

GND

Figure 9-21. TPS7A83A Typical Application: Low-Input, Low-Output (LILO) Voltage Conditions

9.2.1 Design Requirements

For this design example, use the parameters listed in Table 9-10 as the input parameters.

Table 9-10. Design Parameters

PARAMETER

Input voltage

DESIGN REQUIREMENT

1.2 V, ±3%, provided by the dc/dc converter switching at 500 kHz

Bias voltage

5 V, ±5%

Output voltage

0.9 V, ±1%

Output current

2 A (maximum), 100 mA (minimum)

RMS noise, 10 Hz to 100 kHz

PSRR at 500 kHz

Start-up time

< 10 μV_RMS

> 40 dB

< 25 ms

9.2.2 Detailed Design Procedure

At 2 A, the dropout of the TPS7A83A has 180-mV maximum dropout over temperature, thus a 400-mV

headroom is sufficient for operation over both input and output voltage accuracy. The bias rail is provided

for better performance for the LILO conditions. As per Table 9-10, the PSRR is greater than 40 dB in these

conditions and noise is less than 10 µV_RMS

.

The ANY-OUT internal resistor network is also used for maximum accuracy.

To achieve 0.9 V on the output, the 100mV pin is grounded. Equation 15 describes how the voltage value of

100 mV is added to the 0.8-V internal reference voltage for V_OUT(nom)equal to 0.9 V.

V_OUT(nom)= V_NR/SS+ 0.1 V = 0.8 V + 0.1 V = 0.9 V

(15)

Input and output capacitors are selected in accordance with the External Component Selection section. Ceramic

capacitors of 10 µF for the input and one 22-µF capacitor for the output are selected.

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To satisfy the required start-up time and still maintain low-noise performance, a 100-nF C_NR/SSis selected.

Equation 16 calculates this value.

t_SS= (V_NR/SS× C_NR/SS) / I_NR/SS

(16)

At the 2-A maximum load, the internal power dissipation is 0.6 W and corresponds to a 26.04°C junction

temperature rise for the RGR package on a standard JEDEC board. With an 55°C maximum ambient

temperature, the junction temperature is at 94.06°C. To further minimize noise, a feed-forward capacitor (C_FF) of

10 nF is selected.

9.2.3 Application Curves

10

9

8

7

6

5

4

3

2

1

0

100

75

1.2

1

I_OUT

V_{OUT, AC}

50

25

0.8

0.6

0.4

0.2

0

-25

-50

-75

-100

-125

-150

V_EN

V_OUT, C_NR/SS= 0 nF

V_OUT, C_NR/SS= 10 nF

V_OUT, C_NR/SS= 47 nF

V_OUT, C_NR/SS= 100 nF

0

10

20

30

40

50

Time (ms)

60

70

80

90 100

-0.2

0

5

10

15

20 25

Time (ms)

30

35

40

45

50

Figure 9-22. Output Load Transient Response

Figure 9-23. Output Start-Up Response

10 Power Supply Recommendations

The TPS7A83A is designed to operate from an input voltage supply range from 1.1 V to 6.5 V. If the input supply

is less than 1.4 V, then a bias rail of at least 3 V must be used. The input voltage range provides adequate

headroom in order for the device to have a regulated output. This input supply must be well regulated. If the

input supply is noisy, additional input capacitors with low ESR may help improve output noise performance.

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11 Layout

11.1 Layout Guidelines

For best overall performance, place all circuit components on the same side of the circuit board and as near

as practical to the respective LDO pin connections. Place ground return connections to the input and output

capacitor, and to the LDO ground pin as close as possible to each other, connected by a wide, component-side,

copper surface. The use of vias and long traces to the input and output capacitors is strongly discouraged

and negatively affects system performance. The grounding and layout scheme shown in Figure 11-1 minimizes

inductive parasitics, and thereby reduces load-current transients, minimizes noise, and increases circuit stability.

Using a ground reference plane either embedded in the PCB itself or located on the bottom side of the PCB

opposite the components is beneficial to the layout. This reference plane serves to assure accuracy of the

output voltage, shield noise, and behaves similarly to a thermal plane to spread (or sink) heat from the LDO

device when connected to the thermal pad. In most applications, this ground plane is necessary to meet thermal

requirements.

11.2 Layout Example

Ground Plane for Thermal Relief and Signal

Ground

10

9

8

7

6

To PG Pullup Supply

PG Output

1.6V 11

BIAS

5

50mV

PG

C_BIAS

R_PG

To Bias Supply

To Signal Ground

Enable Signal

12

4

3

Thermal Pad

R₂

NR/SS 13

EN 14

FB

To Signal Ground

To Load

C_NR/SS

2

1

SNS

OUT

C_FFR₁

15

IN

16

18 19 20

17

Input Power Plane

Output Power Plane

C_IN

C_OUT

Power Ground Plane

Vias used for application purposes.

Figure 11-1. Example Layout

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12 Device and Documentation Support

12.1 Device Support

12.1.1 Development Support

12.1.1.1 Evaluation Models

An evaluation module (EVM) is available to assist in the initial circuit performance evaluation using the

TPS7A8300. Table 12-1 shows the summary information for this fixture.

Table 12-1. Design Kits and Evaluation Models

NAME

EVALUATION MODEL

TPS7A8300EVM-579 Evaluation Module

SBVU021

The EVM can be requested at the Texas Instruments web site through the TPS7A8300 product folder.

12.1.1.2 Spice Models

Computer simulation of circuit performance using SPICE is often useful when analyzing the performance of

analog circuits and systems. A SPICE model for the TPS7A83A device is available through the TPS7A83A

product folder under simulation models.

12.1.2 Device Nomenclature

Table 12-2. Ordering Information⁽¹⁾

PRODUCT

DESCRIPTION

YYY is the package designator

Z is the package quantity

TPS7A8300A YYYZ

(1) For the most current package and ordering information see the Package Option Addendum at the end of the this document, or see the

device product folder at www.ti.com.

12.2 Documentation Support

12.2.1 Related Documentation

For related documentation see the following:

•

Texas Instruments, High-Accuracy, Overvoltage and Undervoltage Monitor data sheet

Texas Instruments, TPS7A8300EVM-579 Evaluation Module user's guide

Texas Instruments, Pros and Cons of Using a Feed-Forward Capacitor with a Low Dropout Regulator

application report

•

Texas Instruments, TPS3890 Low Quiescent Current, 1% Accurate Supervisor with Programmable Delay

data sheet

12.3 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on

Subscribe to updates to register and receive a weekly digest of any product information that has changed. For

change details, review the revision history included in any revised document.

12.4 Support Resources

TI E2E^™support forums are an engineer's go-to source for fast, verified answers and design help — straight

from the experts. Search existing answers or ask your own question to get the quick design help you need.

Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do

not necessarily reflect TI's views; see TI's Terms of Use.

12.5 Trademarks

ANY-OUT^™are trademarks of Texas Instruments.

TI E2E^™is a trademark of Texas Instruments.

All trademarks are the property of their respective owners.

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12.6 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled

with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may

be more susceptible to damage because very small parametric changes could cause the device not to meet its published

specifications.

12.7 Glossary

TI Glossary

This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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PACKAGE MATERIALS INFORMATION

www.ti.com

14-Oct-2021

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

A0

B0

K0

P1

W

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

TPS7A8300ARGRR

TPS7A8300ARGRT

TPS7A8300ARGWR

TPS7A8300ARGWT

TPS7A8301ARGRR

VQFN

RGR

RGW

RGR

20

3000

250

330.0

180.0

330.0

180.0

330.0

12.4

3.75

5.3

3.75

5.3

1.15

1.1

8.0

12.0

Q2

3000

250

5.3

1.1

3000

3.75

1.15

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

14-Oct-2021

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

TPS7A8300ARGRR

TPS7A8300ARGRT

TPS7A8300ARGWR

TPS7A8300ARGWT

TPS7A8301ARGRR

VQFN

RGR

RGW

RGR

20

3000

250

367.0

210.0

367.0

210.0

367.0

185.0

367.0

185.0

367.0

35.0

3000

250

3000

Pack Materials-Page 2

GENERIC PACKAGE VIEW

RGW 20

5 x 5, 0.65 mm pitch

VQFN - 1 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

This image is a representation of the package family, actual package may vary.

Refer to the product data sheet for package details.

4227157/A

www.ti.com

PACKAGE OUTLINE

VQFN - 1 mm max height

RGW0020A

PLASTIC QUAD FLATPACK-NO LEAD

5.1

4.9

B

PIN 1 INDEX AREA

5.1

4.9

C

1 MAX

SEATING PLANE

0.08 C

0.05

0.00

3.15±0.1

2X 2.6

(0.1) TYP

10

6

16X 0.65

5

11

SYMM

21

2X

2.6

15

1

0.36

0.26

20X

PIN1 ID

(OPTIONAL)

0.1

C A B

C

20

16

0.05

SYMM

0.65

0.45

20X

4219039/A 06/2018

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.

www.ti.com

EXAMPLE BOARD LAYOUT

VQFN - 1 mm max height

RGW0020A

PLASTIC QUAD FLATPACK-NO LEAD

(4.65)

3.15)

(2.6)

(

20

16

16X (0.65)

15

1

(1.325)

21

SYMM

(4.65) (2.6)

(R0.05) TYP

11

5

20X (0.31)

20X (0.75)

(Ø0.2) VIA

6

10

TYP

(1.325)

SYMM

LAND PATTERN EXAMPLE

SCALE: 15X

0.07 MAX

ALL AROUND

0.07 MIN

ALL AROUND

SOLDER MASK

OPENING

EXPOSED METAL

METAL

EXPOSED METAL

METAL UNDER

SOLDER MASK

OPENING

NON SOLDER MASK

SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

4219039/A 06/2018

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

number SLUA271 (www.ti.com/lit/slua271).

5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown

on this view. It is recommended that vias under paste be filled, plugged or tented.

www.ti.com

EXAMPLE STENCIL DESIGN

VQFN - 1 mm max height

RGW0020A

PLASTIC QUAD FLATPACK-NO LEAD

(4.65)

4X ( 1.37)

2X (0.785)

16

20

16X (0.65)

21

1

15

2X (0.785)

SYMM

(4.65) (2.6)

(R0.05) TYP

11

5

20X (0.31)

20X (0.75)

METAL

TYP

6

10

SYMM

(2.6)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

EXPOSED PAD

75% PRINTED COVERAGE BY AREA

SCALE: 15X

4219039/A 06/2018

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

www.ti.com

IMPORTANT NOTICE AND DISCLAIMER

TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE

DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”

AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY

IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD

PARTY INTELLECTUAL PROPERTY RIGHTS.

These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate

TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable

standards, and any other safety, security, regulatory or other requirements.

These resources are subject to change without notice. TI grants you permission to use these resources only for development of an

application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license

is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you

will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these

resources.

TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with

such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for

TI products.

TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	TPS7A8300ARGRR
厂家：	TEXAS INSTRUMENTS
描述：	具有电源正常指示功能的 2A、低输入电压 (1.1V)、低噪声、高精度、超低压降稳压器 \| RGR \| 20 \| -40 to 125 稳压器
文件：	总60页 (文件大小：5314K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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