TPS7B8133QDGNRQ1 [TI]
具有使能功能的汽车类 150mA、电池供电运行 (40V)、超低 IQ、低压降稳压器 | DGN | 8 | -40 to 150;
| 型号： | TPS7B8133QDGNRQ1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有使能功能的汽车类 150mA、电池供电运行 (40V)、超低 IQ、低压降稳压器 | DGN | 8 | -40 to 150 电池 稳压器 |
| 文件： | 总35页 (文件大小：3076K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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TPS7B81-Q1
ZHCSJO2C –MAY 2019–REVISED APRIL 2020
脱离电池运行的 TPS7B81-Q1 150mA、超低 IQ (3µA) 低压降稳压器
1 特性
3 说明
1
•
符合面向汽车 应用的 AEC-Q100 标准：
温度等级 1：-40°C 至 125°C，TA
在汽车电池连接 应用中，低静态电流 (IQ) 对于省电和
延长电池寿命而言非常重要。始终开启的系统必须在扩
展温度范围内实现超低 IQ，以便在车辆点火开关关闭
时也能实现持久运行。
–
•
•
器件结温范围：
-40°C 至 150°C
3V 至 40V 宽 VIN 输入电压范围，瞬态电压高达
45V
TPS7B81-Q1 是一款低压降 (LDO) 线性稳压器，专为
高达 40V VIN 的 这些领域而设计。此器件在轻负载时
的典型静态电流仅为 2.7µA，是用于为待机系统中的微
控制器以及控制器局域网和本地互联网络 (CAN/LIN)
收发器供电的最佳解决方案。
•
•
最大输出电流：150mA
低静态电流 IQ：
–
EN = 低电平时典型值为 300nA
（关断模式）
–
–
轻负载时典型值为 2.7µA
轻负载时最大值为 4.5µA
此器件 具有 集成式短路和过流保护。此器件可在
-40°C 至 +125°C 的环境温度下运行，结温范围为
-40°C 至 +150°C。此外，此器件提供多种具有不同尺
寸和热导率的封装选项。小型 WSON 封装有助于实现
最紧凑的 PCB 设计，即使整个器件散热较多，TO-
252 封装也能让器件实现持久运行。这些 特性 使得此
器件非常适合用作各种电池连接汽车 这些领域。
•
•
线路、负载和温度范围内的输出电压精度为 1.5%
最大压降电压：对于固定 5V 输出电压版
本，150mA 负载电流下为 540mV
•
与低 ESR（0.001Ω 至 5Ω）陶瓷输出稳定电容器
（1µF 至 200µF）搭配使用时可保持稳定
•
•
5V、3.3V 和 2.5V 固定输出电压
器件信息(1)
集成故障保护：
器件型号
封装
HVSSOP (8)
封装尺寸（标称值）
3.00mm × 3.00mm
2.00mm × 2.00mm
6.10mm × 6.60mm
–
–
热关断
短路和过流保护
TPS7B81-Q1
WSON (6)
TO-252 (5)
•
封装：
–
–
–
DGN（8 引脚 HVSSOP），RθJA = 63.9°C/W
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
DRV（6 引脚 WSON），RθJA = 72.8°C/W
KVU（5 引脚 TO-252）)，RθJA = 38.8°C/W
添加了项目符号
典型应用原理图
VBATT
VOUT = 3.3V or 5V
2 应用
OUT
TPS7B81-Q1
IN
•
•
•
•
汽车音响主机
CIN
COUT
前照灯
EN
电池管理系统 (BMS)
逆变器和电机控制
1
本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。 有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确
性和有效性。 在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SBVS370
TPS7B81-Q1
ZHCSJO2C –MAY 2019–REVISED APRIL 2020
www.ti.com.cn
目录
7.4 Device Functional Modes........................................ 12
Application and Implementation ........................ 13
8.1 Application Information............................................ 13
8.2 Typical Application ................................................. 17
Power Supply Recommendations...................... 18
1
2
3
4
5
6
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 5
6.1 Absolute Maximum Ratings ...................................... 5
6.2 ESD Ratings.............................................................. 5
6.3 Recommended Operating Conditions....................... 5
6.4 Thermal Information.................................................. 5
6.5 Electrical Characteristics........................................... 6
6.6 Typical Characteristics.............................................. 7
Detailed Description ............................................ 11
7.1 Overview ................................................................. 11
7.2 Functional Block Diagram ....................................... 11
7.3 Feature Description................................................. 11
8
9
10 Layout................................................................... 19
10.1 Layout Guidelines ................................................. 19
10.2 Layout Example ................................................... 19
11 器件和文档支持 ..................................................... 20
11.1 接收文档更新通知 ................................................. 20
11.2 支持资源................................................................ 20
11.3 商标....................................................................... 20
11.4 静电放电警告......................................................... 20
11.5 Glossary................................................................ 20
12 机械、封装和可订购信息....................................... 20
7
4 修订历史记录
注：之前版本的页码可能与当前版本有所不同。
Changes from Revision B (August 2019) to Revision C
Page
•
•
已更改 将 KVU 封装从“预览”更改为“生产数据”....................................................................................................................... 1
已更改 应用 部分 .................................................................................................................................................................... 1
Changes from Revision A (June 2019) to Revision B
Page
•
•
•
已更改 将 DGN 封装从“预览”更改为“生产数据” ...................................................................................................................... 1
已更改 将 525mV 更改为 540mV（在最大压降电压 特性 项目符号） ................................................................................... 1
已添加 RθJA versus Cu Area for the HVSSOP (DGN) Package through ψJB versus Cu Area for the TO-252 (KVU)
Package figures to Power Dissipation section ..................................................................................................................... 15
•
Deleted values from capacitors CIN and COUT in 图 31......................................................................................................... 17
Changes from Original (May 2019) to Revision A
Page
•
已更改 将“预告信息”更改为“生产数据”.................................................................................................................................... 1
2
Copyright © 2019–2020, Texas Instruments Incorporated
TPS7B81-Q1
www.ti.com.cn
ZHCSJO2C –MAY 2019–REVISED APRIL 2020
5 Pin Configuration and Functions
DGN Package
8-Pin HVSSOP PowerPAD™
Top View
DRV Package
6-Pin WSON PowerPAD™
Top View
IN
EN
1
2
3
6
5
4
OUT
DNC
GND
IN
EN
1
2
3
4
8
7
6
5
OUT
NC
Thermal
Pad
Thermal
Pad
NC
GND
GND
GND
GND
Not to scale
Not to scale
KVU Package
5-Pin TO-252
Top View
GND
Not to scale
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Pin Functions
PIN
NO.
I/O
DESCRIPTION
NAME
DGN
DRV
KVU
Do not connect to a biased voltage. Tie this pin to ground or leave
floating.
DNC
—
5
4
—
Enable input pin. Drive EN greater than VIH to turn on the regulator.
Drive EN less than VIL to put the low-dropout (LDO) into shutdown
mode.
EN
2
2
2
I
GND
4, 5, 6
3,4
3, TAB
—
Ground reference
Input power-supply pin. For best transient response and to
minimize input impedance, use the recommended value or larger
ceramic capacitor from IN to ground as listed in the Recommended
Operating Conditions table and the Input Capacitor section. Place
the input capacitor as close to the output of the device as possible.
IN
1
1
1
I
NC
3, 7
—
—
—
Not internally connected
Regulated output voltage pin. A capacitor is required from OUT to
ground for stability. For best transient response, use the nominal
recommended value or larger ceramic capacitor from OUT to
ground; see the Recommended Operating Conditions table and the
Output Capacitor section. Place the output capacitor as close to
output of the device as possible.
OUT
8
6
5
O
Connect the thermal pad to a large-area GND plane for improved
thermal performance.
Thermal pad
—
4
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TPS7B81-Q1
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ZHCSJO2C –MAY 2019–REVISED APRIL 2020
6 Specifications
6.1 Absolute Maximum Ratings
over operating ambient temperature range (unless otherwise noted)(1)(2)
MIN
–0.3
–0.3
–0.3
–40
MAX
45
UNIT
V
VIN
Unregulated input(3)
Enable input(3)
VEN
VOUT
TJ
VIN
7
V
Regulated output
V
Junction temperature range
Storage temperature range
150
150
°C
°C
Tstg
–40
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to GND.
(3) Absolute maximum voltage, can withstand 45 V for 200 ms.
6.2 ESD Ratings
VALUE
±2000
±750
UNIT
Human-body model (HBM), per AEC Q100-002(1)
Electrostatic
discharge
V(ESD)
Charged-device model (CDM), per
AEC Q100-011
Corner pins
Other pins
V
±500
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
over operating ambient temperature range (unless otherwise noted)
MIN
3
MAX
UNIT
VIN
Unregulated input voltage
40
VIN
200
5
V
V
VEN
COUT
ESR
TA
Enable input voltage
0
Output capacitor requirements(1)
Output capacitor ESR requirements(2)
Ambient temperature range
Junction temperature range
1
µF
Ω
0.001
–40
–40
125
150
°C
°C
TJ
(1) The output capacitance range specified in the table is the effective value.
(2) Relevant ESR value at f = 10 kHz
6.4 Thermal Information
TPS7B81-Q1
DGN
(HVSSOP)
DRV
(WSON)
KVU
THERMAL METRIC(1)
UNIT
(TO-252)
5 PINS
31.1
39.9
9.9
8 PINS
63.9
50.2
22.6
1.8
6 PINS
72.8
85.8
37.4
2.7
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
4.2
ψJB
22.3
12.1
37.3
13.8
9.9
RθJC(bot)
2.8
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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6.5 Electrical Characteristics
over operating ambient temperature range, TJ = –40°C to +150°C, VIN = 14 V, and 10-µF ceramic output capacitor (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
MIN TYP
MAX UNIT
SUPPLY VOLTAGE AND CURRENT (IN)
VOUT(Nom)
+ V(Dropout)
VIN
Input voltage
40
1
V
I(SD)
Shutdown current
EN = 0 V
0.3
1.9
2.7
2.7
µA
VIN = 6 V to 40 V, EN ≥ 2 V,
IOUT = 0 mA
3.5
6.5
4.5
2.7
I(Q)
Quiescent current
DGN package
µA
VIN = 6 V to 40 V, EN ≥ 2 V,
IOUT = 0.2 mA
DRV and KVU
packages
Ramp VIN down until the output turns off
Hysteresis
V
V(IN,
UVLO)
VIN undervoltage
detection
200
10
mV
ENABLE INPUT (EN)
VIL
VIH
IEN
Logic-input low level
0.7
V
V
Logic-input high level
Enable current
2
nA
REGULATED OUTPUT (OUT)
VIN = VOUT + V(Dropout) to 40 V,
IOUT = 1 mA to 150 mA
VOUT
Regulated output
Line regulation
–1.5%
1.5%
V(Line-
Reg)
VIN = 6 V to 40 V, IOUT = 10 mA
10
20
mV
mV
DGN package
V(Load-
Reg)
Load regulation
VIN = 14 V, IOUT = 1 mA to 150 mA
DRV and KVU
packages
10
DGN package
270
325
180
200
540
585
350
390
650
675
IOUT = 150 mA
DRV and KVU
packages
VOUT = 5 V
DGN package
IOUT = 100 mA
DRV and KVU
packages
V(Dropout
)
Dropout voltage
mV
DGN package
IOUT = 150 mA
VOUT = 3.3 V
DRV and KVU
packages
345
255
IOUT = 100 mA
450
750
500
IOUT = 150 mA
IOUT = 100 mA
VOUT = 2.5 V,
DGN package
VOUT in regulation, VIN = 7 V for the fixed 5-V option, VIN = 5.8 V
for the fixed 3.3-V option
IOUT
Output current
0
150
690
mA
mA
dB
I(CL)
Output current limit
VOUT short to 90% × VOUT
180 510
60
Power-supply ripple
rejection
V(Ripple) = 0.5 VPP, IOUT = 10 mA, frequency = 100 Hz, COUT = 2.2
µF
PSRR
OPERATING TEMPERATURE RANGE
Junction shutdown
temperature
T(SD)
175
20
ºC
ºC
Hysteresis of thermal
shutdown
T(HYST)
6
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TPS7B81-Q1
www.ti.com.cn
ZHCSJO2C –MAY 2019–REVISED APRIL 2020
6.6 Typical Characteristics
at TJ = –40°C to +150°C, VIN = 14 V, and VEN ≥ 2 V (unless otherwise noted)
480
450
420
390
360
330
300
270
240
210
180
4.2
3.9
3.6
3.3
3
5 V option
3.3 V option
IOUT = 0 mA; VIN = 6 V
IOUT = 0 mA; VIN = 40 V
IOUT = 200 mA; VIN = 6 V
IOUT = 200 mA; VIN = 40 V
2.7
2.4
2.1
1.8
1.5
-50
-25
0
25
50
75
100 125 150 175
-50
-25
0
25
50
75
100 125 150 175
Temperature (èC)
Temperature (èC)
shut
iq_v
VEN = 0 V
VOUT = 5 V
图 1. Shutdown Current vs Ambient Temperature
图 2. Quiescent Current vs Ambient Temperature
4.2
3.9
3.6
3.3
3
500
450
400
350
300
250
200
150
100
50
IOUT = 0 mA; VIN = 6 V
IOUT = 0 mA; VIN = 40 V
IOUT = 200 mA; VIN = 6 V
IOUT = 200 mA; VIN = 40 V
150èC
125èC
105èC
85èC
25èC
0èC
-40èC
-50èC
2.7
2.4
2.1
1.8
1.5
0
-50
-25
0
25
50
75
100 125 150 175
0
20
40
60
80
IOUT (mA)
100
120
140
160
Temperature (èC)
iq_v
drop
VOUT = 3.3 V
VOUT = 5 V, DRV Package
图 3. Quiescent Current vs Ambient Temperature
图 4. Dropout Voltage vs Output Current
600
550
500
450
400
350
300
250
200
150
100
50
510
480
450
420
390
360
330
300
270
240
210
180
150
120
150èC
125èC
105èC
85èC
25èC
0èC
IOUT = 100mA
IOUT = 150mA
-40èC
-50èC
0
0
20
40
60
80
IOUT (mA)
100
120
140
160
-60 -40 -20
0
20 40 60 80 100 120 140 160
Temperature (èC)
drop
drop
VOUT = 3.3 V, DRV package
图 5. Dropout Voltage vs Output Current
VOUT = 5 V
图 6. Dropout Voltage vs Ambient Temperature
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Typical Characteristics (接下页)
at TJ = –40°C to +150°C, VIN = 14 V, and VEN ≥ 2 V (unless otherwise noted)
600
550
500
450
400
350
300
250
200
150
5.004
5.002
5
IOUT = 100 mA
IOUT = 150 mA
4.998
4.996
4.994
4.992
4.99
4.988
4.986
4.984
IOUT = 1 mA
IOUT = 150 mA
-60 -40 -20
0
20 40 60 80 100 120 140 160
Temperature (èC)
-50
-25
0
25
50
75
100 125 150 175
Temperature (èC)
drop
accu
VOUT = 5 V
VOUT = 3.3 V
图 8. Output Voltage vs Ambient Temperature
图 7. Dropout Voltage vs Ambient Temperature
3.302
3.3
25%
22.5%
20%
17.5%
15%
12.5%
10%
7.5%
5%
3.298
3.296
3.294
3.292
3.29
VIN = 4 V
VIN = 14 V
VIN = 40 V
2.5%
0
-50
-25
0
25
50
75
100 125 150 175
Drift (ppm/èC)
Temperature (èC)
accu
neg4
VOUT = 3.3 V, IOUT = 1 mA
3.3-V and 5-V options, IOUT = 1 mA
图 9. Output Voltage vs Ambient Temperature
图 10. Temperature Drift Histogram (–40°C to +25°C)
5.01
5.005
5
40%
35%
30%
25%
20%
15%
10%
5%
-50èC
-40èC
0èC
85èC
125èC
150èC
25èC
105èC
4.995
4.99
4.985
0
5
10
15
20 25
Input Voltage (V)
30
35
40
Drift (ppm/èC)
accu
25_t
VOUT = 5 V, IOUT = 1 mA
图 12. Output Voltage vs Input Voltage
3.3-V and 5-V options, IOUT = 1 mA
图 11. Temperature Drift Histogram (25ºC to 150ºC)
8
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Typical Characteristics (接下页)
at TJ = –40°C to +150°C, VIN = 14 V, and VEN ≥ 2 V (unless otherwise noted)
525
520
515
510
505
500
495
490
485
480
3.31
3.305
3.3
-50èC
-40èC
0èC
25èC
85èC
125èC
150èC
160èC
3.295
3.29
5 V option; VIN = 7 V
3.3 V option; VIN = 5.8 V
0
5
10
15
20
25
Input Voltage (V)
30
35
40
-60 -40 -20
0
20 40 60 80 100 120 140 160
Temperature (èC)
accu
curr
VOUT = 3.3 V, IOUT = 1 mA
VOUT is shorted to 90% × VOUT(NOM)
图 13. Output Voltage vs Input Voltage
图 14. Output Current Limit vs Ambient Temperature
1.55
1.5
4.5
4
1.45
1.4
3.5
3
1.35
1.3
2.5
2
1.25
1.2
1.15
1.1
1.5
1
VIL (disabled)
VIH (enabled)
1.05
-60 -40 -20
0
20 40 60 80 100 120 140 160
Temperature (èC)
-60 -40 -20
0
20 40 60 80 100 120 140 160
Temperature (C)è
enab
enab
图 15. Enable Voltage vs Ambient Temperature
图 16. Enable Current vs Ambient Temperature
20
15
10
5
2.65
2.55
2.45
2.35
2.25
2.15
2.05
1.95
1.85
VEN
VIN
VOUT
0
V(IN, UVLO), Falling
V(IN, UVLO), Rising
-5
-60 -40 -20
0
20 40 60 80 100 120 140 160
Temperature (èC)
0
0.0005
0.001
Time (s)
0.0015
0.002
uvlo
D005
VOUT = 5 V, CIN = 1 µF, COUT = 1 µF
图 17. UVLO vs Ambient Temperature
图 18. Startup with enable
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Typical Characteristics (接下页)
at TJ = –40°C to +150°C, VIN = 14 V, and VEN ≥ 2 V (unless otherwise noted)
20
17.5
15
0.32
0.28
0.24
0.2
0.12
0.08
0.04
0
0.75
0.5
VIN
VOUT (ac coupled)
12.5
10
0.16
0.12
0.08
0.04
0
0.25
0
7.5
5
2.5
0
-0.04
-0.08
-0.25
IOUT
VOUT (ac coupled)
-2.5
-5
-0.04
-0.08
-0.5
0.002
0
0.0005
0.001
Time (s)
0.0015
0.002
0
0.0005
0.001
Time (s)
0.0015
D004
D006
VOUT = 3.3 V, CIN = 0 µF, COUT = 1 µF,
IOUT = 100 mA, Slew rate = 1 V/µs
VOUT = 5 V, CIN = 1 µF, COUT = 1 µF,
IOUT = 1 mA → 100 mA → 1 mA, Slew rate = 1 mA/µs
图 19. Line Transient
图 20. Load Transient
80
80
60
40
20
0
60
40
20
0
IOUT = 1 mA
IOUT = 100 mA
IOUT = 1 mA
IOUT = 100 mA
10
100
1k
10k
Frequency (Hz)
100k
1M
10M
10
100
1k
10k
Frequency (Hz)
100k
1M
10M
psrr
psrr
VOUT = 5 V, CIN = 0 µF, COUT = 10 µF
VOUT = 3.3 V, CIN = 0 µF, COUT = 10 µF
图 21. PSRR vs Frequency
图 22. PSRR vs Frequency
200
100
10
5
2
1
0.5
0.2
0.1
0.05
0.02
0.01
10
0.005
0.002
0.001
0.0005
VOUT = 5 V; IOUT = 1 mA; 247 mVRMS
VOUT = 5 V; IOUT = 100 mA; 478 mVRMS
VOUT = 3.3 V; IOUT = 1 mA; 203 mVRMS
VOUT = 3.3 V; IOUT = 100 mA; 355 mVRMS
0.0002
0.0001
1
0.001
10
100
1k
10k
Frequency (Hz)
100k
1M
10M
0.01
0.1
ESR (W)
1
5
nois
D014
CIN = 0.1 µF, COUT = 10 µF
图 23. Noise vs Frequency
图 24. Output Capacitance vs ESR Stability
10
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TPS7B81-Q1
www.ti.com.cn
ZHCSJO2C –MAY 2019–REVISED APRIL 2020
7 Detailed Description
7.1 Overview
The TPS7B81-Q1 is a 40-V, 150-mA, low-dropout (LDO) linear regulator with ultralow quiescent current. This
voltage regulator consumes only 3 µA of quiescent current at light load, and is quite suitable for the automotive
always-on application.
7.2 Functional Block Diagram
IN
OUT
Undervoltage
Lockout
–
+
Band Gap
Regulator Control
Vref
EN
GND
Overcurrent
Protection
Thermal Shutdown
7.3 Feature Description
7.3.1 Device Enable (EN)
The EN pin is a high-voltage-tolerant pin. A high input activates the device and turns the regulation on. Connect
this pin to an external microcontroller or a digital circuit to enable and disable the device, or connect to the IN pin
for self-bias applications.
7.3.2 Undervoltage Shutdown
This device has an integrated undervoltage lockout (UVLO) circuit to shut down the output if the input voltage
(VIN) falls below an internal UVLO threshold (V(UVLO)). This feature ensures that the regulator does not latch into
an unknown state during low-input-voltage conditions. If the input voltage has a negative transient that drops
below the UVLO threshold and recovers, the regulator shuts down and powers up with a normal power-up
sequence when the input voltage is above the required level.
7.3.3 Current Limit
This device features current-limit protection to keep the device in a safe operating area when an overload or
output short-to-ground condition occurs. This feature protects the device from excessive power dissipation. For
example, during a short-circuit condition on the output, the fault protection limits the current through the pass
element to I(LIM) to protect the device from excessive power dissipation.
7.3.4 Thermal Shutdown
This device incorporates a thermal shutdown (TSD) circuit as protection from overheating. For continuous normal
operation, the junction temperature must not exceed the TSD trip point. If the junction temperature exceeds the
TSD trip point, the output turns off. When the junction temperature falls below the TSD trip point minus the
thermal shutdown hysteresis, the output turns on again.
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7.4 Device Functional Modes
7.4.1 Operation With VIN Lower Than 3 V
The device normally operates with input voltages above 3 V. The device can also operate at lower input
voltages; the maximum UVLO voltage is 2.7 V. The device does not operate at input voltages below the actual
UVLO voltage.
7.4.2 Operation With VIN Larger Than 3 V
When VIN is greater than 3 V, if VIN is also higher than the output set value plus the device dropout voltage, VOUT
is equal to the set value. Otherwise, VOUT is equal to VIN minus the dropout voltage.
表 1. Device Functional Mode Comparison
OPERATING
PARAMETER
MODE
VIN > VOUT(nom)+ V(Dropout) and
Normal mode
Dropout mode
VEN > VIH
VEN > VIH
IOUT < ICL
IOUT < ICL
TJ < 160°C
TJ < 160°C
VIN ≥ 3 V
3V ≤ VIN < VOUT(nom)+ V(Dropout)
Disabled mode
(any true
condition
VIN < V(IN, UVLO)
VEN < VIL
—
TJ > 160°C
disables the
device)
12
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TPS7B81-Q1
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ZHCSJO2C –MAY 2019–REVISED APRIL 2020
8 Application and Implementation
注
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The TPS7B81-Q1 is a 150-mA, 40-V, low-dropout (LDO) linear regulator with ultralow quiescent current. The
PSpice transient model is available for download on the product folder and can be used to evaluate the basic
function of the device.
8.1.1 Power Dissipation
Circuit reliability demands that proper consideration is given to device power dissipation, location of the circuit on
the printed circuit board (PCB), and correct sizing of the thermal plane. The PCB area around the regulator must
be as free as possible of other heat-generating devices that cause added thermal stresses.
As a first-order approximation, power dissipation in the regulator depends on the input-to-output voltage
difference and load conditions. PD can be approximated using 公式 1:
PD = (VIN – VOUT) × IOUT
(1)
An important note is that power dissipation can be minimized, and thus greater efficiency achieved, by proper
selection of the system voltage rails. Proper selection allows the minimum input-to-output voltage differential to
be obtained. The low dropout of the device allows for maximum efficiency across a wide range of output
voltages.
The main heat conduction path for the device is through the thermal pad on the package. As such, the thermal
pad must be soldered to a copper pad area under the device. This pad area contains an array of plated vias that
conduct heat to any inner plane areas or to a bottom-side copper plane.
The maximum power dissipation determines the maximum allowable junction temperature (TJ) for the device.
Power dissipation and junction temperature are most often related by the junction-to-ambient thermal resistance
(RθJA) of the combined PCB, device package, and the temperature of the ambient air (TA), according to 公式 2.
The equation is rearranged for output current in 公式 3.
TJ = TA + RθJA × PD
(2)
(3)
IOUT = (TJ – TA) / [RθJA × (VIN – VOUT)]
Unfortunately, this thermal resistance (RθJA) is highly dependent on the heat-spreading capability built into the
particular PCB design, and therefore varies according to the total copper area, copper weight, and location of the
planes. The RθJA recorded in the v table is determined by the JEDEC standard, PCB, and copper-spreading area,
and is only used as a relative measure of package thermal performance. Note that for a well-designed thermal
layout, RθJA is actually the sum of the package junction-to-case (bottom) thermal resistance (RθJCbot) plus the
thermal resistance contribution by the PCB copper.
图 25 through 图 30 show the functions of RθJA and ψJB vs. copper area and thickness. These plots are
generated with a 101.6 mm x 101.6 mm x 1.6mm PCB of two and four layers. For the four layer board, inner
planes use 1 oz copper thickness. Outer layers are simulated with both 1 oz and 2 oz copper thickness. A 2 x 1
array of thermal vias of 300 µm drill diameter and 25 µm Cu plating is located beneath the thermal pad of the
device. The thermal vias connect the top layer, the bottom layer and, in the case of the 4-layer board, the first
inner GND plane. Each of the layers has a copper plane of equal area.
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Application Information (接下页)
140
130
120
110
100
90
4 layer PCB, 1 oz copper
4 layer PCB, 2 oz copper
2 layer PCB, 1 oz copper
2 layer PCB, 2 oz copper
80
70
60
50
40
30
0
10
20
30
40
50
60
70
80
90
100
Cu Area Per Layer (cm2)
thet
图 25. RθJA versus Cu Area for the WSON (DRV) Package
34
32
30
28
26
24
22
20
4 layer PCB, 1 oz copper
4 layer PCB, 2 oz copper
2 layer PCB, 1 oz copper
2 layer PCB, 2 oz copper
0
10
20
30
40
50
60
70
80
90
100
Cu Area Per Layer (cm2)
psij
图 26. ψJB versus Cu Area for the WSON (DRV) Package
14
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TPS7B81-Q1
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ZHCSJO2C –MAY 2019–REVISED APRIL 2020
Application Information (接下页)
130
120
110
100
90
4 layer PCB, 1 oz copper
4 layer PCB, 2 oz copper
2 layer PCB, 1 oz copper
2 layer PCB, 2 oz copper
80
70
60
50
40
30
0
10
20
30
40
50
60
70
80
90
100
Cu Area Per Layer (cm2)
thet
图 27. RθJA versus Cu Area for the HVSSOP (DGN) Package
32
30
28
26
24
22
20
18
4 layer PCB, 1 oz copper
4 layer PCB, 2 oz copper
2 layer PCB, 1 oz copper
2 layer PCB, 2 oz copper
0
10
20
30
40
50
60
70
80
90
100
Cu Area Per Layer (cm2)
psij
图 28. ψJB versus Cu Area for the HVSSOP (DGN) Package
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Application Information (接下页)
110
105
100
95
90
85
80
75
70
65
60
55
50
45
40
35
30
25
4 layer PCB, 1 oz copper
4 layer PCB, 2 oz copper
2 layer PCB, 1 oz copper
2 layer PCB, 2 oz copper
0
10
20
30
40
50
60
70
80
90
100
Cu Area Per Layer (cm2)
thet
图 29. RθJA versus Cu Area for the TO-252 (KVU) Package
30
28
26
24
22
20
18
16
14
12
4 layer PCB, 1 oz copper
4 layer PCB, 2 oz copper
2 layer PCB, 1 oz copper
2 layer PCB, 2 oz copper
0
10
20
30
40
50
60
70
80
90
100
Cu Area Per Layer (cm2)
psij
图 30. ψJB versus Cu Area for the TO-252 (KVU) Package
16
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TPS7B81-Q1
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ZHCSJO2C –MAY 2019–REVISED APRIL 2020
Application Information (接下页)
8.1.1.1 Estimating Junction Temperature
The JEDEC standard now recommends the use of psi (Ψ) thermal metrics to estimate the junction temperatures
of the LDO when in-circuit on a typical PCB board application. These metrics are not strictly speaking thermal
resistances, but rather offer practical and relative means of estimating junction temperatures. These psi metrics
are determined to be significantly independent of the copper-spreading area. The key thermal metrics (ΨJT and
ΨJB) are given in the Thermal Information table and are used in accordance with 公式 4.
YJT: TJ = TT + YJT ´ PD
YJB: TJ = TB + YJB ´ PD
where:
•
•
•
PD is the power dissipated as explained in 公式 1
TT is the temperature at the center-top of the device package, and
TB is the PCB surface temperature measured 1 mm from the device package and centered on the package
edge
(4)
8.2 Typical Application
图 31 shows a typical application circuit for the TPS7B81-Q1. Different external component values can be used,
depending on the end application. An application may require a larger output capacitor during fast load steps to
prevent a large drop on the output voltage. TI recommends using a low-equivalent series resistance (ESR)
ceramic capacitor with an X5R- or X7R-type dielectric.
VBATT
VOUT = 3.3V or 5V
OUT
TPS7B81-Q1
IN
CIN
COUT
EN
图 31. TPS7B81-Q1 Typical Application Schematic
8.2.1 Design Requirements
Use the parameters listed in 表 2 for this design example.
表 2. Design Requirements Parameters
PARAMETER
Input voltage range
Output voltage
VALUE
3 V to 40 V
5 V or 3.3 V
Output current
150 mA maximum
8.2.2 Detailed Design Procedure
To begin the design process, determine the following:
•
•
•
Input voltage range
Output voltage
Output current
8.2.2.1 Input Capacitor
Although an input capacitor is not required for stability, good analog design practice is to connect a 10-µF to 22-
µF capacitor from IN to GND. This capacitor counteracts reactive input sources and improves transient response,
input ripple rejection, and PSRR. The voltage rating must be greater than the maximum input voltage.
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8.2.2.2 Output Capacitor
To ensure the stability of the TPS7B81-Q1, the device requires an output capacitor with a value in the range from
1 µF to 200 µF and with an ESR range between 0.001 Ω and 5 Ω. TI recommends selecting a ceramic capacitor
with low ESR to improve the load transient response.
8.2.3 Application Curve
15
12.5
10
7.5
5
2.5
0
VEN
VIN
VOUT
0.002
-2.5
0
0.0005
0.001
Time (s)
0.0015
D007
图 32. TPS7B81-Q1 Power-Up Waveform (5 V)
9 Power Supply Recommendations
The device is designed to operate from an input-voltage supply range from 3 V to 40 V. The input supply must be
well regulated. If the input supply is located more than a few inches from the TPS7B81-Q1, TI recommends
adding a capacitor with a value greater than or equal to 10 µF with a 0.1-µF bypass capacitor in parallel at the
input.
18
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TPS7B81-Q1
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ZHCSJO2C –MAY 2019–REVISED APRIL 2020
10 Layout
10.1 Layout Guidelines
Layout is an important step for LDO power supplies, especially for high-voltage and large-output-current supplies.
If the layout is not carefully designed, the regulator can fail to deliver enough output current because of thermal
limitations. To improve the thermal performance of the device, and to maximize the current output at high
ambient temperature, spread the copper under the thermal pad as far as possible and put enough thermal vias
on the copper under the thermal pad. 图 33 shows an example layout.
10.2 Layout Example
GND
IN
1
2
3
4
8
7
6
5
OUT
EN
GND
图 33. TPSB81-Q1 Example Layout Diagram
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11 器件和文档支持
11.1 接收文档更新通知
要接收文档更新通知，请导航至 ti.com.cn 上的器件产品文件夹。单击右上角的通知我进行注册，即可每周接收产
品信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
11.2 支持资源
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
11.3 商标
PowerPAD, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
11.4 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
11.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且
不会对此文档进行修订。如需获取此数据表的浏览器版本，请查阅左侧的导航栏。
20
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PACKAGE OPTION ADDENDUM
www.ti.com
15-Feb-2022
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPS7B8125QDGNRQ1
TPS7B8133QDGNRQ1
TPS7B8133QDRVRQ1
TPS7B8133QKVURQ1
TPS7B8150QDGNRQ1
TPS7B8150QDRVRQ1
TPS7B8150QKVURQ1
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
HVSSOP
HVSSOP
WSON
DGN
DGN
DRV
KVU
DGN
DRV
KVU
8
8
6
5
8
6
5
2500 RoHS & Green
2500 RoHS & Green
3000 RoHS & Green
2500 RoHS & Green
2500 RoHS & Green
3000 RoHS & Green
2500 RoHS & Green
NIPDAUAG
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-3-260C-168 HR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-3-260C-168 HR
-40 to 150
-40 to 150
-40 to 150
-40 to 150
-40 to 150
-40 to 150
-40 to 150
26GX
1VTX
1X2H
NIPDAUAG
NIPDAU
SN
TO-252
HVSSOP
WSON
7B8133Q1
1VUX
NIPDAUAG
NIPDAU
SN
1WNH
TO-252
7B8150Q1
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
15-Feb-2022
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TPS7B81-Q1 :
Catalog : TPS7B81
•
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
•
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
17-Jul-2020
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS7B8125QDGNRQ1 HVSSOP DGN
TPS7B8133QDGNRQ1 HVSSOP DGN
8
8
6
5
8
6
5
2500
2500
3000
2500
2500
3000
2500
330.0
330.0
180.0
330.0
330.0
180.0
330.0
12.4
12.4
8.4
5.3
5.3
2.3
6.9
5.3
2.3
6.9
3.4
3.4
1.4
1.4
8.0
8.0
4.0
8.0
8.0
4.0
8.0
12.0
12.0
8.0
Q1
Q1
Q2
Q2
Q1
Q2
Q2
TPS7B8133QDRVRQ1
WSON
DRV
KVU
2.3
1.15
2.7
TPS7B8133QKVURQ1 TO-252
16.4
12.4
8.4
10.5
3.4
16.0
12.0
8.0
TPS7B8150QDGNRQ1 HVSSOP DGN
1.4
TPS7B8150QDRVRQ1
WSON
DRV
KVU
2.3
1.15
2.7
TPS7B8150QKVURQ1 TO-252
16.4
10.5
16.0
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
17-Jul-2020
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TPS7B8125QDGNRQ1
TPS7B8133QDGNRQ1
TPS7B8133QDRVRQ1
TPS7B8133QKVURQ1
TPS7B8150QDGNRQ1
TPS7B8150QDRVRQ1
TPS7B8150QKVURQ1
HVSSOP
HVSSOP
WSON
DGN
DGN
DRV
KVU
DGN
DRV
KVU
8
8
6
5
8
6
5
2500
2500
3000
2500
2500
3000
2500
366.0
366.0
210.0
340.0
366.0
210.0
340.0
364.0
364.0
185.0
340.0
364.0
185.0
340.0
50.0
50.0
35.0
38.0
50.0
35.0
38.0
TO-252
HVSSOP
WSON
TO-252
Pack Materials-Page 2
GENERIC PACKAGE VIEW
DRV 6
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4206925/F
PACKAGE OUTLINE
DRV0006A
WSON - 0.8 mm max height
SCALE 5.500
PLASTIC SMALL OUTLINE - NO LEAD
2.1
1.9
A
B
PIN 1 INDEX AREA
2.1
1.9
0.8
0.7
C
SEATING PLANE
0.08 C
(0.2) TYP
0.05
0.00
1
0.1
EXPOSED
THERMAL PAD
3
4
6
2X
7
1.3
1.6 0.1
1
4X 0.65
0.35
0.25
6X
PIN 1 ID
(OPTIONAL)
0.3
0.2
6X
0.1
C A
C
B
0.05
4222173/B 04/2018
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
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EXAMPLE BOARD LAYOUT
DRV0006A
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
6X (0.45)
6X (0.3)
(1)
1
7
6
SYMM
(1.6)
(1.1)
4X (0.65)
4
3
SYMM
(1.95)
(R0.05) TYP
(
0.2) VIA
TYP
LAND PATTERN EXAMPLE
SCALE:25X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4222173/B 04/2018
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If some or all are implemented, recommended via locations are shown.
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EXAMPLE STENCIL DESIGN
DRV0006A
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
SYMM
7
6X (0.45)
METAL
1
6
6X (0.3)
(0.45)
SYMM
4X (0.65)
(0.7)
4
3
(R0.05) TYP
(1)
(1.95)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD #7
88% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:30X
4222173/B 04/2018
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
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GENERIC PACKAGE VIEW
DGN 8
3 x 3, 0.65 mm pitch
PowerPAD VSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4225482/A
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PACKAGE OUTLINE
DGN0008G
PowerPADTM VSSOP - 1.1 mm max height
S
C
A
L
E
4
.
0
0
0
SMALL OUTLINE PACKAGE
C
5.05
4.75
TYP
A
0.1 C
SEATING
PLANE
PIN 1 INDEX AREA
6X 0.65
8
1
2X
3.1
2.9
1.95
NOTE 3
4
5
0.38
8X
0.25
3.1
2.9
0.13
C A B
B
NOTE 4
0.23
0.13
SEE DETAIL A
EXPOSED THERMAL PAD
4
5
0.25
GAGE PLANE
2.15
1.95
9
1.1 MAX
8
0.15
0.05
1
0.7
0.4
0 -8
A
20
DETAIL A
TYPICAL
1.846
1.646
4225480/B 12/2022
PowerPAD is a trademark of Texas Instruments.
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-187.
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EXAMPLE BOARD LAYOUT
DGN0008G
PowerPADTM VSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE
(2)
NOTE 9
METAL COVERED
BY SOLDER MASK
(1.57)
SOLDER MASK
DEFINED PAD
SYMM
8X (1.4)
(R0.05) TYP
8
8X (0.45)
1
(3)
NOTE 9
SYMM
(1.89)
9
(1.22)
6X (0.65)
5
4
(
0.2) TYP
VIA
SEE DETAILS
(0.55)
(4.4)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 15X
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
METAL
EXPOSED METAL
EXPOSED METAL
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
NON-SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
15.000
(PREFERRED)
SOLDER MASK DETAILS
4225480/B 12/2022
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
8. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
9. Size of metal pad may vary due to creepage requirement.
www.ti.com
EXAMPLE STENCIL DESIGN
DGN0008G
PowerPADTM VSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE
(1.57)
BASED ON
0.125 THICK
STENCIL
SYMM
(R0.05) TYP
8X (1.4)
8
1
8X (0.45)
(1.89)
SYMM
BASED ON
0.125 THICK
STENCIL
6X (0.65)
5
4
METAL COVERED
BY SOLDER MASK
SEE TABLE FOR
DIFFERENT OPENINGS
FOR OTHER STENCIL
THICKNESSES
(4.4)
SOLDER PASTE EXAMPLE
EXPOSED PAD 9:
100% PRINTED SOLDER COVERAGE BY AREA
SCALE: 15X
STENCIL
THICKNESS
SOLDER STENCIL
OPENING
0.1
1.76 X 2.11
1.57 X 1.89 (SHOWN)
1.43 X 1.73
0.125
0.15
0.175
1.33 X 1.60
4225480/B 12/2022
NOTES: (continued)
10. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
11. Board assembly site may have different recommendations for stencil design.
www.ti.com
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