TPS7B8550QWDRCRQ1 [TI]
具有集成电压监控功能的汽车类 150mA、40V、低压降稳压器 | DRC | 10 | -40 to 150;
| 型号： | TPS7B8550QWDRCRQ1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有集成电压监控功能的汽车类 150mA、40V、低压降稳压器 | DRC | 10 | -40 to 150 监控 稳压器 |
| 文件： | 总43页 (文件大小：3468K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPS7B85-Q1
SBVS360A – FEBRUARY 2020 – REVISED NOVEMBER 2020
TPS7B85-Q1 150-mA, 40-V, Low-Dropout Regulator
With Power-Good and Integrated Voltage Monitoring
1 Features
3 Description
•
AEC-Q100 qualified for automotive applications:
The TPS7B85-Q1 is a low-dropout linear regulator
designed to connect to the battery in automotive
applications. The device has an input voltage range
extending to 40 V, which allows the device to
withstand transients (such as load dump) that are
anticipated in automotive systems. With only an 18-
µA quiescent current, the device is an optimal solution
for powering always-on components such as
microcontrollers (MCUs) and controller area network
(CAN) transceivers in standby systems.
– Temperature grade 1: –40°C to +125°C, TA
– Junction temperature: –40°C to +150°C, TJ
Input voltage range: 3 V to 40 V (42 V max)
Output voltage range: 3.3 V and 5 V (fixed)
Output current: up to 150 mA
Output voltage accuracy: ±0.75% (max)
Low dropout voltage:
– 225 mV (max) at 150 mA (VOUT ≥ 3.3 V)
Low quiescent current:
•
•
•
•
•
•
•
The device has state-of-the-art transient response
that allows the output to quickly react to changes in
load or line (for example, during cold-crank
conditions). Additionally, the device has a novel
architecture that minimizes output overshoot when
recovering from dropout. During normal operation, the
device has a tight DC accuracy of ±0.75% over line,
load, and temperature.
– 18 µA (typ)
– 4 µA (max) when disabled
Excellent line transient response:
– ±2% VOUT deviation during cold-crank
– ±2% VOUT deviation (1-V/µs VIN slew rate)
Integrated voltage detection
Power-good with adjustable threshold and
programmable delay period
Stable with a 2.2-µF or larger capacitor
Functional Safety-Capable
– Documentation available to aid functional safety
system design
•
•
The TPS7B85-Q1 is equipped with power-good and
integrated voltage monitoring. The power-good delay
and voltage threshold can be adjusted by external
components. The integrated voltage detector can be
used to monitor the input voltage and alert
downstream components (such as MCUs) when the
battery voltage begins to fall.
•
•
•
Package: 10-pin VSON with thermal pad
– Low thermal resistance (RθJA): 50.3°C/W
The device is available in a small VSON package that
facilitates a compact printed circuit board (PCB)
design. The low thermal resistance enables sustained
operation despite significant dissipation across the
device.
2 Applications
•
•
•
Reconfigurable instrument clusters
Body control modules (BCM)
Always-on battery-connected applications:
– Automotive gateways
Device Information (1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
– Remote keyless entries (RKE)
TPS7B85-Q1
VSON (10)
3.00 mm × 3.00 mm
45
40
35
30
25
20
15
10
5
0.25
VIN
VOUT
0.2
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
0.15
0.1
0.05
0
IN
OUT
EN
PGADJ
-0.05
-0.1
-0.15
-0.2
SI
PG
SO
TPS7B85-Q1
I/O
I/O
DELAY
0
0
500
1000
1500
Time (ms)
2000
2500
3000
GND
Line Transient Response (3-V/µs VIN Slew Rate)
Typical Application Schematic
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS7B85-Q1
SBVS360A – FEBRUARY 2020 – REVISED NOVEMBER 2020
www.ti.com
Table of Contents
1 Features............................................................................1
2 Applications.....................................................................1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings ....................................... 4
6.2 ESD Ratings .............................................................. 4
6.3 Recommended Operating Conditions ........................4
6.4 Thermal Information ...................................................5
6.5 Electrical Characteristics ............................................5
6.6 Switching Characteristics ...........................................6
6.7 Typical Characteristics................................................7
7 Detailed Description......................................................14
7.1 Overview...................................................................14
7.2 Functional Block Diagram.........................................14
7.3 Feature Description...................................................15
7.4 Device Functional Modes..........................................18
8 Application and Implementation..................................19
8.1 Application Information............................................. 19
8.2 Typical Application.................................................... 27
9 Power Supply Recommendations................................28
10 Layout...........................................................................29
10.1 Layout Guidelines................................................... 29
10.2 Layout Example...................................................... 30
11 Device and Documentation Support..........................31
11.1 Device Support........................................................31
11.2 Receiving Notification of Documentation Updates..31
11.3 Support Resources................................................. 31
11.4 Trademarks............................................................. 31
11.5 Electrostatic Discharge Caution..............................31
11.6 Glossary..................................................................31
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision * (February 2020) to Revision A (November 2020)
Page
•
Changed document status from advanced information to production data........................................................ 1
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5 Pin Configuration and Functions
IN
OUT
PGADJ
SO
1
2
3
4
5
10
9
SI
Thermal
Pad
8
EN
PG
GND
7
DELAY
NC
6
Figure 5-1. DRC Package, 10-Pin VSON, Top View
Table 5-1. Pin Functions
PIN
TYPE(1)
DESCRIPTION
NAME
DRC
Power-good delay adjustment pin. Connect a capacitor from this pin to GND to set the PG
reset delay. Leave this pin floating for a default (t(DLY_FIX)) delay. See the Power-Good section
for more information. If this functionality is not desired, leave this pin floating because
connecting this pin to GND causes a perminant increase in the GND current.
DELAY
4
O
Enable pin. The device is disabled when the enable pin becomes lower than the enable logic
input low level (VIL). To ensure the device is enabled, the EN pin must be driven above the
logic high level (VIH). This pin should not be left floating as this pin is high impedance if it is
left floating the part may enable or disable.
EN
8
I
GND
NC
6
5
G
Ground pin. Connect this pin to the thermal pad with a low-impedance connection.
No internal connection. Connect this pin to GND for the best thermal resistance.
—
Power-good threshold-adjustment pin. Connect a resistor divider between the PGADJ and
OUT pins to set the power-good threshold. Connect this pin to ground to set the threshold to
VPG(TH,FALLING). See Power-Good for more information.
PGADJ
2
I
Power-good pin. This pin has an internal pullup resistor. Do not connect this pin to VOUT or
any other biased voltage rail. VPG is logic level high when VOUT is above the power-good
threshold. See Power-Good for more information.
PG
SI
7
9
3
O
I
Sense input pin. Connect via an external voltage divider to the supply voltage to be
monitored.
Sense output pin. This pin has an internal pullup resistor. Do not connect this pin to VOUT or
any other biased voltage rail. VSO is logic level low when VSI falls below the sense-low
threshold.
SO
O
Input power-supply voltage pin. For best transient response and to minimize input
impedance, use the recommended value or larger ceramic capacitor from IN to ground as
listed in the Recommended Operating Conditions table and the Input Capacitor section.
Place the input capacitor as close to the input of the device as possible.
IN
10
1
P
Regulated output voltage pin. A capacitor is required from OUT to ground for stability. For
best transient response, use the nominal recommended value or larger ceramic capacitor
from OUT to ground; see the Recommended Operating Conditions table and the Output
Capacitor section. Place the output capacitor as close to the output of the device as possible.
If using a high ESR capacitor, decouple the output with a 100-nF ceramic capacitor.
OUT
O
Thermal pad. Connect the pad to GND for the best possible thermal performance. See the
Layout section for more information.
Thermal pad
—
(1) I = input; O = output; P = power; G = ground.
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
MAX UNIT
IN
Unregulated input
Enable input
42
V
V
V
V
V
V
EN
42
OUT
FB
Regulated output
Feedback
VIN + 0.3(2)
20
42
6
SI
Sense input
Delay
Reset delay input
SO, PG,
PGADJ
Sense output, power-good, power-good adjustable threshold
–0.3
20
V
TA
Operating ambient temperature
Operating junction temperature
Storage temperature
–40
–40
–65
125
150
150
°C
°C
°C
TJ
Tstg
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions isnot implied. Exposure to absolute-maximum-rated conditions for extended periods may affect devicereliability.
(2) The absolute maximum rating is VIN + 0.3 V or 20 V, whichever is smaller.
6.2 ESD Ratings
VALUE
±2000
±500
UNIT
Human-body model (HBM), per AEC Q100-002(1)
V(ESD)
Electrostatic discharge
All pins
Corner pins
V
Charged-device model (CDM), per AEC
Q100-011
±750
(1) AEC Q100-002 indicates that HBM stressing shall be in accordancewith the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
3
TYP
MAX
40
UNIT
VIN
Input voltage
V
V
VOUT
IOUT
Output voltage
Output current
High voltage (I/O)
Delay pin voltage
1.2
0
18
150
40
mA
V
VEN, VSI
VDelay
0
0
5.5
V
VPG, VSO
VPGADJ
,
Low voltage (I/O), power-good adjustable threshold
0
18
V
COUT
ESR
CIN
Output capacitor(2)
2.2
0.001
0.1
220
2
µF
Ω
Output capacitor ESR requirements(3)
Input capacitor(1)
1
µF
uF
°C
CDelay
TJ
Power-good delay capacitor
Operating junction temperature
0
1
–40
150
(1) For robust EMI performance the minimum input capacitance is 500 nF.
(2) Effective output capacitance of 1 µF minimum required for stability.
(3) If using a large ESR capacitor it is recommended to decouple this with a 100-nF ceramic capacitor to improve transient performance.
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6.4 Thermal Information
TPS7B85-Q1
THERMAL METRIC(1) (2)
DRC (VSON)
10 PINS
50.3
UNIT
RθJA
RθJC(top) Junction-to-case (top) thermal resistance
Junction-to-ambient thermal resistance(3)
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
54.5
RθJB
ψJT
Junction-to-board thermal resistance
23.9
Junction-to-top characterization parameter
Junction-to-board characterization parameter
1.2
ψJB
23.9
RθJC(bot) Junction-to-case (bottom) thermal resistance
7.5
(1) The thermal data is based on the JEDEC standard high K profile,JESD 51-7. Two-signal, two-plane, four-layer board with 2-oz. copper.
The copper pad is soldered tothe thermal land pattern. Also, correct attachment procedure must be incorporated.
(2) For more information about traditional and new thermal metrics,see the Semiconductor and IC PackageThermal Metrics application
report.
(3) The 1s0p RθJA is 202.5℃/W for the DRC package.
6.5 Electrical Characteristics
specified at TJ = –40°C to +150°C, VIN = 13.5 V, IOUT = 0 mA, COUT = 2.2 µF, 1 mΩ < COUT ESR < 2 Ω, CIN = 1 µF, and VEN
= 2 V (unless otherwise noted); typical values are at TJ = 25°C
PARAMETER
TEST CONDITIONS
MIN TYP MAX
UNIT
VIN = VOUT + 500 mV to TJ = 25ºC
–0.5
0.5
VOUT
Regulated output accuracy
40 V,
%
IOUT = 100 µA to 150 mA (1)
TJ = –40°C to +150ºC –0.75
0.75
VIN = VOUT + 500 mV
to 40 V,
IOUT = 100 µA
Change in percent of output
voltage
ΔVOUT(ΔVIN)
Line regulation
0.2
0.2
%
VIN = VOUT + 500 mV,
IOUT = 100 µA to
150 mA
Change in percent of output
voltage
ΔVOUT(ΔIOUT) Load regulation
Load transient response settling
COUT = 10 µF
100
µs
time(2) (3)
IOUT = 45 mA to 105
mA
ΔVOUT
COUT = 10 µF
–2%
–10%
10%
Load transient response
overshoot, undershoot(3)
%VOUT
IOUT = 0 mA to 150
mA
TJ = 25ºC
18
21
VIN = VOUT + 500 mV to
40 V, IOUT = 0 mA
IQ
Quiescent current
µA
TJ = –40°C to +150ºC
TJ = –40°C to +150ºC
TJ = 25ºC
26
35
IOUT = 500 µA
VEN = 0 V
2.5
4
ISHUTDOWN
Shutdown supply current (IGND
)
µA
TJ = –40°C to +150ºC
IOUT ≤ 1 mA, VOUT ≥ 3.3 V, VIN = VOUT(NOM) x 0.95
IOUT = 105 mA, VOUT ≥ 3.3 V, VIN = VOUT(NOM)
IOUT = 150 mA, VOUT ≥ 3.3 V, VIN = VOUT(NOM)
VIN rising
43
VDO
Dropout voltage
125
155
2.7
175
225
2.82
2.6
mV
VUVLO(RISING) Rising input supply UVLO
VUVLO(FALLING) Falling input supply UVLO
2.6
V
V
VIN falling
2.38
2.5
VUVLO(HYST)
VUVLO hysteresis
230
mV
V
VIL
VIH
IEN
Enable logic input low level
Enable logic input high level
EN pin current
0.7
50
2
V
VEN = VIN = 13.5 V
nA
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6.5 Electrical Characteristics (continued)
specified at TJ = –40°C to +150°C, VIN = 13.5 V, IOUT = 0 mA, COUT = 2.2 µF, 1 mΩ < COUT ESR < 2 Ω, CIN = 1 µF, and VEN
= 2 V (unless otherwise noted); typical values are at TJ = 25°C
PARAMETER
TEST CONDITIONS
MIN TYP MAX
UNIT
VIN = VOUT(nom) + 1 V, VOUT short to
90% x VOUT(NOM)
ICL
Output current limit
180
220
260
mA
VIN - VOUT = 500 mV, frequency = 1 kHz,
IOUT = 150 mA
PSRR
Power-supply ripple rejection
55
dB
Vn
Output noise voltage
VOUT = 3.3 V, BW = 10 Hz to 100 kHz
280
µVRMS
V
VSI(HIGH)
VSI(LOW)
VSI(HYST)
ISI
Sense input threshold high
Sense input threshold low
Sense input switching hysteresis
Sense input current
VSI rising
VSI falling
1.17 1.21
1.07 1.12
90
1.25
1.15
V
mV
µA
VSI = 40 V
0.015
1.5
50
Sense output internal pullup
resistor
RSO
10
10
30
30
kΩ
V
VSO(OL)
RPG
Sense output low voltage
VSI ≤ 1.07 V, VIN ≥ 3 V
0.4
50
Power-good internal pullup
resistor
kΩ
V
VPG(OL)
PG pin low level output voltage
Default power-good threshold
Power-good hysteresis
VOUT ≤ 0.83 x VOUT
0.4
95
93
VPG(TH,RISING)
VPG(TH,FALLING)
VPG(HYST)
VOUT rising, PGADJpin shorted to ground
VOUT falling, PGADJ pin shorted to ground
85
83
%VOUT
2.5
1
%VOUT
VPGADJ
Switching voltage for the power-
good adjust pin
VOUT falling, PGADJ falling
0.97
5
1.030
50
V
mV
V
(TH,FALLING)
VPGADJ(HYST)
VDLY(TH)
PGADJ hysteresis
35
Threshold to release power-good
high
Voltage at delay pin rising
1.17 1.21
1.25
2
IDLY(CHARGE)
Delay capacitor charging current VDLY = 1 V
1
1.5
175
20
µA
°C
°C
TSD(SHUTDOWN) Junction shutdown temperature
TSD(HYST) Hysteresis of thermal shutdown
(1) Power dissipation is limited to 2W for IC production testing purposes. The power dissipation can be higher during normal operation.
Please see the thermal dissipation section for more information on how much power the device can dissipate while maintaining a
junction temperature below 150℃.
(2) The settling time is measured from when IOUT is stepped from 45mA to 105 mA to when the output voltage recovers to
VOUT = VOUT(nom) - 5 mV.
(3) This specification is specified by design.
6.6 Switching Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
TIMING FOR SENSE INPUT AND OUTPUT (SI, SO)
t(PD_SO_HL)
t(PD_SO_LH)
Sense high reaction time
Sense low reaction time
25
30
µs
µs
TIMING POWER-GOOD
t(DLY_FIX) Power-good propagation delay
t(Deglitch)
No capacitor connected at DELAY pin
No capacitor connected at DELAY pin
100
90
µs
µs
Power-good deglitch time
Delay capacitor value:
C(DELAY) = 100 nF
t(DLY)
Power-good propagation delay
80
ms
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6.7 Typical Characteristics
specified at TJ = –40°C to +150°C, VIN = 13.5 V, IOUT = 100 µA, COUT = 2.2 µF, 1 mΩ < COUT ESR < 2 Ω, CIN = 1 µF, and
VEN = 2 V (unless otherwise noted)
0.1
0.05
0
5.015
5.01
5.005
5
150 mA
100 mA
-55èC
-40èC
0èC
85èC
150èC
25èC
125èC
-0.05
-0.1
-0.15
-0.2
-0.25
-0.3
4.995
4.99
4.985
4.98
4.975
-60 -40 -20
0
20 40 60 80 100 120 140 160
Temperature (èC)
5
10
15
20 25
Input Voltage (V)
30
35
40
VOUT = 5 V, IOUT = 150 mA
Figure 6-2. Line Regulation vs VIN
Figure 6-1. Accuracy vs Temperature
5.015
5.015
5.01
5.005
5
-55èC
-40èC
0èC
25èC
85èC
125èC
150èC
-55èC
-40èC
0èC
25èC
85èC
125èC
150èC
5.01
5.005
5
4.995
4.99
4.985
4.98
4.975
4.995
4.99
4.985
4.98
4.975
5
10
15
20 25
Input Voltage (V)
30
35
40
5
10
15
20 25
Input Voltage (V)
30
35
40
VOUT = 5 V, IOUT = 5 mA
Figure 6-3. Line Regulation vs VIN
VOUT = 5 V, IOUT = 1 mA
Figure 6-4. Line Regulation vs VIN
5.015
5.01
5.005
5
5.01
5.0075
5.005
5.0025
5
-40 èC
25 èC
85 èC
-55èC
-40èC
0èC
85èC
150èC
25èC
125èC
4.995
4.99
4.985
4.98
4.975
4.9975
4.995
4.9925
4.99
0
5
10
15
20
25
Input Voltage (V)
30
35
40
0
25
50 75
Output Current (mA)
100
125
150
COUT = 10 µF
Figure 6-6. Line Regulation at 50 mA
VOUT = 5 V
Figure 6-5. Load Regulation vs IOUT
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6.7 Typical Characteristics (continued)
specified at TJ = –40°C to +150°C, VIN = 13.5 V, IOUT = 100 µA, COUT = 2.2 µF, 1 mΩ < COUT ESR < 2 Ω, CIN = 1 µF, and
VEN = 2 V (unless otherwise noted)
5.01
5.0075
5.005
5.0025
5
275
250
225
200
175
150
125
100
75
-55èC
-40èC
0èC
85èC
150èC
-40 èC
25 èC
85 èC
25èC
125èC
4.9975
4.995
4.9925
4.99
50
25
0
0
30
60 90
Output Current (mA)
120
150
0
5
10
15
20
25
Input Voltage (V)
30
35
40
VIN = 3 V
COUT = 10 µF
Figure 6-7. Line Regulation at 100 mA
Figure 6-8. Dropout Voltage (VDO) vs IOUT
100
90
80
70
60
50
40
30
20
10
100
90
80
70
60
50
40
30
20
10
0
IOUT = 150 mA
IOUT = 100 mA
IOUT = 50 mA
IOUT = 10 mA
IOUT = 1mA
VIN = 5.5 V
VIN = 6 V
VIN = 7 V
VIN = 10 V
VIN = 13.5 V
0
10
100
1k
10k 100k
Frequency (Hz)
1M
10M
10
100
1k
10k 100k
Frequency (Hz)
1M
10M
COUT = 10 µF (X7R 50 V), VOUT = 5 V
COUT = 10 µF (X7R 50 V), IOUT = 150 mA, VOUT = 5 V
Figure 6-9. PSRR vs Frequency and IOUT
Figure 6-10. PSRR vs Frequency and VIN
10
5
10
5
2
1
2
1
0.5
0.5
0.2
0.1
0.2
0.1
0.05
0.05
0.02
0.01
0.02
0.01
IOUT
10 mA, 252.5 mVRMS
150 mA, 267.6 mVRMS
IOUT
10 mA, 364.8 mVRMS
150 mA, 391.4 mVRMS
0.005
0.005
0.002
0.001
0.002
0.001
10
100
1k
10k
Frequency (Hz)
100k
1M
10M
10
100
1k
10k
Frequency (Hz)
100k
1M
10M
VOUT = 3.3 V, COUT = 10 µF
Figure 6-11. Noise vs Frequency at 3.3 V
VOUT = 5 V, COUT = 10 µF
Figure 6-12. Noise vs Frequency at 5.0 V
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6.7 Typical Characteristics (continued)
specified at TJ = –40°C to +150°C, VIN = 13.5 V, IOUT = 100 µA, COUT = 2.2 µF, 1 mΩ < COUT ESR < 2 Ω, CIN = 1 µF, and
VEN = 2 V (unless otherwise noted)
45
40
35
30
25
20
15
10
5
0.25
0.2
10
8
300
240
180
120
60
VIN
VOUT
VIN
VOUT
6
0.15
0.1
4
2
0.05
0
0
0
-2
-4
-6
-8
-10
-60
-0.05
-0.1
-0.15
-0.2
-120
-180
-240
-300
0
0
50 100 150 200 250 300 350 400 450 500
Time (ms)
0
500
1000
1500
Time (ms)
2000
2500
3000
VOUT = 5 V, VIN = 5.5 V to 6.5 V, trise = 1 µs, COUT = 10 µF
VOUT = 5 V, IOUT = 1 mA, VIN = 13.5 V to 40 V,
slew rate = 2.7 V/µs, VEN = 3.3 V, COUT = 10 µF
Figure 6-14. Line Transients at 5.5 V to 6.5 V
Figure 6-13. Line Transients at 13.5 V to 40 V
150
100
50
300
200
100
0
150
100
50
300
-40èC
25èC
150èC
IOUT
-40èC
25èC
150èC
IOUT
200
100
0
0
0
-50
-100
-150
-100
-200
-300
-50
-100
-150
-100
-200
-300
0
0.5
1
1.5
2
2.5
Time (ms)
3
3.5
4
4.5
5
0
20
40
60
80 100 120 140 160 180 200
Time (ms)
VOUT = 5 V, IOUT = 0 mA to 100 mA, slew rate = 1 A/µs,
VEN = 3.3 V, COUT = 10 µF
VOUT = 5 V, IOUT = 0 mA to 100 mA, slew rate = 1 A/µs,
VEN = 3.3 V, COUT = 10 µF
Figure 6-15. Load Transient, No Load to 100 mA
Figure 6-16. Load Transient, No Load to 100-mA Rising Edge
50
40
300
50
40
30
20
10
0
200
150
100
50
-40èC
25èC
150èC
IOUT
-40èC
25èC
150èC
IOUT
240
180
120
60
30
20
10
0
0
0
-50
-10
-20
-30
-40
-50
-60
-10
-20
-30
-40
-100
-150
-200
-250
-120
-180
-240
-300
0
40
80
120
Time (ms)
160
200
240
280
0
20
40
60
80 100 120 140 160 180 200
Time (ms)
VOUT = 5 V, IOUT = 45 mA to 105 mA, slew rate = 0.1 A/µs,
VEN = 3.3 V, COUT = 10 µF
VOUT = 5 V, IOUT = 45 mA to 105 mA, slew rate = 0.1 A/µs,
VEN = 3.3 V, COUT = 10 µF
Figure 6-17. Load Transient, 45 mA to 105 mA
Figure 6-18. Load Transient, 45-mA to 105-mA Rising Edge
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6.7 Typical Characteristics (continued)
specified at TJ = –40°C to +150°C, VIN = 13.5 V, IOUT = 100 µA, COUT = 2.2 µF, 1 mΩ < COUT ESR < 2 Ω, CIN = 1 µF, and
VEN = 2 V (unless otherwise noted)
150
100
50
300
200
100
0
150
100
50
300
200
100
0
-40èC
25èC
150èC
IOUT
-40èC
25èC
150èC
IOUT
0
0
-50
-100
-150
-100
-200
-300
-50
-100
-150
-100
-200
-300
0
0.25
0.5
0.75
1
Time (ms)
1.25
1.5
1.75
2
0
20
40
60
80 100 120 140 160 180 200
Time (ms)
VOUT = 5 V, IOUT = 0 mA to 150 mA, slew rate = 1 A/µs,
VEN = 3.3 V, COUT = 10 µF
VOUT = 5 V, IOUT = 0 mA to 150 mA, slew rate = 1 A/µs, VEN
3.3 V, COUT = 10 µF
=
Figure 6-19. Load Transient, No Load to 150 mA
Figure 6-20. Load Transient, No Load to 150-mA Rising Edge
228
227
226
225
224
223
222
221
220
40
-55èC
-40èC
0èC
85èC
150èC
25èC
125èC
35
30
25
20
15
10
219
Current Limit
218
-75
-45
-15
15
45
75
105
135
Temperature (èC)
5
10
15
20 25
Input Voltage (V)
30
35
40
VIN = VOUT + 1 V, VOUT = 90% × VOUT(NOM)
VOUT = 5 V
Figure 6-22. Quiescent Current (IQ) vs VIN
Figure 6-21. Output Current Limit vs Temperature
175
450
400
350
300
250
200
150
100
50
-55èC
-40èC
0èC
25èC
85èC
125èC
150èC
-55 èC
-40 èC
0 èC
25 èC
85 èC
125 èC
150 èC
150
125
100
75
50
25
0
0
0
5
10
15
20
25
Input Voltage (V)
30
35
40
0
25
50
75
Output Current (mA)
100
125
150
VOUT = 5 V
Figure 6-23. Quiescent Current (IQ) vs VIN
Figure 6-24. Ground Current (IGND) vs IOUT
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6.7 Typical Characteristics (continued)
specified at TJ = –40°C to +150°C, VIN = 13.5 V, IOUT = 100 µA, COUT = 2.2 µF, 1 mΩ < COUT ESR < 2 Ω, CIN = 1 µF, and
VEN = 2 V (unless otherwise noted)
281
280
279
278
277
276
275
274
273
272
271
26
25
24
23
22
21
-75
-50
-25
0
25
50
75
100 125 150
-75
-50
-25
0
25
50
75
100 125 150
Temperature (èC)
Ambient Temperature (èC)
IOUT = 100 mA
IOUT = 500 µA
Figure 6-25. Ground Current
Figure 6-26. Ground Current
1.38
1.36
1.34
1.32
1.3
2.8
Falling Threshold
Rising Threshold
Falling Threshold
Rising Threshold
2.75
2.7
2.65
2.6
1.28
1.26
1.24
1.22
1.2
2.55
2.5
2.45
2.4
-60 -40 -20
0
20 40 60 80 100 120 140 160
Temperature (èC)
-60 -40 -20
0
20 40 60 80 100 120 140 160
Temperature (èC)
Figure 6-27. EN Threshold vs Temperature
Figure 6-28. Undervoltage Lockout (UVLO) Threshold vs
Temperature
92
91
90
89
88
87
1.25
Falling Threshold
Rising Threshold
1.225
Falling Threshold
Rising Threshold
1.2
1.175
1.15
1.125
1.1
-60 -40 -20
0
20 40 60 80 100 120 140 160
Temperature (èC)
-60 -40 -20
0
20 40 60 80 100 120 140 160
Temperature (èC)
Figure 6-30. Sense Input Threshold vs Temperature
Figure 6-29. PG Threshold vs Temperature
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6.7 Typical Characteristics (continued)
specified at TJ = –40°C to +150°C, VIN = 13.5 V, IOUT = 100 µA, COUT = 2.2 µF, 1 mΩ < COUT ESR < 2 Ω, CIN = 1 µF, and
VEN = 2 V (unless otherwise noted)
1.05
1.04
1.03
1.02
1.01
1
6
5.5
5
600
550
500
450
400
350
300
250
200
150
100
50
Rising Threshold
Falling Threshold
VOUT
VPG
IInrush
4.5
4
3.5
3
2.5
2
1.5
1
0.99
0.5
0
0.98
0
-60 -40 -20
0
20 40 60 80 100 120 140 160
Temperature (èC)
0
50 100 150 200 250 300 350 400 450 500
Time (ms)
COUT = 10 µF
Figure 6-31. PGADJ Threshold vs Temperature
Figure 6-32. Startup Plot Inrush Current
20
15
10
5
400
300
200
100
0
20
15
10
5
200
Input Voltage
Output Voltage
Inrush Current
Input Voltage
Output Voltage
Output Current
150
100
50
0
0
0
-5
-100
-5
-50
0
100 200 300 400 500 600 700 800 900 1000
Time (ms)
0
1
2
3
4
5
Time (ms)
6
7
8
9
10
VIN = 13.5 V, COUT = 10 µF
COUT = 10 µF
Figure 6-34. Startup Plot
Figure 6-33. Startup Plot With EN
1.58
20
18
16
14
12
10
8
1.57
1.56
1.55
1.54
1.53
1.52
6
-60 -40 -20
0
20 40 60 80 100 120 140 160
Temperature èC
4
0.2
0.4
0.6
0.8
1
1.2
Injected current (mA)
1.4
1.6
1.8
VDELAY = 1 V
Figure 6-35. Delay Pin Current vs Temperature
Figure 6-36. Output Voltage vs Injected Current
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6.7 Typical Characteristics (continued)
specified at TJ = –40°C to +150°C, VIN = 13.5 V, IOUT = 100 µA, COUT = 2.2 µF, 1 mΩ < COUT ESR < 2 Ω, CIN = 1 µF, and
VEN = 2 V (unless otherwise noted)
10
5
2
1
0.5
OFF
0.2
0.1
0.05
Stable region
0.02
0.01
0.005
0.002
0.001
0.0005
ON
0.0002
0.0001
1
2
3
4 5 67810
20 30 50 70 100 200300 500
COUT (mF)
-50 -25
0
25
50
75 100 125 150 175 200
Temperature (èC)
Figure 6-38. Stability ESR vs COUT
Figure 6-37. Thermal Shutdown
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7 Detailed Description
7.1 Overview
The TPS7B85-Q1 is a low-dropout linear regulator (LDO) designed to connect to the battery in automotive
applications. The device has an input voltage range extending to 40 V, which allows the device to withstand
transients (such as load dumps) that are anticipated in automotive systems. With only a 18-µA quiescent current
at light loads, the device is an optimal solution for powering always-on components.
The device has a state-of-the-art transient response that allows the output to quickly react to changes in the load
or line (for example, during cold-crank conditions). Additionally, the device has a novel architecture that
minimizes output overshoot when recovering from dropout. During normal operation, the device has a tight DC
accuracy of ±0.75% over line, load, and temperature.
The TPS7B85-Q1 is equipped with power-good and integrated voltage monitoring. The power-good delay and
voltage threshold can be adjusted by external components. The integrated voltage detector can be used to
monitor the input voltage and alert downstream components (such as MCUs) when the battery voltage begins to
fall.
7.2 Functional Block Diagram
IN
OUT
Current
Limit
R1
Thermal
Shutdown
œ
+
UVLO
R2
EN
Bandgap
œ
+
VREF
VOUT
VSUBREG
PG
DELAY
œ
MUX
VREF
+
œ
VREF
Cap
Control
PGADJ
+
VOUT
SO
œ
SI
VREF
+
GND
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7.3 Feature Description
7.3.1 Enable (EN)
The enable pin for the device is an active-high pin. The output voltage is enabled when the voltage of the enable
pin is greater than the high-level input voltage of the EN pin and disabled with the enable pin voltage is less than
the low-level input voltage of the EN pin. If independent control of the output voltage is not needed, connect the
enable pin to the input of the device.
7.3.2 Power-Good (PG)
The PG signal provides an easy solution to meet demanding sequencing requirements because PG alerts when
the output nears its nominal value. PG can be used to signal other devices in a system when the output voltage
is near, at, or above the set output voltage (VOUT(nom)). Figure 7-1 shows a simplified schematic. The PG signal
has an internal pullup resistor to the nominal output voltage and is active high. The PG circuit sets the PG pin
into a high-impedance state to indicate that the power is good.
OUT
-
+
PG
+
VREF
œ
Figure 7-1. Simplified Power-Good Schematic
7.3.2.1 Adjustable Power-Good (PGADJ)
One unique feature of this LDO, as shown in Figure 7-2, is the ability to adjust the power-good threshold through
the use of a resistor divider. The adjustable power-good threshold allows the PG threshold to be set to the
desired level to further assist in transient detection or sequencing requirements. If this feature is not desired,
then tie the PGADJ pin to GND and the default PG threshold is used. For more information on how to calculate
the power-good threshold, see the Setting the Adjustable Power-Good Delay section.
OUT
-
R1
PGADJ
PG
+
+
R2
VREF
œ
Figure 7-2. Typical Use of Power-Good Adjust Pin
7.3.3 Adjustable Power-Good Delay Timer (DELAY)
The power-good delay period is a function of the external capacitor on the DELAY pin. The adjustable delay
configures the amount of time required before the PG pin becomes high. This delay is configured by connecting
an external capacitor from this pin to GND. Figure 7-3 illustrates the typical timing diagram for the power-good
delay pin. If the DELAY pin is left floating, the power-good delay is t(DLY_FIX). For more information on how to
program the PG delay, see the Setting the Adjustable Power-Good Delay section.
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VIN
V
(UVLO)
t < t(DEGLITCH)
V(PG_HYST)
V(PG_TH) rising
V(PG_ADJ) rising
V(PG_TH) falling
V(PG_ADJ) falling
VOUT
V
(DLY_TH)
DELAY
t(DEGLITCH)
t(DEGLITCH)
t
t
(DLY)
(DLY)
PG
Power Up
V(PG_TH) falling = V(PG_TH) rising – V(PG_HYST).
Input Voltage Drop
Undervoltage
Power Down
.
Figure 7-3. Typical Power-Good Timing Diagram
7.3.4 Sense Comparator
The sense comparator compares the input signal with an internal voltage reference of 1.223 V for a rising
threshold and 1.123 V for a falling threshold. Using an external voltage divider makes this comparator very
flexible in the application.
The device can supervise the input voltage either before or after the protection diode and provides additional
information to the microprocessor (such as low-voltage warnings).
7.3.5 Undervoltage Lockout
The device has an independent undervoltage lockout (UVLO) circuit that monitors the input voltage, allowing a
controlled and consistent turn on and off of the output voltage. To prevent the device from turning off if the input
drops during turn on, the UVLO has hysteresis as specified in the Electrical Characteristics table.
7.3.6 Thermal Shutdown
The device contains a thermal shutdown protection circuit to disable the device when the junction temperature
(TJ) of the pass transistor rises to TSD(shutdown) (typical). Thermal shutdown hysteresis assures that the device
resets (turns on) when the temperature falls to TSD(reset) (typical).
The thermal time-constant of the semiconductor die is fairly short, thus the device may cycle on and off when
thermal shutdown is reached until power dissipation is reduced. Power dissipation during startup can be high
from large V IN – V OUT voltage drops across the device or from high inrush currents charging large output
capacitors. Under some conditions, the thermal shutdown protection disables the device before startup
completes.
For reliable operation, limit the junction temperature to the maximum listed in the Recommended Operating
Conditions table. Operation above this maximum temperature causes the device to exceed its operational
specifications. Although the internal protection circuitry of the device is designed to protect against thermal
overall conditions, this circuitry is not intended to replace proper heat sinking. Continuously running the device
into thermal shutdown or above the maximum recommended junction temperature reduces long-term reliability.
7.3.7 Current Limit
The device has an internal current limit circuit that protects the regulator during transient high-load current faults
or shorting events. The current limit is a brickwall scheme. In a high-load current fault, the brickwall scheme
limits the output current to the current limit (ICL). ICL is listed in the Electrical Characteristics table.
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The output voltage is not regulated when the device is in current limit. When a current limit event occurs, the
device begins to heat up because of the increase in power dissipation. When the device is in brickwall current
limit, the pass transistor dissipates power [(VIN – VOUT) × ICL]. If thermal shutdown is triggered, the device turns
off. After the device cools down, the internal thermal shutdown circuit turns the device back on. If the output
current fault condition continues, the device cycles between current limit and thermal shutdown. For more
information on current limits, see the Know Your Limits application report.
Figure 7-4 shows a diagram of the current limit.
VOUT
Brickwall
VOUT(NOM)
0 V
IOUT
IRATED
0 mA
ICL
Figure 7-4. Current Limit
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7.4 Device Functional Modes
7.4.1 Device Functional Mode Comparison
The Device Functional Mode Comparison table shows the conditions that lead to the different modes of
operation. See the Electrical Characteristics table for parameter values.
Table 7-1. Device Functional Mode Comparison
PARAMETER
OPERATING MODE
VIN
VEN
IOUT
TJ
Normal operation
Dropout operation
VIN > VOUT(nom) + VDO and VIN > VIN(min)
VIN(min) < VIN < VOUT(nom) + VDO
VEN > VEN(HI)
VEN > VEN(HI)
IOUT < IOUT(max)
IOUT < IOUT(max)
TJ < TSD(shutdown)
TJ < TSD(shutdown)
Disabled
(any true condition
disables the device)
VIN < VUVLO
VEN < VEN(LOW)
Not applicable
TJ > TSD(shutdown)
7.4.2 Normal Operation
The device regulates to the nominal output voltage when the following conditions are met:
•
•
•
The input voltage is greater than the nominal output voltage plus the dropout voltage (VOUT(nom) + VDO)
The output current is less than the current limit (IOUT < ICL)
The device junction temperature is less than the thermal shutdown temperature (TJ < TSD
)
•
The enable voltage has previously exceeded the enable rising threshold voltage and has not yet decreased
to less than the enable falling threshold
7.4.3 Dropout Operation
If the input voltage is lower than the nominal output voltage plus the specified dropout voltage, but all other
conditions are met for normal operation, the device operates in dropout mode. In this mode, the output voltage
tracks the input voltage. During this mode, the transient performance of the device becomes significantly
degraded because the pass transistor is in the ohmic or triode region, and acts as a switch. Line or load
transients in dropout can result in large output-voltage deviations.
When the device is in a steady dropout state (defined as when the device is in dropout, VIN < VOUT(NOM) + VDO
,
directly after being in a normal regulation state, but not during startup), the pass transistor is driven into the
ohmic or triode region. When the input voltage returns to a value greater than or equal to the nominal output
voltage plus the dropout voltage (VOUT(NOM) + VDO), the output voltage can overshoot for a short period of time
while the device pulls the pass transistor back into the linear region.
7.4.4 Disabled
The output of the device can be shutdown by forcing the voltage of the enable pin to less than the maximum EN
pin low-level input voltage (see the Electrical Characteristics table). When disabled, the pass transistor is turned
off, internal circuits are shutdown, and the output voltage is actively discharged to ground by an internal
discharge circuit from the output to ground.
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8 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes. Customers should validate and test their design
implementation to confirm system functionality.
8.1 Application Information
8.1.1 Input and Output Capacitor Selection
The TPS7B85-Q1 requires an output capacitor of 2.2 µF or larger (1 µF or larger capacitance) for stability and an
equivalent series resistance (ESR) between 0.001 Ω and 2 Ω. For the best transient performance, use X5R- and
X7R-type ceramic capacitors because these capacitors have minimal variation in value and ESR over
temperature. When choosing a capacitor for a specific application, be mindful of the DC bias characteristics for
the capacitor. Higher output voltages cause a significant derating of the capacitor. For best performance, the
maximum recommended output capacitance is 220 µF.
Although an input capacitor is not required for stability, good analog design practice is to connect a capacitor
from IN to GND. Some input supplies have a high impedance, thus placing the input capacitor on the input
supply helps reduce the input impedance. This capacitor counteracts reactive input sources and improves
transient response, input ripple, and PSRR. If the input supply has a high impedance over a large range of
frequencies, several input capacitors can be used in parallel to lower the impedance over frequency. Use a
higher-value capacitor if large, fast, rise-time load transients are anticipated, or if the device is located several
inches from the input power source.
8.1.2 Dropout Voltage
Dropout voltage (VDO) is defined as the input voltage minus the output voltage (VIN – VOUT) at the rated output
current (IRATED), where the pass transistor is fully on. IRATED is the maximum IOUT listed in the Recommended
Operating Conditions table. The pass transistor is in the ohmic or triode region of operation, and acts as a
switch. The dropout voltage indirectly specifies a minimum input voltage greater than the nominal programmed
output voltage at which the output voltage is expected to stay in regulation. If the input voltage falls to less than
the nominal output regulation, then the output voltage falls as well.
For a CMOS regulator, the dropout voltage is determined by the drain-source on-state resistance (RDS(ON)) of the
pass transistor. Therefore, if the linear regulator operates at less than the rated current, the dropout voltage for
that current scales accordingly. The following equation calculates the RDS(ON) of the device.
VDO
RDS(ON)
=
IRATED
(1)
8.1.3 Reverse Current
Excessive reverse current can damage this device. Reverse current flows through the intrinsic body diode of the
pass transistor instead of the normal conducting channel. At high magnitudes, this current flow degrades the
long-term reliability of the device.
Conditions where reverse current can occur are outlined in this section, all of which can exceed the absolute
maximum rating of VOUT ≤ VIN + 0.3 V.
•
•
•
If the device has a large COUT and the input supply collapses with little or no load current
The output is biased when the input supply is not established
The output is biased above the input supply
If reverse current flow is expected in the application, external protection is recommended to protect the device.
Reverse current is not limited in the device, so external limiting is required if extended reverse voltage operation
is anticipated.
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8.1.4 Power Dissipation (PD)
Circuit reliability requires consideration of the device power dissipation, location of the circuit on the printed
circuit board (PCB), and correct sizing of the thermal plane. The PCB area around the regulator must have few
or no other heat-generating devices that cause added thermal stress.
To first-order approximation, power dissipation in the regulator depends on the input-to-output voltage difference
and load conditions. The following equation calculates power dissipation (PD).
PD = (VIN – VOUT) × IOUT
(2)
Note
Power dissipation can be minimized, and therefore greater efficiency can be achieved, by correct
selection of the system voltage rails. For the lowest power dissipation use the minimum input voltage
required for correct output regulation.
For devices with a thermal pad, the primary heat conduction path for the device package is through the thermal
pad to the PCB. Solder the thermal pad to a copper pad area under the device. This pad area must contain an
array of plated vias that conduct heat to additional copper planes for increased heat dissipation.
The maximum power dissipation determines the maximum allowable ambient temperature (TA) for the device.
According to the following equation, power dissipation and junction temperature are most often related by the
junction-to-ambient thermal resistance (RθJA) of the combined PCB and device package and the temperature of
the ambient air (TA).
TJ = TA + (RθJA × PD)
(3)
Thermal resistance (R θJA) is highly dependent on the heat-spreading capability built into the particular PCB
design, and therefore varies according to the total copper area, copper weight, and location of the planes. The
junction-to-ambient thermal resistance listed in the Thermal Information table is determined by the JEDEC
standard PCB and copper-spreading area, and is used as a relative measure of package thermal performance.
8.1.4.1 Thermal Performance Versus Copper Area
The most used thermal resistance parameter, RθJA, is highly dependent on the heat-spreading capability built
into the particular PCB design, and therefore varies according to the total copper area, copper weight, and
location of the planes. The R θJA recorded in the Thermal Information table in the Specifications section is
determined by the JEDEC standard (see Figure 8-1), PCB, and copper-spreading area, and is only used as a
relative measure of package thermal performance. For a well-designed thermal layout, RθJA is actually the sum
of the package junction-to-case (bottom) thermal resistance (RθJCbot) plus the thermal resistance contribution by
the PCB copper.
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Mold
Compound
Die
Wire
Die
Attach
2oz
Signal
Trace
Lead
Frame
Internal Signal
or power plane
1oz copper
Thermal
Pad or Tab
of the LDO
Internal
GND plane
1oz copper
Bottom
Relief
2oz copper
Thermal
Vias
Figure 8-1. JEDEC Standard 2s2p PCB
Figure 8-2 and Figure 8-3 depict the functions of RθJA and ψJB versus copper area and thickness. These plots
are generated with a 101.6-mm x 101.6-mm x 1.6-mm PCB of two and four layers. For the four-layer board, the
inner planes use a 1-oz copper thickness. Outer layers are simulated with both a 1-oz and 2-oz copper
thickness. A 4 x 4 array of thermal vias of 300-µm drill diameter and 25-µm Cu plating is located beneath the
thermal pad of the device. The thermal vias connect the top layer, the bottom layer and, in the case of the 4-layer
board, the first inner GND plane. Each of the layers has a copper plane of equal area.
115
105
95
85
75
65
55
45
35
25
30
28
26
24
22
20
18
16
14
12
10
4 Layer PCB, 1 oz copper
4 Layer PCB, 2 oz copper
2 Layer PCB, 1 oz copper
2 Layer PCB, 2 oz copper
4 Layer PCB, 1 oz copper
4 Layer PCB, 2 oz copper
2 Layer PCB, 1 oz copper
2 Layer PCB, 2 oz copper
0
10
20
30
40
50
60
70
80
90 100
0
10
20
30
40
50
60
70
80
90 100
Cu Area Per Layer (cm2)
Cu Area Per Layer (cm2)
Figure 8-2. RθJA vs Copper Area 2s2p DRC
Package
Figure 8-3. R ψJB vs Copper Area 2s2p DRC
Package
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8.1.5 Estimating Junction Temperature
The JEDEC standard now recommends the use of psi (Ψ) thermal metrics to estimate the junction temperatures
of the linear regulator when in-circuit on a typical PCB board application. These metrics are not thermal
resistance parameters and instead offer a practical and relative way to estimate junction temperature. These psi
metrics are determined to be significantly independent of the copper area available for heat-spreading. The
Thermal Information table lists the primary thermal metrics, which are the junction-to-top characterization
parameter (ψJT) and junction-to-board characterization parameter (ψJB). These parameters provide two methods
for calculating the junction temperature (TJ), as described in the following equations. Use the junction-to-top
characterization parameter (ψJT) with the temperature at the center-top of device package (TT) to calculate the
junction temperature. Use the junction-to-board characterization parameter (ψ JB) with the PCB surface
temperature 1 mm from the device package (TB) to calculate the junction temperature.
TJ = TT + ψJT × PD
(4)
where:
•
•
PD is the dissipated power
TT is the temperature at the center-top of the device package
TJ = TB + ψJB × PD
(5)
where
•
TB is the PCB surface temperature measured 1 mm from the device package and centered on the package
edge
For detailed information on the thermal metrics and how to use them, see the Semiconductor and IC Package
Thermal Metrics application report.
8.1.6 SI Pin
8.1.6.1 Calculating the Sense Input (SI) Pin Threshold
To use the SI pin, connect this pin to the rail being monitored through a resistor divider. This input can be
configured as an undervoltage supervisor that can monitor voltage rails greater than 1.2 V or used as an
overvoltage supervisor with an inverted output. Table 8-1 lists typical 1% resistor values for undervoltage
monitoring where the trip point is a 5% threshold. The resistor values can be scaled to decrease the amount of
current flowing through the resistor divider, but increasing the resistor values also decreases the accuracy of the
resistor divider. General practice is for the current flowing through the resistor divider to be 100 times greater
than the current going into the SI pin. This practice ensures the highest possible accuracy. Equation 6 can be
used to calculate the resistors required in the resistor divider for any desired falling threshold. Figure 8-4 depicts
the typical timing for this comparator and Figure 8-5 illustrates a block diagram for the adjustable operation.
R1
≈
’
Vmon(falling) = VSI(LOW)x 1+
∆
÷
◊
R2
«
(6)
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Table 8-1. SI Resistor Divider Values
5% THRESHOLD
INPUT VOLTAGE (V)
R1 (kΩ)
18.2
32.4
41.2
49.9
59
R2 (kΩ)
10
THRESHOLD VOLTAGE (V)
3.3
5
3.13
4.71
5.68
6.65
7.66
8.49
9.49
10.06
11.44
12.77
10
6
10
7
10
8
10
9
66.5
75.5
80.6
93.1
105
10
10
11
12
13.5
10
10
10
10
VSENSE_IN
VSI(HIGH)
VSI(LOW)
Sense Thresholds
SO
Figure 8-4. SI Timing Diagram
VMON
VOUT
SENSEIN
SO
œ
VREF
+
GND
Figure 8-5. SI Basic Block Diagram
8.1.6.2 Different Uses for the Sense Input Pin
The sense input pin incorporates a comparator with hysteresis into the LDO. The SI pin can help replace a
supervisor in the system by connecting the SI pin to rails that need to be monitored. The three most common
uses for this supervisor are described in the Monitoring Input Voltage, Creating OV and UV Power-Good, and
Monitoring a Separate Supply Voltage sections.
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8.1.6.2.1 Monitoring Input Voltage
Monitoring the input voltage of the LDO, as shown in Figure 8-6, is the most common way that the SI pin is used.
The device has a built-in precision comparator that allows the device to compare a divided-down version of the
input to the internal reference of the LDO. When the voltage on the sense pin is below VSI(LOW), the output of the
SO pin is low. However, when VSI crosses VSI(HIGH) the voltage on the SO pin gets pulled up to VOUT through a
pullup resistor, RSO. This pin also has built-in hysteresis to keep the pin from toggling between the two states
from small changes on the SENSE voltage. Figure 8-7 shows a typical timing diagram for the SENSE pin.
TPS7B85-Q1
IN
OUT
PG
EN
I/O
I/O
CIN
COUT
SENSE_IN
DELAY
PGADJ
SENSE_OUT
GND
Figure 8-6. Monitoring the Device Input Voltage
VSENSE_IN
VSI(HIGH)
VSI(LOW)
Sense Thresholds
SO
Figure 8-7. SENSE Pin Timing Diagram
8.1.6.2.2 Creating OV and UV Power-Good
Another feature that is often desired is the ability to monitor the output voltage for overvoltage (OV) or
undervoltage (UV) events. Because the integrated power-good pin only detects undervoltage events, a separate
solution must be implemented to monitor for overvoltage issues. This monitoring can be done by using the
integrated SI pin and connecting this pin to the output through a resistor divider. Then place the rising threshold
of the SI pin where the output voltage is going to be flagged as overvoltage. Equation 7 depicts how to calculate
the resistor divider for this application based on the desired overvoltage threshold. If this method is used for
creating an overvoltage detection, the output of the overvoltage signal has inverted logic. Figure 8-8 shows the
typical configuration for using the device as an overvotlage monitor.
R1
≈
’
Vmon(rising) = VSI(HIGH)x 1+
∆
÷
◊
R2
«
(7)
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TPS7B85-Q1
IN
OUT
EN
PG
PGADJ
I/O
I/O
CIN
COUT
SENSE_IN
DELAY
SENSE_OUT
GND
Figure 8-8. Creating an Overvoltage Detector on the Output
8.1.6.2.3 Monitoring a Separate Supply Voltage
One of the final applications for the SI pin is monitoring a separate supply. This method can be implemented as
either an overvoltage detection or undervoltage detection for the externally monitored supply. Equation 6 and
Equation 7 can be used to calculate the resistor dividers required to implement the supervision of the separate
power supply. Figure 8-9 shows a block diagram for this monitoring application.
IN
OUT
Supply2
GND
TPS7B85-Q1
IN
OUT
PG
EN
I/O
I/O
CIN
COUT
SENSE_IN
DELAY
PGADJ
SENSE_OUT
GND
Figure 8-9. Monitoring a Separate Power Supply
8.1.7 Pulling Up the SO and PG Pins to a Different Voltage
Because the sense out (SO) and power-good (PG) pins are pulled up internally to the output rail, they cannot be
pulled up to any voltage or wire AND'd like a typical open-drain PG output can be. If these signals must be pulled
up to another logic level then an external circuit can be implemented using a PMOS transistor and a pullup
resistor. Implementing the circuit shown in Figure 8-10 allows the outputs to be pulled up to any logic rail. This
implementation also allows the outputs to be AND'd together like the traditional power-good pins.
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SENSE_OUT
Figure 8-10. Additional Components for the SO and PG Pins to be Pulled Up to Another Rail
8.1.8 Power-Good
8.1.8.1 Setting the Adjustable Power-Good Threshold
The power-good threshold is also adjustable from 1 V to 18 V with an external resistor divider between PGADJ
and OUT. Use Equation 8 to calculate this threshold:
≈
∆
«
’
÷
◊
R1 + R2
R2
V
= V
x
(PG _ ADJ)falling
(PGADJ_ TH)falling
≈
∆
«
’
÷
◊
R1 + R2
R2
»
ÿ
x
V
= V(PGADJ_ TH)falling + VPGADJ(HYST)
(PG _ ADJ)rising
⁄
(8)
where
•
•
V(PG_ADJ) rising, V(PG_ADJ) falling is the adjustable power-good threshold
V(PGADJ_TH) falling is the internal comparator reference voltage of the PGADJ pin
By setting the power-good threshold V(PG_ADJ) rising, when VOUT exceeds this threshold, the PG output turns high
after the power-good delay period has expired. When VOUT falls below V(PG_ADJ) falling, the PG output turns low
after a short deglitch time. Figure 8-11 shows a diagram of the PG threshold.
OUT
-
R1
PGADJ
PG
+
+
R2
VREF
œ
Figure 8-11. Adjustable Power-Good Threshold
8.1.8.2 Setting the Adjustable Power-Good Delay
The power-good delay time can be set in two ways: either by floating the delay pin or by connecting a capacitor
from this pin to GND. When the DELAY pin is floating, the time defaults to t(DLY_FIX). The delay time is set by
Equation 9 if a capacitor is connected between the DELAY pin and GND.
≈
’
VDLY(TH)
t = t(DLY _FIX) + CDELAY
∆
∆
«
÷
÷
◊
IDLY(CHARGE)
(9)
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8.2 Typical Application
Figure 8-12 shows a typical application circuit for the TPS7B85-Q1. Use different values of external components,
depending on the end application. An application may require a larger output capacitor during fast load steps in
order to prevent a reset from occurring. TI recommends a low-ESR ceramic capacitor with a dielectric of type
X5R or X7R.
TPS7B85-Q1
IN
OUT
PG
EN
I/O
I/O
CIN
COUT
SENSE_IN
DELAY
PGADJ
SENSE_OUT
GND
Figure 8-12. Typical Application Schematic for the TPS7B85-Q1
8.2.1 Design Requirements
For this design example, use the parameters listed in Table 8-2 as the input parameters.
Table 8-2. Design Parameters
DESIGN PARAMETER
Input voltage range
Output voltage
EXAMPLE VALUE
6 V to 40 V
5 V
Output current
100 mA
10 µF
Output capacitor
Power-good delay capacitor
Sense input trip threshold
100 nF
5.5 V
8.2.2 Detailed Design Procedure
8.2.2.1 Input Capacitor
The device requires an input decoupling capacitor, the value of which depends on the application. The typical
recommended value for the decoupling capacitor is 1 µF. The voltage rating must be greater than the maximum
input voltage.
8.2.2.2 Output Capacitor
The device requires an output capacitor to stabilize the output voltage. The capacitor value must be between
2.2 µF and 200 µF and the ESR range must be between 1 mΩ and 2 Ω. For this design a low ESR, 10-µF
ceramic capacitor was used to improve transient performance.
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8.2.3 Application Curves
20
100
75
50
25
0
100
90
80
70
60
50
40
30
20
10
0
Input Voltage
Enable Voltage
Output Current
IOUT
15
10
5
0
IOUT = 150 mA
IOUT = 100 mA
IOUT = 50 mA
IOUT = 10 mA
IOUT = 1mA
-5
-25
0
500 1000 1500 2000 2500 3000 3500 4000 4500 5000
Time (ms)
10
100
1k
10k 100k
Frequency (Hz)
1M
10M
Figure 8-13. Power-Up Waveform
Figure 8-14. PSRR
50
300
240
180
120
60
-40èC
25èC
150èC
IOUT
40
30
20
10
0
0
-10
-20
-30
-40
-50
-60
-120
-180
-240
-300
0
40
80
120
160
200
240
280
Time (ms)
Figure 8-15. Transient Response
9 Power Supply Recommendations
This device is designed for operation from an input voltage supply with a range between 3 V and 40 V. This input
supply must be well regulated. If the input supply is located more than a few inches from the TPS7B85-Q1, add
an electrolytic capacitor and a ceramic bypass capacitor at the input.
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10 Layout
10.1 Layout Guidelines
For best overall performance, place all circuit components on the same side of the circuit board and as near as
practical to the respective LDO pin connections. Place ground return connections to the input and output
capacitor, and to the LDO ground pin as close as possible to each other, connected by a wide, component-side,
copper surface. The use of vias and long traces to the input and output capacitors is strongly discouraged and
negatively affects system performance. TI also recommends a ground reference plane either embedded in the
PCB itself or located on the bottom side of the PCB opposite the components. This reference plane serves to
assure accuracy of the output voltage, shield noise, and behaves similarly to a thermal plane to spread (or sink)
heat from the LDO device when connected to the thermal pad. In most applications, this ground plane is
necessary to meet thermal requirements.
10.1.1 Package Mounting
Solder pad footprint recommendations for the TPS7B85-Q1 are available at the end of this document and at
www.ti.com.
10.1.2 Board Layout Recommendations to Improve PSRR and Noise Performance
As depicted in Figure 10-1, place the input and output capacitors close to the device for the layout of the
TPS7B85-Q1. In order to enhance the thermal performance, place as many vias as possible around the device.
These vias improve the heat transfer between the different GND planes in the PCB.
To improve ac performance such as PSRR, output noise, and transient response, TI recommends a board
design with separate ground planes for IN and OUT, with each ground plane connected only at the GND pin of
the device. In addition, the ground connection for the output capacitor must connect directly to the GND pin of
the device.
Minimize equivalent series inductance (ESL) and ESR in order to maximize performance and ensure stability.
Place each capacitor as close as possible to the device and on the same side of the PCB as the regulator itself.
Do not place any of the capacitors on the opposite side of the PCB from where the regulator is installed. TI
strongly discourages the use of vias and long traces to connect the capacitors because these can negatively
impact system performance and may even cause instability.
If possible, and to ensure the maximum performance specified in this document, use the same layout pattern
used for the TPS7B85-Q1 evaluation board, available at www.ti.com.
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10.2 Layout Example
IN
OUT
PGADJ
SO
1
2
3
4
5
10
9
SI
8
EN
PG
GND
7
DELAY
6
Denotes a via
Figure 10-1. VSON (DRC) Layout
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Device Nomenclature
Table 11-1. Device Nomenclature (1)
PRODUCT
VOUT
xx is the nominal output voltage (for example, 33 = 3.3 V; 50 = 5.0 V).
Q indicates that this device is a grade-1 device in accordance with the AEC-Q100 standard.
W indicates the package has wettable flanks.
TPS7B85xxQWyyyRQ1
yyy is the package designator.
R is the package quantity. R is for reel (3000 pieces).
Q1 indicates that this device is an automotive grade (AEC-Q100) device.
(1) For the most current package and ordering information see the Package Option Addendum at the end of this document, or visit the
device product folder on www.ti.com.
11.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
11.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
11.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
11.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
11.6 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OUTLINE
DRC0010U
VSON - 1 mm max height
SCALE 4.000
PLASTIC SMALL OUTLINE - NO LEAD
3.1
2.9
B
A
PIN 1 INDEX AREA
3.1
2.9
0.1 MIN
(0.13)
S
C
A
S
E
C
30.0
OI
0
SECTION A-A
TYPICAL
1.0
0.8
C
SEATING PLANE
0.08 C
0.05
0.00
1.65 0.1
2X (0.5)
4X (0.25)
(0.2) TYP
EXPOSED
THERMAL PAD
5
6
(0.16) TYP
A
A
2X
2
11
SYMM
2.4 0.1
10
1
8X 0.5
0.3
0.2
10X
SYMM
10X
PIN 1 ID
(OPTIONAL)
0.1
C A B
C
0.05
0.5
0.3
4225163/A 07/2019
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.
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EXAMPLE BOARD LAYOUT
DRC0010U
VSON - 1 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
(1.65)
(0.5)
10X (0.6)
1
10
10X (0.25)
11
(2.4)
(3.4)
SYMM
(0.95)
8X (0.5)
6
5
(R0.05) TYP
( 0.2) VIA
TYP
(0.25)
(0.575)
SYMM
(2.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:20X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
EXPOSED METAL
EXPOSED METAL
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4225163/A 07/2019
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
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EXAMPLE STENCIL DESIGN
DRC0010U
VSON - 1 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
2X (1.5)
(0.5)
SYMM
EXPOSED METAL
TYP
11
10X (0.6)
1
10
(1.53)
10X (0.25)
2X
(1.06)
SYMM
(0.63)
8X (0.5)
6
5
(R0.05) TYP
4X (0.34)
4X (0.25)
(2.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 11:
80% PRINTED SOLDER COVERAGE BY AREA
SCALE:25X
4225163/A 07/2019
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
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PACKAGE OPTION ADDENDUM
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25-Jan-2021
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPS7B8533QWDRCRQ1
TPS7B8550QWDRCRQ1
ACTIVE
ACTIVE
VSON
VSON
DRC
DRC
10
10
3000 RoHS & Green
3000 RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 150
-40 to 150
7B8533
7B8550
NIPDAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
25-Jan-2021
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS7B8533QWDRCRQ1 VSON
TPS7B8550QWDRCRQ1 VSON
DRC
DRC
10
10
3000
3000
330.0
330.0
12.4
12.4
3.3
3.3
3.3
3.3
1.1
1.1
8.0
8.0
12.0
12.0
Q2
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TPS7B8533QWDRCRQ1
TPS7B8550QWDRCRQ1
VSON
VSON
DRC
DRC
10
10
3000
3000
367.0
367.0
367.0
367.0
35.0
35.0
Pack Materials-Page 2
GENERIC PACKAGE VIEW
DRC 10
3 x 3, 0.5 mm pitch
VSON - 1 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4226193/A
www.ti.com
PACKAGE OUTLINE
DRC0010U
VSON - 1 mm max height
SCALE 4.000
PLASTIC SMALL OUTLINE - NO LEAD
3.1
2.9
B
A
PIN 1 INDEX AREA
3.1
2.9
0.1 MIN
(0.13)
S
C
A
L
E
3
0
.
A
SECTION A-A
TYPICAL
1.0
0.8
C
SEATING PLANE
0.08 C
0.05
0.00
1.65 0.1
2X (0.5)
(0.2) TYP
EXPOSED
THERMAL PAD
4X (0.25)
5
6
(0.16) TYP
A
A
2X
2
11
SYMM
2.4 0.1
10
1
8X 0.5
0.3
0.2
10X
SYMM
10X
PIN 1 ID
0.1
C A B
C
(OPTIONAL)
0.05
0.5
0.3
4225163/A 07/2019
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
DRC0010U
VSON - 1 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
(1.65)
(0.5)
10X (0.6)
1
10
10X (0.25)
11
(2.4)
(3.4)
SYMM
(0.95)
8X (0.5)
6
5
(R0.05) TYP
(
0.2) VIA
TYP
(0.25)
(0.575)
SYMM
(2.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:20X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
EXPOSED METAL
EXPOSED METAL
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
SOLDER MASK
DEFINED
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4225163/A 07/2019
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
DRC0010U
VSON - 1 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
2X (1.5)
(0.5)
SYMM
EXPOSED METAL
TYP
11
10X (0.6)
1
10
(1.53)
10X (0.25)
2X
(1.06)
SYMM
(0.63)
8X (0.5)
6
5
(R0.05) TYP
4X (0.34)
4X (0.25)
(2.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 11:
80% PRINTED SOLDER COVERAGE BY AREA
SCALE:25X
4225163/A 07/2019
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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