TPS7H4010-SEP [TI]
TPS7H4010-SEP Radiation Hardened 3.5-V to 32-V, 6-A Synchronous Step-Down Voltage Converter in Space Enhanced Plastic;型号: | TPS7H4010-SEP |
厂家: | TEXAS INSTRUMENTS |
描述: | TPS7H4010-SEP Radiation Hardened 3.5-V to 32-V, 6-A Synchronous Step-Down Voltage Converter in Space Enhanced Plastic |
文件: | 总49页 (文件大小:2803K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
TPS7H4010-SEP
SNVSBL0 – NOVEMBER 2020
TPS7H4010-SEP Radiation Hardened 3.5-V to 32-V, 6-A Synchronous
Step-Down Voltage Converter in Space Enhanced Plastic
1 Features
2 Applications
•
Radiation Hardened
•
Space satellite point of load supply for FPGAs,
microcontrollers, data converters and ASICs
Communications payload
Command and data handling
Optical imaging payload
Radar imaging payload
Laser communications payload
Navigations payload
Scientific exploration payload
– SEL, SEB, and SEGR immune up to
LET = 43 MeV-cm2/mg
– SET and SEFI characterized up to
LET = 43 MeV-cm2/mg
– TID assured for every wafer lot up to
20 krad(Si)
– TID characterized up to 30 krad(Si)
Space Enhanced Plastic
•
•
•
•
•
•
•
•
– Controlled baseline
3 Description
– Au bondwire and NiPdAu lead finish
– Enhanced mold compound for low outgassing
– One fabrication, assembly and test site
– Extended product life cycle
– Extended product change notification
– Product traceability
Wide voltage conversion range:
– tON-MIN = 60 ns (typical)
– tOFF-MIN = 70 ns (typical)
Low MOSFET ON-resistance:
– RDS_ON_HS = 53 mΩ (typical)
– RDS_ON_LS = 31 mΩ (typical)
Adjustable frequency range: 350 kHz to 2.2 MHz
Synchronizable to external clock
Internal compensation
The TPS7H4010-SEP is an easy-to-use synchronous
step-down DC/DC converter capable of driving up to 6
A of load current from a supply voltage ranging from
3.5 V to 32 V. The TPS7H4010-SEP provides
exceptional efficiency and output accuracy in a very
small solution size. Peak current-mode control is
employed. Additional features such as adjustable
switching frequency, synchronization to an external
clock, FPWM option, power-good flag, precision
enable, adjustable soft start, and tracking provide both
flexible and easy-to-use solutions for a wide range of
applications. Automatic frequency foldback at light
load and optional external bias improve efficiency
over the entire load range. The device requires few
external components and has a pinout designed for
simple PCB layout with optimal EMI and thermal
performance. Protection features include thermal
shutdown, input undervoltage lockout, cycle-by-cycle
current limiting, and hiccup short-circuit protection.
•
•
•
•
•
•
•
•
•
•
•
Power-good flag
Precision enable to program system UVLO
Fixed or adjustable soft-start time
Cycle-by-cycle current limiting
Short-circuit protection with hiccup mode
Thermal shutdown protection
Device Information
PART NUMBER(1)
GRADE
PACKAGE
QFN (30)
6.00 mm × 4.00 mm
Mass = 57.2 mg(2)
20 krad(Si)
RLAT
TPS7H4010MRNPTSEP
L
VIN
VOUT
SW
PVIN
EN
CBOOT
COUT
CIN
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
CBOOT
BIAS
RT
PGND
PGOOD
(2) Mass is accurate to ±10%.
SS/TRK
RFBT
SYNC/
MODE
FB
RFBB
VCC
CVCC
AGND
Simplified Schematic
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS7H4010-SEP
SNVSBL0 – NOVEMBER 2020
www.ti.com
Table of Contents
1 Features............................................................................1
2 Applications.....................................................................1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 5
6.1 Absolute Maximum Ratings ....................................... 5
6.2 ESD Ratings .............................................................. 5
6.3 Recommended Operating Conditions ........................5
6.4 Thermal Information ...................................................6
6.5 Electrical Characteristics ............................................6
6.6 Timing Characteristics ................................................8
6.7 Switching Characteristics ...........................................8
6.8 Typical Characteristics................................................9
7 Detailed Description......................................................11
7.1 Overview................................................................... 11
7.2 Functional Block Diagram......................................... 11
7.3 Feature Description...................................................12
7.4 Device Functional Modes..........................................24
8 Application and Implementation..................................26
8.1 Application Information............................................. 26
8.2 Typical Application.................................................... 26
9 Power Supply Recommendations................................37
10 Layout...........................................................................37
10.1 Layout Guidelines................................................... 37
10.2 Layout Example...................................................... 40
11 Device and Documentation Support..........................41
11.1 Device Support........................................................41
11.2 Related Documentation...........................................41
11.3 Receiving Notification of Documentation Updates..41
11.4 Support Resources................................................. 41
11.5 Trademarks............................................................. 41
11.6 Electrostatic Discharge Caution..............................41
11.7 Glossary..................................................................41
12 Mechanical, Packaging, and Orderable
Information.................................................................... 41
4 Revision History
NOTE: Page numbers for previous revisions may
differ from page numbers in the current version.
DATE
REVISION
NOTES
November 2020
*
Initial release
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5 Pin Configuration and Functions
NC
30
NC
29
NC
28
NC
27
26
25
24
23
22
PGND
PGND
PGND
PGND
PVIN
SW
SW
SW
1
2
3
4
5
SW
SW
CBOOT
VCC
21
20
19
18
17
6
7
DAP
PVIN
PVIN
BIAS
AGND
8
RT
9
EN
SYNC/
MODE
SS/TRK
FB
10
11
16
PGOOD
13
14
NC
15
NC
12
NC
NC
Figure 5-1. RNP Package
30-Pin QFN 6 mm × 4 mm × 0.8 mm
Top View
Table 5-1. Pin Functions
PIN
I/O(1)
DESCRIPTION
NO.
NAME
Switching output of the regulator. Internally connected to source of the HS FET and drain of the LS
FET. Connect to power inductor and bootstrap capacitor.
1, 2, 3, 4, 5
SW
P
P
Bootstrap capacitor connection for HS FET driver. Connect a high-quality 470-nF capacitor from
this pin to the SW pin.
6
7
CBOOT
VCC
Output of internal bias supply. Used as supply to internal control circuits and drivers. Connect a
high-quality 2.2-µF capacitor from this pin to GND. TI does not recommend loading this pin by
external circuitry.
P
Optional BIAS LDO supply input. TI recommends tying to VOUT when 3.3 V ≤ VOUT ≤ 18 V, or tie to
an external 3.3-V or 5-V rail if available, to improve efficiency. BIAS pin voltage must not be greater
than VIN. Tie to ground when not in use.
8
9
BIAS
RT
P
A
Switching frequency setting pin. Place a resistor from this pin to ground to set the switching
frequency. If floating, the default switching frequency is 500 kHz. Do not short to ground.
Soft-start control pin. Leave this pin floating for a fixed internal soft-start ramp. An external
capacitor can be connected from this pin to ground to extend the soft start time. A 2-µA current
sourced from this pin charges the capacitor to provide the ramp. Connect to external ramp for
tracking. Do not short to ground.
10
SS/TRK
A
Feedback input for output voltage regulation. Connect a resistor divider to set the output voltage.
Never short this pin to ground during operation.
11
FB
I
12–15,
27–30
No internal connection. Connect to ground net and copper to improve heat sinking and board-level
reliability.
NC
—
Open drain power-good flag output. Connect to suitable voltage supply through a current limiting
resistor. High = VOUT regulation OK, Low = VOUT regulation fault. PGOOD = LOW when EN = low
and VIN > 2 V.
16
PGOOD
O
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Table 5-1. Pin Functions (continued)
PIN
I/O(1)
DESCRIPTION
NO.
NAME
Synchronization input and mode setting pin. Do not float. Tie to ground if not used.
Tie to ground: auto mode, higher efficiency at light loads;
Tie to logic high: forced PWM, constant switching frequency over load;
17
SYNC/MODE
I
Tie to external clock source: forced PWM, synchronize to the rising edge of the external clock.
Enable input to regulator. Do not float. High = ON, Low = OFF. Can be tied to PVIN. Precision
enable input allows adjustable input voltage UVLO using external resistor divider.
18
19
EN
I
Analog ground. Ground reference for internal circuitry. All electrical parameters are measured with
respect to this pin. Connect to system ground on PCB.
AGND
G
Supply input to internal bias LDO and HS FET. Connect to input supply and input bypass capacitors
CIN. CIN must be placed right next to this pin and PGND pins on PCB, and connected with short
and wide traces.
20–22
23–26
EP
PVIN
PGND
DAP
P
G
G
Power ground, connected to the source of LS FET internally. Connect to system ground, DAP/EP,
AGND, ground side of CIN and COUT on PCB. Path to CIN must be as short as possible
Low impedance connection to AGND. Connect to system ground on PCB. Major heat dissipation
path for the device. Must be used for heat sinking by soldering to ground copper on PCB. Thermal
vias are preferred to improve heat dissipation to other layers.
(1) A = Analog, O = Output, I = Input, G = Ground, P = Power
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range of -55°C to +125°C (unless otherwise noted)(1)
MIN
MAX
UNIT
PVIN to PGND
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–3.5
–0.3
–0.3
–55
36
EN to AGND
PVIN + 0.3
FB, RT, SS/TRK to AGND
PGOOD to AGND
SYNC to AGND
5
Input voltages
20
V
5.5
BIAS to AGND
Lower of (PVIN + 0.3) or 20
AGND to PGND
0.3
SW to PGND
PVIN + 0.3
SW to PGND less than 10-ns transients
CBOOT to SW
36
5
Output voltages
V
VCC to AGND
5
TJ
Junction temperature
Storage temperature
125
150
°C
°C
Tstg
–65
(1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
6.2 ESD Ratings
VALUE UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1)
±2000
±750
V(ESD)
Electrostatic discharge
V
Charged device model (CDM), per JEDEC specification JESD22-C101, all pins(2)
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range of -55°C to +125°C (unless otherwise noted)
MIN
MAX
UNIT
PVIN to PGND
EN
3.5
32
0
PVIN
FB
0
4.5
Input voltages
PGOOD
0
0
18
V
BIAS input not used
BIAS input used
AGND to PGND
VOUT
0.3
0
Lower of (PVIN + 0.3) or 18
–0.1
1
0.1
95% of PVIN
6
Output voltage
Output current
V
A
IOUT
0
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UNIT
SNVSBL0 – NOVEMBER 2020
6.4 Thermal Information
TPS7H4010-SEP
THERMAL METRIC(1)
RNP (QFN)
30 PINS
29.7
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
17.7
9.1
ΨJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
0.2
ΨJB
9.0
RθJC(bot)
1.0
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Electrical Characteristics
Limits apply over the recommended operating junction temperature (TJ) range of -55°C to +125°C, unless otherwise stated.
Minimum and maximum limits are specified through test, design, or statistical correlation. Typical values represent the most
likely parametric norm at TJ = 25°C, and are provided for reference purposes only. Unless otherwise stated, VIN = 12 V.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY VOLTAGE (PVIN PINS)
PVIN
ISD
Operating input voltage
3.5
32
10
V
Shutdown quiescent current;
measured at PVIN pin(1)
VEN = AGND, TJ = 25°C
0.8
0.6
µA
Operating quiescent current
from PVIN (non-switching)
VEN = 2 V, VFB = 1.5 V, VBIAS = 3.3 V
external
IQ_NONSW
12
µA
ENABLE (EN PIN)
VEN_VCC_H
Enable input high level for VCC
output
VEN rising
VEN falling
1.15
V
V
Enable input low level for VCC
output
VEN_VCC_L
0.3
VEN_VOUT_H
VEN_VOUT_HYS
ILKG_EN
Enable input high level for VOUT VEN rising
1.14
1.196
100
1.25
200
V
Enable input hysteresis for VOUTVEN falling hysteresis
mV
nA
Enable input leakage current
VEN = 2 V
1.4
INTERNAL LDO (VCC PIN, BIAS PIN)
PWM operation
PFM operationg
VCC rising
3.27
3.1
V
V
VCC
Internal VCC voltage
2.96
3.14
605
3.09
63
3.27
3.25
V
Internal VCC undervoltage
lockout
VCC_UVLO
VCC falling hysteresis
VBIAS rising
mV
V
VBIAS_ON
Input changeover
VBIAS falling hysteresis
mV
Operating quiescent current
from external VBIAS (non-
switching)
VEN = 2 V, VFB = 1.5 V, VBIAS = 3.3 V
external
IBIAS_NONSW
21
50
µA
VOLTAGE REFERENCE (FB PIN)
VFB
Feedback voltage
PWM mode
0.987
1.6
1.006
0.2
1.017
60
V
ILKG_FB
Input leakage current at FB pin VFB = 1 V
nA
HIGH SIDE DRIVER (CBOOT PIN)
CBOOT - SW undervoltage
lockout
VCBOOT_UVLO
2.2
2.7
V
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Limits apply over the recommended operating junction temperature (TJ) range of -55°C to +125°C, unless otherwise stated.
Minimum and maximum limits are specified through test, design, or statistical correlation. Typical values represent the most
likely parametric norm at TJ = 25°C, and are provided for reference purposes only. Unless otherwise stated, VIN = 12 V.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
CURRENT LIMITS AND HICCUP
Short-circuit, high-side current
IHS_LIMIT
7.4
5.8
8.7
9.85
7.25
A
limit(2)
ILS_LIMIT
INEG_LIMIT
VHICCUP
IL_ZC
Low-side current limit(2)
Negative current limit
Hiccup threshold on FB pin
Zero cross-current limit
6.6
–5
A
A
V
A
0.36
1.8
0.4
0.44
2.2
-0.05
SOFT START (SS/TRK PIN)
ISSC
Soft-start charge current
2
1
µA
kΩ
RSSD
Soft-start discharge resistance UVLO, TSD, OCP, or EN = AGND
POWER GOOD (PGOOD PIN) and OVERVOLTAGE PROTECTION
Power-good overvoltage
threshold
VPGOOD_OV
% of FB voltage
106%
86%
110%
113%
93%
Power-good undervoltage
threshold
VPGOOD_UV
% of FB voltage
% of FB voltage
90%
1.2%
1.3
VPGOOD_HYS
VPGOOD_VALID
Power-good hysteresis
Minimum input voltage for
proper PGOOD function
50-µA pullup to PGOOD pin, VEN =
AGND, TJ = 25℃
2
V
VEN = 2.5 V
40
30
100
90
RPGOOD
Power-good ON-resistance
Ω
VEN = AGND
MOSFETS
High-side MOSFET ON-
resistance
(3)
RDS_ON_HS
IOUT = 1 A, VBIAS = VOUT = 3.3 V
IOUT = 1 A, VBIAS = VOUT = 3.3 V
53
31
90
55
mΩ
mΩ
Low-side MOSFET ON-
resistance
(3)
RDS_ON_LS
THERMAL SHUTDOWN
Thermal shutdown threshold
Recovery threshold
Shutdown threshold
160
135
(4)
TSD
°C
(1) Shutdown current includes leakage current of the switching transistors.
(2) This current limit was measured as the internal comparator trip point. Due to inherent delays in the current limit comparator and
drivers, the peak current limit measured in closed loop with faster slew rate will be larger, and valley current limit will be lower.
(3) Measured at pins.
(4) Ensured by design.
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6.6 Timing Characteristics
PARAMETER
TEST CONDITIONS
MIN
NOM
MAX
UNIT
CURRENT LIMITS AND HICCUP
Number of switching cycles
before hiccup is tripped
(1)
NOC
tOC
128
46
cycles
ms
Overcurrent hiccup retry delay
time
SOFT START (SS/TRK PIN)
tSS Internal soft-start time
CSS = OPEN, from EN rising edge to
PGOOD rising edge
3.5
6.3
ms
POWER GOOD (PGOOD PIN) and OVERVOLTAGE PROTECTION
PGOOD rising edge deglitch
delay
tPGOOD_RISE
tPGOOD_FALL
80
80
140
140
200
200
µs
µs
PGOOD falling edge deglitch
delay
(1) Ensured by design.
6.7 Switching Characteristics
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
PWM LIMITS (SW PINS)
tON-MIN
tOFF-MIN
tON-MAX
Minimum switch on-time
Minimum switch off-time
Maximum switch on-time
60
70
6
82
120
9
ns
ns
µs
HS timeout in dropout
3
OSCILLATOR (RT and SYNC PINS)
fOSC Internal oscillator frequency
RT = Open
440
315
500
350
560
385
kHz
kHz
Minimum adjustable frqeuency
by RT or SYNC
RT = 115 kΩ, 0.1%
fADJ
Maximum adjustable
RT = 17.4 kΩ, 0.1%
1980
0.4
2200
2420
2
frqeuency by RT or SYNC
VSYNC_HIGH
VSYNC_LOW
Sync input high-level threshold
Sync input low-level threshold
V
V
Mode input high-level
threshold for FPWM
VMODE_HIGH
VMODE_LOW
tSYNC_MIN
0.42
0.4
80
V
V
Mode input low-level threshold
for AUTO mode
Sync input minimum ON and
OFF time
ns
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6.8 Typical Characteristics
Unless otherwise specified, VIN = 12 V. Curves represent most likely parametric norm at specified condition.
75
70
65
60
55
50
45
40
35
30
25
20
1600
1500
1400
1300
1200
1100
1000
900
VIN = 3.5 V
VIN = 12 V
HS Switch
LS Switch
800
700
600
500
400
300
200
-40
-20
0
20
40
60
Temperature (°C)
80
100
120
-40
-20
0
20
40 60
Temperature (°C)
80
100 120 140
Plot
CHAR
Figure 6-2. Shutdown Quiescent Current
Figure 6-1. High-Side and Low-Side Switches
RDS-ON
1.01
7.5
Temp = -40°C
Temp = 25°C
Temp = 125°C
1.009
1.008
1.007
1.006
1.005
1.004
1.003
1.002
1.001
1
7
6.5
6
HS
LS
5.5
5
3
6
9
12
15
VIN (V)
18
21
24
27
30
-40
-20
0
20
40
60
Temperature (°C)
80
100
120
CHAR
Figure 6-3. Feedback Voltage
Figure 6-4. TPS7H4010-SEP High-Side and Low-
Side Current Limits
2500
2250
9
8.4
7.8
7.2
6.6
2000
FREQ = 350 kHz
FREQ = 1 MHz
1750
FREQ = 2.2 MHz
1500
HS
LS
1250
1000
750
500
250
0
6
-40
-40
-20
0
20
40
60
Temperature (°C)
80
100
120
-20
0
20
40
60
Temperature (°C)
80
100
120
CHAR
CHAR
Figure 6-6. Switching Frequency Set by RT
Resistor
Figure 6-5. TPS7H4010-SEP High-Side and Low-
Side Current Limit
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550
540
530
520
510
500
490
480
470
460
450
1.28
1.2
1.12
1.04
0.96
0.88
0.8
VEN_VOUT Rising
VEN_VOUT Falling
VEN_VCC Rising
VEN_VCC Falling
VIN = 3.5 V
VIN = 12 V
0.72
0.64
0.56
-40
-20
0
20
40 60
Temperature (°C)
80
100 120 140
-40
-20
0
20
40
60
Temperature (°C)
80
100
120
CHAR
Figure 6-8. Enable Thresholds
Figure 6-7. Switching Frequency with RT Pin Open
Circuit
115
110
105
100
95
OV Tripping
OV Recovery
UV Recovery
UV Tripping
90
85
-40
-20
0
20
40
60
Temperature (°C)
80
100
120
CHAR
Figure 6-9. PGOOD Thresholds
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7 Detailed Description
7.1 Overview
The TPS7H4010-SEP is an easy-to-use synchronous step-down DC/DC converter that operates from a 3.5-V to
32-V supply voltage. It is capable of delivering up to 6-A of DC load current with exceptional efficiency and
thermal performance in a very small solution size.
The TPS7H4010-SEP employs fixed-frequency peak current-mode control with configurable auto or FPWM
operation mode. Auto mode provides very high efficiency at light loads, and FPWM mode maintains constant
switching frequency over entire load range.
The device is internally compensated, which reduces design time and the number of external components. The
switching frequency is programmable from 350 kHz to 2.2 MHz by an external resistor. The TPS7H4010-SEP
can also synchronize to an external clock within the same frequency range. The wide switching frequency range
allows the device to be optimized for a wide range of system requirements. It can be optimized for small solution
size with higher frequency; or for high efficiency with lower switching frequency. The TPS7H4010-SEP has very
low quiescent current, which is critical for battery operated systems. It allows for a wide range of voltage
conversion ratios due to very small minimum on-time (t ON-MIN) and minimum off-time (t OFF-MIN). Automated
frequency foldback is employed at very high or low duty cycles to further extend the operating range.
The TPS7H4010-SEP also features a power-good (PGOOD) flag, precision enable, internal or adjustable soft
start, pre-biased start-up, and output voltage tracking. Protection features include thermal shutdown,
undervoltage lockout (UVLO), cycle-by-cycle current limiting, and short-circuit hiccup protection. It provides
flexible and easy-to-use solutions for a wide range of applications.
The device requires very few external components and has a pin out designed for simple, optimum PCB layout
for enhanced EMI and thermal performance. The TPS7H4010-SEP device is available in a 30-pin QFN leadless
package.
7.2 Functional Block Diagram
ENABLE
VCC
BIAS
LDO
PVIN
ISSC
Internal
SS
VBOOT
Precision
Enable
CBOOT
VCC
SS/TRK
HS I Sense
ICMD
+
VBOOT VSW
EA
+
REF
œ
RC
CC
œ
+
UVLO
FB
UVLO
FB
VSW
OV/UV
Detector
SW
PFM
Detector
CONTROL LOGIC
PGood
PGOOD
TSD
Hiccup
Detector
+
œ
Slope Comp
Oscillator
CLK
ILIMIT
AGND
LS I Sense
FPWM
SYNC/
MODE
RT
PGND
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7.3 Feature Description
7.3.1 Synchronous Step-Down Regulator
The TPS7H4010-SEP is a synchronous buck converter with both power MOSFETs integrated in the device.
Figure 7-1 shows a simplified schematic for synchronous and non-synchronous buck converters. The
synchronous buck integrates both high-side (HS) and low-side (LS) power MOSFETs. The non-synchronous
buck integrates HS MOSFET and works with a discrete power diode as LS rectifier.
Synchronous
Buck
Non Synchronous
Buck
L
L
VIN
VIN
SW
SW
VOUT
COUT
VOUT
VIN
CIN
VIN
CIN
COUT
PGND
PGND
Figure 7-1. Simplified Synchronous vs Non-synchronous Buck Converters
A synchronous converter with integrated HS and LS MOSFETs offers benefits such as less design effort, lower
external components count, reduced total solution size, higher efficiency at heavier load, easier PCB design, and
more control flexibility.
The main advantage of a synchronous converter is that the voltage drop across the LS MOSFET is lower than
the voltage drop across the power diode of a non-synchronous converter. Lower voltage drop translates into less
power dissipation and higher efficiency. The TPS7H4010-SEP integrates HS and LS MOSFETs with very low on-
time resistance to improve efficiency. It is especially beneficial when the output voltage is low. Because the LS
MOSFET is integrated into the device, at light loads a synchronous converter has the flexibility to operate in
either discontinuous or continuous conduction mode.
An integrated LS MOSFET also allows the controller to obtain inductor current information when the LS switch is
on. It allows the control loop to make more complex decisions based on HS and LS currents. It allows the
TPS7H4010-SEP to have peak and valley cycle-by-cycle current limiting for more robust protection.
7.3.2 Auto Mode and FPWM Mode
The TPS7H4010-SEP has pin configurable auto mode or FPWM options.
In auto mode, the device operates in diode emulation mode (DEM) at light loads. In DEM, inductor current stops
flowing when it reaches 0 A. This is also referred to as discontinuous conduction mode (DCM). This is the same
behavior as the non-synchronous regulator, with higher efficiency. At heavier load, when the inductor current
valley is above 0 A, the device operates in continuous conduction mode (CCM), where the switching frequency
is fixed and set by RT pin.
In auto mode, the peak inductor current has a minimum limit, IPEAK_MIN, in the TPS7H4010-SEP. When peak
current reaches I PEAK_MIN, the switching frequency reduces to regulate the required load current. Switching
frequency lowers when load reduces. This is when the device operates in pulse frequency modulation (PFM).
PFM further improves efficiency by reducing switching losses. Light load efficiency is especially important for
battery operated systems.
In forced PWM (FPWM) mode, the device operates in CCM regardless of load with the frequency set by RT pin
or synchronization input. Inductor current can go negative at light loads. At light loads, the efficiency is lower
than auto mode, due to higher conduction losses and switching losses. In FPWM, the device has fixed switching
frequency over the entire load range, which is beneficial to noise sensitive applications.
Figure 7-2 shows the inductor current waveforms in each mode with heavy load, light load, and very light load.
The difference between the two modes is at lighter loads where inductor current valley reaches zero.
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Auto Mode
FPWM Mode
IL
IL
CCM
CCM
Heavy
Loads
t
t
t
t
IL
IL
Light
Loads
CCM
CCM
DCM
PFM
t
IL
IL
Very Light
Loads
t
Figure 7-2. Inductor Current Waveforms at Auto Mode and FPWM Mode With Different Loads
In CCM, the inductor current peak-to-peak ripple can be estimated by Equation 1:
(VIN - VOUT
fSW ì L
)
VOUT
ILripple
=
ì
V
IN
(1)
The average or DC value of the inductor current equals the load current, or output current IOUT, in steady state.
Peak inductor current can be calculated by Equation 2:
IPEAK = IOUT + ILripple / 2
(2)
Valley inductor current can be calculated by Equation 3:
IVALLEY = IOUT – ILripple / 2
(3)
In auto mode, the CCM to DCM boundary condition is when IVALLEY = 0 A. When ILripple ≥ IPEAK_MIN, the load
current at the DCM boundary condition can be found by Equation 4. When the peak-to-peak ripple current is
smaller than ILripple ≥ IPEAK-MIN, the PFM boundary will be reached first.
IOUT_DCM = ILripple / 2
(4)
when
ILripple ≥ IPEAK_MIN
•
In auto mode, the PFM operation boundary condition is when IPEAK = IPEAK_MIN. Frequency foldback occurs
when peak current drops to IPEAK_MIN, no matter whether in CCM or DCM operation. When current ripple is
small, ILripple < IPEAK_MIN, the peak current reaches IPEAK_MIN when still in CCM. The output current at CCM PFM
boundary can be found by Equation 5:
I
OUT_CCM_PFM = IPEAK_MIN – ILripple / 2
(5)
when
ILripple < IPEAK_MIN
•
The current ripple increases with reduced frequency if load reduces. When valley current reaches zero, the
frequency continues to fold back with constant peak current and discontinuous current.
In FPWM mode, there is no IPEAK-MIN limit. The peak current is defined by Equation 2 at light loads and heavy
loads.
Mode setting only affects operation at light loads. There is no difference if load current is above the DCM and
PFM boundary conditions discussed above.
See Frequency Synchronization and Mode Setting section for mode setting options in TPS7H4010-SEP.
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7.3.3 Fixed-Frequency Peak Current-Mode Control
The TPS7H4010-SEP synchronous switched mode voltage regulator employs fixed frequency peak current
mode control with advanced features. The fixed switching frequency is controlled by an internal clock. To get
accurate DC load regulation, a voltage feedback loop is implemented to generate peak current command. The
HS switch is turned on at the rising edge of the clock. As shown in Figure 7-3, during the HS switch on-time tON
,
the SW pin voltage VSW swings up to approximately VIN, and the inductor current IL increases with a linear slope.
The HS switch is turned off when the inductor current reaches the peak current command. During the HS switch
off-time tOFF, the LS switch is turned on. Inductor current discharges through the LS switch, which forces the
VSW to swing below ground by the voltage drop across the LS switch. The LS switch is turned off at the next
clock cycle, before the HS switch is turned on. The regulation loop adjusts the peak current command to
maintain a constant output voltage.
V
SW
D = t
/ T
SW
ON
V
IN
t
t
OFF
ON
0
t
-V
D
T
SW
IL
I
L-PEAK
I
OUT
I
Lripple
I
L-VALLEY
0
t
Figure 7-3. SW Voltage and Inductor Current Waveforms in CCM
Duty cycle D is defined by the on-time of the HS switch over the switching period:
D = tON / TSW
(6)
where
TSW = 1 / fSW is the switching period
•
In an ideal buck converter, where losses are ignored, D is proportional to the output voltage and inverse
proportional to the input voltage: D = VOUT ⁄ VIN.
When the TPS7H4010-SEP is set to operate in auto mode, the LS switch is turned off when its current reaches
zero ampere before the next clock cycle comes. Both HS switch and LS switch are off before the HS switch is
turned on at the next clock cycle.
7.3.4 Adjustable Output Voltage
The voltage regulation loop in the TPS7H4010-SEP regulates the FB pin voltage to be the same as the internal
reference voltage. The output voltage of the TPS7H4010-SEP is set by a resistor divider to program the ratio
from VOUT to VFB. The resistor divider is connected from the output to ground with the mid-point connecting to
the FB pin.
VOUT
RFBT
FB
RFBB
Figure 7-4. Output Voltage Setting by Resistor Divider
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The internal voltage reference and feedback loop produce precise voltage regulation over temperature. TI
recommends using divider resistors with 1% tolerance or better, and with temperature coefficient of 100 ppm or
lower. Typically, RFBT = 10 kΩ to 100 kΩ is recommended. Larger RFBT and RFBB values reduce the quiescent
current going through the divider, which help maintain high efficiency at very light load. But larger divider values
also make the feedback path more susceptible to noise. If efficiency at very light load is critical in a certain
application, RFBT up to 1 MΩ can be used.
RFBB can be calculated by Equation 7:
VFB
RFBB
=
RFBT
VOUT - VFB
(7)
The minimum programmable VOUT equals VFB, with RFBB open. The maximum VOUT is limited by the maximum
duty cycle at a given frequency:
DMAX = 1 – (tOFF-MIN / TSW
)
(8)
where
•
•
tOFF-MIN is the minimum off time of the HS switch
TSW = 1 / fSW is the switching period
Ideally, without frequency foldback, VOUT_MAX = VIN_MIN × DMAX
.
Power losses in the circuit reduces the maximum output voltage. The TPS7H4010-SEP folds back switching
frequency under t OFF_MIN condition to further extend V OUT_MAX. The device maintains output regulation with
lower input voltage. The minimum fold-back frequency is limited by the maximum HS on-time, t ON_MAX
Maximum output voltage with frequency foldback can be estimated by:
.
tON-MAX
tON-MAX + tOFF-MIN
VOUT _MAX = V
ì
- IOUT ì (RDS_ON_HS + DCR)
IN_MIN
(9)
The voltage drops on the HS MOSFET and inductor DCR have been taken into account in Equation 9. The
switching losses were not included.
If the resistor divider is not connected properly, the output voltage cannot be regulated because the feedback
loop cannot obtain correct output voltage information. If the FB pin is shorted to ground or disconnected, the
output voltage is driven close to VIN. The load connected to the output could be damaged under this condition.
Do not short FB to ground or leave it open circuit during operation.
The FB pin is a noise sensitive node. It is important to place the resistor divider as close as possible to the FB
pin, and route the feedback node with a short and thin trace. The trace connecting VOUT to RFBT can be long, but
it must be routed away from the noisy area of the PCB. For more layout recommendations, see Layout section.
7.3.5 Enable and UVLO
The TPS7H4010-SEP regulates output voltage when the VCC voltage is higher than the undervoltage lock out
(UVLO) level, VCC_UVLO, and the EN voltage is higher than VEN_VOUT_H
.
The internal LDO output voltage VCC is turned on when the EN voltage is higher than VEN_VCC_H. The precision
enable circuitry is also turned on when VCC is above UVLO. Normal operation of the TPS7H4010-SEP with
regulated output voltage is enabled when the EN voltage is greater than VEN_VOUT_H. When the EN voltage is
less than VEN_VCC_L, the device is in shutdown mode. The internal dividers make sure VEN_VOUT_H is always
higher than VEN_VCC_H
.
The EN pin cannot be left floating. The simplest way to enable the operation of the TPS7H4010-SEP is to
connect the EN pin to PVIN, which allows self-start-up of the TPS7H4010-SEP when VIN rises. Use of a pullup
resistor between PVIN and EN pins helps reduce noise coupling from PVIN pin to the EN pin.
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Many applications benefit from employing an enable divider to establish a customized system UVLO. This can
be used either for sequencing, system timing requirement, or to reduce the occurrence of deep discharge of a
battery power source. Figure 7-5 shows how to use a resistor divider to set a system UVLO level. An external
logic output can also be used to drive the EN pin for system sequencing.
VIN
RENT
ENABLE
RENB
Figure 7-5. System UVLO
With a selected RENT, the RENB can be calculated by Equation 10:
VEN_ VOUT _H
RENB
=
RENT
V
- VEN_VOUT_H
IN_ON_H
(10)
where
VIN_ON_H is the desired supply voltage threshold to turn on this device
•
Note that the divider adds to supply quiescent current by VIN / (RENT + RENB). Small RENT and RENB values add
more quiescent current loss. However, large divider values make the node more sensitive to noise. RENT in the
hundreds of kΩ range is a good starting point.
7.3.6 Internal LDO, VCC_UVLO, and BIAS Input
The TPS7H4010-SEP integrates an internal LDO, generating VCC voltage for control circuitry and MOSFET
drivers. The VCC pin must have a 1-µF to 4.7-µF bypass capacitor placed as close as possible to the pin and
properly grounded. Do not load the VCC pin or short it to ground during operation. Shorting VCC pin to ground
during operation may damage the device.
The UVLO on VCC voltage, VCC_UVLO, turns off the regulation when VCC voltage is too low. It prevents the
TPS7H4010-SEP from operating until the VCC voltage is enough for the internal circuitry. Hysteresis on
VCC_UVLO prevents the part from turning off during power up if VIN droops due to input current demands. The
LDO generates VCC voltage from one of the two inputs: the supply voltage VIN, or the BIAS input. When BIAS is
tied to ground, the LDO input is VIN. When BIAS is tied to a voltage higher than 3.3 V, the LDO input is VBIAS
BIAS voltage must be lower than both VIN and 18 V.
.
The BIAS input is designed to reduce the LDO power loss. The LDO power loss is:
P
LOSS_LDO = ILDO × (VIN_LDO – VOUT_LDO)
(11)
The higher the difference between the input and output voltages of the LDO, the more loss occurs to supply the
same LDO output current. The BIAS input provides an option to supply the LDO with a lower voltage than VIN, to
reduce the difference of the input and output voltages of the LDO and reduce power loss. For example, if the
LDO current is 10 mA at a certain frequency with VIN = 24 V and VOUT = 5 V. The LDO loss with BIAS tied to
ground is equal to 10 mA × (24 V – 3.27 V) = 207.3 mW, while the loss with BIAS tied to VOUT is equal to 10 mA
× (5 – 3.27) = 17.3 mW.
The efficiency improvement is more significant at light and mid loads because the LDO loss is a higher
percentage in the total loss. The improvements is more significant with higher switching frequency because the
LDO current is higher at higher switching frequency. The improvement is more significant when VIN » VOUT
because the voltage difference is higher.
Figure 7-6 and Figure 7-7 show efficiency improvement with bias tied to VOUT in a VOUT = 5 V and fSW = 2200
kHz application, in auto mode and FPWM mode, respectively.
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100
95
90
85
80
75
70
65
60
55
50
45
40
35
30
100
80
60
40
20
0
VIN = 12 V BIAS = VOUT
VIN = 12 V BIAS = GND
VIN = 24 V BIAS = VOUT
VIN = 24 V BIAS = GND
VIN = 12 V BIAS = VOUT
VIN = 12 V BIAS = GND
VIN = 24 V BIAS = VOUT
VIN = 24 V BIAS = GND
0.001
0.01 0.02 0.05 0.1 0.2 0.5
Load Current (A)
1
2
3 456
0.001
0.010.02 0.05 0.1 0.2 0.5
Load Current (A)
1
2 3 45 7 10
EFF_
EFF_
VOUT = 5 V
fSW = 2200 kHz
Auto Mode
VOUT = 5 V
fSW = 2200 kHz
FPWM Mode
Figure 7-6. TPS7H4010 Efficiency Comparison
With Bias = VOUT to Bias = GND in Auto Mode
Figure 7-7. TPS7H4010 Efficiency Comparison
With Bias = VOUT to Bias = GND in FPWM Mode
TI recommends tying the BIAS pin to VOUT when VOUT is equal to or greater than 3.3 V and no greater than 18 V.
Tie the BIAS pin to ground when not in use. A ceramic capacitor, CBIAS, can be used from the BIAS pin to
ground for bypassing. If VOUT has high frequency noise or spikes during transients or fault conditions, a resistor
(1 to 10 Ω) connected between VOUT to BIAS can be used together with CBIAS for filtering.
The VCC voltage is typically 3.27 V. When the TPS7H4010-SEP is operating in PFM mode with frequency
foldback, VCC voltage is reduced to 3.1 V (typical) to further decrease the quiescent current and improve
efficiency at very light loads. Figure 7-8 shows an example of VCC voltage change with mode change.
3.5
3.4
3.3
3.2
3.1
3
2.9
2.8
2.7
2.6
2.5
2.4
2.3
2.2
2.1
2
Auto Mode
FPWM Mode
0.001
0.01 0.02 0.05 0.1 0.2
Load Current (A)
0.5
1
2 3 45
VCC_
VOUT = 5 V
fSW = 500 kHz
VIN = 12 V
Figure 7-8. VCC Voltage vs Load Current
VCC voltage has an internal UVLO threshold, VCC_UVLO. When VCC voltage is higher than VCC_UVLO rising
threshold, the device is active and in normal operation if V EN > V EN_VOUT_H. If VCC voltage droops below
VCC_UVLO falling threshold, the VOUT is shut down.
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7.3.7 Soft Start and Voltage Tracking
The TPS7H4010-SEP features controlled output voltage ramp during start-up. The soft-start feature reduces
inrush current during start-up and improves system performance and reliability.
If the SS/TRK pin is floating, the TPS7H4010-SEP starts up following the fixed internal soft-start ramp.
If longer soft-start time is desired, an external capacitor can be added from SS/TRK pin to ground. There is a 2-
µA (typical) internal current source, I SSC, to charge the external capacitor. For a desired soft-start time t SS
capacitance of CSS can be found by Equation 12.
,
CSS = ISSC × tSS
(12)
where
•
•
•
CSS = soft-start capacitor value (F)
ISSC = soft-start charging current (A)
tSS = desired soft-start time (s)
The FB voltage always follows the lower potential of the internal voltage ramp or the voltage on the SS/TRK pin.
Thus, the soft-start time can only be extended longer than the internal soft-start time by connecting CSS. Use
CSS to extend soft-start time when there are a large amount of output capacitors, or the output voltage is high, or
the output is heavily loaded during start-up.
TPS7H4010-SEP is operating in diode emulation mode during start-up regardless of mode setting. The device is
capable of starting up into pre-biased output conditions. During start-up, the device sets the minimum inductor
current to zero to avoid back charging the input capacitors.
TPS7H4010-SEP can track an external voltage ramp applied to the SS/TRK pin, if the ramp is slower than the
internal soft-start ramp. The external ramp final voltage after start-up must be greater than 1.5 V to avoid noise
interfering with the reference voltage. Figure 7-9 shows how to use resistor divider to set VOUT to follow an
external ramp.
EXT RAMP
RTRT
SS/TRK
RTRB
Figure 7-9. Soft Start Tracking External Ramp
VOUT tracking also provides the option of ramping up faster than the internal start-up ramp. The FB voltage
always follows the lower potential of the internal voltage ramp and the voltage on the SS/TRK pin. Figure 7-10
shows the case when VOUT ramps slower than the internal ramp, while Figure 7-11 shows when VOUT ramps
faster than the internal ramp. If the tracking ramp is delayed after the internal ramp is completed, VFB follows the
tracking ramp even if it is faster than the internal ramp. Faster start-up time may result in large inductor current
during start-up. Use with special care.
Enable
Internal SS Ramp
Ext Tracking Signal to SS pin
VOUT
Figure 7-10. Tracking With Longer Start-up Time Than the Internal Ramp
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Enable
Internal SS Ramp
Ext Tracking Signal to SS pin
VOUT
Figure 7-11. Tracking With Shorter Start-up Time Than the Internal Ramp
The SS/TRK pin is discharged to ground by an internal pulldown resistor R SSD when the output voltage is
shutting down, such as in the event of UVLO, thermal shutdown, hiccup, or VEN = 0. If a large CSS is used, and
the time when VEN = 0 V is very short, the CSS may not be fully discharged before the next soft start. Under this
condition, the FB voltage follows the internal ramp slew rate until the voltage on CSS is reached, then follow the
slew rate defined by CSS
.
7.3.8 Adjustable Switching Frequency
The internal oscillator frequency is controlled by the impedance on the RT pin. If the RT pin is open circuit, the
TPS7H4010-SEP operates at its default switching frequency, 500 kHz. The RT pin is not designed to be
connected directly to ground. To program the switching frequency by RT resistor, either Equation 13, Figure 7-12,
or Table 7-1 can be used to find the resistance value.
1
RT(kW) =
fSW (kHz) ì 2.675 ì 10-5- 0.0007
(13)
120
110
100
90
80
70
60
50
40
30
20
10
200 400 600 800 1000 1200 1400 1600 1800 2000 2200
Frequency (kHz)
RT_F
Figure 7-12. RT Resistance vs Switching Frequency
Table 7-1. Typical Frequency Setting Resistance
SWITCHING FREQUENCY fSW (kHz)
RT RESISTANCE (kΩ)
350
400
115
100
500
78.7 (or open)
52.3
750
1000
1500
2000
2200
39.2
26.1
19.1
17.4
The choice of switching frequency is usually a compromise between conversion efficiency and the size of the
solution. Lower switching frequency has lower switching losses (including gate charge losses, switch transition
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losses, etc.) and usually results in higher overall efficiency. However, higher switching frequency allows the use
of smaller power inductor and output capacitors, hence a more compact design. Lower inductance also helps
transient response (higher large signal slew rate of inductor current), and has lower DCR. The optimal switching
frequency is usually a trade-off in a given application and thus needs to be determined on a case-by-case basis.
Factors that need to be taken into account include input voltage range, output voltage, most frequent load
current level(s), external component choices, solution size/cost requirements, efficiency and thermal
management requirements.
The choice of switching frequency may also be limited whether an operating condition triggers t ON-MIN or
tOFF-MIN. Minimum on-time, tON-MIN, is the smallest time that the HS switch can be on. Minimum off-time, tOFF-MIN
,
is the smallest duration that the HS switch can be off.
In CCM operation, tON-MIN and tOFF_MIN limits the voltage conversion range given a selected switching frequency,
fSW. The minimum duty cycle allowed is:
DMIN = tON-MIN × fSW
The maximum duty cycle allowed is:
DMAX = 1 – tOFF-MIN × fSW
(14)
(15)
Given an output voltage, the choice of the switching frequency affects the allowed input voltage range, solution
size and efficiency. The maximum operational supply voltage can be found by:
VIN_MAX = VOUT / (fSW × tON-MIN
)
(16)
At lower supply voltage, the switching frequency decreases once tOFF-MIN is tripped. The minimum VIN without
frequency foldback can be approximated by:
VIN_MIN = VOUT / (1 – fSW × tOFF-MIN
)
(17)
With a desired VOUT, the range of allowed VIN is narrower with higher switching frequency.
TPS7H4010-SEP has an advanced frequency fold-back algorithm under both tON_MIN and tOFF_MIN conditions.
With frequency foldback, stable output voltage regulation is extended to wider range of supply voltages.
At very high VIN conditions, where tON-MIN limitation is met, the switching frequency reduces to allow higher VIN
while maintaining VOUT regulation. Note that the peak to peak inductor current ripple will increase with higher VIN
and lower frequency. TI does not recommend designing the circuit to operate with t ON_MIN under typical
conditions.
At very low VIN conditions, where tOFF-MIN limitation is met, the switching frequency decreases until tON-MAX
condition is met. Such frequency foldback mechanism allows the TPS7H4010-SEP to have very low dropout
voltage regardless of frequency setting.
7.3.9 Frequency Synchronization and Mode Setting
The TPS7H4010-SEP switching action can synchronize to an external clock from 350 kHz to 2.2 MHz. TI
recommends connecting the external clock to the SYNC/MODE pin with an appropriate termination resistor.
Ground the SYNC/MODE pin if not used.
SYNC/
EXT CLOCK
MODE
R
SYNC
Figure 7-13. Frequency Synchronization
Recommendations for the external clock include a high level no lower than 2 V, low level no higher than 0.4 V,
duty cycle between 10% and 90%, and both positive and negative pulse width no shorter than 80 ns. When the
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external clock fails at logic high or low, the TPS7H4010-SEP switches at the frequency programmed by the RT
resistor after a time-out period. TI recommends connecting a resistor to the RT pin such that the internal
oscillator frequency is the same as the external clock frequency. This allows the regulator to continue operating
at approximately the same switching frequency if the external clock fails with the same control loop behavior.
The SYNC/MODE pin is also used as an operation mode control input.
•
•
To set the operation in auto mode, connect SYNC/MODE pin to ground, or a logic signal lower than 0.3 V.
To set the operation in FPWM mode, connect SYNC/MODE pin to a bias voltage or logic signal greater than
0.6 V.
•
When the TPS7H4010-SEP is synchronized to an external clock, the operation mode is FPWM.
Table 7-2 summarizes the operation mode and features according to the SYNC/MODE input signal. For more
details, see Active Mode and Auto Mode and FPWM Mode sections.
Table 7-2. SYNC/MODE Pin Settings and Operation Modes
SYNC/MODE
INPUT
SWITCHING
FREQUENCY
OPERATING
MODE
LIGHT LOAD BEHAVIOR
•
•
•
No negative inductor current, device operates in discontinuous conduction mode
(DCM) when current valley reaches 0 A
Minimum peak inductor current is limited at IPEAK_MIN; device operates in pulse
frequency modulation (PFM) mode when peak current reaches IPEAK_MIN
Logic low
Set by RT resistor
Set by RT resistor
Auto mode
Switching frequency reduces in PFM mode
Logic high
•
•
•
Fixed frequency continuous conduction mode (CCM) regardless of load
Inductor current have negative portion at light loads
No IPEAK_MIN
FPWM mode
Set by external
clock
External clock
7.3.10 Internal Compensation and CFF
The TPS7H4010-SEP is internally compensated. The internal compensation is designed such that the loop
response is stable over a wide operating frequency and output voltage range. The internal R-C values are 500
kΩ and 30 pF, respectively.
When large resistance value (MΩ) is used for RFBT, the pole formed by an internal parasitic capacitor and RFBT
can be low enough to reduce the phase margin. If only low ESR output capacitors (ceramic types) are used for
C OUT, the control loop could have low phase margin. To provide a phase boost an external feed-forward
capacitor (CFF) can be added in parallel with RFBT. Choose the CFF capacitor to provide most phase boost at the
estimated crossover frequency fX:
K
fX
=
VOUT ì COUT
(18)
where
•
K = 24.16 with TPS7H4010-SEP
Select COUT so that the fX is no higher than 1/6 of the switching frequency. Typically, fX / fSW = 1/10 to 1/8
provides a good combination of stability and performance.
Place the external feed-forward capacitor in parallel with the top resistor divider RFBT when additional phase
boost is needed.
VOUT
RFBT
CFF
FB
RFBB
Figure 7-14. Feed-Forward Capacitor for Loop Compensation
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The feed-forward capacitor CFF in parallel with RFBT places an additional zero before the crossover frequency of
the control loop to boost phase margin. The zero frequency can be found by Equation 19:
fZ-CFF = 1 / (2π × RFBT × CFF
)
(19)
An additional pole is also introduced with CFF at the frequency of:
fP-CFF = 1 / (2π × CFF × (RFBT / RFBB))
(20)
Select the CFF so that the bandwidth of the control loop without the CFF is centered between fZ-CFF and fP-CFF
.
The zero at fZ-CFF adds phase boost at the crossover frequency and improves transient response. The pole at
fP-CFF helps maintaining proper gain margin at frequency beyond the crossover.
The need of CFF depends on RFBT and COUT. Typically, choose RFBT ≤ 100 kΩ. CFF may not be required,
because the internal parasitic pole is at higher frequency. If COUT has larger ESR, and ESR zero fZ-ESR = 1 / (2π
× ESR × COUT) is low enough to provide phase boost around the crossover frequency, do not use CFF. Equation
21 was tested for ceramic output capacitors:
1
1
CFF
=
ì
2 ì p ì fx
RFBT ì (RFBT // RFBB
)
(21)
The CFF creates a time constant with RFBT that couples in the attenuated output voltage ripple to the FB node. If
the CFF value is too large, it can couple too much ripple to the FB and affect VOUT regulation. It could also couple
too much transient voltage deviation and falsely trigger PGOOD flag.
7.3.11 Bootstrap Capacitor and VBOOT-UVLO
The driver of the HS switch requires a bias voltage higher than the VIN voltage. The capacitor, CBOOT in Figure
8-1, connected between CBOOT and SW pins works as a charge pump to boost voltage on the CBOOT pin to
(VSW + VCC). A boot diode is integrated on the die to minimize external component count. TI recommends a
high-quality 0.47-µF, 6.3-V or higher voltage ceramic capacitor for CBOOT. The VBOOT_UVLO threshold is designed
to maintain proper HS switch operation. If the CBOOT is not charged above this voltage with respect to SW, the
device initiates a charging sequence using the LS switch before turning on the HS switch.
7.3.12 Power-Good and Overvoltage Protection
The TPS7H4010-SEP has a built-in power-good (PGOOD) flag to indicate whether the output voltage is at an
appropriate level or not. The PGOOD flag can be used for start-up sequencing of multiple rails. The PGOOD pin
is an open-drain output that requires a pullup resistor to an appropriate logic voltage (any voltage below 15 V).
The pin can sink 5 mA of current and maintain its specified logic low level. A typical pullup resistor value is 10 kΩ
to 100 kΩ. When the FB voltage is higher than VPGOOD-OV or lower than VPGOOD-UV threshold, the PGOOD
internal switch is turned on, and the PGOOD pin voltage is pulled low. When the FB is within the range, the
PGOOD switch is turned off, and the pin is pulled up to the voltage connected to the pullup resistor. The PGOOD
function also have a deglitch timer for about 140 µs for each transition. If it is desired to pull up PGOOD pin to a
voltage higher than 15 V, a resistor divider can be used to divide the voltage down.
VPU
RPGT
PGOOD
RPGB
Figure 7-15. Divider for PGOOD Pullup Voltage
With a given pullup voltage VPU, select a desired voltage on the PGOOD pin, VPG. With a selected RPGT, the
RPGB can be found by:
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VPG
RPGB
=
RPGT
VPU - VPG
(22)
When the device is disabled, the output voltage is low, and the PGOOD flag indicates logic low as long as VIN
2 V.
>
7.3.13 Overcurrent and Short-Circuit Protection
The TPS7H4010-SEP is protected from overcurrent conditions with cycle-by-cycle current limiting on both HS
and LS MOSFETs.
The HS switch is turned off when HS current goes beyond the peak current limit, IHS-LIMIT. The LS switch can
only be turned off when LS current is below LS current limit, ILS-LIMIT. If the LS switch current is higher than
ILS-LIMIT at the end of a switching cycle, the switching cycle is extended until the LS current reduces below the
limit.
Current limiting on both HS and LS switches provides tighter control of the maximum DC inductor current, or
output current. They also help prevent runaway current at extreme conditions. With TPS7H4010-SEP, the
maximum output current is always limited at:
IDC_LIMIT = (IHS_LIMIT + ILS_LIMIT) / 2
(23)
The TPS7H4010-SEP employs hiccup current protection at extreme overload conditions, including short-circuit
condition. Hiccup is only activated when VOUT droops below 40% (typical) of the regulation voltage and stays
below for 128 consecutive switching cycles. Under overcurrent conditions when VOUT has not fallen below 40%
of regulation, the TPS7H4010-SEP continues operation with cycle-by-cycle HS and LS current limiting.
Hiccup is disabled during soft-start. When hiccup is triggered, the device turns off VOUT regulation and re-tries
soft start after a retry delay time, TOC = 46 ms (typical). The long wait time allows the device, and the load, to
cool down under such fault conditions. If the fault condition still exists when retry, hiccup shuts down the device
and repeats the wait and retry cycle. If the fault condition has been removed, the device starts up normally.
If tracking was used for initial sequencing, the device restarts using the internal soft-start ramp. Hiccup mode
helps to reduce the device power dissipation and die temperature under severe overcurrent conditions and short
circuits. It improves system reliability and prolongs the life span of the device.
In FPWM mode, negative current protection is implemented to protect the switches from extreme negative
currents. When LS switch current reaches INEG-LIMIT, LS switch turns off, and HS switch turns on to conduct the
negative current. HS switch is turned off once its current reaches 0 A.
7.3.14 Thermal Shutdown
Thermal shutdown protection prevents the device from extreme junction temperature. The device is turned off
when the junction temperature exceeds 160°C (typical). After thermal shutdown occurs, hysteresis prevents the
device from switching until the junction temperature drops to approximately 135°C. When the junction
temperature falls below 135°C, the TPS7H4010-SEP restarts.
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7.4 Device Functional Modes
7.4.1 Shutdown Mode
The EN pin provides electrical on/off control of the device. When the EN pin voltage is below VEN_VCC_L, the
device is in shutdown mode. The LDO output voltage VCC = 0 V and the output voltage VOUT = 0 V. In shutdown
mode the quiescent current drops to a very low value.
7.4.2 Standby Mode
The internal LDO has a lower EN threshold than that required to start the regulator. When the EN pin voltage is
above VEN_VCC_H, the internal LDO regulates the VCC voltage. The precision enable circuitry is turned on once
V CC is above V CC_UVLO. The device is in standby mode if EN voltage is below V EN_VOUT_H. The internal
MOSFETs remains in tri-state unless the voltage on EN pin goes beyond V
threshold. The
EN_VOUT_H
TPS7H4010-SEP also employs UVLO protection. If the VCC voltage is below the VCC_UVLO level, the output of
the regulator is turned off.
7.4.3 Active Mode
The TPS7H4010-SEP is in active mode when the EN voltage is above VEN_VOUT_H, and VCC is above VCC_UVLO
.
The simplest way to enable the operation of the TPS7H4010-SEP is to pull up the EN pin to PVIN, which allows
self-start-up when the input voltage ramps up.
In active mode, depending on the load current and mode setting, the TPS7H4010-SEP is in one of four modes:
1. CCM with fixed switching frequency when load current is above half of the peak-to-peak inductor current
ripple;
2. DCM with fixed switching frequency when load current is lower than half of the peak-to-peak inductor current
ripple in CCM operation;
3. PFM when switching frequency is decreased at very light load;
4. Under overcurrent or overtemperature conditions, the device operates in one of the fault protection modes.
See Table 7-2 for mode-setting details.
7.4.3.1 CCM Mode
In CCM operation, inductor current has a continuous triangular waveform. The HS switch is on at the beginning
of a switching cycle and the LS switch is turned off the end of each switching cycle. In auto mode, the
TPS7H4010-SEP operates in CCM when the load current is higher than ½ of the peak-to-peak inductor current
(ILripple). In FPWM mode, the TPS7H4010-SEP operates in CCM regardless of load.
In CCM operation, the switching frequency is typically constant, unless tON-MIN, tOFF-MIN, or IPEAK-MIN conditions
are met. The constant switching frequency is determined by RT pin setting, or the external synchronization clock
frequency. The duty cycle is also constant in CCM: D = VOUT / VIN if loss is ignored, regardless of load. The
peak-to-peak inductor ripple is constant with the same VIN and VOUT, regardless of load.
With very high or very low supply voltages, when the tON-MIN or tOFF-MIN condition is met, the frequency reduces
to maintain VOUT regulation with even higher or lower VIN, respectively. When the IPEAK_MIN condition is met in
auto mode, switching frequency will fold back to provide higher efficiency. IPEAK_MIN is disabled in FPWM mode.
7.4.3.2 DCM Mode
DCM operation only happens in auto mode, when the load current is lower than half of the CCM inductor current
ripple, and peak current is higher than IPEAK-MIN. There is no DCM in FPWM mode. DCM is also known as diode
emulation mode. The LS FET is turned off when the inductor current ramps to 0 A. DCM has the same switching
frequency as CCM, which is set by the RT pin. Duty cycle and peak current reduces with lighter load in DCM.
DCM is more efficient than FPWM under the same condition, because of lower switching losses and lower
conduction losses. When the peak current reduces to IPEAK_MIN at lighter load, the TPS7H4010-SEP operates in
PFM mode.
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7.4.3.3 PFM Mode
Pulse-frequency-modulation (PFM) mode is activated when peak current is lower than IPEAK-MIN, only in auto
mode. Peak current is kept constant and V OUT is regulated by frequency. Efficiency is greatly improved by
lowered switching losses, especially at very light loads.
In PFM operation, a small DC positive offset appears on VOUT. The lower the frequency is folded back in PFM,
the more the DC offset is on VOUT. See VOUT regulation curves in Application Curves section. If the DC offset on
VOUT is not acceptable, a dummy load at VOUT, or lower RFBT and RFBB resistance values can be used to reduce
the offset. Alternatively the device can be run in FPWM mode where the switching frequency is constant, and no
offset is added to affect the VOUT accuracy unless tON_MIN is reached.
7.4.3.4 Fault Protection Mode
The TPS7H4010-SEP has hiccup current protection at extreme overload and short circuit conditions. Hiccup is
activated when V OUT droops below 40% (typical) of the regulation voltage and stays for 128 consecutive
switching cycles. Hiccup is disabled during soft start. In hiccup, the device turns off VOUT and re-tries soft start
after 46-ms wait time. Cycle repeats until overcurrent fault condition has been removed. Hiccup mode helps to
reduce the device power dissipation and die temperature under severe overcurrent conditions and short circuits.
It improves system reliability and prolongs the life span of the device.
Under overcurrent conditions when V OUT droops below regulation but above 40% of regulated voltage, the
TPS7H4010-SEP stays in cycle-by-cycle HS and LS current limiting protection mode.
Thermal shutdown prevents the device from extreme junction temperature by turning off the device when the
junction temperature exceeds 160°C (typical). After thermal shutdown occurs, hysteresis prevents the device
from switching until the junction temperature drops to approximately 135°C. When the junction temperature falls
below 135°C, the TPS7H4010-SEP restarts.
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8 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes. Customers should validate and test their design
implementation to confirm system functionality.
8.1 Application Information
The TPS7H4010-SEP device is a step-down DC-DC voltage regulator. It is designed to operate with a wide
supply voltage range (3.5 V to 32 V), wide switching frequency range (350 kHz to 2.2 MHz), and wide output
voltage range: up to 95% VIN. The TPS7H4010-SEP is a synchronous converter with both HS and LS MOSFETs
integrated, and it is capable of delivering a maximum output current of 6 A. The following design procedure can
be used to select component values for the TPS7H4010-SEP. This section presents a simplified discussion of
the design process.
8.2 Typical Application
The TPS7H4010-SEP requires only a few external components to perform high-efficiency power conversion, as
shown in Figure 8-1.
L
VIN
VOUT
SW
PVIN
EN
CBOOT
COUT
CIN
CBOOT
BIAS
RT
PGND
PGOOD
SS/TRK
RFBT
SYNC/
MODE
FB
RFBB
VCC
CVCC
AGND
Figure 8-1. TPS7H4010-SEP Basic Schematic
The TPS7H4010-SEP also integrates many practical features to meet a wide range of system design
requirements and optimization, such as UVLO, programmable soft-start time, start-up tracking, programmable
switching frequency, clock synchronization and a power-good flag. Note that for ease of use, the feature pins do
not require an additional component when not in use. They can be either left floating or shorted to ground.
Please refer to Pin Configuration and Functions section for details.
A comprehensive schematic with all features utilized is shown in Figure 8-2.
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VIN
RENT
L
CIN
VOUT
PVIN
PGND
EN
SW
COUT
CBOOT
CBOOT
BIAS
RENB
SS/TRK
RT
PGOOD
FB
CSS
RFBT
RFBB
RT
AGND
VCC
SYNC/
MODE
CVCC
RSYNC
Copyright © 2017, Texas Instruments Incorporated
Figure 8-2. TPS7H4010-SEP Comprehensive Schematic With All Features Utilized
The external components must fulfill not only the needs of the power conversion, but also the stability criteria of
the control loop. The TPS7H4010-SEP is optimized to work with a range of external components. For quick
component selection, Table 8-1 can be used.
Table 8-1. Typical Component Selection
fSW (kHz)
350
VOUT (V)
L (µH)
2.2
1.5
0.68
0.47
4.7
3.3
1.8
1.2
6.8
4.7
3.3
2.2
15
COUT (µF)(1)
500
400
200
100
200
150
88
RFBT (kΩ)
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
RFBB (kΩ)
OPEN
OPEN
OPEN
OPEN
43.5
43.5
43.5
43.5
25
RT (kΩ)
115
1
1
500
78.7 or open
39.2
1000
2200
350
1
1
17.4
3.3
3.3
3.3
3.3
5
115
500
78.7 or open
39.2
1000
2200
350
44
17.4
120
88
115
500
5
25
78.7 or open
39.2
1000
2200
350
5
66
25
5
44
25
17.4
12
12
12
24
24
66
9.1
115
500
10
44
9.1
78.7 or open
39.2
1000
350
6.8
22
22
9.1
40
4.3
115
500
15
30
4.3
78.7 or open
(1) All the COUT values are after derating. Add more when using ceramics.
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8.2.1 Design Requirements
Detailed design procedure is described based on a design example. For this design example, use the
parameters listed in Table 8-2.
Table 8-2. Design Example Parameters
DESIGN PARAMETER
Typical input voltage
Output voltage
VALUE
12 V
5 V
Output current
6 A
Operating frequency
Soft-start time
500 kHz
11 ms
8.2.2 Detailed Design Procedure
8.2.2.1 Output Voltage Setpoint
The output voltage of the TPS7H4010-SEP device is externally adjustable using a resistor divider network. The
divider network is comprised of top feedback resistor RFBT and bottom feedback resistor RFBB. Use Equation 24
to determine the output voltage of the converter.
≈
∆
«
’
÷
◊
RFBT
RFBB
VOUT = VFB
ì
1+
(24)
Typically, RFBT = 10 kΩ to 100 kΩ is recommended. Larger RFBT and RFBB values reduce the quiescent current
going through the divider, which help maintain high efficiency at very light loads. But larger divider values also
make the feedback path more susceptible to noise. If efficiency at very light loads is critical in a certain
application, RFBT up to 1 MΩ can be used.
VFB
RFBB
=
RFBT
VOUT - VFB
(25)
RFBT = 100 kΩ is selected here. RFBB = 24.99 kΩ can be calculated to get 5-V output voltage.
8.2.2.2 Switching Frequency
The default switching frequency of the TPS7H4010-SEP device is set at 500 kHz. For this design, the RT pin
can be floating, and the TPS7H4010-SEP switches at 500 kHz in CCM mode. An R T resistor of 78.7 kΩ,
calculated using Equation 13, Figure 7-12, or Table 7-1, can be connected from RT pin to ground to obtain 500-
kHz operation frequency as well.
The TPS7H4010-SEP switching action can synchronize to an external clock from 350 kHz to 2.2 MHz. TI
recommends connecting an external clock to the SYNC/MODE pin with a 50-Ω to 100-Ω termination resistor.
The SYNC/MODE pin must be grounded if not used.
RT pin is floating and SYNC/MODE pin is tied to ground in this design.
8.2.2.3 Input Capacitors
The TPS7H4010-SEP device requires high-frequency ceramic input decoupling capacitors. Depending on the
application, a bulk input capacitor can also be added. The typical recommended ceramic decoupling capacitors
include one small, 0.1 µF to 1 µF, and one large, 10 µF to 22 µF, capacitors. TI recommends high-quality
ceramic type X5R or X7R capacitors. The voltage rating must be greater than the maximum input voltage. As a
general rule, to compensate the derating TI recommends a voltage rating of twice the maximum input voltage.
It is very important in buck regulator applications to place the small decoupling capacitor right next to the PVIN
and PGND pins. This capacitor is used to bypass the high frequency switching noise by providing a return path
of the noise. It prevents the noise from spreading to wider area of the board. The large bypass ceramic capacitor
must also be as close as possible to the PVIN and PGND pins.
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Additionally, some bulk capacitance may be required, especially if the TPS7H4010-SEP circuit is not located
within approximately 2 inches from the input voltage source. This capacitor is used to provide damping to the
voltage spike due to the lead inductance of the cable. The optimum value for this capacitor is four times the
ceramic input capacitance with ESR close to the characteristic impedance of the LC filter formed by your input
inductance and your ceramic input capacitors. It is not critical that the electrolytic filter be at the optimum value
for damping, but it must be rated to handle the maximum input voltage including ripple voltage.
For this design, two 10-µF, X7R dielectric capacitors rated for 50 V are used for the input decoupling
capacitance, and a capacitor with a value of 0.47 µF for high-frequency filtering.
Note
DC bias effect: High capacitance ceramic capacitors have a DC bias derating effect, which will have a
strong influence on the final effective capacitance. Therefore, the right capacitor value has to be
chosen carefully. Package size and voltage rating in combination with dielectric material are
responsible for differences between the rated capacitor value and the effective capacitance.
8.2.2.4 Inductor Selection
The first criterion for selecting an output inductor is the inductance. In most buck converters, this value is based
on the desired peak-to-peak ripple current in the inductor, ILripple. An inductance that gives a ripple current of
10% to 30% of the maximum output current (6 A) is a good starting point. The inductance can be calculated from
Equation 26:
V
IN - VOUT ìD
(
)
L =
ƒSW ìILripple
(26)
where
•
•
•
ILripple = (0.1 to 0.3) × IL_MAX
IL_MAX = 6 A for TPS7H4010-SEP
D = VOUT / VIN
Selected ILripple is between 10% to 30% of the rated current of the device.
As with switching frequency, the selection of the inductor is a tradeoff between size, cost, and performance.
Higher inductance gives lower ripple current and hence lower output voltage ripple. With peak current mode
control, the current ripple is the input signal to the control loop. A certain amount of ripple current is needed to
maintain the signal-to-noise ratio of the control loop. Within the same series (same size/height), a larger
inductance will have a higher series resistance (ESR). With similar ESR, size and/or height will be greater.
Larger inductance also has slower current slew rate during large load transients.
Lower inductance usually results in a smaller, less expensive component; however, the current ripple will be
higher, thus more output capacitor is needed to maintain the same amount of output voltage ripple. The RMS
current is higher with the same load current due to larger ripple. The switching loss is higher because the switch
current, which is the peak current, is higher when the HS switch turns off and LS switch turns on. Core loss of
the inductor is also larger with higher ripple. Core loss needs to be considered, especially with higher switching
frequencies. Check the ripple current over VIN_MIN to VIN_MAX range to make sure current ripple is reasonable
over entire supply voltage range.
For applications with large VOUT and typical VOUT / VIN > 50%, sub-harmonic oscillation can be a concern in peak
current-mode-controlled buck converters. Select inductance so that
L ≥ VOUT / (N × fSW
)
(27)
where
N = 3.6 with TPS7H4010-SEP
•
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The second criterion is inductor saturation current rating. Because the maximum inductor current is limited by the
high-side switch current limit, it is advised to select an inductor with a saturation current higher than the ILIMIT-HS
.
TI recommends selection of soft saturation inductors. A power inductor could be the major source of radiated
noise. When EMI is a concern in the application, select a shielded inductor, if possible.
For this design, 20% ripple of 6 A yields 4.86-µH inductance. A 4.7-µH inductor is selected, which gives 21%
ripple current.
8.2.2.5 Output Capacitor Selection
The output capacitor is responsible for filtering the inductor current, and supplying load current during transients.
Capacitor selection depends on application conditions as well as ripple and transient requirements. Best
performance is achieved by using ceramic capacitors or combinations of ceramic and other types of capacitors.
For high output voltage conditions, such as 12 V and above, finding ceramic capacitors that are rated for an
appropriate voltage becomes challenging. In such cases choose a low-ESR capacitor. It is a good idea to use a
low-value ceramic capacitor in parallel with other capacitors, to bypass high frequency noise between ground
and VOUT
.
For a given input and output requirement, Equation 28 gives an approximation for a minimum output capacitor
required.
2
»
…
…
ÿ
Ÿ
≈
’
1
r
Å
Å
COUT
>
ì
ì(1+ D ) + D ì(1+ r)
∆
∆
÷
(
)
÷
(fSW ìr ì DVOUT / IOUT
)
12
Ÿ
⁄
«
◊
(28)
where
•
•
•
•
•
r = Ripple ratio of the inductor ripple current (ILripple / 6 A )
ΔVOUT = Target output voltage undershoot, for example, 5% to 10% of VOUT
D’ = 1 – duty cycle
fSW = switching frequency
IOUT = load current
Along with Equation 28, for the same requirement calculate the maximum ESR with Equation 29.
Å
D
1
ESR <
ì( + 0.5)
fSW ìCOUT
r
(29)
The output capacitor is also the dominating factor in the loop response of a peak-current mode controlled buck
converter. A simplified estimation of the control loop crossover frequency can be found by Equation 18.
Select COUT so that the fX is no higher than 1/6 of the switching frequency. Typically, fX / fSW = 1/10 to 1/8
provides a good combination of stability and performance.
For this design, one 0.47-µF, 50-V X7R and four 22-µF, 16-V, X7R ceramic capacitors are used in parallel based
on a target output voltage overshoot value of 10%.
8.2.2.6 Feed-Forward Capacitor
The TPS7H4010-SEP is internally compensated. Typically, select RFBT ≤ 100 kΩ, then CFF is not needed. When
very low quiescent current is needed, RFBT = 1 MΩ may be used. If COUT is mainly ceramic type low ESR
capacitors, an external feed-forward capacitor CFF may be needed to improve the phase margin. Add CFF in
parallel with RFBT. CFF is chosen such that the phase boost is maximized at the estimated crossover frequency
fX. Equation 21 was tested.
With this design, because RFBT = 100 kΩ is selected, no CFF is needed.
8.2.2.7 Bootstrap Capacitors
Every TPS7H4010-SEP design requires a bootstrap capacitor, CBOOT. The recommended bootstrap capacitor is
0.47 µF and rated at 6.3 V or greater. The bootstrap capacitor is located between the SW pin and the CBOOT
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pin. The bootstrap capacitor must be a high-quality ceramic type with X7R or X5R grade dielectric for
temperature stability.
8.2.2.8 VCC Capacitor
The VCC pin is the output of an internal LDO for TPS7H4010-SEP. The input for this LDO comes from either VIN
or BIAS pin voltage. The recommended CVCC capacitor is 2.2 µF and rated at 6.3 V or greater. It must be a high-
quality ceramic type with X7R or X5R grade to insure stability. Never short VCC pin to ground during operation.
8.2.2.9 BIAS
Because VOUT = 5 V in this design, the BIAS pin is tied to VOUT to reduce LDO power loss. The output voltage is
supplying the LDO current instead of the input voltage. The power saving is ILDO × (VIN – VOUT). The power
saving is more significant when VIN >> VOUT and with higher frequency operation. To prevent VOUT noise and
transients from coupling to BIAS, a series resistor, 1 Ω to 10 Ω, may be added between VOUT and BIAS. A
bypass capacitor with a value of 1 μF or higher can be added close to the BIAS pin to filter noise.
8.2.2.10 Soft Start
The SS/TRK pin can be floating to start up following the internal soft-start ramp. In order to extend the soft-start
time, an external soft-start capacitor can be used. Use Equation 12 in order to calculate the soft-start capacitor
value.
With a desired soft-start time tSS = 11 ms, a soft-start charging current of ISSC = 2 µA (typical), and VFB = 1.006 V
(typical), Equation 12 yields a soft-start capacitor value of 22 nF.
8.2.2.11 Undervoltage Lockout Setpoint
The system undervoltage lockout (UVLO) is adjusted using the external voltage divider network of RENT and
RENB. With one selected RENT value, RENB can be found by Equation 10.
Note that the divider adds to supply quiescent current by VIN / (RENT + RENB). Small RENT and RENB values add
more quiescent current loss. However, large divider values make the node more sensitive to noise.
In this design, EN pin is tied to PVIN pin with a 100-kΩ resistor.
8.2.2.12 PGOOD
For this design, a 100-kΩ resistor is used to pull up PGOOD to VOUT
.
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8.2.3 Application Curves
100
95
90
85
80
75
70
65
60
55
50
100
95
90
85
80
75
70
65
60
55
50
VIN = 7 V
VIN = 12 V
VIN = 24 V
VIN = 7 V
VIN = 12 V
VIN = 24 V
0.001
0.01 0.02 0.05 0.1 0.2 0.5
Load Current (A)
1
2
3 456
0
0.6 1.2 1.8 2.4
3
Load Current (A)
3.6 4.2 4.8 5.4
6
VOUT = 5 V
fSW = 500 kHz
Auto Mode
VOUT = 5 V
fSW = 500 kHz
FPWM Mode
Figure 8-3. TPS7H4010-SEP Efficiency
Figure 8-4. TPS7H4010-SEP Efficiency
100
100
95
90
85
80
75
70
65
60
55
50
95
90
85
80
75
70
65
60
55
50
VIN = 7 V
VIN = 12 V
VIN = 24 V
VIN = 7 V
VIN = 12 V
VIN = 24 V
0.001
0.01 0.02 0.05 0.1 0.2 0.5
Load Current (A)
1
2
3 456
0
0.6 1.2 1.8 2.4
3
Load Current (A)
3.6 4.2 4.8 5.4
6
EFF_
EFF_
VOUT = 5 V
fSW = 1000 kHz
Auto Mode
VOUT = 5 V
fSW = 1000 kHz
FPWM Mode
Figure 8-5. TPS7H4010-SEP Efficiency
Figure 8-6. TPS7H4010-SEP Efficiency
100
100
95
90
85
80
75
70
65
60
55
50
95
90
85
80
75
70
65
60
55
50
VIN = 7 V
VIN = 12 V
VIN = 24 V
VIN = 7 V
VIN = 12 V
VIN = 24 V
0.001
0.01 0.02 0.05 0.1 0.2 0.5
Load Current (A)
1
2
3 456
0
0.6 1.2 1.8 2.4
3
Load Current (A)
3.6 4.2 4.8 5.4
6
EFF_
EFF_
VOUT = 5 V
fSW = 2200 kHz
Auto Mode
VOUT = 5 V
fSW = 2200 kHz
FPWM Mode
Figure 8-7. TPS7H4010-SEP Efficiency
Figure 8-8. TPS7H4010-SEP Efficiency
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5.2
5.16
5.12
5.08
5.04
5
5.1
5.08
5.06
5.04
5.02
5
4.96
4.92
4.88
4.84
4.8
4.98
4.96
4.94
4.92
4.9
VIN = 7 V
VIN = 12 V
VIN = 24 V
VIN = 7 V
VIN = 12 V
VIN = 24 V
0.001
0.010.02 0.05 0.1 0.2 0.5
Load Current (A)
1
2 3 45 7 10
0
0.6 1.2 1.8 2.4
3
Load Current (A)
3.6 4.2 4.8 5.4
6
VOUT = 5 V
fSW = 500 kHz
Auto Mode
VOUT = 5 V
fSW = 500 kHz
FPWM Mode
Figure 8-9. TPS7H4010-SEP Load and Line
Regulation
Figure 8-10. TPS7H4010-SEP Load and Line
Regulation
6
5.8
5.6
5.4
5.2
5
6
5.8
5.6
5.4
5.2
5
4.8
4.6
4.4
4.2
4.8
4.6
4.4
4.2
Load = 1.5mA
Load = 1A
Load = 3A
Load = 5A
Load = 1.5mA
Load = 1A
Load = 3A
Load = 5A
4
4
3.8
3.8
3.6
3.6
3.4
3.2
3.4
3.2
4
4.4
4.8
5.2
5.6
VIN (V)
6
6.4
6.8
4
4.4
4.8
5.2
5.6
VIN (V)
6
6.4
6.8
DO_5
DO_5
VOUT = 5 V
fSW = 2200 kHz
Auto Mode
VOUT = 5 V
fSW = 2200 kHz
FPWM Mode
Figure 8-11. TPS7H4010-SEP Dropout Curve
Figure 8-12. TPS7H4010-SEP Dropout Curve
6
5.8
5.6
5.4
5.2
5
6
5.8
5.6
5.4
5.2
5
4.8
4.6
4.4
4.2
4.8
4.6
4.4
4.2
Load = 1.5mA
Load = 1A
Load = 3A
Load = 5A
Load = 1.5mA
Load = 1A
Load = 3A
Load = 5A
4
4
3.8
3.8
3.6
3.6
3.4
3.2
3.4
3.2
4
4.4
4.8
5.2
5.6
VIN (V)
6
6.4
6.8
4
4.4
4.8
5.2
5.6
VIN (V)
6
6.4
6.8
DO_5
DO_5
VOUT = 5 V
fSW = 500 kHz
Auto Mode
VOUT = 5 V
fSW = 1000 kHz
Auto Mode
Figure 8-13. TPS7H4010-SEP Dropout Curve
Figure 8-14. TPS7H4010-SEP Dropout Curve
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3.5
3.4
3.3
3.2
3.1
3
13
12.8
12.6
12.4
12.2
12
11.8
11.6
11.4
11.2
11
2.9
2.8
2.7
2.6
2.5
Load = 1.5mA
Load = 1.5mA
Load = 1A
Load = 3A
Load = 5A
10.8
10.6
10.4
10.2
10
Load = 1A
Load = 3A
Load = 5A
11
11.4
11.8
12.2
12.6
VIN (V)
13
13.4
13.8
3.3
3.5
3.7
3.9
4.1
VIN (V)
4.3
4.5
4.7
4.9
DO_1
DO_3
VOUT = 12 V
fSW = 500 kHz
Auto Mode
VOUT = 3.3 V
fSW = 500 kHz
Auto Mode
Figure 8-16. TPS7H4010-SEP Dropout Curve
Figure 8-15. TPS7H4010-SEP Dropout Curve
IINDUCTOR
IINDUCTOR
(1 A/DIV)
(1 A/DIV)
VOUT Ripple
(20 mV/DIV)
VOUT Ripple
(20 mV/DIV)
VSW
VSW
(5 V/DIV)
(5 V/DIV)
Time (500 µs/DIV)
Time (2 µs/DIV)
VIN = 12 V
VOUT = 3.3 V
Auto Mode
fSW = 500 kHz
VIN = 12 V
VOUT = 3.3 V
FPWM Mode
fSW = 500 kHz
IOUT = 1 mA
IOUT = 1 mA
Figure 8-17. TPS7H4010-SEP Switching Waveform Figure 8-18. TPS7H4010-SEP Switching Waveform
and VOUT Ripple
and VOUT Ripple
IINDUCTOR
IINDUCTOR
(1 A/DIV)
(1 A/DIV)
VOUT Ripple
(20 mV/DIV)
VOUT Ripple
(20 mV/DIV)
VSW
(5 V/DIV)
VSW
(5 V/DIV)
Time (5 µs/DIV)
Time (5 µs/DIV)
VIN = 12 V
IOUT = 100 mA
VOUT = 3.3 V
Auto Mode
fSW = 500 kHz
VIN = 12 V
IOUT = 100 mA
VOUT = 3.3 V
FPWM Mode
fSW = 500 kHz
Figure 8-19. TPS7H4010-SEP Switching Waveform Figure 8-20. TPS7H4010-SEP Switching Waveform
and VOUT Ripple
and VOUT Ripple
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IINDUCTOR
IINDUCTOR
(2 A/DIV)
(1 A/DIV)
VOUT Ripple
(20 mV/DIV)
VOUT Ripple
(20 mV/DIV)
VSW
VSW
(5 V/DIV)
(5 V/DIV)
Time (2 µs/DIV)
Time (5 µs/DIV)
VIN = 12 V
IOUT = 6 A
VOUT = 3.3 V
Auto Mode
fSW = 500 kHz
VIN = 3.66 V
IOUT = 3 A
VOUT = 3.3 V fSW set at 500 kHz
Auto Mode
Figure 8-21. TPS7H4010-SEP Switching Waveform Figure 8-22. TPS7H4010-SEP Switching Waveform
and VOUT Ripple
at Dropout
IINDUCTOR
(2 A/DIV)
VOUT
(1 V/DIV)
VOUT
(1 V/DIV)
IINDUCTOR
(2 A/DIV)
VSW
(5 V/DIV)
VSW
(5 V/DIV)
Time (5 µs/DIV)
Time (50 ms/DIV)
VIN = 12 V
VOUT set at 3.3 V fSW set at 500 kHz
VIN = 12 V
VOUT = 3.3 V
fSW = 500 kHz
IOUT = 7.5 A VOUT droops to 2 V
Figure 8-24. TPS7H4010-SEP Short-Circuit Hiccup
Protection and Recovery
Figure 8-23. TPS7H4010-SEP Overcurrent Behavior
Enable
(5 V/DIV)
Enable
(5 V/DIV)
VOUT
(2 V/DIV)
VOUT
(2 V/DIV)
IINDUCTOR
IINDUCTOR
(2 A/DIV)
(2 A/DIV)
PGOOD
PGOOD
(10 V/DIV)
(10 V/DIV)
Time (2 ms/DIV)
Time (2 ms/DIV)
VIN = 12 V
VOUT = 3.3 V
FPWM Mode
fSW = 500 kHz
VIN = 12 V
VOUT = 3.3 V
Auto Mode
fSW = 500 kHz
IOUT= 200 mA
IOUT= 200 mA
Figure 8-25. TPS7H4010-SEP Soft Start With 200-
mA Load in FPWM Mode
Figure 8-26. TPS7H4010-SEP Soft Start With 200-
mA Load in Auto Mode
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Enable
(5 V/DIV)
Enable
(5 V/DIV)
VOUT
(2 V/DIV)
VOUT
(2 V/DIV)
IINDUCTOR
IINDUCTOR
(2 A/DIV)
(2 A/DIV)
PGOOD
PGOOD
(5 V/DIV)
(5 V/DIV)
Time (2 ms/DIV)
Time (2 ms/DIV)
VIN = 12 V
IOUT = 5 A
VOUT = 3.3 V
Auto Mode
fSW = 500 kHz
VIN = 12 V
VPRE-BIAS= 1.5 V
VOUT = 3.3 V
Auto Mode
fSW = 500 kHz
Figure 8-27. TPS7H4010-SEP Soft Start With 5-A
Load
Figure 8-28. TPS7H4010-SEP Soft Start With Pre-
Biased Output Voltage
IOUT
IOUT
(5 A/DIV)
(5 A/DIV)
IINDUCTOR
IINDUCTOR
(5 A/DIV)
(5 A/DIV)
VOUT
(200 mV/
DIV AC)
VOUT
(200 mV/
DIV AC)
Time (200 µs/DIV)
Time (200 µs/DIV)
VIN = 12 V
VOUT = 3.3 V
fSW = 500 kHz
Auto Mode
VIN = 12 V
VOUT = 3.3 V
fSW = 500 kHz
FPWM Mode
IOUT = 10 mA to 6 A to 10 mA
IOUT = 10 mA to 6 A to 10 mA
Figure 8-29. TPS7H4010-SEP Load Transients
Figure 8-30. TPS7H4010-SEP Load Transients
IOUT
IOUT
(5 A/DIV)
(5 A/DIV)
IINDUCTOR
IINDUCTOR
(5 A/DIV)
(5 A/DIV)
VOUT
VOUT
(500 mV/
DIV AC)
(500 mV/
DIV AC)
Time (200 µs/DIV)
Time (200 µs/DIV)
VIN = 12 V
VOUT = 5 V
fSW = 2200 kHz
Auto Mode
VIN = 12 V
VOUT = 5 V
fSW = 2200 kHz
FPWM Mode
IOUT = 10 mA to 5 A to 10 mA
IOUT = 10 mA to 5 A to 10 mA
Figure 8-31. TPS7H4010-SEP Load Transients
Figure 8-32. TPS7H4010-SEP Load Transients
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9 Power Supply Recommendations
The TPS7H4010-SEP is designed to operate from an input voltage supply range from 3.5 V to 32 V. This input
supply must be able to withstand the maximum input current and maintain a voltage above 3.5 V at the PVIN pin.
The resistance of the input supply rail must be low enough that an input current transient does not cause a high
enough drop at the TPS7H4010-SEP supply voltage that can cause a false UVLO fault triggering and system
reset. If the input supply is located more than a few inches from the TPS7H4010-SEP, additional bulk
capacitance may be required in addition to the ceramic bypass capacitors. A 47-μF or 100-μF electrolytic
capacitor is a typical choice.
10 Layout
10.1 Layout Guidelines
The performance of any switching converter depends heavily upon the layout of the PCB. Use the following
guidelines to design a PCB layout with optimum power conversion performance, EMI performance, and thermal
performance.
1. Place ceramic high frequency bypass capacitors as close as possible to the PVIN and PGND pins, which are
right next to each other on the package. Place the small value ceramic capacitor closest to the pins. This is
very important for EMI performance.
2. Use short and wide traces, or localized IC layer planes, for high current paths, such as VIN, VOUT, SW, and
GND connections. Short and wide copper traces reduce power loss and noise due to low parasitic resistance
and inductance. Wide copper traces also help reduce die temperature, because they also provide wide heat
dissipation paths. Use thick copper (2 oz) on high current layer(s) if possible.
3. Confine pulsing current paths (VIN, SW, and ground return for VIN) on the device layer as much as possible to
prevent switching noises from contaminating other layers.
4. CBOOT capacitor also contains pulsing current. Place CBOOT close to the pin and route to SW with short trace.
The pinout of the device makes it easy to optimize the CBOOT placement and routing.
5. Use a solid ground plane at the layer right underneath the device as a noise shielding and heat dissipation
path.
6. Place the VCC bypass capacitor close to the VCC pin. Tie the ground pad of the capacitor to the ground
plane using a via right next to it.
7. Use via next to AGND pin to the ground plane.
8. Minimize trace length to the FB pin. Both feedback resistors must be located right next to the FB pin. Tie the
ground side of RFBB to the ground plane with a via right next to it. Place CFF directly in parallel with RFBT if
used.
9. If VOUT accuracy at the load is important, make sure the VOUT sense point is made close to the load. Route
VOUT sense to RFBT through a path away from noisy nodes and preferably on a layer on the other side of the
ground plane. If BIAS is connected to VOUT, do not use the same trace to route VOUT to BIAS and to RFBT
.
BIAS current contains pulsing driver current and it changes with operating mode. Use separated traces for
BIAS and VOUT sense to optimize VOUT regulation accuracy.
10.Provide adequate device heat sinking. Use an array of heat-sinking vias to connect the exposed pad to the
ground plane and the bottom PCB layer. Connect the DAP and NC pins on the short sides of the device to
the GND net, so that IC layer ground copper can provide an optimal dog-bone shape heat sink. Heat
generated on the die can flow directly from device junction to the DAP then to the copper and spread to the
wider copper outside of the device. Try to keep copper area solid on the top and bottom layer around thermal
vias on the DAP to optimize heat dissipation.
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10.1.1 Layout For EMI Reduction
To optimize EMI performance, place the components in the high di/dt current path, as shown in Figure 10-1, as
close as possible to each other. When the components are close to each other, the area of the loop enclosed by
these components, and the parasitic inductance of this loop, are minimized. The noises generated by the pulsing
current and parasitic inductances are then minimized.
BUCK
CONVERTER
L
VIN
VIN
CIN
SW
VOUT
COUT
PGND
PGND
High di/dt current
Figure 10-1. Pulsing Current Path of Buck Converter
In a buck converter, the high di/dt current path is composed of the HS and LS MOSFETs and the input
capacitors. Because the two MOSFETs are integrated inside the device, they are closer to each other than in
discrete solutions. PVIN and PGND pins are the connections from the MOSFETs to the input capacitors. The first
step of the layout must be placing the input capacitors, especially the small value ceramic bypass one, as close
as possible to PVIN and PGND pins.
The TPS7H4010-SEP pinout is optimized for low EMI layout. Multiple pins are used for PVIN and PGND to
minimized bond wire resistances and inductances. The PVIN and PGND pins are right next to each other to
simplify optimal layout. The CBOOT pin is placed next to SW pin for easy and compact CBOOT capacitor layout.
10.1.2 Ground Plane
The ground plane of a PCB provides the best return path for the pulsing current on the device layer. Make sure
the ground plane is solid, especially the part right underneath the pulsing current paths. Solid copper under a
pulsing current path provide a mirrored return path for the high frequency components and minimize voltage
spikes generated by the pulsing current. It shields the layers on the other side of the plane from switching
noises. Route signal traces on the other side of the ground plane as much as possible. Use multiple vias in
parallel to connect the grounds on the device layer to the ground plane.
10.1.3 Optimize Thermal Performance
The key to thermal optimization on PCB design is to provide heat transferring paths from the device to the outer
large copper area. Use thick copper (2 oz) on high current layer(s) if possible. Use thermal vias under the DAP
to transfer heat to other layers. Connect NC pins to the GND net, so that GND copper can run underneath the
device to create dog-bone shape heat sink. Try to leave copper solid on IC side as much as possible above and
below the device. Place components and route traces away from major heat transferring paths if possible, to
avoid blocking heat dissipation path. Try to leave copper solid, free of components and traces, around the
thermal vias on the other side of the board as well. Solid copper behaves as heat sink to spread the heat to a
larger area and provide more contact area to the air.
When calculating power dissipation, use the maximum input voltage and the average output current for the
application. Many common operating conditions are provided in Application Curves section. Less common
applications can be derived through interpolation. In all designs, the junction temperature must be kept below the
rated maximum of 125°C.
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The thermal characteristics of the TPS7H4010-SEP are specified using the parameter RθJA, which characterize
thermal resistance from the junction of the silicon to the ambient in a specific system. Although the value of RθJA
is dependent on many variables, it still can be used to approximate the operating junction temperature of the
device. To obtain an estimate of the device junction temperature, one may use Equation 30:
TJ = PIC_LOSS × RθJA + TA
(30)
where
•
•
•
•
•
TJ = junction temperature in °C
PIC_LOSS = VIN × IIN × (1 − Efficiency) − 1.1 × IOUT × DCR
DCR = inductor DC parasitic resistance in Ω
RθJA = junction-to-ambient thermal resistance of the device in °C/W
TA = ambient temperature in °C.
The maximum operating junction temperature of the TPS7H4010-SEP is 125°C. RθJA is highly related to PCB
size and layout, as well as environmental factors such as heat sinking and air flow. Figure 10-2 shows measured
results of R θJA with different copper area on 2-layer boards and 4-layer boards, with 1-W and 2-W power
dissipation on the TPS7H4010-SEP.
30
1W @0 fpm - 2layer
28
1W @0 fpm - 4layer
26
2W @0 fpm - 2layer
2W @0 fpm - 4layer
24
22
20
18
16
14
12
10
30mm × 30mm
40mm × 40mm
50mm × 50mm
70mm ×70mm
Copper Area
Figure 10-2. Measured RθJA vs PCB Copper Area on 2-Layer Boards and 4-Layer Boards
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10.2 Layout Example
A layout example is shown in Figure 10-3. A four-layer board is used with 2-oz copper on the top and bottom
layers and 1-oz copper on the inner two layers. Figure 10-3 shows the relative scale of the TPS7H4010-SEP
device with 0805 and 1210 input and output capacitors, 7-mm × 7-mm inductor and 0603 case size for all other
passive components. The trace width of the signal connections are not to scale.
The components are placed on the top layer and the high current paths are routed on the top layer as well. The
remaining space on the top layer can be filled with GND polygon. Thermal vias are used under the DAP and
around the device. The GND copper was extended to the outside of the device, which serves as copper heat
sink.
The mid-layer 1 is right underneath the top layer. It is a solid ground plane, which serves as noise shielding and
heat dissipation path.
The VOUT sense trace is routed on the 3rd layer, which is mid-layer 2. Ground plane provided noise shielding for
the sense trace. The VOUT to BIAS connection is routed by a separate trace.
The bottom layer is also a solid ground copper in this example. Solid copper provides best heat sinking for the
device. If components and traces need to be on the bottom layer, leave the area around thermal vias as solid as
possible. Try not to cut heat dissipation path by a trace. The board can be used for various frequencies and
output voltages, with component variation. For more details, see the TPS7H4010-SEP EVM User's Guide.
Figure 10-3. TPS7H4010-SEP Layout Example
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
11.2 Related Documentation
For related documentation see the following:
•
•
•
•
•
Texas Instruments, TPS7H4010EVM User's Guide
Texas Instruments, TPS7H4010-SEP Total Ionizing Dose (TID) radiation report
Texas Instruments, TPS7H4010-SEP Neutron Displacement Damage Characterization radiation report
Texas Instruments, TPS7H4010-SEP Single-Event Effects Test Report radiation report
Texas Instruments, AN-2020 Thermal Design By Insight, Not Hindsight
11.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
11.4 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
11.5 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
11.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
11.7 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2020 Texas Instruments Incorporated
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41
Product Folder Links: TPS7H4010-SEP
PACKAGE OPTION ADDENDUM
www.ti.com
18-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPS7H4010MRNPSEP
TPS7H4010MRNPTSEP
PREVIEW
ACTIVE
WQFN
WQFN
RNP
RNP
30
30
250
250
TBD
Call TI
Call TI
-55 to 125
-55 to 125
RoHS & Green
NIPDAUAG
Level-3-260C-168 HR
PS7H4010
RNPSEP
V62/19623-01XE
ACTIVE
WQFN
RNP
30
250
RoHS & Green
NIPDAUAG
Level-3-260C-168 HR
-55 to 125
PS7H4010
RNPSEP
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
18-Dec-2020
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Dec-2020
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS7H4010MRNPTSEP WQFN
RNP
30
250
180.0
16.4
4.25
6.25
0.95
8.0
16.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Dec-2020
*All dimensions are nominal
Device
Package Type Package Drawing Pins
WQFN RNP 30
SPQ
Length (mm) Width (mm) Height (mm)
195.0 200.0 45.0
TPS7H4010MRNPTSEP
250
Pack Materials-Page 2
PACKAGE OUTLINE
RNP0030A
WQFN - 0.8 mm max height
S
C
A
L
E
2
.
7
0
0
PLASTIC QUAD FLATPACK - NO LEAD
4.1
3.9
B
A
PIN 1 INDEX AREA
6.1
5.9
0.1 MIN
(0.05)
E
SCAL
C
T
SECTION A-A
TYPICAL
0.8
0.7
C
SEATING PLANE
0.08
0.05
0.00
2.2 0.1
2X 1.5
(0.2) TYP
EXPOSED
THERMAL PAD
12
15
26X 0.5
11
16
SYMM
A
A
4.6 0.1
2X
5
1
26
0.3
PIN 1 ID
(OPTIONAL)
30
27
30X
0.2
0.1
0.05
SYMM
0.5
0.3
8X
C A B
0.65
0.45
22X
4222145/C 02/2018
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
RNP0030A
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(2.2)
SYMM
8X (0.6)
30
27
22X (0.75)
1
26
30X (0.25)
2X
(2.05)
(0.5) TYP
SYMM
(5.8)
(4.6)
6X
(1.16)
(R0.05) TYP
16
11
(
0.2) TYP
VIA
12
15
6X (0.85)
(3.65)
LAND PATTERN EXAMPLE
SCALE:15X
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
SOLDER MASK
DEFINED
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4222145/C 02/2018
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
www.ti.com
EXAMPLE STENCIL DESIGN
RNP0030A
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
SYMM
(0.59) TYP
30
8X (0.6)
27
22X (0.75)
1
26
30X (0.25)
26X (0.5)
(1.16)
TYP
(0.58)
TYP
SYMM
(5.8)
METAL
TYP
8X (0.96)
16
11
(R0.05) TYP
12
15
8X (0.98)
(3.65)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD
74.4% PRINTED SOLDER COVERAGE BY AREA
SCALE:20X
4222145/C 02/2018
NOTES: (continued)
5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you
permission to use these resources only for development of an application that uses the TI products described in the resource. Other
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TI’s products are provided subject to TI’s Terms of Sale (www.ti.com/legal/termsofsale.html) or other applicable terms available either on
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Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2020, Texas Instruments Incorporated
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