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TPS80032

SWCS059I –MARCH 2011–REVISED NOVEMBER 2014

TPS80032 Fully Integrated Power Management With Power Path and Battery Charger

1 Device Overview

• Control:

1.1 Features

– Configurable Power-Up and Power-Down

Sequences (OTP Memory)

1

• Five Highly Efficient Buck Converters

– Configurable Sequences Between SLEEP and

ACTIVE States (OTP Memory)

– One 3 MHz, 0.6 to 2.1 V at 5.0 A, DVS-Capable

– One 6 MHz, 0.6 to 2.1 V at 2.5 A, DVS-Capable

– Three Digital Output Signals that can be

Included in the Startup Sequence to Control

External Devices

– Three 6 MHz, 0.6 to 2.1 V at 1.1 A, One Being

DVS-Capable

• 11 General-Purpose Low-Dropout Voltage

Regulators (LDOs)

– Two Inter-Integrated Circuit (I²C) Interfaces

– All Resources Configurable by I²C

– Six 1.0 to 3.3 V at 0.2 A with Battery or

Preregulated Supply:

• System Voltage Regulator/Battery Charger with

Power Path from USB:

•

One can be Used as Vibrator Driver

One 1.0 to 3.3 V at 50 mA with Battery or

Preregulated Supply

– Input Current Limit to Comply with USB

Standard

– 3-MHz Switched-Mode Regulator with

Integrated Power FET for up to 2.0-A Current

– Dedicated Control Loop for Battery Current and

Voltage

– External Low-Ohmic FET for Power Path and

Battery Charging

– Boost Mode Operation for USB OTG

– Supplement Mode to Deliver Current from

Battery During Power Path Operation

– Charger for Single-Cell Li-Ion and Li-Polymer

Battery Packs

– Safety Timer and Reset Control

– Thermal Protection

– Input/Output Overvoltage Protection

– Charging Indicator LED Driver

– Compliant with:

•

One Low-Noise 1.0 to 3.3 V at 50 mA with

Battery or Preregulated Supply

•

One 3.3 V at 100 mA USB LDO

Two LDOs for TPS80032 Internal Use

• USB OTG Module:

– ID Detection, Accessory Charger Adapter (ACA)

Support

– Accessory Detection Protocol (ADP) Support

• Backup Battery Charger

• 12-bit Sigma-Delta Analog-to-Digital Converter

(ADC) with 19 Input Channels:

– Seven External Input Channels

• 13-bit Coulomb Counter with Four Programmable

Integration Periods

• Low-Power Consumption:

– 8 µA in BACKUP State

– 20 µA in WAIT-ON State

– 110 µA in SLEEP State, with Two DC-DCs

Active

• Real-Time Clock (RTC) with Timer and Alarm

Wake-Up:

– Three Buffered 32-kHz Outputs

• SIM and SD/MMC Card Detections

• Two Digital PWM Outputs

• Thermal Monitoring:

•

USB 2.0

OTG and EH 2.0

USB Battery Charging 1.2

YD/T 1591-2006

Japanese Battery Charging Guidelines

(JEITA)

• Battery Voltage Range from 2.5 to 5.5 V

• Package 5.21 mm × 5.36 mm 155-pin WCSP

– High-Temperature Warning

– Thermal Shutdown

1.2 Applications

•

Mobile Phones and Smart Phones

Tablets

•

Handheld Devices

Industrial Applications

Gaming Handsets

Portable Media Players

Portable Navigation Systems

•

1

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCT PREVIEW Information. Product in design phase of

development. Subject to change or discontinuance without notice.

TPS80032

SWCS059I –MARCH 2011–REVISED NOVEMBER 2014

www.ti.com

1.3 Description

The TPS80032 device is an integrated power-management integrated circuit (PMIC) for applications

powered by a rechargeable battery. The device provides five configurable step-down converters with up to

5.0-A current capability for memory, processor core, I/O, auxiliary, preregulation for LDOs, and so forth.

The device also contains nine LDO regulators for external use that can be supplied from a battery or a

preregulated supply. The power-up/power-down controller is configurable and can support any power-

up/power-down sequence (programmed in OTP memory). The RTC provides three 32-kHz clock outputs:

seconds, minutes, hours, day, month, and year information; as well as alarm wakeup and timer. The

TPS80032 device supports 32-kHz clock generation based on a crystal oscillator.

The device integrates a switched-mode system supply regulator from a USB connector. The device

includes power paths from the USB and battery with supplemental mode for immediate startup, even with

an empty battery. The battery switch uses an external low-ohmic PMOS transistor allowing minimal serial

resistance during fast charging and when operating from battery. The device can also be used without the

external PMOS transistor; the battery is then always tied to the system supply and the switched-mode

regulator is used for battery charging.

The TPS80032 device is available in a 155-pin WCSP package, 5.21 mm × 5.36 mm with a 0.4-mm ball

pitch.

Device Information⁽¹⁾

PART NUMBER

PACKAGE

BODY SIZE

TPS80032

YFF (155)

5.21 mm × 5.36 mm

(1) For more information, see Section 8, Mechanical Packaging and Orderable Information.

2

Device Overview

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SWCS059I –MARCH 2011–REVISED NOVEMBER 2014

1.4 Functional Block Diagram

Figure 1-1 shows the TPS80032 device block diagram.

VSYS

C23

C24

C3

C44

C18

VSYS

C1

C2

BOOT0

BOOT1

BOOT2

Boot mode

selection

SMPS1

System

voltage

monitoring

Test

and

program

VANA

VRTC

RPWRON

PWRON

Control

inputs

PREQ2

PREQ3

External

power request

SMPS5

SMPS3

SMPS4

SMPS2

PREQ1

MSECURE

NRESWARM

CTLI2C_SCL

CTLI2C_SDA

DVSI2C_SCL

DVSI2C_SDA

NRESPWRON

INT

BATREMOVAL

REGEN1

REGEN2

SYSEN

PWM1

PWM2

OSC32KIN

OSC32KOUT

OSC32KCAP

CLK32KAO

CLK32KG

CLK32KAUDIO

Switched

mode

system

supply

regulator

GPADC_IN0

GPADC_IN1

GPADC_IN2

GPADC_IN3

GPADC_IN4

GPADC_IN5

GPADC_IN6

GPADC_VREF

GPADC_START

Linear charger

and

supplement

mode

and

Coulomb

counter

MMC

SIM

Detectors

USB ACA

ID

IREF

VBG

Reference

and

bias

REFGND

Charger

control

PBKG

GND_ANA

GND_DIG_VIO

Grounds

GND_DIG_VRTC

LED

indicator

LDOLN

LDO1

LDO2

LDO3

LDO4

LDO5

LDO6

LDO7

LDOUSB

Figure 1-1. TPS80032 Device Block Diagram

Device Overview

3

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SWCS059I –MARCH 2011–REVISED NOVEMBER 2014

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Table of Contents

1

Device Overview ......................................... 1

1.1 Features .............................................. 1

1.2 Applications........................................... 1

1.3 Description............................................ 2

1.4 Functional Block Diagram ............................ 3

Revision History ......................................... 5

Terminal Configuration and Functions.............. 6

3.1 Pin Diagram .......................................... 6

3.2 Pin Attributes ......................................... 7

Specifications ........................................... 12

4.1 Absolute Maximum Ratings......................... 12

4.2 Handling Ratings.................................... 12

4.3 Recommended Operating Conditions............... 12

5.9 Battery Charging .................................... 61

5.10 USB OTG............................................ 92

5.11 Gas Gauge......................................... 100

5.12 General-Purpose ADC ............................. 102

5.13 Vibrator Driver and PWM Signals ................. 107

5.14 Detection Features................................. 108

5.15 Thermal Monitoring ................................ 109

5.16 I²C Interface ....................................... 110

5.17 Secure Registers .................................. 110

5.18 Access Protocol.................................... 111

5.19 Interrupts ........................................... 112

Recommended External Components............ 115

Device and Documentation Support.............. 117

7.1 Device Support..................................... 117

7.2 Community Resources............................. 117

7.3 Trademarks ........................................ 117

7.4 Electrostatic Discharge Caution ................... 118

7.5 Export Control Notice .............................. 118

7.6 Glossary............................................ 118

7.7 Additional Acronyms ............................... 118

7.8 Detailed Revision History .......................... 118

2

3

4

6

7

4.4

Thermal Characteristics for YFF Package .......... 13

4.5 Electrical Characteristics ............................ 14

4.6 Typical Characteristics .............................. 41

Detailed Description ................................... 42

5.1 Real-Time Clock .................................... 42

5.2 Clocks ............................................... 43

5.3 Power Management................................. 43

5.4 Reset System ....................................... 50

5.5 System Control...................................... 52

5

8

Mechanical Packaging and Orderable

Information............................................. 121

8.1 Packaging Information ............................. 121

5.6

System Voltage/Battery Comparator Thresholds ... 56

5.7 Power Resources ................................... 56

5.8 Backup Battery Charger ............................ 61

4

Table of Contents

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SWCS059I –MARCH 2011–REVISED NOVEMBER 2014

2 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

For a more detailed list of revision notes, see Section 7.8.

Changes from Revision H (August 2012) to Revision I

Page

•

Changed data sheet to standard TI format........................................................................................ 1

Revision History

5

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SWCS059I –MARCH 2011–REVISED NOVEMBER 2014

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3 Terminal Configuration and Functions

3.1 Pin Diagram

Figure 3-1 shows the TPS80032 device bottom view ball mapping.

1

2

3

4

5

6

7

8

9

10

11

12

13

N

M

L

PBKG

SMPS1_SW

SMPS1_GND

SMPS5_IN

SMPS5_SW

LDO2

LDO3

LDO4

SMPS3_SW

SMPS3_IN

SMPS2_GND

SMPS2_SW

PBKG

N

M

L

SMPS3

_GND

SMPS3

_GND

SMPS1_IN

REGEN2

SMPS1_SW

PWRON

SMPS1_GND

SMPS5_IN

SMPS5_GND SMPS5_GND

LDO3_IN

SMPS3_IN

SMPS2_GND

SMPS2_SW

PWM1

SMPS2_IN

SMPS5

_FDBK

GND_DIG

_VIO

GPADC

_START

SMPS3

_FDBK

VDD

LDO2_IN

PREQ2

LDO4_IN

GND_ANA

CLK32KAO

SIM

SMPS2

_FDBK

K

J

MSECURE

SYSEN

INT

CLK32KG

MMC

PWM2

K

J

NRES

PWRON

BAT

REMOVAL

CTLI2C_SCL CTLI2C_SDA

DVSI2C_SCL

DVSI2C_SDA

SMPS4_IN

SMPS4_SW

SMPS4_IN

SMPS1

_FDBK

H

G

F

RPWRON

REGEN1

NRESWARM

PREQ3

VBACKUP

BOOT2

PREQ1

GND_ANA

REFGND

VRTC_IN

VIO

GPADC_IN5

VBG

SMPS4_SW

H

G

F

CHRG_PROT

_GATE

GND_DIG

_VRTC

SMPS4

_FDBK

SMPS4

_GND

SMPS4

_GND

VDD

PBKG

ID

CHRG

_EXTCHRG

_STATZ

CHRG

_EXTCHRG

_ENZ

VBUS

_DET

LDO1

GND_ANA

VBUS

LDO1_IN

GPADC_IN6

LDO5_IN

LDOLN_IN

LDO6_IN

LDO5

LDOLN

LDO6

CHRG

_BOOT

E

D

C

B

A

TESTEN

BOOT1

BOOT0

IREF

VDD

E

D

C

B

A

CHRG

_CSOUT

GPADC

_IN1

GGAUGE

_RESP

GGAUGE

_RESN

CHRG_VREF

CHRG_PMID

CHRG_CSIN

CHRG_SW

VPROG

VAC

VRTC

GND_ANA

VDD

GPADC_IN0

VSYS_BB

CHRG

_GATE

_CTRL

CHRG

_PGND

CLK32K

AUDIO

VBUS

CHRG_SW

REFGND

LDO7_IN

OSC32KCAP

VANA_IN

CHRG_VSYS

GPADC_IN3

CHRG

_PGND

CHRG_LED

_TEST

GPADC

_VREF

CHRG

_VBAT

VBUS

OSC32KOUT

CHRG

_DET_N

CHRG

_PGND

CHRG_LED

_IN

PBKG

1

CHRG_PMID

2

CHRG_SW

3

LDOUSB

7

LDO7

8

OSC32KIN

9

VANA

10

GPADC_IN4

11

GPADC_IN2

12

TESTV

13

4

5

6

Figure 3-1. Bottom View Ball Mapping

6

Terminal Configuration and Functions

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SWCS059I –MARCH 2011–REVISED NOVEMBER 2014

3.2 Pin Attributes

Pin Attributes

PULLUP /

CONNECTION IF

PULLDOW

NOT USED

N

NAME

BALL

TYPE

I/O

DESCRIPTION

System Supply Regulator/Battery Charger

Switched-mode regulator boot-strapped

capacitor for the high-side MOSFET gate driver

CHRG_BOOT

CHRG_CSIN

E2

D4

Analog

O

I

Floating

Ground

–

Switched-mode regulator current-sense input

(without power path)

Switched regulator auxiliary power supply,

connected to the system supply/battery to

provide power in high-impedance mode,

switched regulator system/battery voltage/current

sense input

CHRG_CSOUT

CHRG_DET_N

D5

Analog

I

System supply

–

USB charging port detection signal from USB

PHY

A4

F4

Analog

Digital

I

Ground

Floating

–

CHRG_EXTCHRG_EN

Z

Output control signal to an external VAC charger

(default high)

O

PU

70 to 190

kΩ

CHRG_EXTCHRG_ST

ATZ

F3

Digital

I

External VAC charger status input pin

Floating

CHRG_LED_IN

A6

B6

Power

Analog

I

Input supply for LED indicator

External LED driver output

Ground

–

CHRG_LED_TEST

I/O

A5,

B5,

C5

CHRG_PGND

CHRG_PMID

Ground

Analog

I

Switched regulator power ground

Ground

Floating

–

A2,

B2,

C2

Switched regulator connection point between

reverse blocking MOSFET and high-side

switching MOSFET

O

A3,

B3,

C3,

B4,

C4

CHRG_SW

Power

O

Switched regulator output for inductor connection

Floating

–

CHRG_VREF

VAC

D2

C6

Analog

Power

O

I

Switched regulator internal bias regulator voltage

VAC charger input sense line

Floating

Ground

–

Ground (must be

connected to

B1,

C1,

D1

VBUS if VBUS

detection from

PMIC is needed;

for example, USB

boot up)

VBUS input, USB system supply/battery charger

power supply

VBUS

Power

I/O

–

CHRG_VSYS

CHRG_VBAT

VBUS_DET

C12

B13

F7

Power

Digital

I

System supply

Floating

–

I/O

O

Battery voltage for battery charging

VBUS detection signal (VSYS level)

Control signal for gate of external PMOS (battery

switch)

CHRG_GATE_CTRL

C13

G1

Analog

O

Floating

–

Control signal for gate of external PMOS to

protect against negative input voltage (optional)

CHRG_PROT_GATE

Power Supplies

C7,

E1,

GND_ANA

Ground

I

Analog power ground

Ground

–

H8, L9

GND_DIG_VIO

L7

Ground

I

VIO digital ground

Ground

–

GND_DIG_VRTC

G3

VRTC digital ground

Terminal Configuration and Functions

7

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Pin Attributes (continued)

PULLUP /

PULLDOW

N

CONNECTION IF

NOT USED

NAME

BALL

TYPE

Substrate

Power

I/O

DESCRIPTION

A1,

G4,

N1,

N13

PBKG

VDD

I

Substrate ground

Ground

–

B7,

E11,

Analog input voltage supply

System supply

–

G2, L5

VIO

H10

D6

Power

Analog

Power

I

The PMIC digital I/O input supply voltage (1.8 V)

OTP memory programming voltage

Backup battery connection

N/A

Ground

–

VPROG

VBACKUP

VSYS_BB

Clocking

G6

Ground

C11

Sense line for system supply

System supply

32-kHz digital output clock always on when VIO

input supply is present

CLK32KAO

CLK32KAUDIO

CLK32KG

K9

C9

K8

Digital

Analog

O

I

Floating

–

32-kHz digital gated output clock (for example,

for audio device)

32-kHz digital gated output clock controlled by

software

Floating

VRTC power supply external filtering capacitor

for the 32-kHz crystal oscillator

OSC32KCAP

OSC32KIN

C10

A9

Floating

32-kHz crystal oscillator input or digital clock

input

N/A

32-kHz crystal oscillator output or floating in case

of digital clock input

OSC32KOUT

B9

O

N/A or floating

References

IREF

E10

Analog

Ground

Analog

I/O

I

Reference current generation

System reference ground

N/A

Ground

N/A

–

C8,

G8

REFGND

VBG

F10

O

Band-gap output reference voltage

Testing

PD

170 to 950

kΩ

TESTEN

E3

Digital

I

Test mode enable

Ground

Floating

TESTV

A13

Analog

O

Internal voltages sense line

–

System Control

PPU

1.46 to 7.4

kΩ

CTLI2C_SCL

CTLI2C_SDA

J3

J4

Digital

I

Control I²C serial clock (external pullup)

N/A

PPU

1.46 to 7.4

kΩ

Control I²C serial bidirectional data (an external

pullup)

I/O

INT

K7

J10

E4

D3

F6

Digital

O

I

Maskable interrupt request to the host processor

Battery removal indicator

N/A

–

BATREMOVAL

BOOT0

Floating

Boot ball 0 for power-up sequence selection

Boot ball 1 for power-up sequence selection

Boot ball 2 for power-up sequence selection

System reset/power-on output

Ground or VRTC

Floating

BOOT1

I

BOOT2

I

NRESPWRON

J5

O

PU

70 to 190

kΩ

NRESWARM

PREQ1

H4

H7

Digital

I

Warm reset input

Floating

PPU/*PPD

170 to 950

kΩ

Power request input 1

8

Terminal Configuration and Functions

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SWCS059I –MARCH 2011–REVISED NOVEMBER 2014

Pin Attributes (continued)

PULLUP /

CONNECTION IF

PULLDOW

NOT USED

N

NAME

BALL

K6

TYPE

Digital

I/O

DESCRIPTION

PPU/*PPD

PREQ2

PREQ3

I

Power request input 2

Power request input 3

Floating

170 to 950

kΩ

PPU/*PPD

170 to 950

kΩ

H6

PWM1

PWM2

K12

K11

Digital

O

Pulse width modulation/general-purpose output 1

Pulse width modulation/general-purpose output 2

Floating

–

PU

55 to 370

kΩ

External on-button switch-on event (primary input

to launch system wakeup)

PWRON

J2

Digital

I

N/A

REGEN1

REGEN2

H3

J1

Digital

O

External regulator enable 1

External regulator enable 2

Floating

–

PU

55 to 370

kΩ

External remote switch-on event (secondary

input to launch system wakeup)

RPWRON

SYSEN

H2

K5

K4

Digital

I

O

I

Floating

External system enable

–

PD

Secure mode input. Allows I²C access to secure

registers

MSECURE

Ground or floating 170 to 950

kΩ

PPU

1.46 to 7.4

DVSI2C_SCL

DVSI2C_SDA

J11

Digital

I

DVS I²C serial clock (external pullup)

DVS I²C serial data (external pullup)

N/A

kΩ

PPU

1.46 to 7.4

kΩ

H11

Analog

I/O

Detection

ID

G7

Digital

I/O

I

USB connector identification signal

Floating

–

PPU/*PPD

70 to 190

kΩ

MMC card insertion and extraction detection to

deactivate the LDO5 regulator

MMC

SIM

K10

PPU/*PPD

70 to 190

kΩ

SIM card insertion and extraction detection to

deactivate the LDO7 regulator

J9

Power

I

Floating

LDO Regulators

VANA

A10

B10

N6

L6

Power

O

I

Output voltage for VANA regulator

Input voltage supply for VANA regulator

Output voltage for LDO2 regulator

Input voltage supply for LDO2 regulator

Output voltage for LDO4 regulator

Input voltage supply for LDO4 regulator

N/A

–

VANA_IN

LDO2

System supply

Floating

O

I

LDO2_IN

LDO4

System supply

Floating

N8

L8

O

I

LDO4_IN

System supply

Output voltage for LDO3 regulator (vibrator driver

output)

LDO3

N7

Power

O

Floating

–

LDO3_IN

LDO6

M7

D13

D12

E13

E12

F13

F12

F1

Power

I

O

I

Input voltage supply for LDO3 regulator

Output voltage for LDO6 regulator

Input voltage supply for LDO6 regulator

Output voltage for LDOLN regulator

Input voltage supply for LDOLN regulator

Output voltage for LDO5 regulator

Input voltage supply for LDO5 regulator

Output voltage for LDO1 regulator

Input voltage supply for LDO1 regulator

System supply

Floating

–

LDO6_IN

LDOLN

LDOLN_IN

LDO5

System supply

Floating

O

I

System supply

Floating

O

I

LDO5_IN

LDO1

System supply

Floating

O

I

LDO1_IN

F2

System supply

Terminal Configuration and Functions

9

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Pin Attributes (continued)

PULLUP /

PULLDOW

N

CONNECTION IF

NOT USED

NAME

BALL

TYPE

I/O

DESCRIPTION

VRTC

D7

F8

A7

A8

B8

Power

O

I

Output voltage for VRTC regulator

Input voltage supply for VRTC regulator

Output voltage for LDOUSB regulator

Output voltage for LDO7 regulator

Input voltage supply for LDO7 regulator

N/A

–

VRTC_IN

LDOUSB

LDO7

System supply

Floating

O

I

Floating

LDO7_IN

Monitoring

System supply

Sense resistor input signal negative (ground

side)

GGAUGE_RESN

D10

Analog

I

Ground

–

NOTE: Shared with battery charger.

Sense resistor input signal positive (battery

negative side)

NOTE: Shared with battery charger.

GGAUGE_RESP

GPADC_IN0

D9

Analog

I

Ground

–

General-purpose analog-to-digital converter

(GPADC) input 0

D11

I/O

GPADC_IN1

GPADC_VREF

GPADC_IN2

GPADC_IN3

GPADC_IN4

GPADC_IN5

GPADC_IN6

D8

Analog

I/O

O

I

GPADC input 1

Ground

Floating

Ground

–

B11

A12

B12

A11

G10

F11

GPADC output reference voltage

GPADC input 2

I/O

I

GPADC input 3

GPADC input 4

GPADC input 5

I

GPADC input 6

*PPD

170 to 950

kΩ

Trigger hardware request to start GPADC

synchronous conversion

GPADC_START

L10

Digital

I

Ground

SMPS Regulators

SMPS4_FDBK

G11

Analog

Ground

I

SMPS4 feedback

SMPS4 ground

Ground

–

G12,

G13

SMPS4_GND

SMPS4_IN

J12,

J13

Power

I

SMPS4 input voltage

System supply

–

H12,

H13

SMPS4_SW

Power

Analog

Ground

O

I

SMPS4 switch

SMPS2 feedback

SMPS2 ground

Floating

Ground

–

SMPS2_FDBK

SMPS2_GND

K13

M11,

N11

I

L13,

M13

SMPS2_IN

Power

I

SMPS2 input voltage

SMPS2 switch

System supply

Floating

–

L12,

M12,

N12

SMPS2_SW

O

SMPS3_FDBK

SMPS3_GND

L11

Analog

Ground

I

SMPS3 feedback

SMPS3 ground

Ground

–

M8,

M9

M10,

N10

SMPS3_IN

Power

I

SMPS3 input voltage

System supply

–

SMPS3_SW

N9

H1

Power

Analog

O

I

SMPS3 switch

Floating

Ground

–

SMPS1_FDBK

SMPS1 feedback

K3,

L3,

M3,

N3

SMPS1_GND

Ground

I

SMPS1 ground

Ground

–

10

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Pin Attributes (continued)

PULLUP /

CONNECTION IF

PULLDOW

NOT USED

N

NAME

BALL

TYPE

I/O

DESCRIPTION

K1,

L1,

M1

SMPS1_IN

Power

I

SMPS1 input voltage

SMPS1 switch

System supply

–

K2,

L2,

M2,

N2

SMPS1_SW

Power

O

Floating

–

SMPS5_FDBK

SMPS5_GND

L4

Analog

Ground

I

SMPS5 feedback

SMPS5 ground

Ground

–

M5,

M6

M4,

N4

SMPS5_IN

Power

I

SMPS5 input voltage

SMPS5 switch

System supply

Floating

–

SMPS5_SW

N5

O

Terminal Configuration and Functions

11

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4 Specifications

4.1 Absolute Maximum Ratings

Over operating free-air temperature range (unless otherwise noted)

PARAMETER

MIN

MAX

UNIT

All battery and system supply related input balls (LDOs and SMPSs) and supply

voltage: _IN, VDD, VSYS_BB, CHRG_VSYS, CHRG_VBAT

–0.3

5.5

V

All SMPS-related input balls _FDBK

Backup battery supply voltage VBACKUP

I/O digital supply voltage VIO

–0.3

–0.7

–7.0

–0.3

SMPSmax + 0.3

V

5.5

VIOmax + 0.3

20.0

Battery charger supply voltage VBUS

Battery charger supply voltage VAC

Battery charger CHRG_PMID

20.0

Battery charger CHRG_SW, CHRG_BOOT

Voltage difference between CHRG_CSIN and CHRG_CSOUT inputs

Battery charger CHRG_VREF

20.0

7.0

6.5

Battery charger CHRG_DET_N

5.5

All other charger analog-related input balls, such as CHRG_CSIN, CHRG_CSOUT,

and CHRG_LED_IN

–0.3

5.5

V

Voltage on the USB OTG ID ball

–0.3

5.5

V

Voltage on the VRTC GPADC balls: GPADC_IN0, GPADC_IN1, and GPADC_IN4

VRTCmax + 0.3

Voltage on the VANA GPADC balls: GPADC_IN2, GPADC_IN3, GPADC_IN5, and

GPADC_IN6

–0.3

VANAmax + 0.3

VRTCmax + 0.3

VANAmax + 0.3

V

Voltage on the crystal oscillator OSC32KIN ball

Voltage on all other analog input balls such as GGAUGE_RESN and

GGAUGE_RESP

OTP memory supply voltage VPROG

Voltage on VRTC digital input balls

–0.3

–45

20.0

VRTCmax + 0.3

VIOmax + 0.3

VBATmax + 0.3

150.0

V

Voltage on VIO digital input balls

V

Voltage on VBAT digital input balls

V

Junction temperature range

°C

mA

Peak output current on all terminals other than power resources

–5.0

5.0

4.2 Handling Ratings

MIN

MAX

UNIT

T_stg

Storage temperature range

–65

150

°C

Human Body Model (HBM), per

ANSI/ESDA/JEDEC JS001⁽¹⁾

Charged Device Model (CDM), per JESD22-C101⁽²⁾

All pins

–1

1

kV

V

Electrostatic discharge

(ESD) performance:

V_ESD

–250

250

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

4.3 Recommended Operating Conditions

Over operating free-air temperature range (unless otherwise noted)

PARAMETER

MIN

NOM

MAX

UNIT

All battery and system supply related input balls (LDOs and SMPSs)

and supply voltage: _IN, VDD, VSYS_BB, CHRG_VSYS,

CHRG_VBAT

2.5

3.8

4.8

V

All SMPS-related input balls _FDBK

Backup battery supply voltage VBACKUP

I/O digital supply voltage VIO

V_OUTmin

1.9

V_OUTmax

4.8

V

3.2

VIO

5.0

VIOmin

0

VIOmax

6.7

Battery charger supply voltage VBUS

12

Specifications

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Recommended Operating Conditions (continued)

Over operating free-air temperature range (unless otherwise noted)

PARAMETER

MIN

0

NOM

5.0

MAX

10.0

6.0

UNIT

Battery charger supply voltage VAC

Battery charger CHRG_PMID

V

0

5.0

Battery charger CHRG_SW and CHRG_BOOT

Battery charger CHRG_VREF

0

5.0

6.0

0

5.0

6.5

Battery charger CHRG_DET_N

0

LDOUSB

4.8

All other charger analog-related input balls such as CHRG_CSIN,

CHRG_CSOUT, and CHRG_LED_IN

0

3.8

4.8

V

Voltage on the USB OTG ID ball

LDOUSB

VRTC

LDOUSBmax

VRTCmax

Voltage on the VRTC GPADC balls GPADC_IN0, GPADC_IN1, and

GPADC_IN4

Voltage on the VANA GPADC balls GPADC_IN2, GPADC_IN3,

GPADC_IN5, and GPADC_IN6

VANA

VRTC

VANA

VANAmax

VRTCmax

VANAmax

V

Voltage on the crystal oscillator OSC32KIN ball

Voltage on all other analog input balls such as GGAUGE_RESN and

GGAUGE_RESP

OTP memory supply voltage VPROG

Voltage on VRTC digital input balls

Voltage on VIO digital input balls

Voltage on VBAT digital input balls

Ambient temperature range

8.0

VRTC

VIO

3.8

10.0

VRTCmax

VIOmax

4.8

V

0

V

–40

–65

27

85

°C

Junction temperature (T_J)

27

125

Storage temperature range

27

150

Lead temperature (soldering, 10 seconds)

260

4.4 Thermal Characteristics for YFF Package

NAME

RΘ_JC

RΘ_JB

RΘ_JA

Psi_JT

Psi_JB

DESCRIPTION

(°C/W)⁽¹⁾

AIR FLOW (m/s)⁽²⁾

Junction-to-case (top)

Junction-to-board

Junction-to-free air

Junction-to-package top

Junction-to-board

0.1

19.0

37.7

0.7

0.00

18.6

(1) These values are based on a JEDEC-defined 2S2P system (with the exception of the Theta JC [RΘ_JC] value, which is based on a

JEDEC-defined 1S0P system) and will change based on environment as well as application. For more information, see these

EIA/JEDEC standards:

•

JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions - Natural Convection (Still Air)

JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages

JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages

JESD51-9, Test Boards for Area Array Surface Mount Package Thermal Measurements

The maximum power, 0.4 W, is at 85°C ambient temperature.

(2) m/s = meters per second

Specifications

13

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4.5 Electrical Characteristics

Over operating free-air temperature range (unless otherwise noted)

4.5.1 Switched-Mode Regulators

Table 4-1 through Table 4-3 lists the SMPS electrical characteristics.

Table 4-1. SMPS1 Switched-Mode Regulator Electrical Characteristics

PARAMETER

Input capacitor

TEST CONDITIONS

MIN

1.5

11

TYP

4.7

22

MAX

UNIT

C_I

µF

Output filter capacitor: (3-A mode)

Output filter capacitor: (5-A mode)

29

58

µF

22

44

C_O

Filter capacitor ESR

f = [1 to 10] MHz

1

10

20

mΩ

Filter inductor: (3-A mode)

Filter inductor: (5-A mode)

Single inductor

0.4

0.2

1.0

0.5

1.3

L_O

µH

0.65

Two inductors in parallel, total inductance (value

of single inductor)

0.2

(0.4)

0.5

(1.0)

Filter inductor: (5-A mode)

0.65 (1.3)

100

Filter inductor DC resistance

Filter inductor Q factor

50

mΩ

DCR_L

> 6 MHz

20

–

ILIMIT[1:0] = 00 (No current limitation)

ILIMIT[1:0] = 01 (2.0 A)

ILIMIT[1:0] = 10 (2.5 A)

ILIMIT[1:0] = 11 (3.0 A)

ILIMIT[1:0] = 00 (No current limitation)

ILIMIT[1:0] = 01 (3.3 A)

ILIMIT[1:0] = 10 (4.2 A)

ILIMIT[1:0] = 11 (5.0 A)

–

2800

3500

4100

–

3500

4350

5150

–

4200

5150

6200

–

NMOS current limit (high side)

(3.0-A mode)

mA

3900

4750

5600

4800

5900

6900

5800

7000

8200

NMOS current limit (high side)

(5-A mode)

mA

Input current limit under short-circuit

conditions

SW = 0 V

10

20

30

mA

V

max

(V_OUT

V_INF

Input voltage (functional)

VSYS

+

5.5

0.4, 2.3)

max

(V_OUT

MinDO

V, 2.5)

+

V_INP

Input voltage (performance)

VSYS

3.8

4.8

V

I_OUT= 2.0 A

I_OUT= 2.5 A

I_OUT= 3.0 A

I_OUT= 3.3 A

I_OUT= 4.2 A

I_OUT= 5.0 A

0.55

0.7

0.85

0.91

1.15

1.38

Dropout voltage (performance)

MinDOV

(DOV = V_IN– V_OUT

)

14

Specifications

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Table 4-1. SMPS1 Switched-Mode Regulator Electrical Characteristics (continued)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Total DC output voltage accuracy

(3-A mode)

Includes voltage references, DC

load/line regulations, process, and

temperature

0.6 V

1.0 V

1.2 V

1.3 V

1.8 V

0.591

0.995

1.194

1.293

1.791

0.608

1.013

1.216

1.317

1.824

0.634

1.045

1.255

1.359

1.882

V

(–1.8%/+3.2%) V_OUT> 0.75 V

(–2.8%/+4.2%) V_OUT< 0.75 V

T_DCOV

Total DC output voltage accuracy

(5-A mode)

0.6 V

1.0 V

1.2 V

1.35 V

1.5 V

0.587

0.989

1.187

1.334

1.483

0.608

1.013

1.216

1.367

1.519

0.634

1.045

1.255

1.411

1.568

Includes voltage references, DC

load/line regulations, process, and

temperature

(–2.4%/+3.2%) V_OUT> 0.75 V

(–3.4%/+4.2%) V_OUT< 0.75 V

V

PWM mode: SMPS1 (3-A mode)

PWM mode: SMPS1 (5-A mode)⁽¹⁾

PFM mode

3000

5000

I_OUT

V_OUT

R_V

Rated output current

mA

200

Low range

0.6

0.7

1.3

1.4

V

High range

Step size

12.5

mV

1.35

1.5

1.8

1.9

2.1

Output voltage, programmable

Other selectable voltages

V

Extended voltage range, multiplier for nominal

levels (enabled by OTP bit)

3.0476

PWM mode (3-A mode), I_LOAD= 0 to I_OUTmax

PWM mode (5-A mode), I_LOAD= 0 to I_OUTmax

PFM mode, ∆V_OUT/V_OUT

10

15

20

mVpp

p-p

Ripple voltage

Measured with 20-MHz LPF

30

1.9 %

0.25 %

0.6 %

3.8 %

0.6 %

1.2 %

PWM mode, (3-A mode): I_OUT= 0 to I_OUTmax

PWM mode, (5-A mode): I_OUT= 0 to I_OUTmax

DC_LDRDC load regulation, ∆V_OUT/V_OUT

PWM mode, (3-A mode): V_IN= V_INPminto

V_INPmax, I_OUT= I_OUTmax

0.8 %

1.4 %

12

1.6 %

2.5 %

20

DC_LNRDC line regulation, ∆V_OUT/V_OUT

PWM mode, (5-A mode): V_IN= V_INPminto

V_INPmax, I_OUT= I_OUTmax

Transient load regulation

1.0 V

mV

(3-A mode)

I_OUT= 10 to 500 mA, t_R/t_F= 100 ns

T_LDR

Transient load regulation

1.2 V

67

101

(5-A mode)

I_OUT= 1.5 to 5.0 A, t_R/t_F= 1 µs

V_INstep = ±600 mV

Rise/fall time = 10 µs, V_OUT< 0.75 V

0.7 %

0.5 %

1.0 %

1.4 %

1.0 %

1.9 %

Transient line regulation, (3-A

mode), T_LNR/V_OUT

V_OUT≥ 0.75 V

T_LNR

V_INstep = ±600 mV

Rise/fall time = 10 µs, V_OUT< 0.75 V

Transient line regulation, (5-A

mode), T_LNR/V_OUT

V_OUT≥ 0.75 V

0.8 %

350

1.5 %

500

t_ON

Off to on

On to off

I_OUT= 200 mA, V_OUTwithin accuracy limits

I_OUT= 0, V_OUTdown to 10% x V_OUT

µs

250

500

t_OFF

With 44 µF output capacitance: I_OUT= 0, V_OUT

down to 10% x V_OUT

800

R_PD

SR

Pulldown resistor

Off mode

3.8

11

7.5

30

15

Ω

Slew rate during rise time

From 0.1 × V_OUTto 0.9 × V_OUT

150

mV/us

From V_OUT= 0.6 V to V_OUT= 1.3 V ±5%, I_LOAD

I_LOADmax, <SMPS>_CFG_STEP = 6 (minimum)

=

SR_DVSSlew rate

12.7

14

mV/µs

(1) Lifetime is 75,000 power on hours (POH) at maximum junction temperature of 125°C and V_OUT≤ 1.4 V and 50,000 POH at maximum

junction temperature of 125°C and V_OUT> 1.4 V.

Specifications

15

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Table 4-1. SMPS1 Switched-Mode Regulator Electrical Characteristics (continued)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Output voltage settling time (normal From V_OUT= 0.6 V to V_OUT= 1.3 V ±5%, I_LOAD

=

50

57

65

µs

mode)

I_LOADmax

Overshoot

100

3.5

0.25

1

mV

f_SW

Switching frequency

2.6

3

MHz

Off mode, T = 25°C

Off mode

0.1

0.2

25

I_QOFF

Off ground current

µA

PFM mode, no switching

µA

I_Q

On ground current

PWM mode

I_OUT= 0 mA, V_IN= 3.8 V

12

mA

Table 4-2. SMPS2 Switched-Mode Regulator Electrical Characteristics

PARAMETER

Input capacitor

TEST CONDITIONS

MIN

0.6

4

TYP

4.7

10

MAX

UNIT

C_I

µF

Output filter capacitor: (Option 1)

Output filter capacitor: (Option 2)

Filter capacitor ESR

15

29

µF

mΩ

µH

C_O

11

1

22

f = [1 to 10] MHz

10

20

Filter inductor: (Option 1)

Filter inductor: (Option 2)

Filter inductor DC resistance

Filter inductor Q factor

0.4

0.2

1.0

0.5

50

1.3

0.65

100

L_O

mΩ

DCR_L

> 6 MHz

20

–

ILIMIT[1:0] = 00 (No current limitation)

ILIMIT[1:0] = 01 (1.4 A)

ILIMIT[1:0] = 10 (1.8 A)

ILIMIT[1:0] = 11 (2.5 A)

–

2050

2400

3100

2550

3000

3800

3100

3500

4400

PMOS current limit (high side)

mA

Input current limit under short-circuit

conditions

SW = 0 V

10

20

30

mA

V

max

(V_OUT

V_INF

Input voltage (functional)

VSYS

+

5.5

0.4, 2.3)

max

(V_OUT

MinDO

V, 2.5)

+

V_INP

Input voltage (performance)

VSYS

3.8

4.8

V

I_OUT= 0.5 A

0.3⁽¹⁾

0.5

0.6

0.7

0.9

1.1

1.2

1.3

1.5

1.7

I_OUT= 0.8 A

I_OUT= 1.0 A

I_OUT= 1.2 A

I_OUT= 1.5 A

Dropout voltage (performance)

MinDOV

V

(DOV = V_IN– V_OUT

)

I_OUT= 1.8 A

I_OUT= 2.0 A

I_OUT= 2.2 A

I_OUT= 2.5 A (Option 1)

I_OUT= 2.5 A (Option 2)

(1) Minimum dropout voltage of 0.5 V is needed to ensure PFM operation with V_OUT> 2.1 V.

16 Specifications

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Table 4-2. SMPS2 Switched-Mode Regulator Electrical Characteristics (continued)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

0.6 V

1.1 V

1.225 V

1.3 V

1.35 V

1.8 V

1.9 V

2.1 V

0.601

1.101

1.226

1.301

1.352

1.801

1.902

2.101

0.608

1.114

1.241

1.317

1.368

1.823

1.925

2.127

0.623

1.141

1.271

1.349

1.401

1.867

1.971

2.178

Total DC output voltage accuracy

(Option 1)

Includes voltage references, DC

load/line regulations, process, and

temperature

V

(–1.2%/+2.4%) V_OUT> 0.75 V

T_DCOV

0.6 V

1.1 V

1.225 V

1.3 V

1.35 V

1.8 V

1.9 V

2.1 V

0.598

1.095

1.220

1.295

1.345

1.792

1.892

2.091

0.608

1.114

1.241

1.317

1.368

1.823

1.925

2.127

0.623

1.141

1.271

1.349

1.401

1.867

1.971

2.178

Total DC output voltage accuracy

(Option 2)

Includes voltage references, DC

load/line regulations, process, and

temperature

V

(–1.7%/+2.4%) V_OUT> 0.75 V

PWM mode

PFM mode

Low range

High range

Step size

2500

I_OUT

Rated output current

mA

200

0.6

0.7

1.3

1.4

V

12.5

mV

1.35

1.5

1.8

1.9

2.1

V_OUT

Output voltage, programmable

Other selectable voltages

V

Extended voltage range, multiplier for nominal

levels (enabled by OTP bit)

3.0476

PWM mode: I_OUT= 0 to 2.2 A

5

10

mVpp

p-p

Ripple voltage

(Option 1)

Measured with 20-MHz LPF

PWM mode: I_OUT= 0 to I_OUTmax

5

15

PFM mode, ∆V_OUT/V_OUT

1.0 %

15

2.0 %

25

R_V

PWM mode: I_LOAD= 0 to I_OUTmax

PFM mode, V_OUT> 0.75 V, ∆V_OUT/V_OUT

PFM mode, V_OUT< 0.75 V, ∆V_OUT/V_OUT

PWM mode, (Option 1): I_OUT= 0 to I_OUTmax

PWM mode, (Option 2): I_OUT= 0 to I_OUTmax

mVpp

Ripple voltage

(Option 2)

Measured with 20-MHz LPF

1.0 %

1.5 %

0.25 %

2.0 %

3.0 %

0.5 %

1.2 %

p-p

DC_LDRDC load regulation, ∆V_OUT/V_OUT

DC_LNRDC line regulation, ∆V_OUT/V_OUT

PWM mode, V_IN= V_INPminto V_INPmax, I_OUT

I_OUTmax

=

0.8 %

1.6 %

V_OUT< 0.75 V

I_OUT= 0 to 150 mA, t_R/t_F= 100 ns

I_OUT= 50 to 250 mA, t_R/t_F= 100 ns

I_OUT= 350 to 800 mA, t_R/t_F= 100 ns

3.3 %

4.2 %

Transient load regulation,

∆V_OUT/V_OUT

(Option 1)

V_OUT≥ 0.75 V

I_OUT= 0 to 150 mA, t_R/t_F= 100 ns

I_OUT= 50 to 250 mA, t_R/t_F= 100 ns

I_OUT= 350 to 800 mA, t_R/t_F= 100 ns

2.8 %

1.5 %

3.6 %

3.0 %

T_LDR

V_OUT< 0.75 V

I_OUT= 0 to 150 mA, t_R/t_F= 100 ns

I_OUT= 50 to 250 mA, t_R/t_F= 100 ns

I_OUT= 350 to 800 mA, t_R/t_F= 100 ns

Transient load regulation,

∆V_OUT/V_OUT

(Option 2)

V_OUT≥ 0.75 V

I_OUT= 0 to 150 mA, t_R/t_F= 100 ns

I_OUT= 50 to 250 mA, t_R/t_F= 100 ns

I_OUT= 350 to 800 mA, t_R/t_F= 100 ns

1.3 %

0.7 %

2.5 %

1.4 %

V_INstep = ±600 mV

Rise/fall time = 10 µs, V_OUT< 0.75 V

T_LNR

t_ON

Transient line regulation, T_LNR/V_OUT

Off to on

V_OUT≥ 0.75 V

0.5 %

350

1.0 %

500

I_OUT= 200 mA, V_OUTwithin accuracy limits

µs

Specifications

17

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Table 4-2. SMPS2 Switched-Mode Regulator Electrical Characteristics (continued)

PARAMETER

On to off

TEST CONDITIONS

I_OUT= 0, V_OUTdown to 10% x V_OUT

Off mode

MIN

TYP

250

7.5

MAX

500

15

UNIT

µs

t_OFF

R_PD

SR

Pulldown resistor

3.8

Ω

Slew rate during rise time

From 0.1 × V_OUTto 0.9 × V_OUT

30

150

mV/µs

From V_OUT= 0.6 V to V_OUT= 1.3 V ±5%, I_LOAD

I_LOADmax, <SMPS>_CFG_STEP = 6 (minimum)

=

SR_DVSSlew rate

11

50

12.7

57

14

65

mV/µs

µs

Output voltage settling time (normal From V_OUT= 0.6 V to V_OUT= 1.3 V ±5%, I_LOAD

mode)

I_LOADmax

Overshoot

100

6.6

0.25

1

mV

f_SW

Switching frequency

4.5

6

MHz

Off mode, T = 25°C

Off mode

0.1

0.2

35

I_QOFF

Off ground current

µA

PFM mode, no switching

50

µA

I_Q

On ground current

PWM mode,

I_OUT= 0 mA, V_IN= 3.8 V

12

mA

Table 4-3. SMPS3, SMPS4, SMPS5 Switched-Mode Regulators Electrical Characteristics

PARAMETER

Input capacitor

TEST CONDITIONS

MIN

0.6

4

TYP

4.7

10

MAX

UNIT

µF

C_I

C_O

15

20

µF

Filter capacitor ESR

Filter inductor

f = [1 to 10] MHz

1

10

mΩ

µH

L_O

0.4

1.0

50

1.3

100

Filter inductor DC resistance

Filter inductor Q factor

mΩ

DCR_L

> 6 MHz

20

–

ILIMIT[1:0] = 00 (No current limitation)

ILIMIT[1:0] = 01

–

PMOS current limit (high side)

1300

1640

1620

2050

2000

2520

mA

ILIMIT[1:0] = 1X

Input current limit under short-circuit

conditions

SW = 0 V

10

20

30

mA

V

max

(V_OUT

V_INF

Input voltage (functional)

VSYS

+

5.5

0.4, 2.3)

max

(V_OUT

MinDO

V, 2.5)

0.41⁽¹⁾

0.65

0.9

+

V_INP

Input voltage (performance)

Dropout voltage (performance)

VSYS

3.8

4.8

V

I_OUT= 0.5 A

I_OUT= 0.8 A

I_OUT= 1.0 A

MinDOV

(DOV = V_IN– V_OUT

)

0.6 V

1.1 V

1.225 V

1.3 V

1.35 V

1.8 V

1.9 V

2.1 V

0.601

1.101

1.226

1.301

1.352

1.801

1.902

2.101

0.608

1.114

1.241

1.317

1.368

1.823

1.925

2.127

0.623

1.141

1.271

1.349

1.401

1.867

1.971

2.178

Total DC output voltage accuracy

Includes voltage references, DC

load/line regulations, process, and

temperature

T_DCOV

V

(–1.2%/+2.4%) V_OUT> 0.75 V

PWM mode

PFM mode

1100

I_OUT

Rated output current

mA

200

(1) Minimum dropout voltage of 0.5 V is needed to ensure PFM operation with V_OUT> 2.1 V.

18 Specifications

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Table 4-3. SMPS3, SMPS4, SMPS5 Switched-Mode Regulators Electrical Characteristics (continued)

PARAMETER

TEST CONDITIONS

MIN

0.6

TYP

MAX

1.3

UNIT

Low range

High range

Step size

V

0.7

1.4

12.5

mV

1.35

1.5

1.8

1.9

2.1

V_OUT

Output voltage, programmable

Other selectable voltages

V

Extended voltage range, multiplier for nominal

levels (enabled by OTP bit)

3.0476

PWM mode: I_LOAD= 0 to I_OUTmax

PFM mode, ∆V_OUT/V_OUT

5

10

mVpp

p-p

Ripple voltage

Measured with 20-MHz LPF

R_V

1.0 %

0.25 %

2.0 %

0.5 %

DC_LDRDC load regulation, ∆V_OUT/V_OUT

DC_LNRDC line regulation, ∆V_OUT/V_OUT

PWM mode: I_OUT= 0 to I_OUTmax

PWM mode, V_IN= V_INPminto V_INPmax, I_OUT

I_OUTmax

=

0.8 %

1.6 %

V_OUT< 0.75 V

I_OUT= 0 to 150 mA, t_R/t_F= 100 ns

I_OUT= 50 to 250 mA, t_R/t_F= 100 ns

I_OUT= 150 to 400 mA, t_R/t_F= 100 ns

2.0 %

3.0 %

Transient load regulation,

∆V_OUT/V_OUT

T_LDR

V_OUT≥ 0.75 V

I_OUT= 0 to 150 mA, t_R/t_F= 100 ns

I_OUT= 50 to 250 mA, t_R/t_F= 100 ns

I_OUT= 150 to 400 mA, t_R/t_F= 100 ns

1.0 %

0.7 %

1.5 %

1.4 %

V_INstep = ±600 mV

Rise/fall time = 10 µs, V_OUT< 0.75 V

T_LNR

Transient line regulation, T_LNR/V_OUT

V

_OUT≥ 0.75 V

0.5 %

350

250

7.5

1.0 %

500

15

t_ON

t_OFF

R_PD

SR

Off to on

I_OUT= 200 mA, V_OUTwithin accuracy limits

I_OUT= 0, V_OUTdown to 10% x V_OUT

Off mode

µs

On to off

Pulldown resistor

Slew rate during rise time

3.8

Ω

From 0.1 × V_OUTto 0.9 × V_OUT

30

150

mV/µs

Slew rate

SMPS5

From V_OUT= 0.6 V to V_OUT= 1.3 V ±5%, I_LOAD

I_LOADmax, <SMPS>_CFG_STEP = 6 (minimum)

=

SR_DVS

11

50

12.7

57

14

65

mV/µs

µs

Output voltage settling time (normal From V_OUT= 0.6 V to V_OUT= 1.3 V ±5%, I_LOAD

mode) SMPS5

I_LOADmax

Overshoot

100

6.6

0.25

1

mV

f_SW

Switching frequency

5.4

6

MHz

Off mode, T = 25°C

Off mode

0.1

0.2

35

I_QOFF

Off ground current

µA

PFM mode, no switching

50

µA

I_Q

On ground current

PWM mode,

I_OUT= 0 mA, V_IN= 3.8 V

8

mA

Specifications

19

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4.5.2 LDO Regulators

Table 4-4 lists the LDO regulators electrical characteristics.

Over operating free-air temperature range (unless otherwise noted)

Table 4-4. LDO Regulators Electrical Characteristics

PARAMETER

LDO Regulators

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Connected from LDO_IN to GND. Shared input tank

capacitance (depending on platform requirements

and power tree)

0.3

2.2

C_IN

Input filtering capacitor

µF

Connected from CHRG_PMID to GND

Connected from LDO output to GND

< 100 kHz

0.9

0.6

20

1

4.7

2.2

100

10

6.5

2.7

600

20

C_OUT

R_ESR

Output filtering capacitor

Filtering DC capacitor ESR

Filtering AC capacitor ESR

µF

mΩ

[1 to 10] MHz

VRTC, VBRTC: VSYS during ACTIVE, SLEEP and

WAIT-ON state

2.3

5.5

VRTC, VBRTC: VSYS during BACKUP state

VRTC, VBRTC: V_BACKUPduring BACKUP state

LDO1_IN, LDO2_IN, LDO3_IN, LDO4_IN,

LDO5_IN, LDO6_IN, LDO7_IN, LDOLN_IN (V_OUT

1.5 V)

1.9

3.1

5.5

T_DCOV

D_V– 0.2

+

≥

5.5

V_INF

Input voltage (functional)

V

LDO1_IN, LDO2_IN, LDO3_IN, LDO4_IN,

LDO5_IN, LDO6_IN, LDO7_IN, LDOLN_IN (V_OUT

1.5 V)

<

1.8

VANA

2.3

3.5

2.5

5.5

6.8

4.8

LDOUSB: Supplied from VSYS

LDOUSB: Supplied from CHRG_PMID

VRTC, VBRTC

3.8

VANA

LDO1_IN, LDO2_IN, LDO3_IN, LDO4_IN,

LDO5_IN, LDO6_IN, LDO7_IN, LDOLN_IN (V_OUT

1.5 V)

T_DCOV

D_V

+

≥

3.8

4.8

V_INP

Input voltage (performance)

V

LDO1_IN, LDO2_IN, LDO3_IN, LDO4_IN,

LDO5_IN, LDO6_IN, LDO7_IN, LDOLN_IN (V_OUT

1.5 V)

<

1.8

LDOUSB: from VSYS

3.6

4.3

3.8

5.0

4.8

5.5

LDOUSB: from CHRG_PMID, OVV protection

20

Specifications

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Table 4-4. LDO Regulators Electrical Characteristics (continued)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

1.0 V, _IN ≥ 2.5 V

1.001

0.987

1.202

1.185

1.301

1.283

1.801

1.902

2.002

2.102

2.203

2.302

2.402

2.503

2.753

2.802

2.903

3.003

3.304

3.245

1.018

1.222

1.323

1.832

1.934

2.036

2.138

2.240

2.341

2.443

2.545

2.800

2.850

2.952

3.054

3.359

3.301

1.030

1.236

1.339

1.854

1.957

2.060

2.163

2.266

2.369

2.472

2.575

2.834

2.884

2.987

3.090

3.399

3.341

1.0 V, _IN < 2.5 V

1.2 V, _IN ≥ 2.5 V

1.2 V, _IN < 2.5 V

1.3 V, _IN ≥ 2.5 V

1.3 V, _IN < 2.5 V

1.8 V

Total DC output voltage

accuracy

Includes voltage references, DC 1.9 V

load/line regulations, process

and temperature

(–1.7%/1.2%), _IN ≥ 2.5 V

2.0 V

2.1 V

2.2 V

V

(–3.0%/1.2%), _IN < 2.5 V and 2.3 V

T_DCOV

V_OUT< 1.5 V

(except VRTC, VBRTC and

VANA)

2.4 V

2.5 V

2.75 V

2.8 V

2.9 V

3.0 V

3.3 V

3.3 V (LDOUSB)

VBRTC

VRTC

VANA

1.550

1.801

2.102

1.805

1.832

2.138

1.854

1.890

2.163

V

LDO6, LDOLN: I_OUT= I_OUTmax

LDO5, LDO7: I_OUT= 50 mA

LDOUSB

150

140

200

Dropout voltage

_IN ≥ 2.3 V

LDO1, LDO2, LDO3, LDO4, LDO5, LDO7, VRTC:

V_INPmin= T_DCOV+ D_V

D_V

mV

300

250

400

LDO6, LDOLN: I_OUT= I_OUTmax

Dropout voltage

_IN ≥ 1.8 V

LDO1, LDO2, LDO3, LDO4, LDO5, LDO7: V_INPmin

T_DCOV+ D_V

=

VBRTC

1.5

25

VANA, VRTC

LDOLN

50

LDO1: V_OUT≤ 2.75 V

LDO1: V_OUT≥ 2.8 V

LDOUSB

50

I_OUT

Rated output current

mA

80

100

200

250

3.3

LDO2, LDO3, LDO4, LDO5, LDO6, LDO7

LDO6 (D_V= 300 mV, V_OUT≥ 1.8 V)

Range

1.0

V

mV

V

Output voltage, programmable

(except VRTC, VBRTC and

VANA)

V_OUT

Step size

100

2.75

250

650

Additional selectable voltage level

VANA, VRTC, LDO1, LDOLN

LDOUSB

100

150

400

600

900

I_LIMIT

Load current limitation

mA

mV

LDO2, LDO3, LDO4, LDO5, LDO6, LDO7

DC load regulation, ∆V_OUT

V_OUT

/

DC_LDR

I_OUT= 0 to I_OUTmax

4

10

DC line regulation, ∆V_OUT

V_OUT

/

V_IN= V_INPminto V_INPmax

I_OUT= I_OUTmax

DC_LNR

t_ON

0.1 %

100

0.2 %

500

Turn-on time

I_OUT= 0 , V_OUT= 0.1 V up to V_OUTmin

µs

Turn-off time (except VRTC and

VBRTC)

t_OFF

I_OUT= 0, V_OUTdown to 10% x V_OUT

250

500

Pulldown resistor (except VRTC

and VBRTC)

R_PD

Off mode

40

60

80

Ω

Specifications

21

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UNIT

Table 4-4. LDO Regulators Electrical Characteristics (continued)

PARAMETER

TEST CONDITIONS

f = 217 Hz, I_OUT= I_OUTmax

MIN

45

35

20

45

35

20

TYP

90

MAX

Power supply ripple rejection

(Except LDO1)

f = 50 kHz, I_OUT= I_OUTmax

f = 1 MHz, I_OUT= I_OUTmax

f = 217 Hz, I_OUT= I_OUTmax

f = 50 kHz, I_OUT= I_OUTmax

f = 1 MHz, I_OUT= I_OUTmax

Off mode, T = 25°C

45

35

PSRR

dB

90

Power supply ripple rejection

(LDO1: D_V> 550 mV)

45

35

0.05

0.2

0.15

1

I_QOFF

Off ground current

µA

Off mode

I_OUT= 0, (except LDOLN, LDOUSB, VANA, VRTC,

VBRTC)

12

75

18

29

I_OUT= 0, LDOLN

150

175

60

I_Q0

On ground current

I_OUT= 0, LDOUSB, from VSYS, ACTIVE state

I_OUT= 0, LDOUSB, from VSYS, SLEEP state

I_OUT= 0, LDOUSB, from CHRG_PMID

I_OUT< 100 µA

40

20

4 %

2 %

1 %

On ground current coefficient

α_Q

On mode, I_QOUT= I_Q0+ α_Q

×

100 µA < I_OUT< 1 mA

I_OUT

I_OUT> 1 mA

On mode, I_OUT= 10 mA to I_OUTmax/ 2,

t_R= t_F= 1 µs

–25

–50

28

33

Transient load regulation,

∆V_OUT/ V_OUT

T_LDR

mV

On mode, I_OUT= 100 µA to I_OUTmax/ 2,

t_R= t_F= 1 µs

Transient line regulation, ∆V_OUT

/ V_OUT(except LDO6)

V_INstep = 600 mV_PP, t_R= t_F= 10 µs

0.25 %

0.6 %

1.0 %

T_LNR

Transient line regulation, ∆V_OUT

/ V_OUT(LDO6)

100 Hz < f < 10 kHz

10 kHz < f < 100 kHz

100 kHz < f < 1 MHz

f > 1 MHz

5000

1250

150

250

200

62

8000

2500

300

500

400

125

50

nV/√H

z

Noise (except LDOLN)

Noise (LDOLN)

V_noise

100 Hz < f < 5 kHz

5 kHz < f < 400 kHz

400 kHz < f < 10 MHz

nV/√H

z

25

LDO3 When Used As Vibrator Driver

Output regulated output range

Configurable step of 100 mV

1.0

0.6

70

3.3

2.7

700

50

V

µF

µH

Ω

C_OUT

Output filtering capacitor

Vibrator load inductance

Vibrator load resistance

Connected between LDO3 output and GND

2.2

350

40

L_Vibrator

R_Vibrator

15

22

Specifications

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4.5.3 Reference Generator

Table 4-5 lists the reference generator electrical characteristics.

Table 4-5. Reference Generator Electrical Characteristics

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Connected between VBG and

REFGND

C_OUT

Filtering capacitor

30

100

510

150

nF

Connected between IREF and

REFGND

Biasing resistor (±1%) at 25°C

505

515

50

kΩ

R_Bias

Biasing resistor (±1%) temperature

coefficient

ppm/°C

V_INP

I_Q

Input voltage V_INP

Ground current

Start-up time

Performance

1.9

15

3.8

20

1

5.5

40

3

V

µA

ms

t_startup

Specifications

23

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4.5.4 Crystal Oscillator

Table 4-6 lists the crystal oscillator electrical characteristics.

Table 4-6. Crystal Oscillator Electrical Characteristics

PARAMETER

Crystal Characteristics

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Crystal frequency

Crystal tolerance

at specified load capacitor value

T = 25°C

32768

0

Hz

f_osc

B

–20

20

ppm

ppm/°C

Secondary temperature coefficient

–0.04

–0.035

–0.03

2

R_ESR

DL

Crystal series resistor

Operating drive level

at fundamental frequency

90

kΩ

0.1

0.5

µW

Crystal load capacitor (according to

crystal data sheet)

C_L

12.5

1.4

pF

C_shunt

Q

Shunt capacitor

Quality factor

2.6

8000

0.6

80000

Crystal Oscillator External Components

VRTC power supply external

filtering capacitor

OSC32KCAP

2.2

2.7

µF

pF

Normal and high-performance (HP)

mode:

External capacitor

Load capacitors on OSC32KIN and

OSC32KOUT

External capacitor includes the

parasitics of PCB

9

8

15

10

17

12

Internal capacitance

C_Load

Backup mode:

External capacitor

Internal capacitance

9

0

15

0

17

0

Frequency accuracy (taking into

account crystal tolerance and

internal load capacitors variation)

at 25°C, normal and HP modes

at 25°C, backup mode

–30

–80

0

30

80

ppm

Hz

Oscillator capacitor ratio: C_OSC32KIN

C_OSC32KOUT

/

1

Square Wave Input Clock for Bypass

Frequency

32768

50 %

10

Input bypass clock

OSC32KIN input

OSC32KOUT floating

Duty cycle

40

60 %

20

Rise and fall time (10% to 90%)

Setup time

ns

1

ms

Crystal Oscillator Characteristics

Oscillator contribution in normal and

HP modes (not including the crystal

variations)

Frequency temperature coefficient

±0.5

ppm/°C

SSB phase noise at a 1-kHz offset

from the carrier

HP mode OSC_HPMODE = 1

Normal mode OSC_HPMODE = 0

–125

–105

25

dBc/Hz

ns

SSB phase noise at a 100-Hz offset

from the carrier

Cycle jitter short term (peak-to-

peak)

20 Hz to 20 kHz flat

0.86

0.43

300

400

Integrated jitter (HP mode)

Startup time for power on

ns_RMS

ms

80 Hz to 20 kHz flat

Shunt capacitor ≤ 1.4 pF

Shunt capacitor 1.4 to 2.6 pF

T_startup

Oscillator ratio between negative

resistance at 32 kHz and negative

resistance at 200 kHz (sixth

harmonic)

Sixth harmonic mode rejection

RS32/RS200

10

24

Specifications

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Table 4-6. Crystal Oscillator Electrical Characteristics (continued)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Crystal mounted:

- Backup mode (at 25°C)

- Normal mode: OSC_HPMODE = 0

- HP mode: OSC_HPMODE = 1

- Start-up (boost) phase

z

1.5

3

5

20

I_Q

Ground current

µA

Duty cycle CLK32KAO/CLK32KG

Logic output signal

40

5

50 %

20

60 %

100

T_Rise,T_FallRise and fall time (10% to 20%)

CLK32KAO/CLK32KG

ns

4.5.5 RC Oscillators

Table 4-7 lists the RC oscillators electrical characteristics.

Table 4-7. RC Oscillators Electrical Characteristics

PARAMETER

32-kHz RC Oscillator

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Output frequency

32768

Hz

f_OUT

Output frequency accuracy

Cycle jitter (RMS)

After trimming

–10 %

40 %

10 %

60 %

150

8

D

Output duty cycle

50 %

4

Settling time

µs

µA

nA

I_Q

Active current consumption

Power-down current

I_QOFF

30

6-MHz RC Oscillator

Output frequency

6

MHz

f_OUT

Output frequency accuracy

Cycle jitter (RMS)

After trimming

–10 %

40 %

0 %

10 %

5 %

60 %

5

D

Output duty cycle

50 %

35

Settling time

µs

µA

nA

I_Q

Active current consumption

Power-down current

70

I_QOFF

50

4.5.6 CLK32KAUDIO Buffer

Table 4-8 lists the CLK32AUDIO buffer electrical characteristics.

Table 4-8. CLK32KAUDIO Buffer Electrical Characteristics

PARAMETER

Settling time

TEST CONDITIONS

MIN

TYP

25

7

MAX

50

UNIT

µs

I_Q

Active current consumption

Power down current

5

10

µA

nA

V

I_QOFF

V_HOUT

30

High output level

VRTC supply

1.832

Duty cycle degradation contribution

–2 %

2 %

20 Hz to 20 kHz flat

80 Hz to 20 kHz flat

25

10

50

20

Integrated jitter contribution

External output load

ps_RMS

pF

C_Load

5

10

50

T_Rise

,

Output rise/fall time

Output load = 10 pF

7.5

10

ns

T_Fall

V_OL= 0.2 V

–1

1

–2

2

I_OUT

Output drive strength

mA

V_OH= V_HOUT– 0.2 V

Specifications

25

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4.5.7 Backup Battery Charger

Table 4-9 lists the backup battery charger electrical characteristics.

Table 4-9. Backup Battery Charger Electrical Characteristics

PARAMETER

Backup Battery Charger

TEST CONDITIONS

MIN

TYP

MAX

UNIT

VBACKUP to GPADC input

attenuation

VBACKUP from 2.4 to 4.5 V

0.2

350

0.25

650

0.35

900

V/V

µA

VBACKUP = 0 to 2.6 V

BB_CHG_EN = 1

I_Charge

Backup battery charging current

I_VBACKUP= –10 µA, BB_SEL = 00

(VSYS > 3.2 V)

2.90

3.00

3.10

2.60

3.25

I_VBACKUP= –10 µA, BB_SEL = 01

(VSYS > 2.7 V)

2.42

2.52

End backup battery charging

voltage: VBBCHGEND

I_VBACKUP= –10 µA, BB_SEL = 10

(VSYS > 3.35 V)

V_Charge

3.05

3.15

V

I_VBACKUP= –10 µA, BB_SEL = 11

(VSYS > 2.5 V)

VSYS – 0.3

VSYS – 0.2

VSYS

I_VBACKUP= –10 µA, BB_SEL = XX

(VSYS < 2.5 V)

I_Q

Current consumption

BB_CHG_EN = 1, I_VBACKUP= 0 µA

10

20

µA

Without additional capacitor in

parallel

R_Series

Backup battery serial resistance

Ω

With additional capacitor in parallel

1500

Capacitance of the additional

capacitor (C44)

C_OUT

2.0

4.7

µF

4.5.8 Switched-Mode System Supply Regulator

Table 4-10 lists the system supply regulator electrical characteristics.

Table 4-10. System Supply Regulator Electrical Characteristics

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Switched-Mode System Supply Regulator

0 V < VBUS < 5.25 V

1.2

0.9

1

4.7

10

6.5

20

µF

VBUS capacitor (connected

C_VBUS

0 V < VBUS < 6 V

ESR (1 to 10 MHz)

0 V < VBUS < 5.25 V

0 V < VBUS < 6 V

ESR (1 to 10 MHz)

0 V < CSOUT < 4.5 V

ESR (1 to 10 MHz)

0 V < CSIN < 4.5 V

ESR (100 kHz)

between VBUS and PGND)

mΩ

1.2

0.9

1

4.7

10

6.5

20

µF

PMID capacitor (connected

C_PMID

between PMID and PGND)

mΩ

µF

3

10

15

Output capacitor (connected

C_CSOUT

between CSOUT and PGND)

20

mΩ

nF

20

50

100

2.2

150

400

200

2.86

Output capacitor (connected

C_CSIN

between CSIN and PGND)

mΩ

nF

Bootstrap capacitor (connected

C_BOOT

between BOOT and SW)

ESR (9 MHz)

mΩ

µF

Reference voltage capacitor

0 V < V_REF< 6.5 V

0.7

C_VREF

(connected between V_REFand

PGND)

ESR (1 to 10 MHz)

20

mΩ

Inductance

DCR

0.7

1

1.45

130

µH

Coil (option 1), (connected

between SW and CSIN)

L

mΩ

Sense resistor (connected

between CSIN and CSOUT)

R9

Short circuited with power path

–1%

68 mΩ

+1%

26

Specifications

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Table 4-10. System Supply Regulator Electrical Characteristics (continued)

PARAMETER

Maximum output average current CHRG_SW

VBUS > V_BUSmin, PWM switching

TEST CONDITIONS

MIN

TYP

1.5

10

MAX

UNIT

1.545

A

mA

VBUS > V_BUSmin, PWM not

switching

5

30

5

I_VBUS

VBUS supply current control

0°C < T_J< 85°C, HZ_MODE= 1,

32S mode

µA

V

Leakage current from battery to

VBUS ball

0°C < T_J< 85°C, CSOUT = 4.2 V,

Hi-Z mode

I_{VBUS_LEAK}

Output voltage for

preconditioning/precharge

3.8

VBAT + ΔLIN

3.54

Output voltage for full charge

mode

V

V_SYS

Nominal output voltage,

programmable

20-mV steps

3.50

4.76

V

Voltage regulation accuracy

(except full charge mode), I_OUT

200 mA

T = 25°C

–0.5 %

–1.0 %

0.5 %

1.0 %

<

0°C < T < 125°C

Nominal output current Without

power Path, programmable

With R9 = 68 mΩ

300

1500

mA

VICHRG

I

_OCHARGE≤ 500 mA

_OCHARGE≥ 600 mA

–5 %

–3 %

2.9

5 %

3 %

3.6

Current accuracy

I

VAC_DET rising edge threshold

VAC_DET falling edge threshold

Hysteresis

3.4

3.0

135

3.4

3.0

135

V

mV

V

VAC_DET

VAC detection

2.7

3.4

100

2.9

350

3.6

VBUS_DET rising edge threshold

VBUS_DET falling edge threshold

Hysteresis

VBUS detection

2.8

3.35

170

VBUS_DET

50

mV

ms

VAC/VBUS detection deglitch

time

25

30

3.8

5

36

Input power source detection for

battery charging, threshold for falling

edge

VBUS input voltage lower limit

3.6

4.0

V

V_{VBUS_MIN}

Deglitch time for V_BUSrising

above V_{VBUS_MIN}

Rising voltage, 2-mV overdrive, t_R

100 ns

=

4

6

ms

Hysteresis for V_{VBUS_MIN}

Input voltage rising

100

200

mV

Input current is automatically

reduced, programmable, 80-mV

steps

VBUS collapse threshold

4.2

4.76

V

VBUS DPM loop kick-in threshold

accuracy

–2 %

2 %

t_int

Detection interval

Input power source detection

Programmable

1.7

100

2

2.6

s

2250

–1 %

mA

VBUS input current-limiting

threshold

I_{IN_LIMIT}

Accuracy

–15 %

–9 %

System Supply Regulator, Sleep Comparator (To Detect USB Unplug)

VBUS above CSOUT, 2.3 V ≤

CSOUT ≤ VOREG, VBUS falling

V_SLP

SLEEP state entry threshold

SLEEP state exit hysteresis

0

40

200

32

100

260

34

mV

ms

V_{SLP_ EXIT}

2.3 V ≤ CSOUT ≤ VOREG

140

31

Deglitch time for VBUS rising

above VSLP + VSLP_EXIT

Rising voltage, 2-mV overdrive, t_R

100 ns

=

System Supply Regulator, Battery Detection (Enabled by OTP Bit)

IDETECT battery detection

current before charge done (sink

current)

Begins after termination detected,

CSOUT ≤ VOREG

–0.45

262

mA

ms

TDETECT battery detection time

215

335

Specifications

27

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UNIT

Table 4-10. System Supply Regulator Electrical Characteristics (continued)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

System Supply Regulator, PWM

Internal top reverse blocking

MOSFET on-resistance

100

120

200

mΩ

Internal top N-channel switching

MOSFET on-resistance

Measured from PMID to SW

Measured from SW to PGND

Internal bottom N-channel

MOSFET on-resistance

120

3

240

3.3

mΩ

f_OSC

Oscillator frequency

Minimum duty cycle

Maximum duty cycle

2.7

MHz

D_MIN

D_MAX

0 %

93 %

5.10

Boost Mode for VBUS Voltage Generation

Boost output voltage (to pin

V_{BUS_B}

VBUS)

2.7 V < CHRG_CSOUT < 4.5 V

4.75

5.25

300

100

V

Rated output current of the boost,

combination of VBUS output

current and LDOUSB input

current from CHRG_PMID node

V_{BUS_B}= 5.10 V,

2.7 V < CHRG_CSOUT < 4.5 V

I_BO1

mA

Rated LDOUSB input current

from CHRG_PMID node

V_{BUS_B}= 5.10 V,

2.7 V < CHRG_CSOUT < 4.5 V

mA

A

Cycle-by-cycle current limit for

boost

V_{BUS_B}= 5.10 V,

2.7 V < CHRG_CSOUT < 4.5 V

I_BLIMIT

1.0

Overvoltage protection threshold Threshold over VBUS to turn off

5.8

6.0

125

85 %

5

6.2

V

for boost (VBUS pin)

converter during boost

V_BUSOVP

Hysteresis

VBUS falling from above V_BUSOVP

mV

CSOUT = 3.6 V, I_BO= 200 mA, T_A

25°C, synchronous operation

=

Efficiency

I_DDQ

Quiescent current

mA

V

Maximum system voltage for

boost (CSOUT pin)

VCSOUT rising edge during boost

4.75

4.9

5.05

2.5

V_SYSMAX

VCSOUT falling from above

V_SYSMAX

Hysteresis

200

60

mV

V

Minimum system voltage for

boost (CSOUT pin)

V_SYSMIN

Boost output resistance at HP

mode (from VBUS to PGND)

HZ_MODE = 1

kΩ

System Supply, Protection, Current Consumptions

Threshold over VBUS to turn off

converter during charge

VBUS OVP threshold voltage

6.3

6.5

140

6.7

V

V_{OVP_ VBUS}

Hysteresis

VBUS falling from above V_{OVP_VBUS}

mV

System voltage OVP threshold

voltage, VCSOUT threshold over PWM mode

VOREG to turn off the regulator

Power Path mode and DCDC in

130 %

110 %

133 %

136 %

121 %

V_{OVP_ VSYS}

Other cases

117 %

11 %

during operation

Lower limit for VCSOUT falling from

above V_{OVP_VSYS}

Hysteresis

Threshold over VBAT to turn off

battery charging

VBAT OVP threshold voltage

110 %

117 %

121 %

V_{OVP_ VBAT}

Hysteresis

11 %

3

Debounce time for falling edge

ms

A

BUCK_HSLIMI = 0: 2.55 A

BUCK_HSLIMI = 1: 1.90 A default

CSOUT rising (default)

2.10

1.50

2.00

2.55

1.90

2.10

3.30

2.60

2.20

Cycle-by-cycle current limit for

charge

I_LIMIT

Short-circuit voltage threshold

Hysteresis

V

V_{SYS_ SHORT}

CSOUT falling from above

V_{SYS_SHORT}

100

mV

28

Specifications

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Table 4-10. System Supply Regulator Electrical Characteristics (continued)

PARAMETER

TEST CONDITIONS

CSOUT ≤ V_{SYS_SHORT}

MIN

TYP

MAX

40

UNIT

mA

I_{SYS_ SHORT}

I_VBUS

Short-circuit detection current

VBUS input current

20

30

VBUS = 9.7 V, OVP active

4

mA

Temperature threshold,

T_CHRGSHTDWN

148

10

Regulator thermal shutdown

°C

Hysteresis, T_CHRGHYS

Threshold to start limiting the

current, T_CF

,

130

I_VBUS= 1.5 A

Analog thermal regulation loop

T_CHRGSHTDWN

– 5

Threshold for 0 A current level

System supply regulator enabled,

charger enabled

1.3

0.9

mA

µA

Current consumption of the linear

charger and supplement mode

control

System supply regulator enabled,

charger disabled

System supply regulator disabled,

system switch forced to connect

1

4.5.9 Battery Charger

Table 4-11 lists the battery charger electrical characteristics.

Table 4-11. Battery Charger Electrical Characteristics

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Battery Charger

15-mΩ resistor allows maximum of

2.0-A charging current

20-mΩ resistor allows maximum of

1.5-A charging current

Sense resistor of linear charging

loop⁽¹⁾

R2

15

20

mΩ

VSYS = 3.6 V, VBAT ≤ V_{BAT_SHORT}

VSYS = 3.8 V, VBAT ≤ V_{BAT_SHORT}

13

20

30

27

40

IBAT_SHO Preconditioning current (for short-

mA

V

RT

circuit detection)

Preconditioning positive threshold

voltage

Programmable: 2.1, 2.45, and 2.8-V

voltage levels

2.1

50

2.8

VBAT_SH

ORT

Hysteresis

100

1

150

mV

ms

Debounce time

V_{BAT_SHORT}< VBAT <

V_{BAT_FULLCHRG}

100-mA steps

Linear precharge current,

programmable

100

400

mA

VICHRG_

PC

Accuracy, without autocalibration

Accuracy, with autocalibration

–75 %

–10 %

–5 %

2.61

0 %

+10 %

+5 %

2.73

I_CHARGE< 300 mA

300 mA ≤ I_CHARGE≤ 400 mA

VBAT_FULLCHRG = 000

VBAT_FULLCHRG = 001

VBAT_FULLCHRG = 010

VBAT_FULLCHRG = 011

VBAT_FULLCHRG = 100

VBAT_FULLCHRG = 101

VBAT_FULLCHRG = 110

VBAT_FULLCHRG = 111

2.65

2.75

2.85

2.95

3.05

3.15

3.25

3.35

100

2.705

2.805

2.905

3.00

2.835

2.94

3.04

Threshold level, low to high

transition

V

VBAT_FU

LLCHRG

3.145

3.245

3.35

3.10

3.20

3.295

50

3.455

150

Hysteresis

mV

(1) Battery current level depends on the resistor R2 value as the loop is sensing the voltage across the resistor.

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Table 4-11. Battery Charger Electrical Characteristics (continued)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

VBAT > V_{BAT_FULLCHRG}, 100-mA

steps, R2 = 20 mΩ

100

1500

Linear full charge current,

programmable⁽¹⁾

mA

BAT > V_{BAT_FULLCHRG}, 133-mA

steps, R2 = 15 mΩ

133

2000

VICHRG

VOREG

I

_CHARGE≤ 400 mA

_CHARGE≥ 500 mA

_CHARGE≤ 400 mA

_CHARGE≥ 500 mA

–75 %

–50 %

–5 %

–37 %

0 %

Accuracy, without autocalibration

5 %

Accuracy, with autocalibration

Linear full charge output voltage

Accuracy, with autocalibration

–3 %

3 %

Programmable, 20-mV steps

T = 25°C

3.5

4.76

0.5 %

1.0 %

V

–0.5 %

–1.0 %

0°C < T < 125°C

Programmable, 50-mA steps

R2 = 20 mΩ

50

67

400

533

Charger termination current⁽¹⁾

Accuracy

mA

VITERM

Programmable, 67-mA steps

R2 = 15 mΩ

–33 %

100

33 %

200

20

%

Programmable, 50-mV steps

Accuracy

Charger dropout voltage, voltage

between VSYS and VBAT

ΔLIN

mV

–20

DPPM regulation, voltage between

VSYS and VBAT

0.5 ×

ΔLIN

VBAT > V_{BATMIN_HI}

V

DPPM regulation, VSYS voltage

VBAT < V_{BATMIN_HI}

Positive threshold

Hysteresis

3.4

5.9

V

5.7

50

70

6.1

200

170

VSYS_OV

V

System overvoltage detection

100

120

mV

Below VOREG

Recharge threshold voltage (in

Power Path mode enabled always,

in non-Power Path mode enabled

when CHARGE_ONCE bit is 0)

Deglitch time, VBAT decreasing

below threshold, t_F= 100 ns, 10-mV

overdrive

128

ms

µs

Supplement Mode

Fall time, C_gate= 8 nF, VSYS to

VSYS – 2 V, VSYS = 3.2 V

1.0

PGATE driver time

Rise time, C_gate= 8 nF, 0 V to

VSYS – 0.1 V, VSYS = 3.2 V

2.5

30

VSYS below VBAT, programmable

Accuracy

20

50

10

Supplement mode threshold level

(when entering supplement mode)

mV

mA

–10

Supplement mode threshold level

(when exiting supplement mode)

I_BAT

50

100

150

Check the need for supplement

mode

ms

µs

Charging restart delay

500

Battery Temperature Measurement

Reference voltage

GPADC_VREF

1.25

V

OTP bits, RATIO_LO[2:0],

RATIO_HI[2:0]

0.2 ×

GPADC_VREF

0.9 ×

GPADC_VREF

Low and high threshold voltages

Threshold error

1 %

10

%

Comparator offset

mV

Battery Presence Detector

R_BRI

External pulldown resistor

130

kΩ

See Table 4-15, GPADC_IN0

current source.

I_BRI

V_BRIRef

Detection threshold

Threshold

1.5

1.6

10

V

Current consumption of the

comparator

µA

30

Specifications

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Table 4-11. Battery Charger Electrical Characteristics (continued)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Delay of the comparator

With > 10-mV overdrive

10

µs

4.5.10 Indicator LED Driver

Table 4-12 lists the indicator LED driver electrical characteristics.

Table 4-12. Indicator LED Driver Electrical Characteristics

PARAMETER

Indicator LED Driver

TEST CONDITIONS

MIN

TYP

MAX

UNIT

VSYS

4.8

V

CURR_LED[1:0] = 00

0

1

CURR_LED[1:0] = 01

CURR_LED[1:0] = 10

CURR_LED[1:0] = 11

0.85

2.125

4.25

1.15

2.875

5.75

LED current

mA

2.5

5

Transition on PWM signal, 10 to

90%

Rise and fall time for the current

Startup time

5

µs

CURR_LED[1:0] from 00 to any

other value

20

Disabled

VRTC

2

VAC (at 20 V)

70

µA

CHRG_PMID (at 5.25 V)

CHRG_PMID (at 20 V)

CURR_LED[1:0] = 01 (1 mA)

CURR_LED[1:0] = 10 (2.5 mA)

CURR_LED[1:0] = 11 (5 mA)

20

Quiescent current

70

200

400

750

CURR_LED[1:0] = 00, can be

disabled by DIS_PULLDOWN bit

Pulldown resistance

50

100

200

3.2

5.5

kΩ

V

Voltage at the output for

performance

CHRG_LED_TEST pin is driven

externally

Voltage at the output for tolerance

V

Dropout voltage

1 mA

0.2

0.4

0.6

4.1

4.0

2.3

Minimum voltage between

CHRG_LED_IN and

CHRG_LED_TEST

2.5 mA

V

5 mA

VAC voltage

During operation

V

VBUS voltage

CHRG_LED_IN voltage

5.5

Specifications

31

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4.5.11 USB OTG

Table 4-13 lists the USB OTG electrical characteristics.

Table 4-13. USB OTG Electrical Characteristics

PARAMETER

Pullup and Pulldown Resistors

TEST CONDITIONS

MIN

TYP

MAX

UNIT

R_{ID_PU_100K}

R_{ID_PU_220K}

R_{ID_GND_DRV}

ID 100k pullup to LDOUSB

ID 220k pullup to LDOUSB

ID 10k pulldown to ground

70

160

1

100

220

10

130

280

20

kΩ

ID internal leakage without GPADC

(7 V)

350

nA

R_{ID_ LKG}

ID internal leakage without GPADC

(2 V)

650

1

nA

µA

kΩ

ID external leakage

–1.5

10

0

A-device VBUS Input Impedance To

GND

R_{A_BUS_IN}

40

10

2.5

100

15

5

R_{VBUS_DISCHRG}

R_{VBUS_CHRG_VBAT}

R_{VBUS_CHRG_PMID}

V_{VBUS_LKG}

B-device VBUS SRP pulldown

5

B-device VBUS SRP pullup on

VBAT

1.5

B-device VBUS SRP pullup on

CHRG_PMID

1.5

2.5

5

kΩ

V

OTG device leakage voltage

0.7

2.5

B-device unconfigured average

VBUS input current

I_{B_UNCFG}

mA

External ID resistances

R_{ID_FLOAT}

ID pulldown when ID pin is floating

220

122

ACA ID pulldown, OTG device as A-

device

R_{ID_A}

R_{ID_B}

R_{ID_C}

124

68

126

69

ACA ID pulldown, OTG device as B-

device, can't connect

67

36

kΩ

ACA ID pulldown, OTG device as B-

device, can connect

36.5

37

1

R_{ID_GND}

ID pulldown when ID pin is grounded

Comparators

V_{ID_WK}

ID wake-up comparator threshold

No hysteresis

0.300

10

0.650

100

1.150

220

V

ID wake-up equivalent threshold

resistance

R_{ID_WK_UP}

kΩ

V_{ID_CMP1}

ID comparator 1 threshold

ID comparator 2 threshold

ID comparator 3 threshold

ID comparator 4 threshold

No hysteresis

0.150

0.683

1.300

2.350

0.200

0.720

1.400

2.500

0.250

0.757

1.500

2.650

V

V_{ID_CMP2}

V_{ID_CMP3}

V_{ID_CMP4}

Current Sources

I_{ID_WK_SRC}

I_{ID_SRC_16u}

I_{ID_SRC_5u}

ID wake-up current source

ID current source (trimmed)

ID current source

V_ID< 2.75 V

3.5

15.5

4.5

9

16

5

25

16.5

5.5

µA

ADP Comparators

V_{ADP_ PRB}

ADP probing voltage threshold

ADP sensing voltage threshold

ADP discharge voltage

No hysteresis

0.6

0.65

0.40

0.7

V

V_{ADP_ SNS}

0.20

0.55

0.15

V_{ADP_ DSCHRG}

ADP Current Sources/Sinks

VBUS_IADP_SRC ADP source current

VBUS < 0.8 V

1.10

1.40

1.65

mA

32

Specifications

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Table 4-13. USB OTG Electrical Characteristics (continued)

PARAMETER

TEST CONDITIONS

0.5 V < V_BUS< 0.8 V

0.15 V < V_BUS< 0.8 V

MIN

1.1

TYP

1.5

MAX

UNIT

2

VBUS_IADP_SINK

ADP sink current

mA

0.5

1.5

ADP Timings

T_ADP_SINK

TA_ADP_PRB

TB_ADP_PRB

T_ADP_SNS

Comparators

ADP sink time

13

1.25

1.9

3

14

1.75

2.0

15

1.85

2.6

ms

s

ADP probing period, A-device

ADP probing period, B-device

ADP sensing time-out

s

Positive threshold

Hysteresis

2.8

50

3.2

3.6

V

VVBUS_WKUP_UP

VA_VBUS_VLD

VBUS wake-up comparator

100

175

mV

A-device VBUS valid comparator

threshold

Threshold, no

hysteresis

4.4

4.5

4.6

V

Positive threshold

Hysteresis

2.2

20

2.4

80

2.6

140

1.3

70

V

mV

V

VB_SESS_VLD_UP

B-device session valid comparator

A-device session valid comparator

B-device session end comparator

Positive threshold

Hysteresis

0.9

10

1.1

40

VA_SESS_VLD_UP

VB_SESS_END_UP

mV

V

Positive threshold

Hysteresis

0.3

10

0.5

40

0.8

70

mV

V

Positive threshold

Hysteresis

2.90

20

3.10

80

3.40

140

6.8

180

VOTG_SESS_VLD_UP OTG session valid comparator

mV

V

Positive threshold

Hysteresis

6.3

40

6.5

110

VOTG_OVV_UP

OTG overvoltage comparator

mV

Specifications

33

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4.5.12 Gas Gauge

Table 4-14 lists the gas gauge electrical characteristics.

Table 4-14. Gas Gauge Electrical Characteristics

PARAMETER

TEST CONDITIONS

20-mΩ sense resistor

15-mΩ sense resistor

MIN

–3.1

-4.13

TYP

MAX

3.1

UNIT

Current measurement range

Measurement accuracy of single

measurement result after calibration. CC_ACTIVE_MODE[1:0] = 00

Includes reference, temperature,

offset, and 3σ statistical variation.

Tolerance of the sense resistor R2 is CC_ACTIVE_MODE[1:0] = 11

not included.

A

4.13

–Vmeas × 1%

–0.11

Vmeas × 1%

0.11

CC_ACTIVE_MODE[1:0] = 01

CC_ACTIVE_MODE[1:0] = 10

–0.28

–0.74

–2.15

0.28

0.74

2.15

mV

CC_ACTIVE_MODE[1:0] = 00

CC_ACTIVE_MODE[1:0] = 01

CC_ACTIVE_MODE[1:0] = 10

CC_ACTIVE_MODE[1:0] = 11

200

450

Offset before autocalibration

µV

CC_ACTIVE_MODE[1:0] = 00

Offset after autocalibration (software CC_ACTIVE_MODE[1:0] = 01

must calculate the calibrated result) CC_ACTIVE_MODE[1:0] = 10

CC_ACTIVE_MODE[1:0] = 11

10

100

450

Usable input voltage range

–62

62

mV

Hz

Input clock frequency

32-kHz crystal oscillator

32768

50

Power on; FG_EN = 1

70

Current consumption

µA

Power off; FG_EN = 0

0.2

CC_ACTIVE_MODE[1:0] = 00

CC_ACTIVE_MODE[1:0] = 01

CC_ACTIVE_MODE[1:0] = 10

250

62.5

Integration period (sample counter

uses 32-kHz crystal oscillator)

ms

15.625

3.9062

5

CC_ACTIVE_MODE[1:0] = 11

R2

External sense resistor

10

20

mΩ

CC_ACTIVE_MODE[1:0] = 00

CC_ACTIVE_MODE[1:0] = 01

CC_ACTIVE_MODE[1:0] = 10

CC_ACTIVE_MODE[1:0] = 11

CC_ACTIVE_MODE[1:0] = 00

1 + 13

1 + 11

1 + 9

1 + 7

Integrator data size (2s complement)

Bit

–3.5

–2.5

–2.0

–1.5

3.5

2.5

2.0

1.5

Integral nonlinearity (average on 10 CC_ACTIVE_MODE[1:0] = 01

INL

LSB

measurement results)

CC_ACTIVE_MODE[1:0] = 10

CC_ACTIVE_MODE[1:0] = 11

CC_ACTIVE_MODE[1:0] = 00

Differential nonlinearity (average on CC_ACTIVE_MODE[1:0] = 01

–4.0

–2.5

–1.5

–1.0

4.0

2.5

1.5

1.0

DNL

10 measurement results)

CC_ACTIVE_MODE[1:0] = 10

CC_ACTIVE_MODE[1:0] = 11

Accumulator data size

Offset data size

1 + 31

1 + 9

24

Bit

Sample counter data size

34

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4.5.13 GPADC

Table 4-15 lists the GPADC electrical characteristics.

Table 4-15. GPADC Electrical Characteristics

PARAMETER

Current consumption

Off mode current

TEST CONDITIONS

GPADC_EN = 1

MIN

TYP

MAX

UNIT

µA

I_Q

1600

I_QOFF

f

GPADC_EN = 0

1

µA

Running frequency

Resolution

3

12

7

MHz

Bit

Number of external inputs

Number of internal inputs

12

GPADC_EN 0 to 1 or GPADC_EN 1

to 0

Turn on/off time

10

20

µs

Gain error without calibration (inputs

without scaler)

–2 %

2 %

GPADC_IN10

–5 %

–3

3 %

Gain error without calibration (inputs

with scaler)

Others than GPADC_IN10

3

36

Offset error without calibration

–36

LSB

GPADC_IN10

–0.7 %

–0.22 %

-3

0.7 %

0.22 %

3

Gain error with calibration (at 25°C

temperature)⁽¹⁾

Others than GPADC_IN10

GPADC_IN10

Offset error with calibration (at 25°C

temperature)⁽¹⁾

Others than GPADC_IN10

-5

5

GPADC_IN0 - GPADC_IN6,

GPADC_IN17

–0.6 %

–2

0.25 %

0.45 %

2

Gain error drift (Temperature and

supply)

Other channels

Offset drift (Temperature and

supply)

LSB

Best fitting, GPADC_IN9

Best fitting, GPADC_IN14

Best fitting, other channels

–3

–16

–3

4

12

3

INL

Integral nonlinearity

DNL

C_IN

Differential nonlinearity

Input capacitance

–2

2

LSB

pF

GPADC_IN17

Other inputs

4

0.5

Source resistance without

capacitance

20

kΩ

Source input impedance (external

inputs)⁽²⁾

R_Ext

Source capacitance with > 20-kΩ

source resistance

100

nF

GPADC_VREF voltage reference

GPADC_VREF output current

1.25

V

External load

Typical range

200

µA

Input range (Sigma-Delta ADC; the

input voltage and nonsaturated

ranges of the scaled inputs are

described in Table 5-2)

0

1.25

V_IN

V

Assured range without saturation

0.01

1.215

1 channel, sampling = 0

1 channel, sampling = 1

2 channels, sampling = 0

2 channels, sampling = 1

210

640

290

720

7

T_Conv

Conversion time

µs

GPADC_IN0 current source

6.65

20.9

7.35

23.1

µA

GPADC_IN0 with additional current

source

GPADC_ISOURCE_EN = 1

22

(1) Total accuracy is a combination of Gain error with calibration (at 25°C temperature), Gain error drift, Offset error with calibration (at 25°C

temperature), Offset drift and INL.

(2) If the source impedance is more than 20 kΩ, then 100 nF must be connected to the input.

Specifications

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Table 4-15. GPADC Electrical Characteristics (continued)

PARAMETER

TEST CONDITIONS

GPADC_REMSENSE[1:0] = 00

GPADC_REMSENSE[1:0] = 01

GPADC_REMSENSE[1:0] = 10

GPADC_REMSENSE[1:0] = 11

MIN

TYP

0

MAX

UNIT

8.5

340

675

9.5

380

750

10.5

420

825

GPADC_IN3 current sources

µA

36

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4.5.14 Thermal Monitoring

Table 4-16 lists the thermal monitoring electrical characteristics.

Table 4-16. Thermal Monitoring Electrical Characteristics

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

0.1

UNIT

Off mode

Off ground current (two sensors on

the die, specification for one sensor)

I_QOFF

µA

at 25°C off mode

0.5

On mode, standard mode

On mode, GPADC measurement

Rising temperature

Falling temperature

Rising temperature

Falling temperature

Rising temperature

Falling temperature

Rising temperature

Falling temperature

Rising temperature

Falling temperature

7

15

On ground current (two sensors on

the die, specification for one sensor)

I_Q

µA

°C

25

40

104

95

117

108

121

112

125

116

130

120

148

138

127

119

132

123

136

128

141

132

160

150

00 (first hot-die threshold)

01 (second hot-die threshold)

10 (third hot-die threshold)

11 (fourth hot-die threshold)

Thermal shutdown

109

99

113

104

118

108

136

126

4.5.15 System Control Thresholds

Table 4-17 lists the system control thresholds electrical characteristics.

Table 4-17. System Control Thresholds Electrical Characteristics

PARAMETER

VSYSMIN_HI threshold, rising edge

VSYSMIN_HI threshold accuracy

VSYSMIN_LO threshold, falling edge

VSYSMIN_LO threshold accuracy

POR rising-edge threshold

TEST CONDITIONS

MIN

2.5

TYP

MAX

3.55

UNIT

Programmable, step size is 50 mV

V

–1.6 %

2.3

+3.2 %

3.1

Programmable, step size is 50 mV

Rising edge to falling edge

V

–1.6 %

2.00

1.90

40

+3.2 %

2.50

2.15

2.00

150

V

POR fallng-edge threshold

2.10

POR hysteresis

350

mV

4.5.16 Current Consumption

Table 4-18 lists the current consumption electrical characteristics.

Table 4-18. Current Consumption Electrical Characteristics

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Backup Mode

VSYS = 0 V

VBACKUP = 3.2 V

I_{VBACKUP(Backup)}

VBACKUP, supplied on VBACKUP

VSYS, supplied on VSYS

8

10

19

µA

VBACKUP = 0 V

VSYS = 2.7 V

I_VSYS(Backup)

12

WAIT-ON State

I_{VSYS(WAIT-ON)}

SLEEP State

I_VSYS(SLEEP)

VSYS = 3.8 V, VRTC in a low-power

mode

20

30

µA

SMPS2 and SMPS3 enabled, no

load

VSYS = 3.8 V

110

Specifications

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4.5.17 Digital Input Signal Electrical Parameters

Table 4-19 lists the digital input signal electrical parameters.

Table 4-19. Digital Input Signal Electrical Parameters

TEST

CONDITIONS

PARAMETER

MIN

TYP

MAX

UNIT

PWRON, RPWRON

Low-level input voltage related to

VSYS/VDD

V_IL

V_IH

–0.3

0

0.35 × VSYS

V

High-level input voltage related to

VSYS/VDD

0.65 × VSYS

VSYS

VSYS + 0.3 ≤ 5.5

GPADC_START, MMC, MSECURE, NRESWARM, PREQ1, PREQ2, PREQ3, SIM, TESTEN

V_IL

V_IH

Low-level input voltage related to VIO

High-level input voltage related to VIO

–0.3

0

0.35 × VIO

VIO + 0.3

V

0.65 × VIO

VIO

BOOT0, BOOT1, BOOT2, CHRG_EXTCHRG_STATZ, OSC32KIN

V_IL

V_IH

Low-level input voltage related to VRTC

High-level input voltage related to VRTC

–0.3

0

0.35 × VRTC

VRTC + 0.3

V

0.65 × VRTC

VRTC

CTLI2C_SCL, CTLI2C_SDA, DVSI2C_SCL, DVSI2C_SDA

V_IL

V_IH

Low-level input voltage related to VIO

High-level input voltage related to VIO

Hysteresis

–0.3

0

0.3 × VIO

VIO + 0.3

V

0.7 × VIO

0.1 × VIO

VIO

1.2-V Specific Related I/Os: PREQ3⁽¹⁾⁽²⁾

V_IL

V_IH

Low-level input voltage related to VIO

High-level input voltage related to VIO

–0.3

0

0.3 × VIO

VIO + 0.3

V

0.7 × VIO

VIO

(1) PREQ3 can be programmed for two different input supplies (1.2 V/1.8 V) and, as such, has a configurable input threshold.

(2) Applying 1.8-V input logic on the PREQ3 ball when the 1.2-V supply mode is selected does not damage the PREQ3 input buffer.

Nevertheless, because the threshold is reduced to its 1.2-V configuration, the input buffer is more sensitive to the low 1.8-V logic level.

4.5.18 Digital Output Signal Electrical Parameters

Table 4-20 lists the digital output signal electrical parameters.

Table 4-20. Digital Output Signal Electrical Parameters

PARAMETER⁽¹⁾

TEST CONDITIONS

MIN

TYP

MAX

UNIT

REGEN1, REGEN2, VBUS_DET

V_OL

V_OH

Low-level output voltage

High-level output voltage

I_OL= 100 µA

I_OH= 100 µA

0

0.2 × VSYS

VSYS

V

0.8 × VSYS

BATREMOVAL, CLK32KAO, CLK32KG, INT, NRESPWRON, PWM1, PWM2, SYSEN

Low-level output voltage related to

VIO

V_OL

V_OH

I_OL= 2 mA

0

0.45

0.2

V

Low-level output voltage related to

VIO

I_OL= 100 µA

I_OH= 2 mA

I_OH= 100 µA

0

High-level output voltage related to

VIO

VIO – 0.45

VIO – 0.2

VIO

High-level output voltage related to

VIO

CLK32KAUDIO, CHRG_EXTCHRG_ENZ

Low-level output voltage related to

VRTC

V_OL

I_OL= 2 mA

0

0.45

0.2

V

Low-level output voltage related to

VRTC

V_OL

I_OL= 100 µA

(1) All output signals are assured low when VRTC is not available, especially REGEN1, REGEN2, and SYSEN, all three of which control

some external power resources.

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Table 4-20. Digital Output Signal Electrical Parameters (continued)

PARAMETER⁽¹⁾

TEST CONDITIONS

MIN

TYP

MAX

VRTC

UNIT

High-level output voltage related to

VRTC

V_OH

I_OH= 2 mA

VRTC – 0.45

V

High-level output voltage related to

VRTC

I_OH= 100 µA

VRTC – 0.2

0

VRTC

V

CTLI2C_SDA, DVSI2C_SDA

Low-level output voltage related to

VIO

V_OL

3-mA sink current

0.2 × VIO

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4.5.19 Digital Output Signal Timing Characteristics

Table 4-21 lists the digital output signal timing characteristics.

Table 4-21. Digital Output Signal Timing Characteristics

LOAD (pF)

RISE/FALL TIME (ns)

NOM

BALL NAME/OUTPUT BUFFER

CHRG_EXTCHRG_ENZ

MIN

5

MAX

35

MIN

5

MAX

15

25

15

6

INT

5

BATREMOVAL

NRESPWRON

PWM1

5

PWM2

5

REGEN1

REGEN2

SYSEN

5

1

20

35

50

5

4

11

15

20

9

VRTC supply output buffer and

VIO supply output buffer

5

8

1

20

35

50

5

3

17

25

34

15

30

45

100

VSYS supply output buffer

5

6

5

20

35

50

8

CLK32KAO output buffer and

CLK32KG output buffer

10

15

40

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4.6 Typical Characteristics

Figure 4-1 shows the 5.0-A SMPS regulator efficiency. Figure 4-2 shows 1.1-A SMPS regulator efficiency.

5.0 A

1.1 A

VBAT = 3.8 V, V_OUT= 1.8 V and 1.2 V

VBAT = 3.8 V, V_OUT= 1.2 V

95

90

85

80

75

70

65

60

55

50

95

90

85

80

75

70

65

60

55

50

1.8 V

1.2 V

COILCRAFT_XFL4020 – 1 µH

2 // TOKO_DFE322512C ‐ 1 µH

0.0001

0.001

0.01

0.1

1

10

0.0001

0.001

0.01

0.1

1

10

I_OUT(A)

5.0 A

V_BAT= 3.8 V

V_OUT= 1.2 V

1.1 A

V_BAT= 3.8 V

V_OUT= 1.8 V and 1.2 V

Figure 4-1. 5.0-A SMPS Regulator Efficiencies

Figure 4-2. 1.1-A SMPS Regulator Efficiencies

Figure 4-3 and Figure 4-4 show 2.5-A SMPS regulator efficiencies with two different inductor options.

2.5 A

VBAT = 3.8 V, V_OUT= 1.8 V and 1.3 V

95

90

85

80

75

70

65

60

55

1.8V,

95

90

85

80

75

70

65

60

55

50

1.3V,

3.8V

1.8, 3.8

1.3, 3.8

50

0.0001

0.001

0.01

0.1

10

1

I _OUT(A)

2.5 A

V_BAT= 3.8 V

V_OUT= 1.8 V and 1.3 V

0.0001

0.001

0.01

0.1

1

10

I _OUT(A)

Figure 4-4. 2.5-A SMPS Regulator Efficiencies (Option 2)

2.5 A

V_BAT= 3.8 V

V_OUT= 1.8 V and 1.3 V

Figure 4-3. 2.5-A SMPS Regulator Efficiencies (Option 1)

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5 Detailed Description

5.1 Real-Time Clock

The RTC is driven by the 32-kHz oscillator and provides the alarm and timekeeping functions. The RTC is

supplied by the backup battery (when available) if the main battery fails and if no external power is

applied.

The main functions of the RTC block are:

•

Time information (seconds/minutes/hours) in binary coded decimal (BCD) code.

Calendar information (day/month/year/day of the week) in BCD code up to year 2099.

Programmable interrupts generation. The RTC can generate two interrupts:

–

Timer interrupts periodically (1s/1m/1h/1d period) in the ACTIVE and SLEEP states (can be

masked during the SLEEP period with the IT_SLEEP_MASK_EN bit in the

RTC_INTERRUPTS_REG register in order to prevent the host processor from waking up)

–

Alarm interrupt at a precise time of the day (alarm function) in the ACTIVE and SLEEP states and

switch-on transition from the WAIT_ON state

•

Oscillator frequency calibration and time correction with 1/32768 resolution.

For security purposes, the registers related to time and calendar information are protected by restricting

their write access to software running in the secure mode of the host (the MSECURE pin set to 1). Read

access is always allowed, even in a nonsecured mode. However, it is possible to disable the secure mode

with the MSECURE OTP bit. In this case, the read and write accesses are available regardless of the

status of the MSECURE pin.

32-kHz clock

input

Frequency

compensation

Week

days

32-kHz

counter

Control

Days

Seconds

Minutes

Hours

Months

Years

INT_ALARM

Interrupt

Alarm

INT_TIMER

SWCS057-005

Figure 5-1. Block Diagram of the RTC Digital Section

42

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5.2 Clocks

The TPS80032 device is independent of any high-frequency system clock; it provides only a 32-kHz clock

to the platform. The oscillator can use an external crystal unit to generate the clock or use an external 32-

kHz oscillator, in which case the internal oscillator module is bypassed.

To provide a high-performance 32-kHz clock for peripherals, like an audio device, a dedicated output

buffer is implemented on the CLK32KAUDIO ball. This audio buffer uses the 1.8-V VRTC regulator as

power. CLK32KAO is always active when 1.8-V I/O voltage is available, whereas the CLK32KG and

CLK32KAUDIO outputs can be controlled by PREQ signals and register bits (CLK32KG_CFG_TRANS,

CLK32KG_CFG_STATE, CLK32KAUDIO_CFG_TRANS, and CLK32KAUDIO_CFG_STATE).

The TPS80032 device also includes a 32-kHz RC oscillator and a 6-MHz RC oscillator, which are used

internally.

5.3 Power Management

The power-management state machine manages control of the state of the different resources included in

the TPS80032 device depending on system activity and energy availability. It ensures the detection of

external or internal triggering events that initiate a change of system power state. It controls the transition

sequences required to change the system from current power state to a new power state by configuring

the resources according to the desired final power state.

Host processor can access the configuration registers using the general-purpose I²C interface (CTL-I²C).

Figure 5-2 shows a block diagram of the power-management system.

Detailed Description

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PWRON

RPWRON

RTC-ALARM

VAC_DET

HW events

Detection

VBUS_DET

Sequence arbitration

Internal POR

Debouncing

THERM_DET

Emergency

MBAT_PLUG

BBAT_PLUG

NRESWARM

Sequence

Tables

CTLI2C_SDA

Software

FSM

commands

CTLI2C_SCL

I²C control

PREQ2

PREQ3

DVSI2C_SDA

Commands

controller

DVS software

Resources

commands

DVSI2C_SCL

I²C

Figure 5-2. Block Diagram of the Power Controller

5.3.1 Finite State Machine (FSM)

The TPS80032 FSM controls boot sequences, TPS80032 state changes and resources initialization. The

power sequences are stored in a hard coded table (OTP memory). The FSM reacts on events, which

initiates power state transitions.

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5.3.2 Hardware Events

•

Starting events (going into ACTIVE state):

–

Power on button (PWRON ball)

Remote power on (Accessories) (RPWRON ball)

Battery plug (VSYS ball)

VAC detection (VAC ball)

USB VBUS detection (VBUS ball)

USB ID detection (USB ID ball)

RTC alarm

•

Stopping events (going into OFF state):

–

Short PWRON key press (interrupt to the processor that initiates switch off)

Long PWRON key press (hardware switch off)

Remote power on (RPWRON) (interrupt to processor that initiates switch off)

Primary watchdog expire (hardware switch off)

Regulator short circuit protection (hardware switch off)

Thermal shutdown (hardware switch off)

Backup events or shutdown events (going into NO SUPPLY or BACKUP state):

–

Removal of main and/or backup battery

Low main and/or backup battery

5.3.3 Software Events

•

Stopping events (going into OFF state):

–

DEVOFF instruction: DEV_OFF register bit all set to one (PHOENIX_DEV_ON register)

Software reset (SW_RESET), going to OFF state and then restart to ACTIVE

5.3.4 Resource Definition

A resource is an element that provides the necessary to a system to operate. Typical resources are

supplies, clocks, resets, references, bias. Each resource can be addressed with its unique I²C address

RES_ID (Resource Identification).

A remapping of the resource state versus the system state can be done. For example, a resource can be

set either ON or OFF when the system state is SLEEP.

5.3.5 Resource Operating Modes

5.3.5.1 Voltage Regulator Operating Modes (All Types)

In order to optimize the power consumption, three operating modes may be allowed for a voltage

regulator:

•

OFF mode: The output voltage is not maintained and the power consumption is minimized.

AMS mode: The regulator is able to deliver its nominal output voltage with a full load current capability.

Quiescent current adapts automatically to load current.

•

FORCE mode: Force active mode.

5.3.5.2 REGEN1 / REGEN2 / SYSEN Operating Modes

•

DISABLE: The REGEN1 / REGEN2 / SYSEN I/O drives the signal to its disable state.

ACTIVE: The REGEN1 / REGEN2 / SYSEN I/O drives the signal to its active state.

5.3.5.3 SMPS Operating Modes

•

OFF mode: The output voltage is not maintained and the power consumption is minimized.

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•

AUTO mode: The SMPS is able to deliver its nominal output voltage with a full load current capability.

PFM or PWM is automatically selected versus load current.

FORCED_PWM mode: The SMPS runs always in PWM even at light load. It allows to maintain a low

output voltage ripple.

5.3.5.4 Main Bandgap Operating Modes

•

OFF mode: The reference voltage is not maintained and the bandgap power consumption is

minimized.

•

ON ACCURATE mode: The bandgap is able to deliver accurate nominal reference voltage.

LOW POWER mode: A nominal but less accurate voltage reference is maintained with very low power

consumption.

•

ON FAST mode: The nominal reference voltage is maintained with less precision as the low pass filter

on the VBG output is disabled. This condition during power up phase allows a quicker setting of the

reference voltage. This mode is only used during a BOOT or WAKEUP phase.

5.3.5.5 Comparators Operating Modes

•

OFF mode: The comparator is disabled, result of compare operation is forced to true, power

consumption is minimized.

•

ON mode: The comparator is enabled result of compare depends on its inputs.

5.3.5.6 Hot-die Warning Operating Modes

•

ACTIVE mode: The hot-die warning feature is enabled.

OFF mode: The hot-die warning feature is disabled.

5.3.5.7 Clocks and PWM1 / PWM2 Drivers Operating Modes

•

DISABLE mode: The signal at driver output is stopped.

ACTIVE mode: The signal at driver output is running.

5.3.6 Addressing Resources Registers

Three types of register can be associated to a resource:

•

Configuration Registers:

–

CFG_TRANS register

CFG_STEP register (DVS resource)

•

State Register:

CFG_STATE register

DVS Registers:

–

CFG_FORCE register

CFG_VOLTAGE register (DVS resource)

The configuration registers are intended for resource configuration, while state registers are intended to

manage the resource state transition; finally DVS registers are intended to dynamic voltage control via

DVS-I²C. Configuration and state registers contribute to determine resource behavior. The state register

defines to which state the resource has to switch and the timing for the transition. The configuration

register defines the resource behavior in a defined state. Although both types of registers can be access

by the FSM and the CTL-I²C, it is preferable to reserve I²C access to configuration registers and FSM

access to state registers. Access to DVS registers is exclusively done via DVS-I²C in applications using

DVS capability.

These registers can be accessed in different ways, individual access to allow accessing registers through

their physical address (ID) and broadcast messages that are interpreted by individual resources in function

of their configuration

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5.3.6.1 State Register (CFG_STATE)

Purpose of this register is to set the state of the resource. If the resource is associated to a Power request

pin (PREQ1, PREQ2 or PREQ3), any state change of the Power request pin will be transmitted to all its

associated resources.

5.3.6.2 State Mapping Register (CFG_TRANS)

Purpose of this register is to map the individual resource state to the state resulting from system states

arbitration (RES_STATE).

5.3.6.3 Voltage Register (CFG_VOLTAGE)

This register is dedicated to resources belonging to the power provider category (LDO or SMPS), is used

to set the voltage level of the SMPS and LDO.

5.3.6.4 Force Register (CFG_FORCE)

This register is dedicated to DVS-SMPS. It can be accessed through DVS-I²C and power management

control FSM during power on sequence. This is used to force the voltage without ramping.

5.3.6.5 Step Register (CFG_STEP)

This register is dedicated to DVS-SMPS; its purpose is to control the slope of voltage ramping when VSEL

content is modified.

5.3.7 Power Management I/Os Functionality

5.3.7.1 BOOT[2:0]

Purpose of these input balls is to select the boot sequence executed by the TPS80032 device during the

startup phase. BOOT [2:0] balls provide indication on the following parameters to select the correct value

for the supply voltages and detection thresholds (see PH_STS_BOOT register).

•

BOOT0: Battery chemistry (cut-off voltage), described in EPROM Application Note.

BOOT1: Described in EPROM Application Note.

BOOT2: Described in EPROM Application Note.

5.3.7.2 PWRON

The PWRON ball is intended to be connected to a push button to control system power on / off. An

internal pull up on the battery domain is implemented on this input.

Three timers are associated to this input duration:

•

A short timer of 15ms to confirm the key press detection; this confirmation initiates a power-on

sequence or generation of an interrupt depending on system state.

A long timer, programmable from 50 ms to 1.55 seconds, that measures the key press. A register bit

(KPD_STS bit in KEY_PRESS_DURATION_CFG register) is set and an interrupt (SPDURATION) is

generated if the key press duration exceeds the timer duration.

•

A very long timer of 8 or 4 seconds (the duration is selected with LPK_TIME bit in

KEY_PRESS_DURATION_CFG register) that generates a shutdown by forcing the TPS80032 device

to the WAIT-ON state. The shutdown reason is indicated by a register bit (DEVOFF_LPK in

PHOENIX_LAST_TURNOFF_STS register). The shutdown feature can be disabled by an OTP

memory bit (LPK_DISABLE) and there is another OTP memory bit (LPK_RESTART) which can be

used to generate a startup just after the transition to WAIT-ON.

PWRON detection is performed on both falling and rising edges (1 interrupt line, 1 interrupt status bit). The

polarity is defined as following:

•

High level: Key released

Low level: Key pressed

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5.3.7.3 RPWRON

RPWRON is also intended to control the system power on / off. An internal pull up on the battery domain

is implemented on this input. One timer is associated to this input duration:

•

A short timer of 15ms to confirm detection, this confirmation initiates a power-on sequence or

generation of an interrupt depending on system state.

RPWRON can be programmed with OTP bit (RPWRON_OFF_DIS) to generate a shutdown sequence. In

this situation there is 1 second delay between the interrupt generation and the shutdown sequence.

RPWRON detection is performed on both falling and rising edges. The polarity is defined as following:

•

High level: Key released

Low level: Key pressed

5.3.7.4 REGEN1, REGEN2

The power management FSM controls these output signals. These balls are activated during the power on

/ power off sequences. The timing of activation is dependant of the power sequence (OTP memory).

REGEN1 and REGEN2 can be used to control two different external power supplies. The associated

registers are:

•

REGEN1_CFG_TRANS, REGEN1_CFG_STATE

REGEN2_CFG_TRANS, REGEN2_CFG_STATE

The polarity is defined as following:

•

High level: Active

Low level: Disabled

5.3.7.5 SYSEN

This output signal is controlled by the power management FSM, is activated during the power on / power

off sequences. The timing of activation is dependant of power sequence. SYSEN can be used to control

an external power supply or a slave PM device. SYSEN related registers are:

•

SYSEN_CFG_TRANS, SYSEN_CFG_STATE

The polarity is defined as following:

•

High level: Active

Low level: Disabled

5.3.8 PREQ1, PREQ2, PREQ3 Hardware Commands

ACTIVE and SLEEP state transitions are transmitted to the TPS80032 device using signal PREQ1. On a

PREQ1 transition, the FSM executes an ACTIVE to SLEEP or SLEEP to ACTIVE sequence. This

sequence is hardcoded in the OTP memory. FSM conveys sequence information to the resources

assigned to PREQ1 (assigned by PREQ1_RES_ASS_X register), by writing in to CFG_STATE register

and set each resource in a state based on the state of the PMIC and based on the translation state

register setting (XXX_CFG_TRANS). The request signals PREQ2 and PREQ3 are used as enable signals

for resources. The regulators and SYSEN, REGEN1, and REGEN2 signals can be assigned to PREQ2 or

PREQ3 (PREQ2_RES_ASS_X and PREQ3_RES_ASS_X register), and they are controlled as

enabled/disabled with PREQ2 or PREQ3 signals.

If one of the request signal requests the resource, it will be enabled. If none of the request signal requests

the resource and the corresponding CFG_STATE register is cleared, it will be disabled.

By default PREQ signals are masked. System state is not affect by PREQ signals while they are masked.

PREQ masks configuration bits (MSK_PREQ1, MSK_PREQ2, MSK_PREQ3) are located in the register

PHOENIX_MSK_TRANSITION.

PREQ balls status are available in the STS_HW_CONDITIONS register (STS_PREQ1, STS_PREQ2 and

STS_PREQ3 bits). PREQ1, PREQ2, PREQ3 are supplied on VIO voltage domain.

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The polarity is defined as following:

•

High level: resources are in active state

Low level: resources are in sleep state

Dedicated register bits (SENS_PREQ1, SENS_PREQ2 and SENS_PREQ3) allow reversing the PREQ

balls polarity (PHOENIX_SENS_TRANSITION register).

5.3.9 DVS Software Commands

Only SMPS DVS compliant can be accessed by the DVS-I²C.

On top of hardware commands, DVS compliant power resources (SMPS1/2/5) can receive additional

commands via the DVS-I²C. The DVS-I²C port can address two types of register:

•

A command register

A voltage register

The DVS command field (2 MSB bits of xxxx_CFG_FORCE register) will be interpreted as follow:

•

00: ON Force Voltage: The power resource is set in ON mode with the voltage value defined in the 6

LSB bits of the command register SMPS1/2/5_CFG_FORCE

01: ON: The power resource is set in ON mode with the voltage value defined in the

SMPS1/2/5_CFG_VOLTAGE voltage register

10: SLEEP Force Voltage: The power resource is set in SLEEP mode with the voltage value defined in

the 6 LSB bits of the command register SMPS1/2/5_CFG_FORCE

11: SLEEP: The power resource is set in SLEEP mode with the voltage value defined in the

SMPS1/2/5_CFG_VOLTAGE voltage register

The SLEEP Force Voltage command with the voltage value set at 000000 must be naturally interpreted as

a shutdown command for the power resource.

ON FORCE / SLEEP FORCE set the voltage independently of the adaptive voltage scaling. ON / SLEEP

follow the adaptive voltage scaling.

NOTE

•

Default value is the voltage value register (both register will be set with the same default

value)

When the voltage is switched on the force voltage value, this is done smoothly with a

maximum ramping define by register STEP

DVS has only access to register voltage and force voltage (no access to register step) for

SMPS1, SMPS2 and SMPS5

All power resources, LDOs and non-DVS-SMPS, can be accessed by the control I²C (CTL-I²C). The

control I²C allows the host processor to access all the internal registers for configuration purpose or

resource commands. LDOs state can be changed by writing to the register xxx_CFG_STATE register and

the output voltage level can be controlled by xxx_CFG_VOLTAGE register. The five LSBs represent a

binary value used to compute the absolute voltage value to be generated by the LDO:

Absolute Voltage value = 1.0 V + 0.1 V * (binary value - 00000001)

This equation applies to all general-purposes LDOs, for all codes from 00000001 to 00011000. For the

remaining codes, it has been specified dedicated output voltages:

•

00000000 sets the output voltage to 0 V

00011001 to 00011110 codes are reserved

00011111 code sets the output voltages at 2.75 V

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SMPS state (on/off) can be changed by writing to the register xxx_CFG_STATE register. SMPS_OFFSET

and SMPS_MULT are used to control the offset and the extended mode of the SMPS respectively. The

output voltage of the SMPS is calculated based on the equations below:

•

Offset and Extended mode disabled

Nominal Voltage value = 0.6077 V + 0.01266 V * (binary value – 00000001)

Offset enabled and Extended mode disabled

Nominal Voltage value = 0.6077 V + 0.1013 V + 0.01266 V * (binary value – 00000001)

Offset disabled and Extended mode enabled

Nominal Voltage value = (0.6077 V + 0.01266 V * (binary value – 00000001)) * (43/21 + 1)

Offset and Extended mode enabled

–

Nominal Voltage value = (0.6077 V + 0.1013 V + 0.01266 V * (binary value – 00000001)) * (43/21 +

1)

5.4 Reset System

This section describes the different reset triggers and the signals related to resets.

5.4.1 Warm Reset (NRESWARM)

The TPS80032 device detects a request for a warm reset on the NRESWARM ball. The warm reset

restarts the system without turning off the supplies. After a warm reset, the system is configured the same

as after a first switch on (default configuration), except that the states of all resources are unchanged and

all supply voltage values can be preserved, depending on the warm-reset sensitivity bit value (WR_S bit in

SMPSx_CFG_VOLTAGE and LDOx_CFG_VOLTAGE registers):

•

All resources not included in the switch-on sequence keep the state (ON or OFF) they have just before

the warm reset occurs.

Depending on the sensitivity bit, those resources either keep the value they had before the warm reset

or are set to their default value.

All resources included in the start-up sequence are always restarted.

During the power-on sequence, the TPS80032 device ignores the warm reset until the host processor

releases it.

NRESWARM is an input reset signal. A peripheral or host processor can activate this signal by a software

reset. A reset button can be connected to this line to generate a warm reset. The minimum duration of

NRESWARM is two clock periods of 32 kHz. The polarity of NRESWARM is active low.

The warm reset affects the POWER and CHARGER registers. Registers for other modules like the USB,

FUEL GAUGE, GPADC, and PWM are not affected by a warm reset.

5.4.2 Primary Watchdog Reset

The TPS80032 device includes a primary watchdog timer that generates a reset of the system in case of a

software anomaly (no response, infinite loop). The primary watchdog is programmable from 1 to 127

seconds with 1-second steps and a default value of 32 seconds. If the primary watchdog expires, a reset

with

a

new startup is generated. At the same time, the DEVOFF_WDT bit (in the

PHOENIX_LAST_TURNOFF_STS register) is set to indicate the primary watchdog expiration. The

DEVOFF_WDT bit must be cleared in order to allow a new reset/start-up sequence if a primary watchdog

expires again. If the bit has not been cleared the TPS80032 device generates a reset, thus forcing the

device to the WAIT-ON/OFF state. This prevents infinite looping in case of software corruption.

The watchdog is initialized to its default value when the system is in the WAIT-ON/OFF state, and starts

leaving the WAIT-ON/OFF state to go to the ACTIVE/SLEEP states. The primary watchdog cannot be

disabled by I²C writing if it is enabled by the MSK_WDT OTP memory bit.

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The HOLD_WDG_INSLEEP bit (in the CFG_INPUT_PUPD1 register) is used to select the states in which

the watchdog is running. If the bit is 0, the watchdog is running in the SLEEP and ACTIVE states, whereas

if the bit is 1, the watchdog is running in the ACTIVE state and is gated in the SLEEP state.

5.4.3 Thermal Shutdown

If the die temperature gets too high, the thermal shutdown generates a reset, thus forcing the TPS80032

device to the WAIT-ON/OFF state.

5.4.4 NRESPWRON

The NRESPWRON output signal is the reset signal delivered to the host processor at the end of the

power-on sequence. It is released when all the TPS80032 supply voltages (core and I/Os) are correctly

set up. In addition, the NRESPWRON signal is gated until the 32-kHz crystal oscillator is stable and

delivered to the platform. The polarity of the NRESPWRON signal is active low.

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5.5 System Control

Internal hardware monitors the different energy sources (main and backup) and charging sources (VAC or

VBUS). A set of comparators is dedicated to energy source selection to generate an uninterrupted power

supply (UPR), which exists as soon as a valid energy source is present. The backup battery is considered

to be a valid energy source after the device is first powered up. POR is released when UPR rises above to

POR threshold and the voltage regulator VBRTC provides a supply for the digital control, the 32-kHz

oscillators, and the low-power bandgap.

When the system voltage rises above the V_{SYSMIN_LO}threshold, the digital control enables the checks of

the startup events. When a startup event is detected, a final check of the system voltage is done versus

the V_{SYSMIN_HI}threshold to pursue the power-up sequence.

When the system is active the V_{SYSMIN_HI}comparator can be used for system voltage monitoring

(VSYS[5:0] bits in VSYSMIN_HI_THRESHOLD register) to perform checks on system voltage. It

compares system voltage versus a programmable value and generates interrupt (VSYS_VLOW) when

voltage rises above and drops below the programmed threshold. The comparator can be programmed

from 2.3 to 4.6 V in 50-mV steps. The interrupt generation can be masked if the feature is not used.

If the system voltage drops below the V_{SYSMIN_LO}threshold during operation, the TPS80032 system enters

the WAIT-ON state.

Figure 5-3 shows a block diagram of the analog power control.

VAC

VEXT

Shunt

Reg

VPOR

VBUS

POR

Source

select

UPR

DIG SUPPLY

VSHUNT_MIN

VBACKUP

VBRTC

Digital power-

management

controller

VREF

Backup

battery

BG

VSYSMIN_LO

VSYSMIN_HI

VSYSMIN_LO

VSYSMIN_HI

VSYS

VRTC

Main

battery

SWCS057-006

Figure 5-3. Block Diagram of the Analog Power Control

NOTE

•

UPR = V_SYSif: (V_SYS> V_{SYSMIN_LO}) or (V_SYS> V_BACKUP) and (V_SHUNT< V_{SHUNT_MIN})

UPR = V_BACKUPif: (V_SYS< V_{SYSMIN_LO}) and (V_SYS< V_BACKUP– 0.1 V) and (V_SHUNT

V_{SHUNT_MIN}) and POR = 0

<

•

UPR = V_SHUNTif: (V_SYS< V_{SYSMIN_LO}) and (V_SHUNT> V_{SHUNT_MIN})

Figure 5-4 shows the power state transition diagram.

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From any

state

T2

NO

SUPPLY

BACKUP

T1

T8

WAIT-ON

OFF

All groups

From any

state

T4

T3

ACTIVE

Any groups

SLEEP

All groups

T6

T5

T7

SWCS057-008

Figure 5-4. Power State Transition Diagram

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•

Power-on transitions: T1

–

System is in NO SUPPLY or BACKUP state. Connection of a valid energy source initiates the

transition to WAIT-ON state.

–

Triggering event: VSYS > V_{SYSMIN_LO}

•

Insertion of a charged main battery

Precharge is active main battery voltage rises

–

Condition: VUPR > VPOR

•

Power-off transition: T2

–

The system is in any state. Removal of all energy sources initiates a transition to NO SUPPLY

state.

–

Triggering event: VUPR < VPOR

•

Main battery discharge or removal

Backup battery discharge or removal

Charger unplugged

–

Condition: No more valid energy source

•

Switch-on transition: T3

–

The system is in WAIT-ON state, able to accept a hardware switch-on condition, which initiates a

transition to ACTIVE state.

–

Triggering event:

•

Push button pressed and released (PWRON)

Charging source plug (USB or external)

RTC alarm

Accessory plug (RPWRON)

Insertion of a charged main battery or battery charge running (enabled by default)

Software reset (following transition T4)

USB ID plug insertion (disabled by default)

–

Condition: VSYS > V_{SYSMIN_HI}and no thermal shutdown active

•

Switch-off transition: T4

–

System is powered and in ACTIVE or SLEEP state. A hardware condition may initiate a transition to

reach WAIT-ON state.

–

Triggering event:

•

Group DEVOFF command (software)

Thermal shutdown

Primary watchdog timer expired

Software reset (followed by transition T3)

Long key press (8/4 seconds) on PWRON

•

Sleep-on transition: T5

–

System is powered and in ACTIVE state. A hardware condition initiates a transition to SLEEP state.

Triggering event: Subsystem group sleep command (hardware) (PREQ1 ball)

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•

Sleep-off transition: T6

–

System is powered and in SLEEP state. A hardware condition can initiate a transition to ACTIVE

state.

–

Triggering event:

•

Subsystem group active command (hardware) (PREQ1 ball)

Warm reset (reinitialization of the TPS80032 device)

Active reset transition: T7

–

System is powered and in ACTIVE state. A hardware condition can initiate a reset; system

remains in ACTIVE state.

–

Triggering event: Warm reset (reinitialization of the device)

•

Backup-on transition: T8

–

System is powered and in ACTIVE, SLEEP, or WAIT-ON state. The detection of a low main

battery initiates the transition to BACKUP state.

–

Triggering event: System voltage < V_{SYSMIN_LO}(discharge/removal)

Condition: VUPR > VPOR

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5.6 System Voltage/Battery Comparator Thresholds

Three thresholds of battery voltage condition the system state transitions:

•

POR

–

Released when the energy source provides a voltage greater than 2 V

POR threshold is the minimum voltage below which the TPS80032 device is reset.

•

VSYSMIN_LO

–

Threshold of hardware switch off

Two values, depending on the battery technology, are stored in OTP memory (VSYSMIN_LO_MIN,

VSYSMIN_LO_MAX bits) and selected by BOOT0 pin.

–

The comparator threshold (V_{SYSMIN_LO}) is configurable from 2.0 to 3.1 V in 50-mV steps.

•

VSYSMIN_HI

–

Threshold of switch on

Checked as condition to initiate any sequence to ACTIVE state

Two values, depending on the battery technology, are stored in OTP memory (VSYSMIN_HI_MIN,

VSYSMIN_HI_MAX bits) and selected by BOOT0 pin.

–

The comparator threshold (V_{SYSMIN_HI}) is configurable from 2.5 to 4.6 V in 50-mV steps.

For correct system behavior, the value of the V_{SYSMIN_HI}threshold must not be programmed higher

than the default system supply/charging voltage. Otherwise, the TPS80032 device does not switch

on after a charger plug with empty battery.

NOTE

The system voltage must be above the VSYSMIN_HI threshold level in order to begin the

start-up sequence. The TPS80032 device initiates the shut-down sequence if the system

voltage decreases below VSYSMIN_LO. The dropout voltage requirements for the SMPSs

and LDOs must be taken into account, otherwise the regulators may not fulfill their

specifications.

5.7 Power Resources

The power resources provided by the TPS80032 device include inductor-based SMPSs and linear LDO

voltage regulators. These supply resources provide the required power to the external processor cores

and external components as well as to the modules embedded in the TPS80032 device.

5.7.1 Short-Circuit Protection

The short-circuit current limits for all LDOs and SMPS regulators embedded in the TPS80032 device are

approximately twice their respective maximum load current. For specific LDO use cases, when the output

of the module is shorted to ground, the power dissipation can exceed the power dissipation requirement, if

no continuous preventive action is engaged.

The short-circuit protection scheme compares an LDO/SMPS output voltage to a reference voltage and

detects a short circuit if the regulator voltage drops slightly below its minimum output voltage (1 V for

LDOs and 0.6 V for SMPSs). A short-circuit protection scheme is included in each power resource of the

TPS80032 device to ensure that if the output of an LDO or SMPS is short-circuited, the power dissipation

does not increase drastically.

All LDOs/SMPSs include this short-circuit protection that monitors the regulator output voltage and

generates an interrupt when a short-circuit is detected (see interrupt mapping). The VRTC regulator is the

unique power resource that cannot generate an interrupt when shorted. Therefore, this regulator includes

a different analog short-circuit mechanism that does not require a switch off the regulator.

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If the short-circuit is detected the SMPS_LDO_SHORT_STS register is updated and the application

processor needs to clear the short-circuit interrupt (VXXX_SHORT) and turn off the associated power

resource within the 10-ms default time. If the interrupt is not cleared before the counter expires, the

TPS80032 device switches off automatically. In parallel, the primary watchdog can shut down the device,

if the watchdog expires.

In normal use conditions, when the TPS80032 device is turned off, all LDO/SMPS resources (except

VRTC/VBRTC) are turned off and their corresponding short-circuit mechanisms are reset. If a short-circuit

condition persists in which all power resources should normally be off, the TPS80032 device does not

power up again.

CAUTION

If the external components of the SMPSs or LDOs are not placed and the regulator is

enabled, the short-circuit detection triggers. If software is unable to clear the interrupt

and shut down the regulator within the short-circuit counter time, the PMIC shuts down.

To generate a succesful start-up sequence, all the regulators enabled during start up

must include the external components (capacitors and coils).

5.7.2 SMPS Regulators

The TPS80032 device includes five SMPS regulators, three of which have DVS capability and thus can be

selected to provide independent core voltage domains to the host processor. Each SMPS is a high-

frequency, synchronous, step-down DC-DC converter allowing the use of low-cost chip inductors and

capacitors.

SMPS1 operates with a 3-MHz fixed-switching frequency and the other SMPSs operate at 6-MHz fixed-

switching frequency and enters the power-save mode operation at light load currents to maintain high

efficiency over the entire load current. Pulse-frequency modulation (PFM) mode extends the battery life by

reducing the quiescent current to 30 µA (typical) during light load and standby operation. For noise-

sensitive applications, the appropriate SMPS can be forced into fixed-frequency pulse-width modulation

(PWM) mode (FORCE PWM setting in SMPSx_CFG_TRANS registers). In shutdown mode, the current

consumption is reduced to less than 1 µA.

Each SMPS is a synchronous step-down converter operating with a fixed-frequency, PWM at moderate-to-

heavy load currents. At light load currents, the converter operates in power-save mode with PFM. The

converter uses a unique frequency locked-ring oscillating modulator to achieve best-in-class load and line

response and allows the use of tiny inductors and small ceramic input and output capacitors. At the

beginning of each switching cycle, the P-channel MOSFET switch is turned on and the inductor current

ramps up, raising the output voltage until the main comparator trips. The control logic then turns off the

switch.

One key advantage of the nonlinear architecture is the absence of a traditional feedback loop. The loop

response to change in VO is essentially instantaneous, which explains its extraordinary transient

response. The absence of a traditional, high-gain compensated linear loop means that the regulator is

inherently stable over a wide range of L and CO. Each SMPS integrates a current limit in the P-channel

MOSFET (in SMPS1 in the high-side N-channel MOSFET). When the current in the MOSFET reaches its

current limit, the MOSFET is turned off and the low-side N-channel MOSFET is turned on for at least 150

ns.

With decreasing load current, the device automatically switches into pulse-skipping operation in which the

power stage operates intermittently based on load demand. By running cycles periodically, the switching

losses are minimized, and the device runs with a minimum quiescent current and maintains high

efficiency. The converter positions the DC output voltage approximately 1% above the nominal output

voltage. This voltage-positioning feature minimizes voltage drops caused by a sudden load step. When in

PFM mode, the converter resumes its operation when the output voltage trips below the nominal voltage.

It ramps up the output voltage with a minimum of three pulses and goes into PFM mode when the inductor

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current has returned to a zero steady state. Because of the dynamic voltage positioning, the average

output voltage in PFM mode is slightly higher than its nominal value in PWM mode. During PFM operation,

the converter operates only when the output voltage trips below a set threshold voltage. It ramps up the

output voltage with several pulses and goes into PFM mode when the output voltage exceeds the nominal

output voltage.

The rated output current is 5.0/3.0 A for SMPS1, 2.5 A for SMPS2, and 1.1 A for SMPS3, SMPS4, and

SMPS5 regulators.

5.7.2.1 Soft Start

Each SMPS has an internal soft-start circuit that limits the inrush current and thus the input voltage drop

during start up. The soft-start system progressively increases the on-time from a minimum pulse-width of

30 ns as a function of the output voltage. This mode of operation continues for 200 µs after enable. If the

output voltage does not reach its targeted value by this time, such as in the case of heavy load, the soft-

start transitions to a second mode of operation. The converter then operates in a current-limit mode,

specifically the PMOS current limit is set to half the nominal limit and the N-channel MOSET remains on

until the inductor current is reset. After an additional 100 µs, the device ramps up to full current-limit

operation, providing that the output voltage rises above approximately 0.7 V. Therefore, the start-up time

mainly depends on the output capacitor and load current.

5.7.2.2 Inductor Selection

All step-down converters are designed to operate with an effective inductance value from 0.40 to 1.30 µH

and with output capacitors from 4 to 15 µF (15 to 29 µF for SMPS1 ). The maximum output capacitor

value is normally used during the start-up phase, when the capacitor is still unbiased. The internal

compensation is optimized to operate with an output filter of L = 1.0 µH and CO = 10 µF (SMPS2, SMPS3,

SMPS4, and SMPS5) and CO = 22 µF (SMPS1 ). Larger or smaller inductor values can be used to

optimize the performance of the device for specific operation conditions. If SMPS1 is used for up to 5.0-A

current levels, it is recommended to use two 1.0-µH inductors in parallel.

The inductor value affects the following:

•

The peak-to-peak ripple current

The PWM-to-PFM transition point

The output voltage ripple

The efficiency

The selected inductor must be rated for its DC resistance and saturation current. The ripple current of the

inductor decreases with higher inductance and increases with higher VI or VO.

In high-frequency converter applications, the efficiency is essentially affected by the inductor AC

resistance (quality factor) and to a smaller extension by the inductor DCR value. To achieve high-

efficiency operation, special care must be taken to select inductors featuring a quality factor above 20 at

the switching frequency. Increasing the inductor value produces lower RMS currents, but degrades

transient response. For a given physical inductor size, increased inductance usually results in an inductor

with lower saturation current.

The total losses of the coil consist of the losses in the DC resistance and the following frequency-

dependent components:

•

The losses in the core material (magnetic hysteresis loss, especially at high switching frequencies)

Additional losses in the conductor from the skin effect (current displacement at high frequencies)

Magnetic field losses of the neighboring windings (proximity effect)

Radiation losses

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5.7.2.3 Output Capacitor Selection

SMPS advanced fast-response voltage mode control allows the use of tiny ceramic capacitors. Ceramic

capacitors, with low ESR values, provide the lowest output voltage ripple. The output capacitor requires

either an X7R or an X5R dielectric. Y5V and Z5U dielectric capacitors, aside from their wide variation in

capacitance over temperature, become resistive at high frequencies.

At nominal load current, the device operates in PWM mode and the overall output voltage ripple is the

sum of the voltage step caused by the output capacitor ESL and the ripple current flowing through the

output capacitor reactance.

At light loads, the device operates in power-save mode, and the output voltage ripple is independent of the

output capacitor value. The output voltage ripple is set by the internal comparator thresholds and

propagation delays.

5.7.2.4 Input Capacitor Selection

Because the buck converter has a pulsating input current, a low ESR input capacitor must prevent large

voltage transients that can cause misbehavior of the device or interferences with other circuits in the

system. Although a 2.2-µF capacitor is sufficient for most applications, a 4.7-µF capacitor is recommended

to improve input noise filtering.

CAUTION

Take care when using only ceramic input capacitors. When a ceramic capacitor is used

at the input and the power is being supplied through long wires, such as from a wall

adapter, a load step at the output can induce ringing at the VIN pin. This ringing can

couple to the output and be mistaken as loop instability or could even damage the part.

In this case, additional bulk capacitance (electrolytic or tantalum) must be placed

between C_Iand the power source lead to reduce ringing that can occur between the

inductance of the power source leads and C_I.

5.7.2.5 SMPS1, SMPS2, SMPS5

The TPS80032 device includes three SMPS buck converters (SMPS1, SMPS2, and SMPS5) with DVS-

control capability; their output voltages (SMPSx_CFG_FORCE registers) are independently controlled

using the DVS-I²C dedicated interface. The output voltages can be also controlled using the CTL-I²C

interface with SMPSx_CFG_VOLTAGE registers. Default output voltage at power up is configurable by the

OTP memory. The regulators can be used, for example, for a processor or 1.8-V I/O supply.

SMPS1 has two output current ranges selectable by OTP memory bit (SMPS1_5A). A 3-A mode supports

output currents up to a 3-A level and 5-A mode supports output currents up to a 5-A level. The electrical

characteristics depend on the selected mode (see Table 4-1).

5.7.2.6 SMPS3, SMPS4

The TPS80032 device includes two SMPS buck converters (SMPS3 and SMPS4) that can be used, for

example, for memory supply, peripheral, or preregulation.

5.7.3 LDO Regulators

All LDOs are integrated so that they can be connected to an internal preregulator, to an external buck

boost SMPS, or to another preregulated voltage source.

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The output voltages of all LDOs can be selected, regardless of the LDO input voltage level V_IN. There is

no hardware protection to prevent software from selecting an improper output voltage if the V_INminimum

level is lower than T_DCOV(total DC output voltage) + D_V(dropout voltage). In such conditions, the output

voltage would be lower and nearly equal to the input supply. For example, in further electrical tables, only

the possible input supplies, which fulfill the electrical performances on all their range, are mentioned at

each selected output.

The regulator output voltage cannot be modified on the fly, from the voltage range of 1.0 to 2.1 V to the

other voltage range of 2.2 to 3.3 V and vice versa. The regulator must be restarted in these cases.

If an LDO is not needed and not turned on by software or a switch-on sequence, the external components

can be removed. The TPS80032 device is not damaged by this configuration, and the other functions do

not depend on the unmounted LDOs and continue to work.

5.7.3.1 VANA

The VANA voltage regulator is dedicated to supply the analog functions of the TPS80032 device, such as

the GPADC, gas gauge, and other analog circuitries.

VANA can be enabled and disabled individually or when associated with a power group. This power

resource control optimizes the overall SLEEP state current consumption. This regulator also can be used

at platform level to supply other applications, provided they do not generate noise to the supply line and

the maximum current is less than 15 mA.

5.7.3.2 VRTC, VBRTC

The VRTC voltage regulator supplies always-on functions, such as RTC and wake-up functions. This

power resource is active as soon as a valid energy source is present.

This resource has two modes:

•

Normal mode when supplied from main battery and able to supply all digital part of the TPS80032

device

•

Backup mode when supplied from a backup battery or from weak main battery and able to supply only

always-on parts

VRTC supplies the digital part of the TPS80032 device. In BACKUP state, the VRTC regulator is in low-

power mode (VBRTC) and is supplied from backup battery or from weak main battery; the digital activity is

reduced to the RTC parts only and maintained in retention registers of the backup domain. The rest of the

digital is under reset and the clocks are gated.

In WAIT-ON state, the turn-on events and detection mechanism are also added to the previous RTC

current load and are still supplied on VRTC or VBRTC (the supply is controlled with VRTC_EN_OFF_STS

bit in BBSPOR_CFG register).

In ACTIVE state, by default the VRTC switches automatically into standard power mode (the supply is

controlled with VRTC_PWEN bit in BBSPOR_CFG register). The reset is released and the clocks are

available.

In SLEEP state, VRTC is kept active. The reset is released and only the 32-kHz clock is available. Still, to

reduce power consumption, VBRTC instead of VRTC can be used by software (VRTC_EN_SLP_STS bit

in BBSPOR_CFG register).

5.7.3.3 LDO1, LDO2, LDO3, LDO4, LDO5, LDO6, LDO7

LDO5 is a programmable linear voltage converter used to power, for example, a multimedia card (MMC)

slot. On top of the normal control by the power controller, it can be turned off when card removal is

detected (the LDO5_AUTO_OFF bit in the MMCCTRL register).

Voltage regulator LDO7 can be used to supply removable USIM memory. In addition to the normal control

by the power controller, it can be turned off when card removal is detected (the VSIM_AUTO_OFF bit in

the SIMCTRL register).

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The TPS80032 device includes five general-purpose resources (LDO1, LDO2, LDO3, LDO4, and LDO6)

to supply external peripherals, such as cameras sensors, display drivers, memories (eMMC), and others.

When not used as a supply, LDO3 can deliver a PWM supply to drive a vibrator motor.

5.7.3.4 LDOLN, LDOUSB

The LDOLN regulator supplies noise-sensitive functions. LDOLN can be preregulated by SMPS.

The LDOUSB regulator supplies the USB PHY from the PMID node of the USB VBUS input or from

system supply/battery.

5.8 Backup Battery Charger

The TPS80032 device provides a BACKUP state in which a backup battery powers the RTC and other

secure registers when no other energy source is available. The backup battery is optional and can be

nonrechargeable or rechargeable. The rechargeable battery can be charged from the system supply using

the backup battery charger.

The backup battery charger includes two control loops (CC and CV). A current loop limits the charging

current when backup battery voltage is low and a voltage loop that gradually reduces the charging current

as backup battery voltage approaches its final value. The charge current limit is fixed and the end of

charge voltage is programmable (BB_SEL[1:0] bits in BBSPOR_CFG register).

The backup battery charger is controlled with BB_CHG_EN bit (in BBSPOR_CFG register) and the

charging starts if the system supply voltage is 100 mV above backup battery voltage; charging stops when

backup battery voltage equals either the selected end of charge voltage level or the system supply

voltage, if it is below the end of the charge level programmed. Backup battery charge cannot start if

system supply voltage is lower than VSYSMIN_LO. The backup battery switch controls when the system

enters BACKUP state (supplied by the backup battery).

During the transition from system supply to backup battery there can be a current spike from the backup

battery. If the output resistance of the backup battery is large, an additional capacitor is needed in parallel

with the backup battery. See the electrical characteristics for more details.

Figure 5-5 shows a block diagram of the backup battery charger.

VSYS

Vref

I_lim

VBACKUP

Voltage

selection

SWCS057-010

Figure 5-5. Block Diagram of the Backup Battery Charger

5.9 Battery Charging

The TPS80032 device has an integrated switched-mode battery charger designed to generate a system

supply and to charge the battery from a USB port. In addition, it can control an external battery charging

IC (like BQ24159) to generate a system supply and charge the battery during hardware-controlled

charging and selects the priority of the chargers so that only one is enabled at time.

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Figure 5-6 shows the block diagram of the USB charging electronics. The figure shows the USB charging-

related functions with external components. The device supports two charging configurations, operation

with Power Path and without Power Path.

In the Power Path configuration the battery line is connected to the system supply with external PMOS

transistor. The system supply is regulated by switched-mode regulator and the battery charging current

and voltage are controlled with a battery charger loop and external PMOS transistor. The sense resistor at

the output of switched-mode regulator is not needed. When the platform is supplied by battery the external

PMOS is closed.

In the non-Power Path configuration the battery line is used as a system supply and the external PMOS is

not needed because the battery current is monitored with a resistor placed between ground and negative

terminal of the battery. In this configuration a sense resistor at the output of the switched-mode regulator

is needed as it is used to control the battery charging current.

For information about the functions and external components related to VAC charging, see Section 5.9.12,

Support for External Charging IC.

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Optional

VBUS

C36

VBUS

connector

CHRG_LED_IN

S2

R10

CHRG_LED_TEST

D1

Q1

Q2

CHRG_PROT_GATE

CHRG_PMID

C37

CHRG_BOOT

C40

CHRG_DET_N

ID

Switched-mode

system

L11

C38

CHRG_SW

voltage

regulator

CHRG_CSIN

With Power Path

R9

Without Power Path

CHRG_CSOUT

System

voltage

Q3

C39

CHRG_VREF

C34

CHRG_PGND

VAC

CHRG_VSYS

C45

VAC

CONNECTOR

Battery

charger

and

Without Power Path

With Power Path

C35

S1

supplement

mode

control

CHRG_GATE

_CTRL

CHRG_EXTCHRG_ENZ

CHRG_EXTCHRG_STATZ

CHRG_VBAT

Battery

pack

CGAUGE_RESP

R2

CGAUGE_RESN

Gas gauge

Figure 5-6. Block Diagram of the System Supply Regulator and Battery Charger

The TPS80032 device supports a wide variety of rechargeable lithium-based battery technologies. Recent

battery technologies, such as Li-SiAn and LiFePo4, present a flat discharge region in the range of 3.2–3.3

V; technologies such as LiCoO2 and LiNiMnCoO2 present a flat discharge region in the range of 3.6–3.7

V. To support the different battery chemistries effectively, the TPS80032 device has programmable

VSYSMIN thresholds (OTP bits).

The charger also performs monitoring functions:

•

AC charger detection

VBUS detection

Battery presence detection

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•

VBUS overvoltage detection

Battery overvoltage detection

Battery end-of-charge detection

Thermal protection

Watchdogs

The same switches and external components that are used for system supply generation in buck mode

can be used to generate a 5-V USB OTG supply in boost mode. In this mode, the TPS80032 device can

deliver up to 300 mA of total current for USB connector and for LDOUSB.

The VBUS input in the TPS80032 device operates up to 6.3 V; above this, level the system supply

regulator is disabled. The VBUS input tolerates up to 20-V input voltages and down to –0.3-V input

voltages. The negative input voltage protection can be improved with external PMOS transistor and

resistor (shown in Figure 5-6 as optional components). This gives tolerance down to –14 V.

NOTE

The charging source terms are defined as follows (USB Battery Charging Specification, Rev.

1.2)

•

Standard Downstream Port (SDP): a downstream port on a device that complies with the

USB 2.0 definition of a host or hub.

Charging Downstream Port (CDP): a downstream port on a device that complies with the

USB 2.0 definition of a host or a hub, except that it shall support the Charging

Downstream Port features allowing higher charging currents.

•

Dedicated Charging Port (DCP): a downstream port on a device that outputs power

through a USB connector, but is not capable of enumerating a downstream device.

•

USB Charger: a device with a DCP, such as a wall adapter or car power adapter.

Accessory Charger Adaptor (ACA): an adaptor which allows a single USB port to be

attached to both a charger and another device at the same time.

•

Charging Port: a DCP, CDP or ACA

5.9.1 Charger and System Supply Regulator Controller Operation

The operation of the battery charger and the system supply regulator depends on the platform

configuration. There are two different configurations for hardware:

•

Power Path configuration (POP_APPSCH OTP bit is 1); an external PMOS is needed between VSYS

and VBAT.

•

Non-Power Path configuration (POP_APPSCH OTP bit is 0); VBAT is used as a system voltage.

In addition, software interaction with battery charging in both configurations depends on the

AUTOCHARGE OTP bit:

•

Hardware controlled charging (AUTOCHARGE bit is 1); software interaction is minimized.

Software controlled charging (AUTOCHARGE bit is 0); software controls the battery charging.

The operation in the four different modes has been described in Section 5.9.1.1 through Section 5.9.1.4.

The flow chart for startup, shutdown, and fallback (Power Control) operates in parallel with a flow chart of

the system supply regulator and battery charging (Charger Control). The safety timer and watchdog

operation is described in Section 5.9.6 and the charging profile and default charging parameters are

described in Section 5.9.3.

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5.9.1.1 Power Path with Hardware Controlled Charging

The TPS80032 device starts up for the VBUS or VAC plug insertion as soon as the system voltage is

above the VSYSMIN_HI threshold level if the device is not already powered on. The hardware starts the

system supply regulation and battery charging automatically if a USB Charging Port or VAC Charger is

detected, or if the battery voltage is below VBATMIN_HI and the device is powered off. If the VBUS is

supplied by the USB standard downstream port and the battery is above VBATMIN_HI or the device is

powered on, the system supply regulator and battery charger are not started by hardware. The host

processor must enumerate to the USB host, configure to a certain current level, set the VBUS input

current limit, and enable the system supply regulator and battery charging.

If the system voltage drops below VSYSMIN_LO, the device shuts down and sets a fallback bit to indicate

the fallback situation. A new startup is initiated when the battery is charged above the VBATMIN_HI

voltage level and after startup, the host processor clears the bit. If the fallback bit is active during the

shutdown, the system supply regulator and battery charging is disabled. This prevents infinite looping in a

low/no battery case with a weak charger. The operation is shown in Figure 5-7.

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VBUS OR VAC

Plug insertion

VBUS OR VAC

Plug insertion

E_MSK_

VBATMIN_

CHECK = ’1'

(OTP)

No

Host processor

No

Yes

No

USB Charging

Port detected

VBAT <

VBATMINHI

enumerates to

USB Host and

configures

VAC detected

Yes

PMIC in PowerON

No

Yes

PMIC in PowerON

No

HW sets VBUS input

current limit to

CIN_LIMIT (OTP)

Yes

HW enables external

VAC DCDC

Host prosessor

sets the VBUS

input current limit

and enables

DCDC

No

VSYS >

VSYSMIN_HI

HW sets VBUS inpiut

current limit to

E_CIN_LIMIT

Yes

HW enables DCDC

Startup

HW enables/continues

battery charging

PowerON

Host processor

clears Fallback bit

when VBAT >

VBATMIN_HI

(if needed)

Termination

current detected

by HW

No

Yes

VBAT decreases

below recharge

threshold

HW gates battery

charging

No

VSYS <

VSYSMIN_LO

No

Yes

VBUS removal AND

DCDC enabled

VAC removal AND

VAC DCDC enabled

Shutdown

Yes

PMIC in PowerON

Host processor enables

charging from the

remaining source or stops

the charging

No

HW sets

Fallback to ’1'

Fallback = 1

Yes

No

Yes

VAC present

No

VBUS present

No

HW disables DCDC

and battery charging

VBAT >

VBATMINHI

Yes

No

HW enables battery

charging and remaining

DCDC

HW disables VAC

DCDC and battery

charging

HW disables DCDC

and battery charging

POWER CONTROL

CHARGER CONTROL

Figure 5-7. Battery Charging Flowchart (With Power Path, AUTOCHARGE=1)

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5.9.1.2 Power Path with Software Controlled Charging

The TPS80032 device starts up for the VBUS or VAC plug insertion as soon as system voltage is above

the VSYSMIN_HI threshold level if the device is not already powered on. If the device is powered off, the

hardware sets the correct VBUS input current limit and starts the system supply regulator either from

VBUS or from VAC and the battery charging using the default values from OTP memory. The default

charging voltage must be set to the proper battery threshold voltage level to comply with the USB

standard. When the device is powered on, the host processor takes control over charging.

If the system voltage drops below VSYSMIN_LO, the device shuts down and sets a fallback bit to indicate

the fallback situation. A new startup is initiated when the battery is charged above the VBATMIN_HI level

and the host processor clears the bit. If the fallback bit is active during the shutdown, the system supply

regulator and battery charging is disabled. This prevents infinite looping in a low/no battery case with a

weak charger. The operation is shown in Figure 5-8.

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VBUS OR VAC

Plug insertion

VBUS OR VAC

Plug insertion

Yes

PMIC in PowerON

No

VBUS detected

AND USB

Charging Port

detected

No

VAC detected

Yes

No

VSYS >

VSYSMIN_HI

Yes

HW sets VBUS input

Yes

current limit to

E_CIN_LIMIT

HW sets VBUS input

current limit to

CIN_LIMIT (OTP)

HW enables external

VAC DCDC

Startup

HW enables DCDC

and battery charging

HW enables battery

charging

PowerON

SW controlled charging

- Clears Fallback bit when VBAT >

VBATMIN_HI (if needed)

- Enumerates and configures to USB

host if needed

SW controlled

charging

- Checks interrupts

- Monitors battery temperature

- Updates watchdog

VBUS removal AND

charging from VBUS

enabled

VAC removal AND

charging from VAC

enabled

- Monitors USB suspend

- Selects priority between chargers

- Updates charging parameters

No

Yes

VSYS <

VSYSMIN_LO

PMIC in PowerON

Yes

Host processor enables

charging from the

remaining source or stops

the charging

Yes

No

Shutdown

VBAT >

VSYSMINHI

Yes

VAC present

No

VBUS present

No

HW sets

Fallback to ’1'

Fallback = 1

Yes

HW enables battery

charging and remaining

DCDC

HW disables VAC

DCDC and battery

charging

HW disables DCDC

and battery charging

HW disables DCDC

and battery charging

CHARGER CONTROL

POWER CONTROL

Figure 5-8. Battery Charging Flowchart (With Power Path, AUTOCHARGE=0)

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5.9.1.3 Non-Power Path with Hardware Controlled Charging

The TPS80032 device starts up for the VBUS or VAC plug insertion as soon as battery voltage is above

the VSYSMIN_HI threshold level if the device is not already powered on. The hardware starts the battery

charging automatically if USB Charging Port or VAC Charger is detected, or if the battery voltage is below

VBATMIN_HI and the device is powered off. If the VBUS is supplied by the USB standard downstream

port and the battery voltage is above VBATMIN_HI or the device is powered on, the battery charger is not

started by hardware. The host processor must enumerate to the USB host, configure to a certain current

level, set the VBUS input current limit, and enable the battery charging.

If the battery voltage drops below VSYSMIN_LO, the device shuts down and sets a fallback bit to indicate

about the fallback situation. A new startup is initiated when the battery is charged above the VSYSMIN_HI

threshold level and after startup the host processor clears the bit. If the fallback bit is active during

shutdown, the battery charging is disabled. This prevents infinite looping in low/no battery case with weak

charger. The operation is shown in Figure 5-9.

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VBUS OR VAC

Plug insertion

VBUS OR VAC

Plug insertion

E_MSK_

VBATMIN_

CHECK = ’1'

(OTP)

No

VBUS detected

AND USB

Charging Port

detected

No

VBAT >

VBATMINHI

Yes

VAC detected

Yes

PMIC in PowerON

No

Yes

No

PMIC in PowerON

Yes

HW sets VBUS input

current limit to

CIN_LIMIT (OTP)

HW enables battery

charging from VAC

HW sets VBUS input

current limit to

No

VBAT >

VSYSMIN_HI

E_CIN_LIMIT

Host processor

HW enables battery

charging from VBUS

enumerates to

USB Host and

configures

Yes

Startup

HW continues battery

charging

Host prosessor

sets the VBUS

input current limit

and enables

PowerON

battery charging

from VBUS

Termination

current detected

by HW

No

Host processor

clears Fallback bit

(if it is ’1')

Yes

VBAT decreases

below recharge

threshold

HW gates battery

charging

No

VBAT <

VSYSMIN_LO

No

Yes

VBUS removal AND

charging from VBUS

enabled

VAC removal AND

charging from VAC

enabled

Shutdown

Yes

PMIC in PowerON

No

HW sets

Fallback to ’1'

Host processor enables

charging from the

remaining source or stops

the charging

Fallback = 1

Yes

No

Yes

HW disables battery

charging

VBAT >

VSYSMINHI

VAC present

No

VBUS present

No

Yes

No

HW enables battery

charging from the

remaining source

HW disables battery

charging

HW disables battery

charging

POWER CONTROL

CHARGER CONTROL

Figure 5-9. Battery Charging Flowchart (Without Power Path, AUTOCHARGE=1)

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5.9.1.4 Non-Power Path with Software Controlled Charging

The TPS80032 device starts up for the VBUS or VAC plug insertion as soon as battery voltage is above

the VSYSMIN_HI threshold level if the device is not already powered on. If the device is powered off, the

hardware sets the correct VBUS input current limit and starts the battery charging using the default values

from OTP memory. The default charging voltage need to be set to good battery threshold voltage level in

order to comply with the USB standard. When the device is powered on, the host processor takes control

over charging.

If the battery voltage drops below VSYSMIN_LO, the device shuts down and sets a fallback bit to indicate

the fallback situation. A new startup is initiated when the battery is charged above the VSYSMIN_HI

threshold level and the host processor clears the bit. If the fallback bit is active during the shutdown, the

battery charging is disabled. This prevents infinite looping in a low/no battery case with a weak charger.

The operation is shown in Figure 5-10.

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VBUS OR VAC

Plug insertion

VBUS OR VAC

Plug insertion

Yes

PMIC in PowerON

No

VBUS detected

AND USB

Charging Port

detected

No

VAC detected

Yes

No

VBAT >

VSYSMIN_HI

Yes

HW sets VBUS input

current limit to

CIN_LIMIT (OTP)

Yes

HW enables battery

charging from VAC

current limit to

E_CIN_LIMIT

Startup

HW enables battery

charging from VBUS

PowerON

SW controlled charging

- Clears Fallback bit when (if needed)

- Enumerates and configures to USB

host if needed

SW controlled

charging

- Checks interrupts

- Monitors battery temperature

- Updates watchdog

- Monitors USB suspend

- Selects priority between chargers

- Updates charging parameters

VBUS removal AND

charging from VBUS

enabled

VAC removal AND

charging from VAC

enabled

No

Yes

VBAT <

VSYSMIN_LO

PMIC in PowerON

Yes

Host processor enables

charging from the

remaining source or stops

the charging

Yes

No

Shutdown

VBAT >

VSYSMINHI

Yes

VAC present

No

VBUS present

No

HW sets

Fallback to ’1'

Fallback = 1

Yes

HW enables battery

charging from the

remaining source

HW disables battery

charging

HW disables battery

charging

HW disables battery

charging

CHARGER CONTROL

POWER CONTROL

Figure 5-10. Battery Charging Flowchart (Without Power Path, AUTOCHARGE=0)

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5.9.2 System Supply Regulator

During software-controlled charging, software selects the VBUS input current limit, the VBUS input voltage

collapse level, and the system supply regulation voltage. The programmable resources are:

•

Input limit current set point register CIN_LIMIT[3:0] (maximum current drawn from VBUS charging

source)

•

Input voltage set point register BUCK_VTH[2:0] (VBUS voltage collapsing level)

System supply voltage set point register

The system supply regulation voltage can be a fixed voltage or follow the battery voltage allowing the

linear battery charger to regulate the charging current and voltage (DPPM control mode).

5.9.3 Battery Charging

5.9.3.1 Power Path Configuration

When the Power Path configuration is used, the battery charging consists of two different regulators, the

system supply regulator generating the system supply (VSYS) from the USB VBUS voltage and a linear

battery charging loop regulating the battery node (VBAT) from the system supply (VSYS) using an

external PMOS transistor. During the preconditioning phase, an integrated current source is used for

battery charging. The use of the dedicated loop for battery charging allows monitoring of the battery

current and voltage independently and minimizes the power dissipation thanks to the low-ohmic external

transistor.

The TPS80032 device includes five analog loops that influence the system supply regulator's output

current:

•

System voltage regulation loop, maintaining the system voltage (VSYS) at constant level (VSYS_PC)

during preconditioning and precharging and at (VBAT+DLIN[1:0]) level during full-charge phase and

end-of-charge phase.

•

VBUS voltage anticollapse loop sensing the VBUS voltage and preventing the VBUS voltage from

dropping below the programmed level (BUCK_VTH[2:0]).

VBUS input current loop sensing the input current and limiting it below the programmed level

(CIN_LIMIT[5:0]).

•

Thermal regulation loop sensing the DCDC temperature and limiting it below thermal shutdown level.

Cycle-by-cycle current monitoring loop sensing the current in high-side switch and limiting it below

cycle-by-cycle limit (BUCK_HSLIMI).

The dedicated battery charging control includes three loops that influence the battery charging current:

•

Constant current (CC) loop sensing the battery current and limiting it below charging current level

(VICHRG[3:0]).

Constant voltage (CV) loop sensing the battery voltage and limiting it below charging voltage level

(VOREG[5:0]).

DPPM loop monitoring the voltage between system voltage and battery voltage and limiting the voltage

to threshold level (DLIN[1:0]/2) by decreasing the charging current.

Figure 5-11 shows the control loops for the system supply regulation and for the battery charging.

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VBUS

CbC

CIN_LIMIT

BUCK_VTH

L11

PWM

Control

VSYS

C39

T_J

125ºC

VSYS_PC

DLIN

Supplement Mode

S1

Gate

Control

VBAT

DLIN/2

VOREG

R2

VICHRG

Figure 5-11. System Supply Regulator and Battery Charging Control Loops

CAUTION

Resistor R2 is used for charging current control in Power Path configuration and must

be placed even if Gas Gauge is not used.

In addition, a battery current is monitored and if the termination current level (VITERM[2:0]) is detected an

interrupt is generated and battery charging is stopped according to the selected operation.

The battery charging profile consists of three phases:

•

Preconditioning

Precharging

Full-charge phase

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NOTE

The DLIN[1:0] voltage level must be selected so that the voltage is higher than the maximum

dropout on the switch (maximum charging current multiplied by the maximum resistance of

the switch).

Figure 5-12 shows a charging profile and the different parameters programmed in OTP memory and

software programmable parameters for charging with Power Path. The charging current is usually limited

by the VBUS input current loop when charging from the standard downstream port because the limit is set

to 100 or 500 mA. If the charging source cannot provide the current the charger is drawing, the VBUS

voltage decreases. The VBUS anticollapse loop senses the VBUS voltage and decreases the current so

that the voltage does not fall below the programmed voltage level (see Section 5.9.4).

VBAT, VSYS

50-200mV, 50mV steps

(OTP and SW)

DLIN

3.5-4.76V, 20mV steps

(OTP and SW)

VOREG

VBAT_FULLCHRG

VBAT_SHORT

System Voltage

3.6/3.8V

(OTP and SW)

VBATMIN_HI

2.65-3.35V, 0.1V steps

(OTP and SW)

Tracking mode

Battery

Voltage

2.1/2.45/2.8V

(OTP)

CC-charging

CV-charging

IBAT

0.1-1.5A

(OTP and SW)

VICHRG

Battery

Current

0.1/0.2/0.3/0.4A

(OTP and SW)

Termination current

50mA-400mA,

50mA steps

VICHRG_PC

VTERM

30mA

(OTP and SW)

Pre-Conditioning

Pre-Charge

Full-Charge

Charging stopped

System supplied

from charger

Figure 5-12. Battery Charging Profile with Power Path (Resistor R2 = 20 mΩ)

5.9.3.2 Non-Power Path Configuration

When the non-Power Path configuration is used, the battery charging is controlled by switched-mode

regulator from the USB VBUS voltage.

The TPS80032 device includes six analog loops that influence the output current:

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•

VBUS voltage anticollapse loop sensing the VBUS voltage and preventing the VBUS voltage from

dropping below the programmed level (BUCK_VTH[2:0]).

VBUS input current loop sensing the input current and limiting it below the programmed level

(CIN_LIMIT[5:0]).

Constant voltage (CV) loop sensing the battery voltage and limiting it below charging voltage level

(VOREG[5:0]).

Constant current (CC) loop sensing the battery current and limiting it below charging current level

(VICHRG[3:0]).

Cycle-by-cycle current monitoring loop sensing the current in high-side switch and limiting it below

cycle-by-cycle limit (BUCK_HSLIMI).

Thermal regulation loop sensing the DCDC temperature and limiting it below thermal shutdown level.

Figure 5-13 shows the control loops for the battery charging.

VBUS

CbC

CIN_LIMIT

BUCK_VTH

L11

PWM

Control

C39

T_J

125ºC

VOREG

R9

VBAT

VICHRG

Figure 5-13. Battery Charging Control Loops.

In addition, a battery current is monitored and if the termination current level (VITERM[2:0]) is detected an

interrupt is generated and battery charging is stopped according to the selected operation.

The battery charging profile consists of three phases:

•

Preconditioning

Precharging

Full-charge phase

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Figure 5-14 shows a charging profile and the different parameters programmed in OTP memory and

software programmable parameters for HW controlled operation (AUTOCHARGE=1) and Figure 5-15

shows a charging profile and the different parameters programmed in OTP memory and software

programmable parameters for SW controlled operation (AUTOCHARGE=0). The charging current is

usually limited by the VBUS input current loop when charging from the standard downstream port because

the limit is set to 100 or 500 mA. If the charging source cannot provide the current the charger is drawing,

the VBUS voltage decreases. The VBUS anticollapse loop senses the VBUS voltage and decreases the

current so that the voltage does not fall below the programmed voltage level (see Section 5.9.4).

VBAT

3.5-4.76V, 20mV steps

VOREG

(SW)

2.5-3.8V, 50mV steps

VSYSMIN_HI

(OTP)

Battery

Voltage

2.1V

VBAT_SHORT

PowerOFF

PowerON

Pre-Conditioning

Pre-Charge

Full-Charge

Charging

Stopped

IBAT

0.3-1.5A

(SW)

VICHRG

Battery

Current

0.3-0.45A, 50mA steps

(OTP)

Termination current

50mA-400mA,

50mA steps

VICHRG_PC

IBAT_SHORT

VITERM

30mA

(OTP and SW)

Figure 5-14. Battery Charging Profile Without Power Path (AUTOCHARGE=1, Resistor R9 = 68 mΩ)

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VBAT

3.5-4.76V, 20mV steps

VOREG

(SW)

2.5-3.8V, 50mV steps

VSYSMIN_HI

(OTP)

Battery

Voltage

2.1V

VBAT_SHORT

PowerOFF

PowerON

Pre-Conditioning

Pre-Charge

Full-Charge

Charging

Stopped

IBAT

0.3-1.5A

(SW)

VICHRG

Battery

Current

0.3-1.5A

(OTP)

Termination current

50mA-400mA,

50mA steps

VICHRG

VITERM

30mA

IBAT_SHORT

(OTP and SW)

Figure 5-15. Battery Charging Profile Without Power Path (AUTOCHARGE=0, Resistor R9 = 68 mΩ)

5.9.3.3 Preconditioning

During preconditioning, the battery voltage is below the VBAT_SHORT level and the charging current is

limited to 30 mA (IBAT_SHORT). If the system supply in Power Path configuration decreases during the

preconditioning phase, the preconditioning current is automatically reduced. In this mode, the charger

uses a linear charging operation mode. This phase detects a defective (shorted) battery and brings the

battery voltage to a level acceptable for higher charging current. If the battery is defective (shorted) and

the battery voltage doesn't increase above VBAT_SHORT level the charger stays in preconditioning

phase. As soon as the battery voltage is above VBAT_SHORT, a precharging phase is entered

automatically. In Power Path configuration the VBAT_SHORT level is programmed by OTP memory

(VBAT_SHORT[1:0] bits).

5.9.3.4 Precharge Phase

The precharging phase is used when the battery voltage is between VBAT_SHORT and

VBAT_FULLCHRG (VSYSMIN_HI without Power Path). If the system supply in Power Path configuration

decreases during the precharge phase, the precharge current is automatically reduced (DPPM loop).

During precharging, the charging current is limited to decrease the power dissipation in the external

PMOS. The precharging current is programmed in OTP memory (VICHRG_PC[1:0] bits).

The precharge current level is controlled by monitoring the voltage across the sense resistor. The default

currents are available with resistor R9 = 68 mΩ without Power Path and R2 = 20 mΩ with Power Path.

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5.9.3.5 Full-Charge Phase

The full-charge phase starts when the battery voltage is above VBAT_FULLCHRG and the system supply

is regulated from a charging source (without Power Path, the threshold level is VSYSMIN_HI).

With Power Path, the transition from a fixed system supply level into a tracking system supply level is

done when the battery voltage is at the VBATMIN_HI level. The VBATMIN_HI level is the same as

VSYSMIN_HI level (defined by OTP memory bits, VSYSMIN_HI[5:0]) except that the level is limited to 3.7

V. This means that if the VSYSMIN_HI is programmed above the 3.7-V level, the transition is done at the

3.7-V level. VBATMIN_HI is defined in the VBATMIN_HI_THRESHOLD register and the host processor

can change the level. The threshold is updated with the default value from OTP memory during startup.

If the system voltage decreases during the full-charge phase, the charging current is automatically

reduced (DPPM loop) to a value keeping the dropout voltage higher than 50% of the dropout voltage

setting (programmed with the DLIN[1:0] bits in the CONTROLLER_VSEL_COMP register), to ensure

proper operation of the charging circuitry.

The full-charge current level is controlled by monitoring the voltage across the sense resistor. The default

currents are available with resistor R9 = 68 mΩ without Power Path and R2 = 20 mΩ with Power Path.

5.9.3.6 Termination Current Detection

The battery current is monitored during CV-charging and if the termination current level is triggered in the

Power Path configuration, the battery charging is gated but the system voltage regulation from the VBUS

input continues. If the battery voltage decreases 120 mV below the charging voltage (VOREG) level, the

full-charge phase is continued.

In the non-Power Path configuration the operation during termination current level detection is defined by

the CHARGE_ONCE and TERM bits. If the CHARGE_ONCE bit is 1, the battery charging is terminated

when the termination current threshold is triggered. If the CHARGE_ONCE bit is 0 and TERM bit is 1, the

battery charging is gated when the termination current level is triggered. If the battery voltage decreases

120 mV below the charging voltage (VOREG) level, the full-charge phase is continued.

The termination current level is monitored by measuring the voltage across the sense resistor. The default

currents are available with resistor R9 = 68 mΩ without Power Path and R2 = 20 mΩ with Power Path.

5.9.4 Anticollapse Loop and Supplement Mode

There are two different anticollapsing loops; one monitoring the VBUS input and controlling the switched-

mode regulator and another one with Power Path operation (DPPM) monitoring the VSYS line and

controlling the linear battery charger loop.

The anticollapse loop of the VBUS input operates so that the VBUS input voltage is monitored

continuously and the current of the switched-mode regulator is controlled by an analog loop to maintain

the defined VBUS input voltage (programmed with the BUCK_VTH[2:0] bits in the

ANTICOLLAPSE_CTRL1 register). If the VBUS source cannot deliver high enough current and the VBUS

voltage drops, the VBUS input current is decreased by the analog loop so that the VBUS voltage stays at

programmed level. If an external PMOS is used to protect the VBUS input against negative voltage, then

the VBUS voltage at the connector can be slightly different because the anticollapse loop monitors the

voltage at the PMIC input.

The anticollapse loop of the linear battery charger (DPPM) monitors the system voltage (VSYS) and

controls the battery charging current. If battery voltage is below the VBATMIN_HI the threshold, the level

for the DPPM loop is 3.4 V, whereas if the battery voltage is above VBATMIN_HI, the VSYS voltage

tracks the VBAT voltage and the DPPM threshold is 50% of the programmed tracking voltage.

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Figure 5-16 shows an example of DPPM loop and supplement mode operation. The charging current is

set to 1 A and the VBUS input current limit is 1.5 A. When the system load is small the 1000 mA charging

current can be generated with around 750 mA VBUS current, thanks to the efficient DCDC converter. If

the system load is increased to around 900 mA level, the 1500 mA VBUS input current limit is reached

and the DPPM loop decreases the battery charging current in order to maintain 50% of the programmed

tracking voltage across the external FET. If the system load is increased further up to around 1900 mA

level, the battery charging current decreases to 0 mA and the supplement mode is enabled. Increasing the

system load above 1900 mA level directly affects the battery discharge current level. When the system

load is decreased the operation is opposite entering from supplement mode into DPPM loop operation and

finally out from VBUS input current limit mode.

I_SYS

~2400 mA

~1900 mA

~900 mA

0 mA

I_VBUS

1500 mA

~750 mA

0 mA

I_BAT

1000 mA

0 mA

-500 mA

V_SYS

3.6 V

3.55 V

~3.5 V

DPPM

Supplement Mode

loop

active

loop active

Figure 5-16. Example of DPPM Loop and Supplement Mode Operation (V_VBUS= 5 V, V_BAT= 3.5 V, 1.5 A

VBUS Input Current Limit)

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5.9.5 Battery Temperature Monitoring

JEITA requirements define the maximum battery charging current and voltage at different temperature

ranges for Li-Ion batteries. The TPS80032 device supports the JEITA requirements with hardware-based

temperature measurement gating the battery charging below and above the preset temperature values

(typically 0°C and 60°C). Between these limits host processor must monitor the battery temperature using

the integrated general-purpose analog-to-digital converter (GPADC) and setting the charging current and

voltage accordingly. Figure 5-17 shows the voltage and current limits at different temperatures.

4.25 V

0.5C

current

#2

4.15 V

4.10 V

1C

current

#1

0°C

10°C

45°C 50°C

60°C

SWCA105-001

Figure 5-17. Charging Current and Voltage Limits at Different Temperatures

Figure 5-17 allows two options for charging between 0°C and 10°C. As shown in the figure, #1 allows

charging up to 4.10 V with 1C current and #2 allows charging up to 4.25 V with 0.5C current. The term 1C

defines the charging current related to the battery capacity. For a 1200-mA-h battery 1C corresponds to a

1.2-A current.

The battery temperature is measured using an external NTC resistor. The measurement is enabled before

the charging starts and the temperature is constantly monitored during charging. If the battery temperature

is outside of the valid range, the charging is gated; if the temperature returns to the valid range, the

charging continues. In Power Path mode the system supply regulation is continued when the battery

charging is gated. The gating of the charging can be disabled with an OTP memory bit (EN_BAT_TEMP) if

needed. The temperature measurement circuitry is enabled if VBUS or an external charger is detected. An

interrupt (CHRG_CTRL) is always generated when the battery temperature crosses the temperature limits

in both directions. The interrupt generation can be masked if needed.

Figure 5-18 shows the battery temperature measurement circuitry.

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GPADC_VREF

RATIO_TLO[2:0]

RATIO_THI[2:0]

MUX

R_X

GPADC_IN1

R_Y

R_NTC

Figure 5-18. Battery Temperature Measurement

Because the NTC characteristics are highly nonlinear, it is combined with two resistors allowing

linearization of its characteristics and making the sensitivity of the system more constant over a wide

temperature range. The resulting voltage at GPADC_IN1 can be measured using the GPADC and is also

monitored by two comparators that enable the charge of the battery only when the temperature is within a

specified window, typically 0°C to 60°C. Resistors R_Xand R_Yare used to set the desired temperature

threshold levels.

5.9.6 Safety Timer and Charging Watchdog

The TPS80032 device includes a safety timer, the timing of which depends on the charging control mode

and the USB Charging Port detection result. During hardware-controlled charging, the period for the USB

charging port and the USB standard downstream port is approximately 6 minutes; for customer-specific

chargers, this period is approximately 14 minutes. Longer values can be selected with the OTP memory

(CHWDT_DEP0 bit), 11 minutes instead of 6 minutes and 29 minutes instead of 14 minutes. Charger

source dependency on the timer values can be enabled and disabled by OTP memory

(CHWDT_DEP_DETN bit). If disabled, the timer value is always set as for the USB standard downstream

port and for the customer-specific charger (longer timer value). During software-controlled charging the

safety timer is replaced by charging watchdog (SW WDT), host processor can select the watchdog time

up to 127 seconds. The transition from safety timer to software-controlled watchdog occurs when software

updates the WDG_RST, WDT[6:0], VICHRG[3:0], VOREG[5:0] bits or CONTROLLER_CTRL1 register.

The different safety timer and watchdog times are summarized in the EPROM bits Application Note. If the

AUTOCHARGE mode is selected by OTP memory bit, the fixed 8-hour watchdog (HW WDT) is taken into

use when the battery voltage is above the VBATMIN_HI level.

If the safety timer or watchdog expires, the battery charging is gated and interrupt is sent to host

processor. In Power Path configuration, the system supply regulator still continues to operate when the

battery charging is gated.

The operation of the safety timer and watchdog is presented in Figure 5-19.

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Battery Charging

started

Battery Charging

terminated

Safety Timer

Yes

VBAT <

VBATMIN_HI

Safety Timer and

Watchdog cleared

4-29 min

(depends on OTP bits)

No

AUTOCHARGE

= 1

SW writing*

Yes

* Writing into one of the following

registers:

Yes

- CONTROLLER_CTRL1

- CONTROLLER_WDG

- VOREG

Safety Timer Reset

HW WDT Reset

- VICHRG

No

HW WDT

SW WDT

SW writing to

(VOREG OR VICHRG) OR

(SW writing to

Yes

8 hour

Watchdog counting

0...127 s Watchdog

counting

CONTROLLER_CTRL1 and then

to CONTROLLER_WDT)

No

Yes

VBAT <

VBATMIN_HI

AUTOCHARGE=1 AND

(SW write CONTROLLER_WDT) AND

(SW has not written to

No

Yes

HW WDT Reset

CONTROLLER_CTRL1)

Figure 5-19. Safety Timer and Charging Watchdog

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5.9.7 Limit Registers

During the full-charge phase, host processor sets the charging voltage and current. However, the device

limits the current and voltage to a level that is defined in the limit registers (CHARGERUSB_CTRLLIMIT1

and CHARGERUSB_CTRLLIMIT2). The limit registers in the device must be written just after the startup.

Host processor must check the battery type and define the maximum charging current and voltage for the

battery being used, write the limit values, and lock the limit registers with the LOCK_LIMIT bit, so that

these cannot be changed when the device is powered on. This ensures that third-party software or a virus

cannot set a charging current or voltage that is too high. The limit values are reset during power off by the

NRESPWRON signal and they must be written by host processor during every power up. Figure 5-20

shows the structure of the limit and programming registers.

Registers

Charging voltage

Charging

voltage

Charging current

Minimum

Limit registers

Charging

current

LOCK_LIMIT

Charging voltage

NRESPWRON

(NRESWARM)

Charging current

Figure 5-20. Charging Current and Voltage Limit Registers

5.9.8 Battery Presence Detector

The TPS80032 device supports battery detection. The presence of the battery can be detected with the

GPADC_IN0 input signal. The interface has two different functions:

•

Detect battery removal and presence

Measure the size of the resistor connected to the GPADC_IN0 line in the battery pack using the

GPADC

Battery pack removal is detected by a comparator that monitors GPADC_IN0. The battery pack must have

a pull-down resistor (R_BRI) and the device has a current source (I_BRI) in the line. If the battery pack is

removed, GPADC_IN0 rises above the comparator threshold level, the battery removal is detected, and

the device sends an indication (BAT interrupt) to the host processor. In addition, battery charging is

terminated if the battery is not present. Battery removal is detected with a comparator and a current

source supplied on the VRTC supply domain. This supply scheme allows detection in a dead battery case

configuration, because the VRTC can be supplied from the VBUS or VAC lines. The battery presence

detection module is enabled during the charging and during the ACTIVE and SLEEP states.

Figure 5-21 shows a block diagram of the battery presence detection circuitry.

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VRTC

I_BRI

GPADC_IN0

R_BRI

BatRemoval

V_BRIRef

SWCS057-014

Figure 5-21. Battery Presence Detector

CAUTION

If the GPADC_IN0 line is not used for battery presence detection in the Power Path

configuration (POP_APPSCH OTP bit is 1), the capacitance of the VBAT line must be

below 100 µF. Otherwise a fully discharged battery cannot be detected correctly by the

battery charging loop.

5.9.9 Indicator LED Driver

The device has an indicator LED driver that indicates charging is ongoing during hardware-controlled

charging. During hardware-controlled charging, the LED driver is enabled only if the charging is ongoing

and it is turned off if the battery is not charged. The supply for the charging indicator LED driver is

generated from CHRG_PMID or VAC, depending on the active charging path. The CHRG_PMID pin is

used instead of the VBUS line so that the LED indicator current is included into the VBUS input current

limit.

During power on, host processor can control the indicator LED regardless of the charging with register bits

(LED_PWM_CTRL1 and LED_PWM_CTRL2). The supply for the LED can be selected as CHRG_PMID,

VAC, or CHRG_LED_IN. The current level can also be selected and the dimming function can be used.

Dimming is done with a 128-Hz PWM signal, which has 255 linear steps. The LED output pin has a

selectable pulldown when the module is disabled; the pulldown is enabled by default.

The indicator LED driver is also used to indicate if the device cannot power on after a key press

(PWRON). If the battery voltage is too low for startup, the LED driver gives three 300-ms pulses with a

300-ms duration between the pulses.

5.9.10 Supported Charging Sources

The following chargers are supported with the integrated switched-mode charger from the USB connector:

•

Dedicated Charging Port (DCP)

Charging Downstream Port (CDP)

Standard Downstream Port (SDP)

Chinese charger

To configure the system supply regulator and charger for proper operation mode depending on the

charging source characteristics, the charging source type must be detected and identified. The detection

of the charger attached to the USB connector is made inside the device by detecting a voltage greater

than VINmin on the charger input.

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To minimize the capacitance of the data lines, the type of the charger connected to the USB connector

can be identified by the USB PHY and the information of the maximum current drawn from the charging

source can be transmitted to the device with a dedicated signal (CHRG_DET_N). The TPS80032 device

enables detection by delivering the LDOUSB supply (selectable by OTP memory bit,

AUTO_LDOUSB_DIS). The charger detection circuitry must deliver at least a 1.8-V voltage level to the

CHRG_DET_N input pin, by default a high logic level indicating that a USB charging port is detected. The

polarity of the charger detection signal can be selected with an OTP memory (DET_N_POL bit). The

accessory charger adapter (ACA) is identified in the TPS80032 device. A typical connection of the PMIC

and USB PHY is shown in Figure 5-22.

VBUS

PMIC

ID

ACA

detection

VSYS

Control

logic

Power

path

USB

connector

VBUS

VSYS

VBAT

Battery

charger

LDOUSB

LDOUSB_OUT

CHRG_DET_N

Charger

detect

D-

D+

USB

PHY

Application processor or

stand-alone USB PHY

Charger_detection_scheme

Figure 5-22. Connection for the USB Charging Port Detection

The device can be interfaced with an ACA (external to the terminal) to support charging from the USB

Charging Port and USB communication to other USB devices from the USB port. For a description of ACA

detection, see USB OTG, USB OTG.

5.9.11 USB Suspend

The TPS80032 device includes a HZ_MODE bit which is usable, for example during USB suspend

periods. The benefit of the bit is that it can be used to gate the charging without changing any charging

parameters. When the suspend period ends, clearing the bit continues the battery charging.

5.9.12 Support for External Charging IC

The TPS80032 device can be interfaced with an auxiliary stand-alone charger device to support the

following use cases:

•

Simultaneous battery charging from other than USB connector (different connector) and OTG operating

mode with USB connector (the integrated switched-mode system supply regulator used as the VBUS

supply)

•

System supply generation and charging from the sources not connected to the USB connector

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In the Power Path configuration the battery charging is always controlled by the TPS80032 device and the

external IC only generates the system supply which is needed for the battery charging. In the non-Power

Path configuration the external IC is used for battery charging. Figure 5-23 shows the connections

between TPS80032 device, application processor and external charging IC (BQ24159) in Power Path

configuration.

Application

Processor

VAC

INT

VAC

Detector

+

I2C

OVV

Detector

Iout FB

VAC

Detector

NRESPWRON

Vsense FB

Thermal FB

Thermal

Prot

Isense

CHRG_EXTCHRG_ENZ

Vsense

Control

& WD

VSYS

CHRG_EXTCHRG_STATZ

PMIC

External IC, e.g.

BQ24159

CHRG_VSYS

CHRG_GATE

_CTRL

Battery

Charger

CHRG_VBAT

BATTERY

PACK

CGAUGE_RESP

CGAUGE_RESN

Gas Gauge

Figure 5-23. Connection Diagram for External Charging Interface in Power Path Configuration

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The external IC is enabled with a 1.8-V CMOS level signal, CHRG_EXTCHRG_ENZ. A low logic level

indicates that the regulator is enabled. The system supply regulation / battery charging status is indicated

with the CHRG_EXTCHRG_STATZ signal. An external IC pulls the signal down during operation.

The integrated USB regulator can be associated with an external VAC regulator. For that reason, the VAC

wall charger input is connected to the device to define the priorities. These priorities are controlled by

hardware when the device is powered off (NRESPWRON=0):

•

When the VBUS is detected and the VAC is not detected, the USB input is used.

When the VAC is detected and the VBUS is not detected, the external charging input (VAC) is used.

When the VBUS and VAC are detected:

–

If CHRG_DET_N = 0 and ACA (RID_A, RID_B or RID_C) is not detected (100-mA VBUS input

current limit), the VAC wall charger is expected to be better (or equivalent) and thus is chosen as

the default input path.

–

If CHRG_DET_N = 1 or ACA (RID_A, RID_B or RID_C) is detected (USB Charging Port detected),

the USB is expected to be sufficient for system supply generation and charging and thus is chosen

as the default input path.

If there is a fault condition on a charger during hardware-controlled operation and the fault condition

continues for at least 2.5 seconds, the input source is changed for a lower priority input. The change into a

lower priority input only prevents infinite looping between inputs. If only one charger is attached, the

regulator is not disabled in a fault condition, and if the fault condition does not disappear; the input is

terminated when the watchdog expires.

NOTE

In the Power Path mode the system voltage level is regulated according to the voltage level

set in the BQ24159. There is no automatic tracking of the battery voltage like when

integrated DCDC is used for system supply regulation. The voltage tracking must be done by

host processor in order to maintain high enough dropout for the external PMOS transistor

and on the other hand to limit the power dissipation in the PMOS transistor.

5.9.13 Battery Charger Interrupts

Figure 5-24 shows the system supply regulator and battery charger interrupt handling structure.

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INT

Signal

HW signal

REGISTER NAME

(affected BIT)

- BIT NAME (R/F) (M)

M = Maskable

INT_STS_A

R = Rising edge sensitive

F = Falling edge sensitive

INT_STS_B

INT_STS_C

- CHRG_CTRL (M)

- EXT_CHRG (M)

- INT_CHRG (M)

Latched, cleared on writing ’1'

CONTROLLER_STAT1

(EXT_CHRG)

- CHRG_EXTCHRG_STAT

(M)

-> VAC_FAULT (M)

-> VAC_EOC (M)

CHARGERUSB_INT_STATUS

(INT_CHRG)

- CURRENT_TERM (M)

- CHARGERUSB_STAT (M)

- CHARGERUSB_THMREG (M)

- CHARGERUSB_FAULT (M)

- EN_LINCH (R) (M)

(CHRG_CTRL)

- LINCH_GATED (R) (M)

- FAULT_WDG (R) (M)

- VAC_DET (R/F) (M)

- VBUS_DET (R/F) (M)

Live status

Latched, cleared on read

Real reason must be read

from external charger

CONTROLLER_STAT1

(LINCH_GATED)

CHARGERUSB_STATUS_INT2

(CURRENT_TERM)

(CHRG_CTRL)

- CURRENT_TERM (R)

- BAT_REMOVED (R/F) (M)

- BAT_TEMP_OVRANGE (R/F)

(M)

Live status

Available only with

Power Path

Live status

CHARGERUSB_STATUS_INT2

(CHARGERUSB_STAT)

- CHARGE_DONE (R)

- ANTICOLLAPSE (R)

LINEAR_CHRG_STS

(LINCH_GATED)

- CRYSTAL_OSC_OK

- END_OF_CHARGE

- VBATOV

Available only

without Power Path

Live status

CHARGERUSB_STATUS_INT1

(CHARGERUSB_THMREG)

- TMREG (R/F)

- VSYSOV

Live status

CHARGERUSB_STATUS_INT1

(CHARGERUSB_FAULT)

- NOBAT (R/F)

- BST_OCP (R/F)

- TH_SHUTD (R/F)

- BAT_OVP (R/F)(VSYS voltage w/ PP)

- POOR_SRC (R/F)

- SLP_MODE (R/F)

- VBUS_OVP (R/F)

Live status

Figure 5-24. Interrupt Generation Architecture

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When the INT interrupt signal is set, host processor must read the reason of the interrupt by reading the

three interrupt status registers (INT_STS_A, INT_STS_B, and INT_STS_C). The battery charging related

register bits (CHRG_CTRL, EXT_CHRG, and INT_CHRG) are in the INT_STS_C register. The source of

the interrupt is

•

CHRG_CTRL: The interrupt source is in the charger controller.

EXT_CHRG: The interrupt source is in external charging IC.

INT_CHRG: The interrupt source is in the TPS80032 battery charger.

The CHRG_CTRL indication can be further identified from the CONTROLLER_STAT1 register. This

register shows the actual status of the different interrupt sources, so if the situation disappears before

software can read it, software cannot know the real reason for the interrupt.

The origin of the external charger interrupt must be read from the external charging IC. The

CHRG_EXTCHRG_STATZ bit shows the actual level of the status signal.

The source for the INT_CHRG interrupt must be further clarified in the CHARGERUSB_INT_STATUS

register, which stores the latched information. The bits in the CHARGERUSB_INT_STATUS register are

cleared by read access.

As an example, if the battery temperature goes above threshold level the BAT_TEMP_OVRANGE bit in

CONTROLLER_STAT1 register is high. This sets LINCH_GATED bit in CONTROLLER_STAT1 register to

high which sets CHRG_CTRL interrupt bit high and sets INT line low. Host processor detects the interrupt

and reads INT_STS_A, INT_STS_B, INT_STS_C, CONTROLLER_STAT1 and LINEAR_CHRG_STS

registers and finds the reason for the interrupt.

5.9.13.1 Sources of the Interrupt

The interrupt sources are described in the following lists, together with the actions software must take.

5.9.13.1.1 Charger Controller Interrupts

The charger controller interrupts are:

•

FAULT_WDG: The charging watchdog has expired. Host processor must reset the timer in the

CONTROLLER_WDG register. In addition, host must initialize the charging and restart it.

•

VAC_DET: The VAC detection threshold voltage has been crossed. The VAC charger has been either

inserted or removed. If the VAC charger is inserted, host processor can initialize and enable the

charging and select the charging source using the CONTROLLER_CTRL1 register bits. The

parameters for the VAC charging are programmed in the external IC.

•

VBUS_DET: The VBUS detection threshold voltage has been crossed. The USB plug has been either

inserted, removed, or the VBUS delivery has been started or stopped. If the USB plug is inserted, the

host processor can initialize and enable the charging and select the charging source using the

CONTROLLER_CTRL1 register bits.

•

BAT_REMOVED: The battery is either removed or inserted. This battery detection is based on the pull-

down resistor on the GPADC_IN0 line. This feature can be enabled and disabled using the OTP

memory (EN_BAT_DET bit).

BAT_TEMP_OVRANGE: The battery temperature has crossed the minimum or maximum temperature

limit set by the external resistors. The battery charging is gated outside of the valid range automatically

by hardware. This feature can be enabled and disabled using the OTP memory (EN_BAT_TEMP bit).

•

CRYSTAL_OSC_OK: The charger crystal oscillator failed.

END_OF_CHARGE: The end of charge current is detected from the linear charger loop. The host

processor can terminate the charging if the battery is full. This function is valid only with Power Path

(OTP bit POP_APPSCH = 1).

•

VBATOV: Battery overvoltage is detected. There is something wrong in the battery charging and it

should be stopped. This function is valid only with Power Path (OTP bit POP_APPSCH = 1).

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•

VSYSOV: System supply overvoltage is detected. There is something wrong or there is transient spike

in the system supply. The system supply level must be monitored with the ADC, and if it is

continuously too high, the system suppy regulator must be disabled. This function is valid only with

Power Path (OTP bit POP_APPSCH = 1).

5.9.13.1.2 External Charger Interrupt

The external charger interrupt is:

•

EXT_CHRG: Interrupt from the external charger IC. The reason for the interrupt must be read from the

external charger IC.

5.9.13.1.3 Internal Charger Interrupts

The internal charger interrupts are:

•

CURRENT_TERM: The current termination level has been detected. The functionality must be

controlled by host processor using the TERM and CHARGE_ONCE bits in the CHARGERUSB_CTRL1

and CHARGERUSB_CTRL3 registers. This bit is controlled only when the PMIC is used without Power

Path (OTP bit POP_APPSCH = 0).

•

CHARGE_DONE: The charging termination current level is detected. Host processor can terminate the

battery charging. This bit is controlled only when the PMIC is used without Power Path (OTP bit

POP_APPSCH = 0).

•

ANTICOLLAPSE: The anticollapse loop limiting the VBUS input voltage drop is active.

TMREG: The thermal regulation loop of the USB charger is active. The temperature of the IC must be

monitored and if it becomes too high, some power dissipation must be removed by decreasing the

charging current or by disabling functions.

WARNING

The thermal regulation loop does not work if the CIN_LIMIT[5:0] VBUS input

current limit is set to unlimited. The thermal regulation loop shares the same

analog loop as the VBUS input current limit and it is disabled in this situation.

However, the high temperature detection still operates and it gates the DC-DC

operation if triggered.

NOTE

The thermal regulation loop generates an interrupt when the DC-DC in Power Path mode

and the battery charger in non-Power Path mode is enabled. The host processor must check

the TMREG bit to see if the thermal regulation loop is active to identify and clear the false

interrupt.

•

NOBAT: The battery is not detected by the USB charger. This bit is controlled only when the PMIC is

used without Power Path (OTP bit POP_APPSCH = 0) and the feature is enabled and disabled using

the OTP bit (EN_BQBAT_DET).

BST_OCP: The OTG boost supply overcurrent protection is active. There can be a short circuit or an

excessively high load in the VBUS. The boost regulator must be disabled if the VBUS voltage is not

increasing.

TH_SHUTD: The temperature of the USB charger is higher than the threshold level and the battery

charging is gated. The power dissipation must be decreased by reducing the charging current or by

disabling some functions.

BAT_OVP: The battery voltage is higher than the overvoltage threshold, and the charging is gated

(without Power Path). Something may be wrong in the battery charging and it should be stopped. This

bit indicates system overvoltage with Power Path.

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•

POOR_SRC: The VBUS voltage is between the system supply voltage and the minimum VBUS

detection voltage. The voltage is too low for battery charging. The charging from VBUS must be

terminated.

•

SLP_MODE: The charger is in a low-power sleep mode. The VBUS voltage is below the sleep-mode

entry threshold and VBUS is higher than the VBUS detection threshold.

VBUS_OVP: The VBUS voltage is higher than the overvoltage threshold and the charging is gated.

The voltage can be monitored with the ADC and if the high voltage situation continues, the charging

from VBUS must be terminated by host processor.

•

EN_LINCH: The linear charging has been enabled by the charger controller. This bit is controlled only

when the PMIC is used with Power Path (OTP bit POP_APPSCH = 1).

5.10 USB OTG

The device embeds all hardware analog mechanisms associated to VBUS and ID lines. The other aspects

of the OTG system, such as the OTG controller (hardware/software) or the USB data line (DP/DM) with

HNP and SRP signaling, are embedded in the USB PHY, which can be either integrated into the

application processor or there is stand-alone USB OTG PHY.

The device supports the Battery Charging Specification Revision 1.2 and it includes hardware required for

both OTG 1.3 and OTG 2.0 standards.

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The device supports the following functions.

FUNCTION/FEATURE

REGISTER/REGISTER

BIT

OTG

Rev.

MODE/STATE

ACTIVE

SUPPLIES

NEEDED

SRP – Pulsing method

VBUS charge on VSYS

VBUS_CHRG_VSYS

VBUS_CHRG_PMID

VBUS_DISCHRG

OTG 1.3

OTG 2.0

VRTC

VSYS

SRP – Pulsing method

VBUS charge on PMID

ACTIVE

VRTC

CHRG_PMID

SRP – Pulsing method

VBUS discharge

ACTIVE

VRTC

ADP – Probing

VBUS charge

VBUS_IADP_SRC,

VADP_PRB

ACTIVE

VRTC

VANA

ADP – Probing

VBUS discharge

VBUS_IADP_SINK,

VADP_PRB

ACTIVE

VRTC

ADP – Sensing

VADP_SNS

SLEEP

VRTC

ACTIVE

VBUS detection

VA_VBUS_VLD,

VA_SESS_VLD,

VB_SESS_VLD,

VB_SESS_END,

VOTG_SESS_VLD

OTG 1.3

OTG 2.0

SLEEP

ACTIVE

VRTC

VANA

VBUS wake-up detection Always enabled if VBUS

or VAC is present

–

PRECHARGE/OFF

SLEEP/ACTIVE

VRTC

VBUS GPADC

measurement

VBUS_MEAS

ID_PU_220K

ID_PU_100K

ACTIVE

VRTC

VANA

ID 220-kΩ pullup on

LDOUSB

VRTC

LDOUSB

ID 100-kΩ pullup on

VRTC

LDOUSB

ID ground drive

ID_GND_DRV

ID_SRC_16U

–

VRTC

ID 16-µA source current

BC 1.2

PRECHARGE

VRTC

SLEEP/ACTIVE

LDOUSB

ID 5-µA source current

ID detection

ID_SRC_5U

–

ACTIVE

VRTC

LDOUSB

ID_GND, ID_A, ID_B,

ID_C, ID_FLOAT

BC 1.2

OTG 1.3

OTG 2.0

PRECHARGE

SLEEP/ACTIVE

VRTC

LDOUSB

ID wake-up detection

ID_WK_UP_COMP

–

OFF

VRTC

SLEEP/ACTIVE

ID GPADC measurement ID_MEAS

–

ACTIVE

VRTC

VANA

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NOTE

•

Both VBUS and ID wake-up comparators can generate a start event when the device is

in WAIT-ON state. The VBUS wake-up is enabled always, the ID wake-up enable is

configurable and disabled by default (ID_WK_UP_COMP bit in BACKUP_REG register).

Those comparators can also make the device leave the SLEEP state and enter the

ACTIVE state. An interrupt is sent to the host processor if they are not masked.

•

In PRECHARGE state, the VBUS wake-up comparator, the LDOUSB regulator, the ID

comparators, and the 16-µA current source are enabled automatically. The ACA

detection result increases the VBUS input current limit in case USB Charging Port is

detected.

The OTG_REV bit (in BACKUP_REG register) unlocks the respective VBUS detection

features and associated electrical parameters specific to each OTG revision 1.3 and

revision 2.0 (see the VBUS_ACT_COMP bit).

•

All TPS80032 OTG registers are unlocked and operate either with a read/write (R/W)

access or a read/set/clear (R/S/C) process.

VBUS_ACT_COMP (USB_VBUS_CTRL_SET/USB_VBUS_CTRL_CLR) is the only R/W

register bit that relies on the OTG_REV OTP bit value. This bit enables the needed

VBUS comparators, reducing the power consumption of the OTG VBUS analog section.

Therefore, all deactivated comparators have their corresponding source and latch

registers fixed at 0.

•

For some of the analog electrical parameters that are not backward-compatible between

OTG revision 1.3 and OTG revision 2.0 but also are not manageable through the

OTG_REV preselection bit, it is assumed throughout this section that the OTG revision

2.0 characteristic limits supersede the OTG revision 1.3 electrical limits and, thus, OTG

2.0 is the reference.

•

OTG revision 1.3 devices have just emerged on the electronic market and should be

outnumbered shortly by OTG revision 2.0 devices.

In addition, the USB-IF consortium suggests a fast-forward transition to OTG revision 2.0

to solve current incompatibilities and limitations between OTG revision 1.3 devices.

All electrical parametric deviations from OTG revision 1.3 are explicitly highlighted

through this section.

The full list of nonbackward-compatible electrical parameters is available on the USB-IF

website in the developer forum section.

There are two types of VBUS and ID comparators, referred to throughout this section as wake-up

(normally used in TPS80032 SLEEP state) and active comparators (generally activated in TPS80032

ACTIVE state). Those comparators are not exclusively working in respective TPS80032 SLEEP, and

ACTIVE states, but can also pretend to additional usages’ conditions. Indeed, the wake-up comparators

are targeting low power consumptions, whereas the active comparators are intended for accurate level

detections:

•

The wake-up comparators are working in TPS80032 PRECHARGE, WAIT-ON, SLEEP, and ACTIVE

states. Those comparators can wake up the device from SLEEP state but can also switch on the

device from WAIT-ON state. VBUS wake-up comparator can also start the precharge, provided that all

other precharging conditions are met.

•

The active comparators work in TPS80032 SLEEP and ACTIVE states. When working in the SLEEP

state, all required power and clock resources should remain active. ID active comparators, used for

ACA detections, are automatically enabled in PRECHARGE state; VBUS active comparators remain

off.

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5.10.1 ID Line

The USB Battery Charging Specification describes the operation of the ACA. The RID_A, RID_B, and

RID_C resistors are related only to the different ACA operations, whereas the grounded and floating IDs

(ROTG_A, ROTG_B = RID_FLOAT) are related to the connections of the USB OTG standard plugs (See

"Battery Charging Specification, Revision 1.2"). When either of the RID_A, RID_B, or RID_C resistance is

in place, the VBUS is delivered by the ACA. This allows the device to wake up from VBUS or ID. The host

can then enable the ID active comparators by writing ID_ACT_COMP bit (in USB_ID_CTRL_SET register)

to correctly identify the different RID values. In addition, an interrupt is generated if the resistance on the

ID ball is changing.

During hardware-controlled charging, the TPS80032 device monitors if an ACA is connected and sets the

corresponding VBUS input current limit.

The following pullup and pulldown resistors and current sources can be connected to the ID line:

•

ID_PU_220K bit enables an ID 220-kΩ pullup to the LDOUSB supply.

ID_PU_100K bit enables an ID 100-kΩ pullup to the LDOUSB supply.

ID_GND_DRV bit enables an ID 10-kΩ pulldown.

ID_SRC_16U bit enables an ID 16-µA current source on the LDOUSB supply.

ID_SRC_5U bit enables an ID 5-µA current source on the LDOUSB supply.

ID_WK_UP_COMP enables an ID 9-µA current source (IID_WK_SRC) on the VRTC supply.

The ID wake-up comparator is used when the TPS80032 device is in the WAIT-ON or SLEEP state. It

allows start up of the TPS80032 device when a USB cable A-plug is attached (A-plug has a pulldown

resistor, ROTG_A, to ground on the ID line).

Four comparators, supplied on the LDOUSB regulator, are implemented to evaluate the proper external ID

resistor. Additional logic between those comparators allows the detection of the five debounced interrupts

(fixed 30-ms debouncing):

•

ID_FLOAT

ID_A

ID_B

ID_C

ID_GND

It is possible to use the GPADC to monitor the voltage on the ID line (channel 14). A 6.875-V maximum

voltage on the ID line corresponds to a 1.25-V maximum dynamic at the input stage of the GPADC

converter, allowing a 6.0-V maximum measurement.

Figure 5-25 shows the block diagram of the ID resistance detection and the decoding.Table 5-1 lists the ID

resistance interrupt decoding.

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R_{ID_FLOAT}

V_{ID_CMP4}

V_{ID_CMP3}

V_{ID_CMP2}

V_{ID_CMP1}

R_{ID_A}

R_{ID_B}

R_{ID_C}

ID

R_ID

R_{ID_GND}

Figure 5-25. ID Resistance Detection

Table 5-1. ID Resistance Interrupt Decoding

ID pin level

R_IDResistance

Interrupt

V_ID< V_{ID_CMP1}

R_ID< 1 kΩ

ID_GND

ID_C

V_{ID_CMP1}< V_ID< V_{ID_CMP2}

V_{ID_CMP2}< V_ID< V_{ID_CMP3}

V_{ID_CMP3}< V_ID< V_{ID_CMP4}

V_ID> V_{ID_CMP4}

36 kΩ < R_ID< 37 kΩ

67 kΩ < R_ID< 69 kΩ

122 kΩ < R_ID< 126 kΩ

R_ID> 220 kΩ

ID_B

ID_A

ID_FLOAT

5.10.2 VBUS Line

The VBUS wake-up comparator is used when the TPS80032 device is in the PRECHARGE, WAIT-ON,

SLEEP, or ACTIVE state. It allows startup of the TPS80032 device when a USB cable plug is attached

with a VBUS voltage level of 3.6 V minimum being present on the VBUS line.

The LDOUSB regulator, the ACA comparators and 16-µA current source can be selected to be controlled

by the VBUS wake-up comparator until the first I²C write access to the LDOUSB resource state register

(LDOUSB_CFG_STATE) (by setting the AUTO_LDOUSB_DIS OTP bit to 0).

The following pullup and pulldown resistors and current sinks/sources can be connected to the VBUS line:

•

VBUS_CHRG_VBAT bit enables a VBUS 2-kΩ pullup to the VSYS supply.

VBUS_CHRG_PMID bit enables a VBUS 2-kΩ pullup to the CHRG_PMID supply.

VBUS_DISCHRG bit enables a VBUS 10-kΩ pulldown.

VBUS_IADP_SRC bit enables a VBUS 1.4-mA current source on the VANA supply.

VBUS_IADP_SINK bit enables a VBUS 1.5-mA current sink.

RA_BUS_IN resistor is fixed and a combination of all parallel resistor bridges implemented on VBUS in

the various IPs such as backup battery, OTG, and charger.

•

RVBUS_LKG represents the TPS80032 device internal leakage.

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Related to the OTG 1.3 revision, four comparators supplied on the VANA regulator are implemented to

evaluate the proper voltage level on the VBUS line.

In the OTG 2.0 revision, only one comparator is required for the session valid detection

(VOTG_SESS_VLD) supplied also on the VANA domain. Still, the VA_VBUS_VLD comparator can be

used to detect a possible VBUS short-circuit condition.

The TPS80032 device embeds the OTG 2.0 optional features related to the VBUS ADP probing and

sensing, and hence with two additional comparators supplied on VANA (VADP_PRB and VADP_SNS).

Seven comparators allow the detection of the four OTG 1.3 and the three OTG 2.0 debounced interrupts:

•

VA_VBUS_VLD (OTG 1.3/OTG 2.0) – fixed 30-ms debouncing

VB_SESS_VLD (OTG 1.3) – fixed 30-ms debouncing

VA_SESS_VLD (OTG 1.3) – fixed 30-ms debouncing

VB_SESS_END (OTG 1.3) – fixed 30-ms debouncing

VOTG_SESS_VLD (OTG 2.0) – fixed 30-ms debouncing

VADP_PRB (OTG 2.0) – fixed 2x 30-µs debouncing

VADP_SNS (OTG 2.0) – fixed 2x 30-µs debouncing

It is possible to use the GPADC to monitor the voltage on the VBUS line (channel 10), see GENERAL-

PURPOSE ADC for more information.

NOTE

•

If the system switches off, the LDOUSB regulator stays on if the VBUS is still connected.

When the NRESPWRON signal is released, only I²C accesses enable the regulator, if

not previously enabled by the VBUS wake-up comparator in the PRECHARGE state.

•

The LDOUSB regulator is a dual-input supply LDO. The LDOUSB regulator enable is

independent of the overvoltage condition.

When

a VBUS overvoltage condition occurs, the CHRG_PMID input switch is

automatically opened, protecting the LDOUSB from possible overvoltage stresses.

When neither the VSYS nor PMID input supply is selected, the LDOUSB regulator

cannot output

a proper voltage, even if its control enable is set (see the

LDOUSB_CFG_TRANS register).

•

Host should keep monitoring the VBUS overvoltage condition and turn off the LDOUSB

regulator when necessary.

The VBUS detection mechanism works only when the VANA supply is present:

–

TPS80032 SLEEP state – VANA should remain active.

TPS80032 ACTIVE state – VANA is always on.

•

For ADP detection, host can use the TPS80032 embedded mechanism or directly use

the output of the comparators with their associated interrupts.

There is no source and enable low register bits associated with the ADP interrupt,

because this ADP interrupt represents the output of the digital ADP module and not the

output of an analog comparator.

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5.10.3 ADP on VBUS Line

The ADP lets the device detect when a remote device is attached or detached with a low power

consumption. The ADP detects the change in the VBUS capacitance that occurs when two devices are

attached or detached. The capacitance is detected by first discharging (VBUS_IADP_SINK) the VBUS line

and then measuring the time it takes for VBUS to charge to a VADP_PRB voltage level with a

VBUS_IADP_SRC current source. The change in the capacitance is detected by looking for a change in

the T_ADP_RISE charge time. This procedure is called ADP probing.

If an A-device is attached to a B-device, and both support ADP features, the A-device performs ADP

probing and the B-device performs ADP sensing. During ADP sensing, the B-device looks for ADP

probing activity on the VBUS line. If ADP probing activity is detected, the B-device determines that the A-

device is still attached.

As shown in Figure 5-26, the ADP module has timing register bits (T_ADP_HIGH, T_ADP_LOW, and

T_ADP_RISE), control logic, a current source (VBUS_IADP_SRC), a current sink (VBUS_IADP_SINK),

and two comparators (VADP_PRB [ADP probing] and VADP_SNS [ADP sensing]).

VBUS_IADP_SRC

Upper

T_ADP_HIGH[7:0]

limit

Time interval

measurement

VBUS

Lower

limit

T_ADP_LOW[7:0]

VADP_PRB

T_ADP_RISE[7:0]

VBUS_IADP_SINK

ADP probing and sensing

ADP interrupt

control

VADP_SNS

32.768-kHz crystal clock

ADP_MODE[1:0]

SWCS057-016

Figure 5-26. Attach Detection Protocol Scheme

Figure 5-27 shows the ADP timing diagram.

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VBUS

voltage

T_ADP_RISE

TA_ADP_PRB or TB_ADP_PRB

VADP_PRB

VADP_SNS

VADP_DSCHRG

Time

T_ADP_SINK

SWCS057-017

Figure 5-27. ADP Timing Diagram

OPERATION

ADP_MODE[1:0]

00

01

10

11

ADP digital module is disabled.

ADP sensing mode is enabled.

ADP probing mode as an A-device is enabled.

ADP probing mode as a B-device is enabled.

The limit registers (T_ADP_LOW[7:0] and T_ADP_HIGH[7:0]) and the last measurement time

(T_ADP_RISE[7:0]) are reset when the digital module is disabled.

During the ADP sensing mode, the VADP_SNS comparator is used. The digital module monitors the

comparator output to ensure that it toggles and the time duration between the rising edge of the

comparator output signal is shorter than T_ADP_SNS. If there is no new rising edge within the

T_ADP_SNS period, the module generates an ADP interrupt.

Figure 5-28 shows the ADP sensing timing diagram.

T_ADP_SNS

32.768-kHz crystal clock

ADP interrupt

ADP_MODE[1:0]

01

00

Comp(VADP_SNS)

SWCS057-018

Figure 5-28. ADP Sensing Timing Diagram

During ADP probing, the VADP_PRB comparator is used. The time interval measurement counter is reset

and the VBUS_IADP_SINK current sink is turned on for T_ADP_SINK. The T_ADP_SINK time is long

enough to discharge the VBUS voltage below VADP_DSCHG. There is no comparator to monitor the

discharge level. After that, the current sink is turned off, the current source VBUS_IADP_SRC is turned

on, and the time interval measurement counter starts to count 32.768-kHz crystal clock cycles. When the

VBUS voltage reaches VADP_PRB voltage level the current source is turned off, and the time interval

measurement counter is stopped. If the VADP_PRB voltage is not reached before counter value is 255,

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the counter value is stopped to 255. The current source is disabled when the voltage reaches VADP_PRB

level or the next current sink period starts. If the measured time interval value is lower than

T_ADP_LOW[7:0] or higher than T_ADP_HIGH[7:0], an interrupt is generated. The host processor sets

the limit values so that the operation fulfills the requirements of the OTG 2.0 specification. Figure 5-29

shows the ADP probing timing diagram.

>T_ADP_HIGH or

<T_ADP_LOW

32.768-kHz crystal clock

ADP interrupt

ADP_MODE[1:0]

00

10/11

00 10/11

T_ADP_SINK

VBUS_IADP_SINK

VBUS_IADP_SRC

Comp(VADP_PRB)

T_ADP_RISE

TA_ADP_PRB or TB_ADP_PRB

Figure 5-29. ADP Probing Timing Diagram

5.11 Gas Gauge

The gas gauge, also called the current gauge, measures the current from the battery or the current into

the battery. An ADC (Coulomb counter) is required to measure the voltage over the external sense

resistor, R2. This resistor is connected to the negative side of the battery. The integration period of the

ADC is programmable from 3.9 to 250 ms with CC_ACTIVE_MODE[1:0] bits (in FG_REG_00 register).

The gas gauge works continuously, which means that the new measurement starts immediately after the

previous result becomes available. The accumulated result is calculated by the TPS80032 digital module

but requires host processor to calculate the battery energy (See ).

Figure 5-30 shows a block diagram of the gas gauge.

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Battery

Li-Ion

or

Li-Pol

Autocalibration switches

PAD_GGAUGE_RESP

Digital control

Accumulator

DS Coulomb Counter

13 bits

R_sense

Digital filter

1 bit

13 bits+Sign

Integrator

Sample counter

Calibration

Registers

PAD_GGAUGE_RESN

Analog

Digital

SWCS057-020

Figure 5-30. Gas Gauge Block Diagram

5.11.1 Autocalibration

Autocalibration is enabled by host. During autocalibration, the gas gauge performs eight measurements so

that the inputs for the ADC are short-circuited. The result indicates the offset error of the gas gauge. The

result is stored in the CC_OFFSET[9:0] bits and the completion of the measurement procedure is

indicated with the CC_AUTOCAL interrupt. Software must read the offset error result (CC_OFFSET[9:0]

bits in FG_REG_08 and FG_REG_09 registers) and use that to compensate the actual measurement

results. The CC_CAL_EN bit self-clears when the calibration completes. The gas gauge must be enabled

(FGS bit TOGGLE1 register) before starting the calibration. The temperature variation changes the offset

error, so the recalibration is preferred during operation.

5.11.2 Auto-Clear and Pause

The auto-clear function is used in the sequence of changing from one integration period to another. Before

changing the integration period, the CC_PAUSE bit must be set to 1. Setting the CC_AUTOCLEAR bit to

1 clears the CC_OFFSET[9:0], CC_SAMPLE_CNTR[23:0], and CC_ACCUM[31:0] bit fields. The

CC_AUTOCLEAR bit self-clears when the registers are reset.

Setting CC_PAUSE to 1 keeps the analog from updating the integrator, accumulator, and sample counter

registers. The integrator continues to run. If an integration period ends while the CC_PAUSE bit is 1, the

value that is normally written to these registers is lost and the next integration period starts automatically.

5.11.3 Dithering

The FGDITHS bit is set to 1 to enable dithering in the ADC, which keeps idle tones from being generated

with a DC input value. FGDITHS is not affected by the CC_AUTOCLEAR bit. Use the FGDITHR bit to

disable the dithering. The dithering feature status is available in the FGDITH_EN bit.

5.11.4 Operation Guidelines

In order to start the current gauging the host processor must first set the correct integration period

(CC_ACTIVE_MODE[1:0] bits), enable the gas gauge (FGS toggle bit), and perform the calibration

(CC_CAL_EN bit) to get the offset error and use that to make corrections to the measurement results. The

current gauge enters normal operation automatically when calibration completes. After that, host

processor can read the sample counter (CC_SAMPLE_CNTR[23:0] bits) and accumulator

(CC_ACCUM[31:0] bits) results and calculate the energy accordingly.

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To record the current consumption waveform,the host must use an interrupt (CC_EOC) to detect when the

integration sample result is ready. The integration register CC_INTEG[13:0] always stores the result of the

last measurement.

WARNING

Anti-aliasing filter (RC-filtering) is not allowed with Charger Power Path

configuration. The charger senses the battery current using the same resistor as

Gas Gauge and RC filtering affects the charger loops and may generate stability

problems.

5.12 General-Purpose ADC

The GPADC consists of a 12-bit sigma-delta ADC combined with a 19-input analog multiplexer. The

GPADC enables the host processor to monitor a variety of analog signals using analog-to-digital

conversion on the input source. After the conversion completes, an interrupt is generated

(GPADC_RT_EOC or GPADC_SW_EOC) for the host processor and it can read the result of the

conversion through the I²C interface.

The GPADC supports 19 analog inputs: 7 of these inputs are available on external balls and the remaining

12 are dedicated to internal resource monitoring. Two of the seven external inputs are associated with

current sources allowing measurements of resistive elements (battery type and temperature or other

thermal sensor). The reference voltage (GPADC_VREF) is available when the GPADC is enabled.

GPADC_IN0 is associated with a current source of 7 µA. An additional 15-µA current source can be

enabled by register bit (GPADC_ISOURCE_EN bit in GPADC_CTRL register). A comparator connected to

this input is intended to detect the presence or absence of the battery (resistance to ground is less than

130 kΩ in the battery pack). The removal and insertion of the battery pack generates an interrupt and the

detection result is also available at the BATREMOVAL ball.

GPADC_IN1 and GPADC_IN4 are associated with a voltage reference equal to the ADC reference and

are intended to measure temperature with an NTC sensor. In addition, a detection module is connected to

GPADC_IN1 to permanently monitor the temperature and gate the charge for the battery.

GPADC_IN3 is associated with the three selectable current sources and can be used, for example, to

measure a voltage across an external resistor or diode. The selectable current levels are 10 µA, 400 µA,

and 800 µA and the current is controlled by a register bits (GPADC_REMSENSE[1:0] bits in

GPADC_CTRL2 register).

Figure 5-31 shows the block diagram of the GPADC.

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7/22µA

BATREMOVAL

BAT_DET

GPADC_IN0

Logic

GPADC_VREF

GPADC_IN1

Battery Temperature

Measurement

GATE CHARGING

Comparators

GPADC_IN2

ADC Voltage reference

INPUT

SCALER

RT CONVERSION

10/400/800µA

RESULT

RT CONVERSION

RESULT

12-bit

Sigma-Delta ADC

GPADC_IN3

GPADC_IN4

SW CONVERSION

RESULT

INTERNAL

CHANNELS

(12)

BCI CONVERSION

RESULT

GPADC_IN5

GPADC_IN6

RT CONV request

SW CONV request

BCI CONV request

INTERRUPT

ADC Control

Figure 5-31. Block Diagram of the GPADC

For all the measurements performed by the monitoring ADC, the means to scale of the signal to be

measured to the ADC input range are integrated in the TPS80032 device (voltage dividers, current to

voltage converters, and current source).

The conversion requests are initiated by the host processor, either by software through the I²C or by

hardware through a dedicated external ball GPADC_START. This last mode is useful when real-time

conversion is required. An interrupt signal is generated when the conversion result is ready.

There are three kinds of conversion requests with the following priority:

•

Real-time conversion request (RT)

Asynchronous conversion request (SW)

Battery charging module internal conversion request (BCM)

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Before starting the measurement, the software can enable channels, scalers, current sources and select

other parameters:

•

GPADC_IN0: Additional current source with the GPADC_ISOURCE_EN bit in the GPADC_CTRL

register. (Can be enabled only if OTP bit EN_BAT_DET=1)

•

GPADC_IN1: Enable channel with the GPADC_TEMP1_EN bit in the GPADC_CTRL register.

GPADC_IN2: Enable channel with the GPADC_SCALER_EN_CH2 bit in the GPADC_CTRL register.

GPADC_IN3: Select current source level with the GPADC_REMSENSE [1:0] bits in the

GPADC_CTRL2 register.

•

GPADC_IN4: Enable channel with the GPADC_TEMP2_EN bit in GPADC_CTRL the register.

GPADC_IN7: Select scaler ratio with the VSYS_SCALER_DIV4 bit in GPADC_CTRL the register.

GPADC_IN11: Enable channel with the GPADC_SCALER_EN_CH11 bit in GPADC_CTRL the

register.

•

GPADC_IN12: Enable channel with the TMP1_EN_MONITOR bit in GPADC_CTRL the register.

GPADC_IN13: Enable channel with the TMP2_EN_MONITOR bit in GPADC_CTRL the register.

GPADC_IN18: Enable channel with the GPADC_SCALER_EN_CH18 bit and select scaler ration with

the VBAT_SCALER_DIV4 bit in the GPADC_CTRL2 register.

•

Polarity of the GPADC_START signal for RT measurement: GPADC_START_POLARITY bit in the

TOGGLE1 register.

Sampling window time (16.5 μs / 450 μs): GPADC_SAMP_WINDOW bit in the TOGGLE1 register.

The 450-μs sampling window is beneficial, for example, when measuring system/battery voltage level

synchronized with GSM burst. During the 450-μs delay the system/battery voltage settles to a loaded

situation.

5.12.1 Real-Time Conversion Request (RT)

The real-time conversion is requested with the GPADC_START signal. Before requesting the conversion,

software must enable the required channels, scalers, and current sources. In addition, software must

enable the GPADC with the GPADCS bit in the TOGGLE1 register and select one or two channels for

conversion with the RTSELECT_LSB, RTSELECT_ISB, and RTSELECT_MSB register bits. If more than

two channels are selected for the conversion, the two lowest input numbers are converted. At the end of

the conversions, the GPADC writes the conversion results into the results register (RTCH0_LSB,

RTCH0_MSB, RTCH1_LSB, and RTCH1_MSB) and sets the GPADC_RT_EOC interrupt (if interrupt is

unmasked).

If a GPADC_START real-time request occurs while a software-initiated conversion or BCM internal

conversion is running, the ongoing conversion is aborted, the real-time conversion is started, and a new

software-initiated or BCM internal conversion is rescheduled after the real-time conversion is ready.

5.12.2 Asynchronous Conversion Request (SW)

Software can also request a conversion asynchronously with respect to the GPADC_START signal. This

conversion is not critical in terms of start-of-conversion positioning.

Software enables the required channels, scalers, current sources, enables the GPADC with GPADCS bit

in TOGGLE1 register and selects the channel to be converted with GPSELECT_ISB register bits. The

conversion is requested with SP1 bit in the CTRL_P1 register. When the conversion is ready a

GPADC_SW_EOC interrupt is generated (if interrupt is unmasked) and the conversion result is available

in GPCH0_LSB and GPCH0_MSB registers. A GPADC_START-initiated conversion (RT) and BCM

internal conversion have higher priority than the software-initiated conversion.

If a software request occurs while a GPADC_START-initiated sequence (RT) or BCM internal conversion

is running, the software request is placed on hold and the ongoing conversion continues until it completes

and the converted data is stored. A GPADC_RT_EOC interrupt is then generated and sent to the

processor in case of RT sequence. The digital control executes the software request when the higher

priority conversion are completed. A GPADC_SW_EOC interrupt is then generated.

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5.12.3 BCM Internal Conversion Request

The GPADC is automatically enabled when an internal BCM request is asserted. When this occurs, the

GPADC input channel 17 is selected for a conversion. At the end of the conversion, the GPADC result is

passed internally to the BCM digital control. Interrupt is not generated at the end of the BCM conversion

request.

GPADC_START-initiated conversion (RT) has a higher priority than the BCM-initiated conversion.

The different ADC channels are summarized in the following table.

Table 5-2. GPADC Input Channels

INPUT VOLTAGE

CHANNEL

TYPE

PERFORMANCE

RANGE⁽²⁾

OPERATION

FULL RANGE⁽¹⁾

0

1

2

3

4

5

6

External

0–1.25 V⁽³⁾

0–1.875 V⁽³⁾

0–1.25 V⁽³⁾

0.01–1.215 V

0.015–1.822 V

0.01–1.215 V

Battery type, resistor value

Battery temperature, NTC resistor value

Audio accessory/general purpose

Temperature with external diode/general purpose

Temperature measurement/general purpose

General purpose

0.04–4.86 V or

0.05–6.075 V

7

Internal

0–5 V or 0–6.25 V

System supply

8

9

Internal

0–6.25 V

0–11.25 V

0–27.25 V

0.05–4.8 V

2.0–10.0 V

0.01–6.0 V

Backup battery

External charger input

VBUS

10

VBUS DC-DC output current (available only

without power path, OTP memory bit

POP_APPSCH = 0, R9 = 68 mΩ)

11

Internal

0–1.875 A

0.015–1.5 A

12

13

14

15

16

Internal

0–1.25 V

0–6.875 V

0–6.25 V

0–4.75 V

0.01–1.215 V

0.055–6.68 V

0.05–6.075 V

0.038–4.617 V

Die temperature

USB ID line

Test network

Battery charging current (with 20-mΩ sense

resistor) (available only with power path, OTP

memory bit POP_APPSCH = 1)

17

18

Internal

0–7.8125 A

0–1.5 A

0.04–4.86 V or

0.05–6.075 V

0–5 V or 0–6.25 V

Battery voltage

(1) The minimum and maximum voltage in full range corresponds to typical minimum and maximum output codes (0 and 4095).

(2) The performance voltage is a range where gain error drift, offset drift, INL and DNL, and specification parameters are ensured.

(3) The maximum current sourced into the input is 1mA in NO SUPPLY, BACKUP, and WAIT-ON states.

5.12.4 Calibration

The GPADC channels are calibrated in the production line using a two point calibration method. The

channels are measured with two known values (X1 and X2) and the difference (D1 and D2) to the ideal

values (Y1 and Y2) are stored in OTP memory. The principle of the calibration is shown in Figure 5-32.

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Measured

Code

D2=Y2-X2

Y2

Ideal

Curve

Measured

Curve

Y1

D1=Y1-X1

Offset

Ideal Code

X1

X2

Calibration Points

Measured Points

Figure 5-32. ADC Calibration Scheme

The corrected result can be calculated using the following equations.

Gain: k = 1 + ((D2 – D1) / (X2 – X1))

Offset: b = D1 – (k - 1) × X1

If the measured code is a, the corrected code a' is:

a' = (a – b) / k

Some of the GPADC channels can use the same calibration data. Table 5-3 lists the parameters X1 and

X2, and the register of D1 and D2 needed in the calculation for all the channels.

Table 5-3. GPADC Calibration Parameters

CHANNEL

X1

X2

D1⁽¹⁾

D2⁽¹⁾

COMMENTS

0, 1, 3, 4,

5, 6, 12,

13

GPADC_TRIM3[4:0] * 4 +

GPADC_TRIM1[2:1], sign =

GPADC_TRIM1[0]

GPADC_TRIM4[5:0] * 4 +

GPADC_TRIM2[2:1], sign =

GPADC_TRIM2[0]

1441

(0.44 V)

3276

(1.0 V)

Channel 3 trimming is

used

GPADC_TRIM3[4:0] * 4 +

GPADC_TRIM1[2:1], sign =

GPADC_TRIM1[0]

GPADC_TRIM4[5:0] * 4 +

GPADC_TRIM2[2:1], sign =

GPADC_TRIM2[0]

1441

(0.66 V)

3276

(1.5 V)

Channel 3 trimming is

used

2

(GPADC_TRIM3[4:0] * 4 +

GPADC_TRIM1[2:1], sign =

GPADC_TRIM1[0]) +

(GPADC_TRIM8[4:3] * 16 +

GPADC_TRIM7[4:1], sign =

GPADC_TRIM7[0])

(GPADC_TRIM4[5:0] * 4 +

GPADC_TRIM2[2:1], sign =

GPADC_TRIM2[0]) +

(GPADC_TRIM10[4:0] * 4 +

GPADC_TRIM8[2:1], sign =

GPADC_TRIM8[0])

1441

(2.2 V)

3276

(5.0 V)

Channel 3 and channel

8 trimming is combined

8

(GPADC_TRIM3[4:0] * 4 +

GPADC_TRIM1[2:1], sign =

GPADC_TRIM1[0]) +

(GPADC_TRIM14[4:3] * 16 +

GPADC_TRIM12[4:1], sign =

GPADC_TRIM12[0])

(GPADC_TRIM4[5:0] * 4 +

GPADC_TRIM2[2:1], sign =

GPADC_TRIM2[0]) +

(GPADC_TRIM16[4:0] * 4 +

GPADC_TRIM14[2:1], sign =

GPADC_TRIM14[0])

1441

(3.96 V)

3276

(9.0 V)

Channel 3 and channel

9 trimming is combined

9

(1) The result is coded so that the LSB defines the sign and the MSBs define the magnitude (not 2's complement).

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Table 5-3. GPADC Calibration Parameters (continued)

CHANNEL

X1

X2

D1⁽¹⁾

D2⁽¹⁾

COMMENTS

GPADC_TRIM11[3:0] * 8 +

GPADC_TRIM9[3:1], sign =

GPADC_TRIM9[0]

GPADC_TRIM15[3:0] * 8 +

GPADC_TRIM13[3:1], sign =

GPADC_TRIM13[0]

150

(1.0 V)

751

(5.0 V)

10

Dedicated trimming

GPADC_TRIM3[4:0] * 4 +

GPADC_TRIM1[2:1], sign =

GPADC_TRIM1[0]

GPADC_TRIM4[5:0] * 4 +

GPADC_TRIM2[2:1], sign =

GPADC_TRIM2[0]

1441

(0.66 A)

3276

(1.5 A)

Channel 3 trimming is

used

11

14

GPADC_TRIM3[4:0] * 4 +

GPADC_TRIM1[2:1], sign =

GPADC_TRIM1[0]

GPADC_TRIM4[5:0] * 4 +

GPADC_TRIM2[2:1], sign =

GPADC_TRIM2[0]

1441

(2.42 V)

3276

(5.5 V)

Channel 3 trimming is

used

(GPADC_TRIM3[4:0] * 4 +

GPADC_TRIM1[2:1], sign =

GPADC_TRIM1[0]) +

(GPADC_TRIM5[6:1], sign =

GPADC_TRIM5[0])

(GPADC_TRIM4[5:0] * 4 +

GPADC_TRIM2[2:1], sign =

GPADC_TRIM2[0]) +

(GPADC_TRIM6[7:1], sign =

GPADC_TRIM6[0])

Channel 3 and channel

18 trimming is

combined, input voltage

range is 0–6.25 V

1441

(2.2 V)

3276

(5.0 V)

7, 18

17

I_charge= (a – GPADC_TRIM20[7:0]) * (1 + GPADC_TRIM21[5:0] / 512) * 1.25 V / 4096 / 8 / R2 ;

a = measured code, GPADC_TRIM20[7:0] is an unsigned value,

Dedicated equation

in GPADC_TRIM21[5:0] the bit 5 is the sign and bits[4:0] are the magnitude

5.13 Vibrator Driver and PWM Signals

The LDO3 regulator can be used as a generic voltage supply or as a vibrator motor driver. The output

voltage level is controlled with the LDO3_CFG_VOLTAGE register and the regulator provides output

current up to 200 mA.

The vibrator mode is selected with the SEL_VIB bit in the MISC2 register. The duty cycle and frequency

are controlled with the DSEL[1:0] and FREQ[1:0] bits in the VIBCTRL and VIBMODE registers. The

vobrator is started with the VIBS bit and stopped with the VIBC bit in the TOGGLE2 register. The vibrator

driver allows a soft turn on (500-µs maximum) and turn off (2-ms maximum).

Figure 5-33 shows a block diagram of the vibrator motor driver.

LDO_IN

(from the battery)

V PWL

+

VIB_OUT

–

SWCS057-021

Figure 5-33. Block Diagram of Vibrator Motor Driver

The PWM1 and PWM2 digital outputs provide PWM signals on the 1.8-V I/O domain. The current drive

capability of both PWM buffer is 4 mA and the outputs can also be active when the system is in the

SLEEP state.

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The period of the PWM signals can be selected separately with the PWM1_LENGTH and

PWM2_LENGTH bits in the PWM1ON and PWM2ON registers. The selection of 128 clock cycles results

as a 256-Hz PWM signal and the selection of 64 cycles results as 512-Hz PWM signal. Both PWM signals

have dedicated counters. The counters are started by first enabling the 32768-Hz clock inputs with the

PWM1EN and PWM2EN bits in the TOGGLE3 register and then setting the PWM1S and PWM2S bits.

The rising and falling-edge positions are selected with the PWM1ON[6:0], PWM1OFF[6:0], PWM2ON[6:0],

and PWM2OFF[6:0] bits in the PWM1ON, PWM1OFF, PWM2ON, and PWM2OFF registers as shown in

Figure 5-34.

0

1

2

3

4

123

124

125

126

127

0

1

2

CLK1

PWM1S

PWM1

PWM1ON = 0x03

PWM1OFF = 0x7C

0

1

2

3

4

123

124

125

126

127

0

1

2

CLK2

PWM2S

PWM2

PWM2ON = 0x01

PWM2OFF = 0x7E

Figure 5-34. PWM Signal Timings (128 Clock Cycles in Period, Clocks Synchronized)

NOTE

The clock inputs for generation of PWM signals are enabled with the PWM1EN and

PWM2EN bits in the TOGGLE3 register. The start and stop of the PWM signal generation is

controlled with the PWM1S, PWM2S, PWM1C, and PWM2C bits in the TOGGLE3 register.

To get a clean start and stop, the clock input must be enabled before starting PWM signal

generation and the PWM signal generation must be stopped before disabling the clock input.

The CLK1 and CLK2 counters can be synchronized by setting both the PWM1S and PWM2S

bits high with the same I²C write.

The PWM signal is constantly high if PWMxON[6:0] is equal to PWMxOFF[6:0].

The following rules must be fulfilled for the PWMxON and PWMxOFF settings:

•

PWMxOFF[6:0] ≥ PWMxON[6:0]

PWMxON[6:0] > 0x00

5.14 Detection Features

The TPS80032 device supports the following detection functions:

•

Detection of SIM card insertion and extraction with programmable debouncing using SIM pin,

automatic power shutdown of LDO7 when extraction is detected (configurable)

Detection of MMC card insertion and extraction with programmable debouncing using MMC pin,

automatic power shutdown of LDO5 when extraction is detected (configurable)

Detection of battery presence and removal with GPADC_IN0 input (see Section 5.9.8)

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The TPS80032 device supports SIM card and MMC card insertion and extraction detections with

programmable debounce times. The debounce times are programmed with SIMDEBOUNCING and

MMCDEBOUNCING registers. When the SIM card or MMC card is inserted, a mechanical contact

connected on the TPS80032 device terminal SIM or MMC is tripped, and after debouncing an interrupt is

generated. The SIM card and MMC card presence detection logic is active even when the system is in idle

mode; the debouncing logic (programmable) is based on the 32-kHz clock. When a card insertion is

detected, the required regulator must be enabled by host processor. When a card is extracted, the LDO7

for SIM card and LDO5 for MMC card can be selected to turn off automatically. These are controlled by

SIMCTRL and MMCCTRL registers. An interrupt is generated when a plug or unplug is detected.

The SIM card or MMC card plug and battery insertion/extraction are detected in SLEEP and ACTIVE

states. Both card detections and battery detection have dedicated maskable interrupts (MMC, SIM, and

BAT).

5.15 Thermal Monitoring

The TPS80032 device includes several different thermal monitoring functions:

•

Thermal protection module in the TPS80032 device, close to SMPSs and LDOs

Thermal shutdown for system supply regulator inside the TPS80032 device

Battery temperature monitoring with external NTC resistor (can be used to gate the battery charging)

Platform temperature monitoring with external NTC resistor

Platform temperature monitoring with external diode

A thermal protection module inside the TPS80032 device monitors the temperature of the device. It

generates a warning to the system when excessive power dissipation occurs and shuts down the

TPS80032 device if the temperature rises to a value at which damage can occur.

CAUTION

The silicon technology used to build the TPS80032 device supports a maximum

operating temperature of 150°C. Regarding packaging technology,

operation above 125°C requires special packaging and must be avoided.

a continuous

By default, thermal protection is always enabled except in the BACKUP or OFF state.

The TPS80032 device integrates two HD detection mechanisms to monitor and alert the host that the

junction temperature is rising and must take action to reduce consumption. Those mechanisms are placed

on two opposite sides of the chip and closed to the LDOs and SMPSs. Even if there are two identical

thermal feature instances on the chip, it is always considered through the specification to be unique. In

addition to those HD detections, there is another HD feature embedded in the system supply regulator.

This HD is specified in Section 5.9, Battery Charging, and does not behave exactly as described in the

following section.

5.15.1 Hot-Die Function

The HD detector monitors the temperature of the die and provides a warning to the host processor

through the interrupt (HOT_DIE) when temperature reaches a critical value. The temperature threshold

value is programmable with the THERM_HD_SEL[1:0] bits in the TMP_CFG register. The threshold has

typically 10°C hysteresis to avoid the generation of multiple interrupts.

When an interrupt is triggered by the power-management software, immediate action to reduce the

amount of power drawn from the TPS80032 device must be taken (for example, noncritical applications

must be closed).

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5.15.2 Thermal Shutdown

The thermal shutdown detector monitors the temperature on the die. If the junction reaches a temperature

at which damage can occur, a switch-off transition is initiated and a thermal shutdown event is written into

a status register.

To avoid interrupts at restart, the system cannot be restarted until the die temperature falls below the HD

threshold.

The thermal shutdown monitor function is integrated to generate an immediate, unconditional TPS80032

device switch off when an overtemperature condition exists. This function must be distinguished with the

early warning provided to host processor by the HD monitor function.

In the TPS80032 device, the threshold (T_Jrising) of the thermal shutdown is 148°C nominal. The thermal

shutdown hysteresis is 10°C in typical conditions. The reset generation is debounced. The thermal

shutdown function can be masked only in the SLEEP state (the TMP_CFG_TRANS register) and in test

mode.

5.15.3 Temperature Monitoring with External NTC Resistor or Diode

The GPADC_IN1 and GPADC_IN4 channels can be used to measure a temperature with an external NTC

resistor. External pullup and pulldown resistors can be connected to the input to linearize the

characteristics of the NTC resistor. GPADC_IN1 can be used to gate the battery charging at invalid

temperatures. The temperature limits are set by external resistors.

GPADC_IN3 can be used to measure the temperature with external diode. The input channel has three

selectable current sources.

5.16 I²C Interface

A general-purpose serial control interface (CTL-I²C) allows read-and-write access to the configuration

registers of all resources of the system.

A second serial control interface (DVS-I²C) is dedicated to dynamic voltage scaling (DVS).

Both control interfaces comply with the HS-I²C specification and support the following features:

•

Mode: Slave only (receiver and transmitter)

Speed

–

Standard mode (100 kbps)

Fast mode (400 kbps)

High-speed mode (3.4 Mbps)

•

Addressing: 7-bit mode addressing device

The following features are not supported:

•

10-bit addressing

General call

5.17 Secure Registers

Certain registers of the TPS80032 device can be protected by restricting their access in write mode to

software running in the secure mode. Read access to protected registers is always possible. Secure

access is enabled or disabled by the MSECURE control signal.

The following components or actions can be protected:

•

All RTC registers

64 bits of general-purpose memory (8 × 8) in the VALIDITY backup domain

The read accesses are independent to the MSECURE value.

110

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When MSECURE is logical level 1, all read and write accesses are authorized; when MSECURE is logical

level 0, only read accesses are authorized.

The MSECURE detection security feature is enabled and disabled by an OTP bit.

5.18 Access Protocol

For compatibility purpose, the I²C interface of the TPS80032 device uses the same read/write protocol

based on an internal register size of 8 bits as do other TI power ICs. Supported transactions are described

in the following sections.

5.18.1 Single-Byte Access

A write access is initiated by a first byte including the address of the device (7 most-significat bits [MSBs])

and a write command (least-significant bit [LSB]), a second byte provided the address (8 bits) of the

internal register, and the third byte represents the data to be written in the internal register.

Figure 5-35 shows a write access single-byte timing diagram.

DAD: Device address

W

S

T

A

R

T

D

A

D

6

D

A

D

5

D

W

A

C

K

R

A

D

2

3

R

A

D

1

2

R

A

D

A

T

6

D D

A

D

A

T

3

D

A

T

2

D

A

T

1

D

A

T

0

A

C

K

S

T

O

P

D

A

R

A

R

I

A

C

A

T

A

C

A

RAD: Register address

DAT: Data

D

K

T

4

D

K

D

K

T

4

3

2

1

0

T

E

7

6

5

4

3

0

7

5

6

5

1

0

7

0

SCL

SDA

Master drives SDA

Slave drives SDA

SWCS057-022

Figure 5-35. I²C Write Access Single Byte

A read access is initiated by:

•

A first byte, including the address of the device (7 MSBs) and a write command (LSB)

A second byte, providing the address (8 bits) of the internal register

A third byte, including again the device address (7 MSBs) and the read command (LSB)

The device replies by sending a fourth byte representing the content of the internal register.

Figure 5-36 shows a read access single-byte timing diagram.

S

T

A

R

T

D

A

D

6

D

A

D

5

D

A

D

4

D

A

D

3

D

A

D

2

D

A

D

1

D

A

D

0

W

R

I

A

C

K

R

A

D

7

R

A

D

6

R

A

D

5

R

A

D

4

R

A

D

3

R

A

D

2

R

A

D

1

R

A

D

0

A

C

K

S

T

A

R

T

D

A

D

6

D

A

D

5

D

A

D

4

D

A

D

3

D

A

D

2

D

A

D

1

D

A

D

0

R

E

A

D

A

C

K

D

A

T

7

D

A

T

6

D

A

T

5

D

A

T

4

D

A

T

3

D

A

T

2

D

A

T

1

D

A

T

0

A

C

K

S

T

O

P

T

E

SCL

SDA

SWCS057-023

Figure 5-36. I²C Read Access Single Byte

5.18.2 Multiple-Byte Access to Several Adjacent Registers

A write access is initiated by:

•

A first byte, including the address of the device (7 MSBs) and a write command (LSB)

A second byte, providing the base address (8 bits) of the internal registers

The following N bytes represent the data to be written in the internal register, starting at the base address

and incremented by 1 at each data byte.

Figure 5-37 shows a write access multiple-byte timing diagram.

Detailed Description

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S

T

A

R

T

D

A

D

6

D

A

D

5

D

A

D

4

D

A

D

3

D

A

D

2

D

A

D

1

D

A

D

0

W

R

I

A

C

K

R

A

D

7

R

A

D

6

R

A

D

5

R

A

D

4

R

A

D

3

R

A

D

2

R

A

D

1

R

A

D

0

A

C

K

D

A

T

7

D

A

T

6

D

A

T

5

D

A

T

4

D

A

T

3

D

A

T

2

D

A

T

1

D

A

T

0

A

C

K

D

A

T

7

D

A

T

6

D

A

T

5

D

A

T

4

D

A

T

3

D

A

T

2

D

A

T

1

D

A

T

0

A

C

K

S

T

O

P

T

E

SCL

SDA

SWCS057-024

Figure 5-37. I²C Write Access Multiple Bytes

A read access is initiated by:

•

A first byte, including the address of the device (7 MSBs) and a write command (LSB)

A second byte, providing the base address (8 bits) of the internal register

A third byte, including again the device address (7 MSBs) and the read command (LSB)

The device replies by sending a fourth byte representing the content of the internal registers, starting at

the base address and next consecutive ones.

Figure 5-38 shows a read acces multiple-byte timing diagram.

S

T

A

R

T

D

A

D

6

D

A

D

5

D

A

D

4

D

A

D

3

D

A

D

2

D

A

D

1

D

A

D

0

W

R

I

A

C

K

R

A

D

7

R

A

D

6

R

A

D

5

R

A

D

4

R

A

D

3

R

A

D

2

R

A

D

1

R

A

D

0

A

C

K

S

T

A

R

T

D

A

D

6

D

A

D

5

D

A

D

4

D

A

D

3

D

A

D

2

D

A

D

1

D

A

D

0

R

E

A

D

A

C

K

D

A

T

7

D

A

T

6

D

A

T

5

D

A

T

4

D

A

T

3

D

A

T

2

D

A

T

1

D

A

T

0

A

C

K

D

A

T

7

D

A

T

6

D

A

T

5

D

A

T

4

D

A

T

3

D

A

T

2

D

A

T

1

D

A

T

0

A

C

K

S

T

O

P

T

E

SCL

SDA

SWCS057-025

Figure 5-38. I²C Read Access Multiple Bytes

5.19 Interrupts

The INT signal (active low) indicates the host processor of events occurring on the TPS80032 device. The

host processor then reads the interrupt status registers (INT_STS_A, INT_STS_B, and INT_STS_C)

through I²C to identify the interrupt source. Each interrupt source can be individually masked through the

interrupt mask registers. If the source is masked with mask line register (INT_MSK_LINE_A, B, C) then

the INT signal is not generated for host processor but the interrupt status register (INT_STS_A, B, C) is

set in case of source event. If the source is masked with mask status register (INT_MSK_STS_A, B, C)

then the INT signal is not generated and the status register is not set in case of source event. The block

diagram of the interrupt handler is shown in Figure 5-39.

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INT_MSK_STS_A

INT_STS_A

INT_MSK_LINE_A

Shadow

Register

INT_MSK_STS_A

Shadow

Register

Shadow

Register

INT

OR

Clear on Write

INT_A lines

INT_B lines

INT_C lines

Figure 5-39. Block Diagram of Interrupt Handler

In order to clear the status registers and the interrupt signal, a write in any of the status registers

(INT_STS_A, B, or C) must be done. Each write has the same effect (interrupt line goes high and all

status registers are cleared). This requires that the three status registers must be read before

acknowledging the interrupt to avoid losing any interrupt sources.

If additional interrupt or interrupts occur while the status registers and interrupt line are not cleared, the

status registers are not updated immediately. Instead, the interrupts are held pending in a shadow

registers. When the previous interrupt(s) are cleared, the interrupt line goes high and the content of the

shadow registers is moved to status registers. If there are new unmasked events the interrupt signal is set

to low again.

If the unmasked source event occurs when the INT signal is high, the interrupt status bit is set without

using the shadow register.

NOTE

•

An interrupt associated with a function must be masked before enabling or disabling the

feature; otherwise, it might generate a false interrupt directly linked to the state change of

the source and not related to a detection event (for example, a SYS_VLOW interrupt with

the VSYSMIN_HI comparator).

•

INT is always active low.

When a interrupt occurs:

–

Software should first read all status registers INT_STS_A, INT_STS_B, and

INT_STS_C.

–

Execute the subroutines related to the read interrupts.

Clear the interrupt signal and interrupt status of all status registers.

#

REG BIT

SECTION

INTERRUPT

PWRON

Description

00

A

0

PM

PWRON detection: Power-on button pressed and released. Detection

performed on falling and rising edges. Interrupt sent in the SLEEP or

ACTIVE state only, not in WAIT-ON.

01

02

A

1

2

PM

RPWRON

RPWRON detection: Remote power on signal change. Interrupt sent in

the SLEEP or ACTIVE state only, not in WAIT-ON.

VSYS_VLOW

System voltage low: System voltage decreasing and crossing

V_{SYSMIN_HI}

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03

04

A

3

4

RTC

RTC_ALARM

RTC_PERIOD

RTC alarm event: Occurs at programmed determinate date and time

RTC periodic event: Occurs at programmed regular period of time

(every second or minute)

05

06

A

5

6

Thermal monitoring HOT_DIE

and shutdown

At least one of the two embedded thermal monitoring modules detects

a die temperature above the HD detection threshold.

SMPS/LDO

VXXX_SHORT

At least one of the following power resources has its output shorted:

SMPS1, SMPS2, SMPS3, SMPS4, SMPS5, VANA, LDO1, LDO2,

LDO3, LDO4, LDO5, LDO6, LDO7, LDOLN, LDOUSB

07

08

09

10

11

12

A

B

7

0

1

2

3

4

PM

SPDURATION

WATCHDOG

BAT

PWRON short press duration

Warning of primary watchdog expiration

Battery detection plug/unplug

SIM card plug/unplug

PM

Detection

GPADC

SIM

MMC

MMC card plug/unplug

GPADC_RT_EOC

End of conversion: Completion of a real-time conversion cycle; result

available

13

14

B

5

6

GPADC

GPADC_SW_EOC

CC_EOC

End of conversion: Completion of a software (SW) conversion cycle;

result available

Gas gauge

End of conversion: Completion of gas gauge measurement (end of

integration period); result available

15

16

17

18

19

20

21

22

23

B

C

7

0

1

2

3

4

5

6

7

Gas gauge

OTG

CC_AUTOCAL

ID_WKUP

VBUS_WKUP

ID

Calibration procedure finished and the result is available in the register.

ID wake-up event (from WAIT-ON/SLEEP states)

VBUS wake-up event (from WAIT-ON/SLEEP states)

ID event detection in SLEEP/ACTIVE states

VBUS event detection in SLEEP/ACTIVE states

Charger controller

OTG

VBUS

Charger

CHRG_CTRL

EXT_CHRG

INT_CHRG

External charger fault

Internal USB charger fault

Reserved

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6 Recommended External Components

Table 6-1. Recommended External Components

SIZE

(mm)

(2)

REF

COMPONENT⁽¹⁾

PCS

#

MANUFACTURER

PART NUMBER

VALUE

PACK⁽³⁾

Input Power Supplies External Components

C1, C2

VDD tank capacitor⁽⁴⁾

Backup capacitor

2

1

Murata

GRM188R60J106ME84

XH414H-IV01E

10 µF, 6V3

0.08 F

0603

0402

1.6 x 0.8 x 0.8

ø4.8, 1.4

C3

1

Seiko Instruments

Murata

C44

Capacitor (optional)

GRM155R60J475M

4.7 µF

1.0 x 0.5 x 0.5

Crystal Oscillator External Components

X1

Crystal

1

2

3

1

Microcrystal

Epson

CC7V-T1A

32.768 kHz

2.2 µF, 6V3

12 pF, 6V3

3.2 x 1.5 x 0.9

3.2 x 1.5 x 0.8

1.0 x 0.5 x 0.5

1

FC135

NDK

NX3215SA

C4

Supply decoupling

Crystal decoupling

1

2

Murata

GRM155R60J225ME15

GRM1555C1H220JZ01

0402

C5, C6

Bandgap External Components

R1

C7

Bias resistor

Capacitor

1

Multicomp

Murata

MC0.0625W, 1%

510 kΩ

0402

1.0 x 0.5 x 0.5

GRM155R61C104KA88

100 nF, 6V3

Gas Gauge and Charger External Components

R2

Resistor

1

2

Panasonic

ERJ3BWFR020V

ERJ8BWFR020V

20 mΩ, 0.25W, 1%

20 mΩ, 0.5W, 1%

0603

1206

1.6 x 0.8 x 0.45

3.2 x 1.6 x 0.65

1

Panasonic

GPADC External Components

NCL15WB473F03RC

R3, (R4)

NTC resistor (optional)

Bias resistor (optional)

2

4

2

1

Murata

47 kΩ

0402

1 x 0.5 x 0.5

R5, R6, (R7,

R8)

The resistor values depends on the required temperature levels

C42, (C43)

Capacitor (optional)

Murata

GRM155R61C104K

SMPS External Components

100 nF, 6V3

C8...C12

C13

Input capacitor

5

1

Murata

GRM155R60J475M

4.7 µF

22 µF

0402

0603

1.0 x 0.5 x 0.5

1.6 x 0.8 x 0.8

Output capacitor

Murata

GRM188R60G226MEA0

Output capacitor, up to 5

A

Murata (2 in parallel)

2

4

1

22 µF

2x 0603

2 pcs 1.6 x 0.8 x 0.8

C14...C17

L6, L7, L8

Output capacitor

Inductor, 1.1 A

1

2

3

1

Murata

GRM188R60J106ME84L

LQM2MPN1R0NG0

MDT2520-CN1R0M

MLP2520S1R0M

XFL4020-102ME

10 µF

0603

0806

1008

1.6 x 0.8 x 0.8

2.0 x 1.6 x 0.9

2.5 x 2.0 x 1.2

2.5 x 2.0 x 1.0

4.0 x 4.0 x 2.1

Murata

1 µH (1.4 A)

1 µH (1.35 A)

1 µH (1.5 A)

1 µH (5.4 A)

3

TOKO

TDK

L9

Inductor, up to 5.0 A

COILCRAFT

TOKO (2 in parallel)

DFE322512C

1 µH (3.1 A), 2 in

parallel (5 A)

2

2x 1210

2 pcs 3.2 x 2.5 x 1.2

1

3

4

5

1

2

3

4

1

TOKO

TDK

DFE322512C

1 µH (3.1 A)

1 µH (3.0 A)

1 µH (2.8 A)

1 µH (1.8 A)

1 µH (3.1 A)

1 µH (3.0 A)

0.68 µH (2.0 A)

0.47 µH (3.7 A)

1210

1008

3.2 x 2.5 x 1.2

2.5 x 2.0 x 1.2

3.2 x 3.0 x 1.2

3.2 x 2.5 x 1.0

3.2 x 2.5 x 1.2

2.5 x 2.0 x 1.2

2.0 x 2.0 x 1.0

3.2 x 2.5 x 1.2

DFE252012C

SPM3012T-1R0M

LQM32PN1R0MG0

DFE322512C

L10

Inductor, up to 2.5 A

Inductor (Option 2)

Murata

TOKO

Coilcraft

TOKO

1210

1008

0808

1210

1

DFE252012C

EPL2010-681MLB

DFE322512C

LDO External Components

C18...C22

C23...C33

Input capacitor

5

1

TDK

C1005X5R0J225M

2.2 µF, 6V3

0402

1.0 x 0.5 x 0.5

Output capacitor

11

Charger External Components

L11

Inductor

1

2

3

FDK

MIPS2520D1R0

CKP25201R0M-T

DFE252012C

1 µH (1.2 A)

1 µH (1.4 A)

1 µH (3.0 A)

2520

1008

2.5 x 2.0 x 1.0

2.5 x 2.0 x 1.2

1

Taiyoyuden

TOKO

(1) Component minimum and maximum tolerance values are provided in the electrical parameters section for each IP.

(2) The # column refers to the first (1), second (2), and third (3) source suppliers, for which the IPs are either simulated or characterized.

(3) The PACK column describes the external component package type.

(4) The VDD tank capacitors filter the VSYS/VDD input voltage of the LDO and SMPS core architectures.

Recommended External Components

115

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Table 6-1. Recommended External Components (continued)

S1

PMOS battery switch

(with power path)

Texas Instruments (C45 = 4.7 nF CSD25201W15

needed)

1

33 mΩ (V_GS= -4.5 V)

1.5 x 1.5 x 0.62

2

3

4

5

1

Vishay (C45 not needed)

Vishay (C45 = 4.7 nF needed)

Rohm (C45 = 15 nF needed)

Murata

Si8417DB

21 mΩ (V_GS= -4.5 V)

22 mΩ (V_GS= -4.5 V)

21 mΩ (V_GS= -4.5 V)

16 mΩ (V_GS= -4.5 V)

4.7 nF, 10 V

2.4 x 2.0 x 0.65

2.05 x 2.05 x 0.6

3.0 x 2.8 x 0.8

1.0 x 0.5 x 0.5

1

Si8407DB

SiA429DJT

RQ1A060ZP

C45

R9

Gate capacitor (with

power path, see S1

comments)

GRM155R61A472KA01D

GRM155R71C153KA01D

0402

1

Murata

2

15 nF, 10 V

1.0 x 0.5 x 0.5

Sense resistor (shorted

with power path)

Panasonic

ERJ3BWFR068V

1

68 mΩ, 0.25 W

2.2 µF, 10 V

100 nF, 16 V

0603

0402

1.6 x 0.8 x 0.8

1.0 x 0.5 x 0.5

C34

C35

CHRG_VREF capacitor

Murata

GRM188R61A225KE34D

GRM155R61C104K

VAC decoupling

capacitor

C36

C37

C38

VBUS decoupling

1

Murata

GRM219R61C475KE15

GRM155R61C104K

4.7 µF, 16 V

0805

2.0 x 1.25 x 0.85

CHRG_PMID capacitor

CHRG_CSIN capacitor

(not placed with power

path)

1

100 nF, 6V3

0402

1 x 0.5 x 0.5

C39

C41

C40

S2

CHRG_CSOUT cap1

CHRG_CSOUT cap2

CHRG_SW capacitor

1

Murata

Vishay

GRM188R60J106ME84L

GRM155R61A105KE15D

GRM155R61C104K

Si8417DB

10 µF, 6V3

1 µF, 6V3

0603

0402

1.6 x 0.8 x 0.8

1.0 x 0.5 x 0.5

100 nF, 16 V

PMOS switch for

negative voiltage

protection

1

22 mΩ

2.4 x 2.0 x 0.65

R10

D1

Pull-down resistor

LED

1

100 kΩ

0402

1.0 x 0.5 x 0.5

1.0 x 0.5 x 0.35

Everlight

16S-216UTD/S559/TR8

2 mA

116

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SWCS059I –MARCH 2011–REVISED NOVEMBER 2014

7 Device and Documentation Support

7.1 Device Support

7.1.1 Development Support

TI offers an extensive line of development tools, including tools to evaluate the performance of the

processors, generate code, develop algorithm implementations, and fully integrate and debug software

and hardware modules. The tool's support documentation is electronically available within the Code

Composer Studio™ Integrated Development Environment (IDE).

The following products support development of the TPS80032 device applications:

Software Development Tools: Code Composer Studio Integrated Development Environment (IDE):

including Editor C/C++/Assembly Code Generation, and Debug plus additional development tools

Scalable, Real-Time Foundation Software (DSP/BIOS™), which provides the basic run-time target

software needed to support any TPS80032 device applications.

Hardware Development Tools: Extended Development System ( XDS™) Emulator

7.1.2 Device Nomenclature

To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all

microprocessors (MPUs) and support tools. Each device has one of three prefixes: X, P, or null (no prefix)

(for example, TPS80032). Texas Instruments recommends two of three possible prefix designators for its

support tools: TMDX and TMDS. These prefixes represent evolutionary stages of product development

from engineering prototypes (TMDX) through fully qualified production devices and tools (TMDS).

Production devices and TMDS development-support tools have been characterized fully, and the quality

and reliability of the device have been demonstrated fully. TI's standard warranty applies.

Predictions show that prototype devices (X or P) have a greater failure rate than the standard production

devices. Texas Instruments recommends that these devices not be used in any production system

because their expected end-use failure rate still is undefined. Only qualified production devices are to be

used.

TI device nomenclature also includes a suffix with the device family name. This suffix indicates the

package type (for example, YFF) and the temperature range (for example, blank is the default commercial

temperature range).

For orderable part numbers of TPS80032 devices in the YFF package types, see the Package Option

Addendum of this document, the TI website (www.ti.com), or contact your TI sales representative.

7.2 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the

respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views;

see TI's Terms of Use.

TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster

collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge,

explore ideas and help solve problems with fellow engineers.

TI Embedded Processors Wiki Texas Instruments Embedded Processors Wiki. Established to help

developers get started with Embedded Processors from Texas Instruments and to foster

innovation and growth of general knowledge about the hardware and software surrounding

these devices.

7.3 Trademarks

Code Composer Studio, XDS, E2E are trademarks of Texas Instruments.

Device and Documentation Support

117

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7.4 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more

susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

7.5 Export Control Notice

Recipient agrees to not knowingly export or re-export, directly or indirectly, any product or technical data

(as defined by the U.S., EU, and other Export Administration Regulations) including software, or any

controlled product restricted by other applicable national regulations, received from disclosing party under

nondisclosure obligations (if any), or any direct product of such technology, to any destination to which

such export or re-export is restricted or prohibited by U.S. or other applicable laws, without obtaining prior

authorization from U.S. Department of Commerce and other competent Government authorities to the

extent required by those laws.

7.6 Glossary

SLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

7.7 Additional Acronyms

Additional acronyms used in this data sheet are described below.

TERM

ADC

IC

DEFINITION

Analog-to-Digital Converter

Integrated Circuit

I2C/I²C

LDO

LSB

Inter-IC Control Bus

Low Dropout Voltage Regulator

Least-Significant Bit

Most-Significant Bit

MSB

PFM

PWM

RTC

Pulse Frequency Modulation

Pulse Width Modulation

Real-Time Clock

7.8 Detailed Revision History

VERSION

DATE

03/2010

06/2011

NOTES

(1)

*

See

.

(2)

A

(1) SWCS059, TPS80032 Data Manual: Initial release

(2) SWCS059A: Update

•

Table 4-10, Boost mode for VBUS voltage generation: I_BO1and I_BLIMITupdated.

Long Key Press (PWRON), OTP memory bit to generate startup after shutdown.

Table Table 6-1, S2, R10, and C40 updated.

PCB Placement and Routing Guidelines chapter removed, there will be a separate Application Note.

updated.

Section 5.19, second paragraph updated.

Section 5.4.1 updated.

Section 5.7.2, last paragraph updated.

Section 5.9 updated.

USB ID resistance detection figure added, Figure 5-25.

USB ID resistance detection table added, Table 5-1.

Caution added to short-circuit protection chapter, Section 5.7.1.

Major updates in Battery Charging chapter Section 5.9.

Updated .

Recommended SMPS External Components updated, Table 6-1.

LDOUSB 3.3 V output voltage levels updated, Table 4-4.

GPADC INL error for GPADC_IN14 added, Section 4.5.13.

GPADC channel scaler changed to input voltage range, Section 5.12.3.

Thermal characteristics updated, Section 8.1.

118

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SWCS059I –MARCH 2011–REVISED NOVEMBER 2014

VERSION

DATE

09/2011

11/2011

NOTES

(3)

B

C

See

.

(4)

(3) SWCS059B: Update

•

Update : CHRG_CSOUT connection when not used.

Update Section 1.1: Battery voltage range from 2.5 to 5.5 V.

Typo corrected Section 4.5.1: T_LDRfor SMPS2 and SMPS5 swapped.

Typo corrected Section 4.5.1: I_Qfor SMPS2 and SMPS5 swapped.

Update Section 5.9: Example of external charger changed to BQ24159.

Update Section 4.5.11: Several parameters added into Pullup and Pulldown Resistors chapter.

Update Section 4.5.1: I_Qfor SMPS1 added.

Update Section 4.5.1: V_INP, V_INF, and MinDOV clarified.

Update Section 4.5.13: Offset from +/–9 LSB to +/–36 LSB.

Update Table 5-2: Nonsaturated input voltage range added.

Update Section 5.10.3 and Figure 5-29: VBUS_IADP_SRC operation during ADP probing.

Update Section 5.9.13.1.3: Warning about thermal regulation loop operation added.

Update Section 5.7.2.2: Inductor value for optimized operation.

Update Table 6-1: C13 and L9 updated.

Update Section 5.7.2: Numerous parameters updated.

Update Figure 4-1: SMPS1 efficiency curve updated.

Update Table 5-2: Table notes added and VBUS and VAC range updated.

Update Table 4-15: Channel 11 offset from +/–20 to +/–36 LSB.

Update Table 4-4: LDO's minimum PSRR updated.

Update : CTLI2C_SCL, CTLI2C_SDA, DVSI2C_SCL, and DVSI2C_SDA pull-up resistor range changed (new value is 1.46 k to 7.4

k).

•

Update Section 5.7.2.5: 3-A and 5-A mode clarified for SMPS1.

Update : Ordering information updated.

Update Section 4.5.16: Condition for WAIT-ON current clarified.

Update Table 4-10: Boost mode quiescent current updated to 5 mA.

Update Section 5.9.4: VBUS anticollapse sensing point clarified.

Update Table 4-1: Additional points for SMPS2 dropout voltage added.

Update Figure 4-3.

(4) SWCS059C: Update

•

Update Section 5.19: The interrupts chapter clarified and figure added.

Update Section 5.12: The block diagram, calibration and software guidelines added.

Update Section 5.13: The operation is clarified and the software guidelines are added.

Update Section 5.2, DVS Software Commands, Boot Pins, Section 5.4.1, Section 5.4.2, PWRON, RPWRON, Section 5.5,

Section 5.8, Section 5.10, Section 5.10.1, Section 5.11: Register names added.

Update Section 5.4.4: Chapter updated.

Update Table 4-10: Parameters of analog thermal regulation loop updated.

Update Section 5.9.13.1.3: CURRENT_TERM, CHARGE_DONE, NO_BAT and EN_LINCH dependency of Power Path usage is

clarifier.

•

Update Table 4-10: V_{OVP_ VSYS}updated.

Update Table 4-1: SMPS2 rated current increased to 2.5 A. ILIMIT, MinDOV, R_V, DC_LDR, T_DCOVupdated.

Update Section 5.14: Description clarified, names of the registers and bits added.

Update Section 5.15: Description clarified, names of the registers and bits added.

Update : Ordering information updated.

Update Section 5.9: Major updates in the chapter.

Update Section 5.5: Regulator short circuit detection added to stopping event.

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VERSION

DATE

NOTES

(5)

D

E

F

12/2011

02/2012

04/2012

See

.

(6)

(7)

(5) SWCS059D: Update

•

Update Section 8.1: MSL Peak Temp added.

Update Table 5-2: Performance range of CH11 and CH17 updated.

Update Tablenote: Note updated for the result's coding.

Update Table 4-1: SMPS1 turn off time with 44 F output capacitance, SMPS1 on ground current and SMPS2 DC_LDRupdated.

Update Figure 5-12: Min. VICHRG level changed from 0.3 A to 0.1 A and VSYSMIN_HI replaced by VBATMIN_HI.

Update Section 5.6: Note about system voltage level and regulator's dropout requirements added.

Update Tablenote, Section 5.9.3.4, Section 5.9.3.5, Section 5.9.3.6: Battery charging and termination current depends on sense

resistor R_senseor R_SNS

.

•

Update Section 5.9.3.6: Termination current described.

Update Section 5.9.13.1.3: Note for TMREG bit added.

Update Section 5.4.2: The HOLD_WDG_INSLEEP register bit described.

Update Table 4-1: SMPS overshoot changed from max. 10% to max. 100 mV, SMPS1's (3-A mode) DC_LDRupdated.

Update Section 4.5.13: GPADC_VREF output current capability and source resistance specified.

Update Section 4.5.2: LDO1's PSRR updated.

Update Section 4.5.8: System supply regulator's D_MAXspecified.

Update Section 5.9.12: Priority between VBUS and VAC clarified.

Update Table 5-3: Equation for channel 17 added.

Update Figure 1-1, Table 6-1: Capacitor C45 added.

Update : Pullup and pulldown resistors clarified; fixed, programmable, default.

Update Section 5.9.3.1: Note added.

Update Table 4-10: I_{IN_LIMIT}max increased to 2250 mA.

Update Table 4-1: R_Vmeasured with 20-MHz LPF.

Update Section 5.1: Alarm and Timer interrupts clarified.

Update : Ordering information updated.

Update Section 5.9.4: Operation clarified and figure added.

(6) SWCS059E: Update

Update Table 4-10: (System Supply Regulator, PWM) MOSFET on-resistances updated.

•

Update Table 4-10: C_BOOTvalue updated from 10nF to 100nF.

Update Table 5-3: X1 and X2 values updated for channel 10.

Update Table 4-15: GPADC_IN3 current source values updated.

Update Table 5-2: Input voltage performance range updated for channel 8.

Update Table 4-10: Output voltage for full charge mode, typo corrected (VBAT instead of VSYS).

Update Table 4-13: External ID resistances added.

Update Figure 5-29: Figure updated.

Update Section 5.3: Major updates in the chapter.

Update Section 5.4: Some updates in the chapter.

Update Table 4-11: Threshold error and comparator offset updated for Battery Temperature Measurement.

Update Table 4-15: Offset, gain error, INL, GPADC_IN0 current levels updated.

Update Table 4-2: Switching frequency updated.

Update Table 4-11: A range of ΔLIN updated.

Update Section 5.9.12: Figure added, description clarified.

Update Section 5.9.3.1: Figure added, description clarified.

Update Figure 5-24: Figure updated.

Update Figure 5-22: Figure added.

Update: Boot sequence figure removed.

Update: Chapter "Group and Subsystem Groups Power States" removed.

Update Section 5.3.7.3: Shutdown generation added.

(7) SWCS059F: Update

•

Update Table 4-4, Section 5.7.3.2: VBRTC electrical parameters added and control clarified.

Update ⁽⁾: Note for 100 nF capacitor requirement with over 20 kΩ source impedance added.

Update and .

Update Table 4-15: GPADC_VREF output impedance spec removed. GPADC_IN0 current source spec updated.

Update Figure 5-7, Figure 5-8, Figure 5-9, Figure 5-10: Text clarified in the flowcharts.

Update : R_SNSand R_sensereplaced by R2 and R9 for clarification.

Update Section 5.9.6: Description added that system supply regulator operates after watchdog or safety timer expires.

Update Section 5.9.3.1: Caution about resistor R2 usage added.

Update Table 4-11: VBAT_FULLCHRG parameters added.

Update Table 4-17: VSYSMIN_HI and VSYSMIN_LO thresholds added.

Update Section 4.5.8: VBUS and VAC detection thresholds updated.

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SWCS059I –MARCH 2011–REVISED NOVEMBER 2014

VERSION

DATE

NOTES

(8)

G

H

I

08/2012

11/2014

See

.

(9)

.

(10)

.

(8) SWCS059G: Update

•

Update Table 4-4, Section 5.7.3.2: VBRTC electrical parameters added and control clarified.

Update ⁽⁾: Note for 100 nF capacitor requirement with over 20 kΩ source impedance added.

Update and .

Update Table 4-15: GPADC_VREF output impedance spec removed. GPADC_IN0 current source spec updated.

Update Figure 5-7, Figure 5-8, Figure 5-9, Figure 5-10: Text clarified in the flowcharts.

Update : R_SNSand R_sensereplaced by R2 and R9 for clarification.

Update Section 5.9.6: Description added that system supply regulator operates after watchdog or safety timer expires.

Update : Section 5.9.3.1: Caution about resistor R2 usage added.

Update Table 4-11: VBAT_FULLCHRG parameters added.

Update Table 4-17: VSYSMIN_HI and VSYSMIN_LO thresholds added.

Update Section 4.5.8: VBUS and VAC detection thresholds updated.

Update Section 5.11.4: Warning about RC-filtering added.

Update Section 5.9: Note about the terminology of different charging sources added.

(9) SWCS059H: Update

•

Update : Ordering information updated.

Update : ESD Specification updated.

(10) Changed data sheet to standard TI format

8 Mechanical Packaging and Orderable Information

8.1 Packaging Information

The following pages include mechanical packaging and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and

revision of this document.

Mechanical Packaging and Orderable Information

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121

IMPORTANT NOTICE AND DISCLAIMER

TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE

DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”

AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY

IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD

PARTY INTELLECTUAL PROPERTY RIGHTS.

These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate

TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable

standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you

permission to use these resources only for development of an application that uses the TI products described in the resource. Other

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TI’s products are provided subject to TI’s Terms of Sale (www.ti.com/legal/termsofsale.html) or other applicable terms available either on

ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable

warranties or warranty disclaimers for TI products.

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	TPS80032A2FAYFFR
厂家：	TEXAS INSTRUMENTS
描述：	具有电源路径和电池充电器的全集成式电源管理 IC (PMIC) \| YFF \| 155 \| -40 to 85 电池集成电源管理电路
文件：	总124页 (文件大小：1574K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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