TPS82150SILR [TI]
具有集成电感器的 17V 输入 1A 同步降压转换器 MicroSiP™ 模块 | SIL | 8 | -40 to 125;
| 型号： | TPS82150SILR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有集成电感器的 17V 输入 1A 同步降压转换器 MicroSiP™ 模块 | SIL | 8 | -40 to 125 开关 输出元件 电感器 转换器 |
| 文件： | 总27页 (文件大小：908K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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TPS82150
ZHCSGD2 –JUNE 2017
TPS82150 17V 输入、1A 降压转换器 MicroSiP™模块
1 特性
3 说明
1
•
3.0mm x 2.8mm x 1.5mm MicroSiP™封装
输入电压范围：3.0V 至 17V
TPS82150 是一款 17V 输入、1A 降压转换器
MicroSiP™电源模块，经优化兼具小型解决方案尺寸和
高效率优势。该模块集成了同步降压转换器和电感，可
简化设计、减少外部元件数量并节省印刷电路板
(PCB) 的面积。该器件采用紧凑的薄型封装，适合通
过标准表面贴装设备自动组装。
•
•
•
•
•
•
•
•
•
•
•
•
•
1A 持续输出电流
DCS-Control™拓扑技术
在轻负载条件下实现高效率的省电模式
20µA 静态工作电流
0.9V 至 6V 可调节输出电压
可实现最低压降的 100% 占空比
电源正常输出
为了最大限度地提高效率，该转换器以 2.0MHz 的标
称开关频率在脉宽调制 (PWM) 模式下工作，并且会在
轻负载电流条件下自动进入节能工作模式。在节能模式
下，该器件静态工作电流的典型值为 20µA。凭借
DCS-Control™拓扑，器件可获得出色的负载瞬态性能
和精确的输出稳压。
具有跟踪功能的可编程软启动
热关断保护
与 TPS82130 和 TPS82140 引脚对引脚兼容
-40°C 至 125°C 的工作温度范围
空白
使用 TPS82150 并借助 WEBENCH® 电源设计器
创建定制设计方案
器件信息(1)
器件型号
封装
封装尺寸（标称值）
2 应用
TPS82150SIL
µSiL (8)
3.0mm x 2.8mm x 1.5mm
•
•
•
•
工业 应用
(1) 要了解所有可用封装，请见数据表末尾的可订购产品附录。
电信和网络 应用
固态硬盘
逆变电源
空白
空白
典型应用电路原理图
空白空白
效率与输出电流，VIN=12V
空白
100
90
TPS82150
VIN
VOUT
VIN
VOUT
12V
1.8V/1A
C1
10µF
C2
22µF
R1
124k
R3
100k
EN
SS/TR
FB
80
C3
3.3nF
R2
100k
PG
GND
70
POWER GOOD
Copyright © 2017, Texas Instruments Incorporated
VOUT = 1.0 V
VOUT = 1.8 V
60
VOUT = 2.5 V
VOUT = 3.3 V
50
1m
10m
100m
1
Load (A)
D017
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SLVSDN4
TPS82150
ZHCSGD2 –JUNE 2017
www.ti.com.cn
目录
1
2
3
4
5
6
特性.......................................................................... 1
8
9
Application and Implementation ........................ 11
8.1 Application Information............................................ 11
8.2 Typical Applications ................................................ 11
8.3 System Examples ................................................... 17
Power Supply Recommendations...................... 18
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings.............................................................. 4
6.3 Recommend Operating Conditions........................... 4
6.4 Thermal Information.................................................. 4
6.5 Electrical Characteristics.......................................... 5
6.6 Typical Characteristics.............................................. 6
Detailed Description .............................................. 7
7.1 Overview ................................................................... 7
7.2 Functional Block Diagram ......................................... 7
7.3 Feature Description................................................... 8
7.4 Device Functional Modes.......................................... 9
10 Layout................................................................... 18
10.1 Layout Guidelines ................................................. 18
10.2 Layout Example .................................................... 18
10.3 Thermal Consideration.......................................... 19
11 器件和文档支持 ..................................................... 20
11.1 器件支持 ............................................................... 20
11.2 接收文档更新通知 ................................................. 20
11.3 社区资源................................................................ 20
11.4 商标....................................................................... 20
11.5 静电放电警告......................................................... 20
11.6 Glossary................................................................ 20
12 机械、封装和可订购信息....................................... 21
7
4 修订历史记录
日期
修订版本
注意
2017 年 6 月
*
初始发行版。
2
Copyright © 2017, Texas Instruments Incorporated
TPS82150
www.ti.com.cn
ZHCSGD2 –JUNE 2017
5 Pin Configuration and Functions
space
8-Pin µSiL Package
(SIL0008C Top View)
EN
1
2
3
4
8
7
6
5
SS/TR
PG
VIN
GND
FB
VOUT
VOUT
space
Pin Functions
PIN
I/O
DESCRIPTION
NAME
NO.
Enable pin. Pull High to enable the device. Pull Low to disable the device. This pin has an
internal pull-down resistor of typically 400kΩ when the device is disabled.
EN
1
I
VIN
2
3
PWR Input pin.
Ground pin.
GND
VOUT
4,5
PWR Output pin.
Feedback reference pin. An external resistor divider connected to this pin programs the output
voltage.
FB
6
7
8
I
O
I
Power good open drain output pin. A pull-up resistor can be connected to any voltage less than
6V. Leave it open if it is not used.
PG
Soft startup and voltage tracking pin. An external capacitor connected to this pin sets the internal
reference voltage rising time.
SS/TR
The exposed thermal pad must be connected to the GND pin. Must be soldered to achieve
appropriate power dissipation and mechanical reliability.
Exposed Thermal Pad
Copyright © 2017, Texas Instruments Incorporated
3
TPS82150
ZHCSGD2 –JUNE 2017
www.ti.com.cn
6 Specifications
6.1 Absolute Maximum Ratings(1)
MIN
–0.3
–0.3
–0.3
0
MAX
UNIT
VIN
20
EN, SS/TR
Voltage at pins(2)
VIN + 0.3
V
PG, FB
7
VOUT
7
Sink current
PG
10
125
125
mA
°C
Module operating temperature
Storage temperature
–40
–55
°C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to network ground pin.
6.2 ESD Ratings
VALUE
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
±2000
V(ESD)
Electrostatic discharge
V
Charged device model (CDM), per JEDEC specification JESD22-
C101(2)
±1000
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommend Operating Conditions
MIN
MAX
UNIT
VIN
Input voltage
3
17
6
V
V
VPG
VOUT
IOUT
TJ
Power good pull-up resistor voltage
Output voltage
0.9
0
6
V
Output current
1
A
Module operating temperature range for 100,000 hours lifetime(1)
–40
110
°C
(1) The module operating temperature range includes module self temperature rise and IC junction temperature rise. In applications where
high power dissipation is present, the maximum operating temperature or maximum output current must be derated. For applications
where the module operates continuously at 125 °C temperature, the maximum lifetime is reduced to 50,000 hours.
6.4 Thermal Information
TPS82150
THERMAL METRIC(1)
8-Pin SIL
JEDEC 51-5
UNIT
EVM
46.1
9.4
RθJA
Junction-to-ambient thermal resistance
58.2
9.4
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top) Junction-to-case (top) thermal resistance
RθJB
ψJT
Junction-to-board thermal resistance
14.4
0.9
14.4
0.9
Junction-to-top characterization parameter
Junction-to-board characterization parameter
ψJB
14.2
21.3
14.0
21.3
RθJC(bot) Junction-to-case (bottom) thermal resistance
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
Theta-JA can be improved with a custom PCB design containing thermal vias where possible.
4
Copyright © 2017, Texas Instruments Incorporated
TPS82150
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ZHCSGD2 –JUNE 2017
6.5 Electrical Characteristics
TJ = -40°C to 125°C and VIN = 3.0V to 17V. Typical values are at TJ = 25°C and VIN = 12V, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP MAX UNIT
SUPPLY
IQ
Quiescent current into VIN
Shutdown current into VIN
No load, device not switching
20
1.5
35
7.4
2.8
3.0
µA
µA
V
ISD
EN = Low
VIN falling
VIN rising
TJ rising
2.6
2.8
2.7
VUVLO
Under voltage lock out threshold
Thermal shutdown threshold
2.9
V
160
140
°C
°C
TJSD
TJ falling
LOGIC INTERFACE (EN)
VIH
High-level input voltage
0.9
0.65
0.45
0.01
V
V
VIL
Low-level input voltage
0.3
1
Ilkg(EN)
Input leakage current into EN pin
EN = High
µA
CONTROL (SS/TR, PG)
ISS/TR SS/TR pin source current
2.1
92%
87%
2.5
2.8
µA
VOUT rising, referenced to VOUT nominal
VOUT falling, referenced to VOUT nominal
Isink = 2mA
95% 99%
90% 94%
VPG
Power good threshold
VPG,OL
Power good low-level voltage
0.1
1
0.3
V
Ilkg(PG)
Input leakage current into PG pin
VPG = 1.8V
400
nA
OUTPUT
785
788
785
788
800 815
800 812
800 823
800 815
PWM mode
TJ = 0°C to 85°C
VFB
Feedback regulation voltage
mV
COUT = 22µF
PSM
COUT = 2x22µF, TJ = 0°C to 85°C
Ilkg(FB)
Feedback input leakage current
Line regulation
VFB = 0.8V
1
0.002
0.12
100
nA
IOUT = 1A, VOUT = 1.8V
IOUT = 0.5A to 1A, VOUT = 1.8V
%/V
%/A
Load regulation
POWER SWITCH
ISW = 500mA, VIN ≥ 6V
ISW = 500mA, VIN = 3V
ISW = 500mA, VIN ≥ 6V
ISW = 500mA, VIN = 3V
100% mode, VIN ≥ 6V
100% mode, VIN = 3V
90 170
120
40
High-side FET on-resistance
RDS(on)
mΩ
mΩ
70
Low-side FET on-resistance
Dropout resistance
50
125
160
2.2
RDP
ILIMF
fSW
High-side FET switch current limit VIN = 6V, TJ = 25°C
PWM switching frequency IOUT = 1A, VOUT = 1.8V
1.7
2.7
A
2.0
MHz
版权 © 2017, Texas Instruments Incorporated
5
TPS82150
ZHCSGD2 –JUNE 2017
www.ti.com.cn
6.6 Typical Characteristics
50
40
30
20
10
0
250
TJ = -40°C
TJ = 25°C
TJ = 85°C
TJ = 125°C
200
150
100
50
VIN = 3.0 V
VIN = 6.0 V
3
5
7
9
11
13
15
17
-40
-20
0
20
40
60
80
100
120
Input Voltage (V)
Module Temperature (°C)
D025
D014
图 2. Quiescent Current
图 1. Dropout Resistance
8
TJ = -40°C
TJ = 25°C
TJ = 85°C
TJ = 125°C
6
4
2
0
3
5
7
9
11
13
15
17
Input Voltage (V)
D026
图 3. Shutdown Current
6
版权 © 2017, Texas Instruments Incorporated
TPS82150
www.ti.com.cn
ZHCSGD2 –JUNE 2017
7 Detailed Description
7.1 Overview
The TPS82150 synchronous step-down converter MicroSiP™ power module is based on DCS-Control™ (Direct
Control with Seamless transition into Power Save Mode). This is an advanced regulation topology that combines
the advantages of hysteretic and voltage mode control.
The DCS-Control™ topology operates in PWM (Pulse Width Modulation) mode for medium to heavy load
conditions and in PSM (Power Save Mode) at light load currents. In PWM mode, the converter operates with its
nominal switching frequency of 2.0 MHz having a controlled frequency variation over the input voltage range. As
the load current decreases, the converter enters Power Save Mode, reducing the switching frequency and
minimizing the IC's quiescent current to achieve high efficiency over the entire load current range. DCS-Control™
supports both operation modes using a single building block and therefore has a seamless transition from PWM
to PSM without effects on the output voltage. The TPS82150 offers excellent DC voltage regulation and load
transient regulation, combined with low output voltage ripple, minimizing interference with RF circuits.
7.2 Functional Block Diagram
space
space
PG
VIN
VFB
High Side
Current Sense
VREF
Bandgap
Undervoltage Lockout
Thermal Shutdown
EN
L(2)
400kΩ(1)
MOSFET Driver
Control Logic
VIN
Ramp
Direct Control
and
Compensation
VOUT
Voltage
Clamp
VREF
SS/TR
22pF
Timer
ton
FB
Comparator
VREF
Error Amplifier
DCS - Control TM
GND
Note:
(1) When the device is enabled, the 400 kΩ resistor is disconnected.
(2) The integrated inductor of 1 µH in the module.
Copyright © 2016, Texas Instruments Incorporated
space
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7
TPS82150
ZHCSGD2 –JUNE 2017
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7.3 Feature Description
7.3.1 PWM and PSM Operation
The TPS82150 includes an on-time (tON) circuitry. This tON, in steady-state operation in PWM and PSM modes, is
estimated as:
space
VOUT
tON = 500ns´
V
IN
(1)
space
In PWM mode, the TPS82150 operates with pulse width modulation in continuous conduction mode (CCM) with
a tON shown in 公式 1 at medium and heavy load currents. A PWM switching frequency of typically 2.0MHz is
achieved by this tON circuitry. The device operates in PWM mode as long as the output current is higher than half
the inductor's ripple current estimated by 公式 2.
space
VIN - VOUT
DIL = tON
´
L
(2)
space
To maintain high efficiency at light loads, the device enters Power Save Mode seamlessly when the load current
decreases. This happens when the load current becomes smaller than half the inductor's ripple current. In PSM,
the converter operates with reduced switching frequency and with a minimum quiescent current to maintain high
efficiency. PSM is also based on the tON circuitry. The switching frequency in PSM is estimated as:
space
2´IOUT
fPSM
=
V
VIN - VOUT
2
IN
´
tON
´
VOUT
L
(3)
space
In PSM, the output voltage rises slightly above the nominal output voltage in PWM mode. This effect is reduced
by increasing the output capacitance. The output voltage accuracy in PSM operation is reflected in the electrical
specification table and given for a 22-µF output capacitor.
For very small output voltages, an absolute minimum on-time of about 80ns is kept to limit switching losses. The
operating frequency is thereby reduced from its nominal value, which keeps efficiency high. Also the off-time can
reach its minimum value at high duty cycles. The output voltage remains regulated in such cases.
When VIN decreases to typically 15% above VOUT, the TPS82150 can't enter Power Save Mode, regardless of
the load current. The device maintains output regulation in PWM mode.
7.3.2 Low Dropout Operation (100% Duty Cycle)
The TPS82150 offers a low input to output voltage differential by entering 100% duty cycle mode. In this mode,
the high-side MOSFET switch is constantly turned on. This is particularly useful in battery powered applications
to achieve longest operation time by taking full advantage of the whole battery voltage range. The minimum input
voltage to maintain a minimum output voltage is given by:
space
V
= VOUT(min) + IOUT ´RDP
IN(min)
(4)
space
Where
RDP = Resistance from VIN to VOUT, including high-side FET on-resistance and DC resistance of the inductor
VOUT(min) = Minimum output voltage the load can accept.
8
版权 © 2017, Texas Instruments Incorporated
TPS82150
www.ti.com.cn
ZHCSGD2 –JUNE 2017
Feature Description (接下页)
7.3.3 Switch Current Limit
The switch current limit prevents the device from high inductor current and from drawing excessive current from
the battery or input voltage rail. Excessive current might occur with a heavy load/shorted output circuit condition.
If the inductor peak current reaches the switch current limit after a propagation delay of typically 30ns, the high-
side FET is turned off and the low-side FET is turned on to ramp down the inductor current.
7.3.4 Undervoltage Lockout
To avoid mis-operation of the device at low input voltages, an under voltage lockout is implemented, which shuts
down the devices at voltages lower than VUVLO with a hysteresis of 200mV.
7.3.5 Thermal Shutdown
The device goes into thermal shutdown and stops switching once the junction temperature exceeds TJSD. Once
the device temperature falls below the threshold by 20°C, the device returns to normal operation automatically.
7.4 Device Functional Modes
7.4.1 Enable and Disable (EN)
The device is enabled by setting the EN pin to a logic High. Accordingly, the shutdown mode is forced if the EN
pin is pulled Low with a shutdown current of typically 1.5 μA.
An internal pull-down resistor of 400kΩ is connected to the EN pin when the EN pin is Low. The pull-down
resistor is disconnected when the EN pin is High.
7.4.2 Soft Startup (SS/TR)
The internal voltage clamp controls the output voltage slope during startup. This avoids excessive inrush current
and ensures a controlled output voltage rise time. When the EN pin is pulled high, the device starts switching
after a delay of typically 55μs and the output voltage rises with a slope controlled by an external capacitor
connected to the SS/TR pin. Using a very small capacitor or leaving the SS/TR pin floating provides fastest
startup time.
The TPS82150 is able to start into a pre-biased output capacitor. During the pre-biased startup, both the power
MOSFETs are not allowed to turn on until the internal voltage clamp sets an output voltage above the pre-bias
voltage.
When the device is in shutdown, undervoltage lockout or thermal shutdown, the capacitor connected to SS/TR
pin is discharged by an internal resistor. Returning from those states causes a new startup sequence.
7.4.3 Voltage Tracking (SS/TR)
The SS/TR pin is externally driven by another voltage source to achieve output voltage tracking. The application
circuit is shown in 图 4.
VOUT1
VOUT2
TPS82150
R1
R3
SS/TR
FB
R2
R4
图 4. Output Voltage Tracking
版权 © 2017, Texas Instruments Incorporated
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TPS82150
ZHCSGD2 –JUNE 2017
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Device Functional Modes (接下页)
When the SS/TR pin voltage is between 50 mV and 1.2 V, the VOUT2 tracks the VOUT1 as described in 公式 5.
space
VOUT2
R2
R3 + R4
» 0.64 ´
´
VOUT1
space
R1+ R2
R4
(5)
When the SS/TR pin voltage is above 1.2 V, the voltage tracking is disabled and the FB pin voltage is regulated
at 0.8 V. For decreasing SS/TR pin voltage, the device doesn't sink current from the output. So the resulting
decreases of the output voltage may be slower than the SS/TR pin voltage if the load is light. When driving the
SS/TR pin with an external voltage, do not exceed the voltage rating of the SS/TR pin which is VIN+0.3V.
Details about tracking and sequencing circuits are found in SLVA470.
7.4.4 Power Good Output (PG)
The device has a power good (PG) output. The PG pin goes high impedance once the output is above 95% of
the nominal voltage, and is driven low once the output voltage falls below typically 90% of the nominal voltage.
The PG pin is an open drain output and is specified to sink up to 2mA. The power good output requires a pull-up
resistor connecting to any voltage rail less than 6V.
The PG pin goes low when the device is in shutdown or thermal shutdown. When the device is in UVLO, the PG
pin is high impedance. The PG signal can be used for sequencing of multiple rails by connecting it to the EN pin
of other converters. Leave the PG pin floating when it is not used. 表 1 shows the PG pin logic.
表 1. Power Good Pin Logic
PG Logic Status
Device State
High Impedance
Low
V
FB ≥ VTH_PG
FB ≤ VTH_PG
√
Enable (EN=High)
V
√
√
√
√
Shutdown (EN=Low)
UVLO
0.7 V < VIN < VUVLO
TJ > TSD
Thermal Shutdown
Power Supply Removal
VIN < 0.7 V
√
10
版权 © 2017, Texas Instruments Incorporated
TPS82150
www.ti.com.cn
ZHCSGD2 –JUNE 2017
8 Application and Implementation
注
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The output voltage of the TPS82150 is adjusted by component selection. The following section discusses the
design of the external components to complete the power supply design for several input and output voltage
options by using typical applications as a reference.
8.2 Typical Applications
8.2.1 1.8-V Output Application
space
TPS82150
VIN
VOUT
VIN
VOUT
12 V
1.8 V/1 A
C1
10µF
C2
22µF
R1
R3
124kΩ 100kΩ
EN
SS/TR
FB
C3
3.3nF
R2
100kΩ
PG
GND
POWER GOOD
Copyright © 2016, Texas Instruments Incorporated
图 5. 1.8-V Output Application
space
8.2.1.1 Design Requirements
For this design example, use the following as the input parameters.
表 2. Design Parameters
DESIGN PARAMETER
EXAMPLE VALUE
Input voltage range
Output voltage
12V
1.8V
< 20mV
1A
Output ripple voltage
Output current rating
The components used for measurements are given in the following table.
表 3. List of Components
REFERENCE
C1
DESCRIPTION(1)
MANUFACTURER
10 µF, 25 V, X7R, ±20%, size 1206, C3216X7R1E106M160AE
22 µF, 10 V, X7S, ±20%, size 0805, C2012X7S1A226M125AC
TDK
TDK
C2
3300 pF, 50 V, ±5%, C0G/NP0, size 0603,
GRM1885C1H332JA01D
C3
Murata
R1, R2, R3
Standard
(1) See Third-party Products Disclaimer
版权 © 2017, Texas Instruments Incorporated
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ZHCSGD2 –JUNE 2017
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8.2.1.2 Detailed Design Procedure
8.2.1.2.1 Custom Design with WEBENCH® Tools
Click here to create a custom design using the TPS82150 device with the WEBENCH® Power Designer.
1. Start by entering your VIN, VOUT, and IOUT requirements.
2. Optimize your design for key parameters like efficiency, footprint and cost using the optimizer dial and
compare this design with other possible solutions from Texas Instruments.
3. The WEBENCH Power Designer provides you with a customized schematic along with a list of materials with
real time pricing and component availability.
4. In most cases, you will also be able to:
–
–
–
–
Run electrical simulations to see important waveforms and circuit performance
Run thermal simulations to understand the thermal performance of your board
Export your customized schematic and layout into popular CAD formats
Print PDF reports for the design, and share your design with colleagues
5. Get more information about WEBENCH tools at www.ti.com/WEBENCH.
8.2.1.2.2 Setting the Output Voltage
The output voltage is set by an external resistor divider according to the following equations:
space
R1
R1
æ
ö
æ
ö
VOUT = VFB
´
1 +
= 0.8 V ´ 1 +
ç
÷
ç
÷
R2
R2
è
ø
è
ø
(6)
space
R2 should not be higher than 100kΩ to achieve high efficiency at light load while providing acceptable noise
sensitivity. Larger currents through R2 improve noise sensitivity and output voltage accuracy. 图 5 shows the
external resistor divider value for a 1.8-V output. Choose appropriate resistor values for other outputs.
In case the FB pin gets opened, the device clamps the output voltage at the VOUT pin internally to about 7V.
8.2.1.2.3 Input and Output Capacitor Selection
For best output and input voltage filtering, low ESR ceramic capacitors are required. The input capacitor
minimizes input voltage ripple, suppresses input voltage spikes and provides a stable system rail for the device.
A 10-µF or larger input capacitor is required. The output capacitor value can range from 22μF up to more than
400μF. Higher values are possible as well and can be evaluated through the transient response. Larger soft start
times are recommended for higher output capacitances.
High capacitance ceramic capacitors have a DC Bias effect, which will have a strong influence on the final
effective capacitance. Therefore the right capacitor value has to be chosen carefully. Package size and voltage
rating in combination with dielectric material are responsible for differences between the rated capacitor value
and the effective capacitance.
8.2.1.2.4 Soft Startup Capacitor Selection
A capacitance connected between the SS/TR pin and the GND allows programming the startup slope of the
output voltage. A constant current of 2.5 μA charges the external capacitor. The capacitance required for a given
soft startup time for the output voltage is given by:
space
ISS/ TR
CSS/ TR = tSS/ TR
´
1.25V
(7)
12
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TPS82150
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ZHCSGD2 –JUNE 2017
8.2.1.3 Application Performance Curves
TA = 25°C, VIN = 12 V, VOUT = 1.8 V, unless otherwise noted.
100
90
100
90
80
70
60
50
80
70
60
VIN = 3.3 V
VIN = 5.0 V
VIN = 12 V
IOUT = 0.1 A
IOUT = 1.0 A
50
1m
10m
100m
1
3
5
7
9
11
13
15
17
Load (A)
Input Voltage (V)
D001
D019
图 6. Efficiency, VOUT = 1.0 V
图 7. Efficiency, VOUT = 1.0 V
100
100
90
80
70
60
50
90
80
70
60
50
VIN = 3.3 V
VIN = 5.0 V
VIN = 12 V
IOUT = 0.1 A
IOUT = 1.0 A
1m
10m
100m
1
3
5
7
9
11
13
15
17
Load (A)
Input Voltage (V)
D002
D020
图 8. Efficiency, VOUT = 1.8 V
图 9. Efficiency, VOUT = 1.8 V
100
90
80
70
60
50
100
90
80
70
60
50
VIN = 3.3 V
VIN = 5.0 V
VIN = 12 V
IOUT = 0.1 A
IOUT = 1.0 A
1m
10m
100m
1
3
5
7
9
11
13
15
17
Load (A)
Input Voltage (V)
D003
D021
图 10. Efficiency, VOUT = 2.5 V
图 11. Efficiency, VOUT = 2.5 V
版权 © 2017, Texas Instruments Incorporated
13
TPS82150
ZHCSGD2 –JUNE 2017
www.ti.com.cn
100
90
80
70
60
100
90
80
70
60
50
VIN = 5.0 V
VIN = 12 V
IOUT = 0.1 A
IOUT = 1.0 A
50
1m
10m
100m
1
5
7
9
11
13
15
17
Load (A)
Input Voltage (V)
D004
D022
图 12. Efficiency, VOUT = 3.3 V
图 13. Efficiency, VOUT = 3.3 V
100
90
80
70
60
100
90
80
70
60
50
IOUT = 0.1 A
IOUT = 1.0 A
VIN = 12 V
50
1m
10m
100m
1
6
7
8
9
10 11 12 13 14 15 16 17
Input Voltage (V)
Load (A)
D023
D024
图 14. Efficiency, VOUT = 5.0 V
图 15. Efficiency, VOUT = 5.0 V
1.5
1
1.5
1
0.5
0.5
VIN = 3.3 V
VIN = 5.0 V
VIN = 12 V
VIN = 3.3 V
VIN = 5.0 V
VIN = 12 V
0
0
45
55
65
75
85
95
105
115
125
45
55
65
75
85
95
105
115
125
Ambient Temperature (°C)
Ambient Temperature (°C)
D002
D001
θJA = 46.1 °C/W
θJA = 46.1 °C/W
图 17. Thermal Derating, VOUT = 1.8 V
图 16. Thermal Derating, VOUT = 1 V
14
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TPS82150
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ZHCSGD2 –JUNE 2017
1.5
1.5
1
1
0.5
0.5
VIN = 5.0V
VIN = 12 V
VIN = 8.4 V
VIN = 12 V
0
0
45
55
65
75
85
95
105
115
125
45
55
65
75
85
95
105
115
125
Ambient Temperature (°C)
Ambient Temperature (°C)
D003
D003
θJA = 46.1 °C/W
θJA = 46.1 °C/W
图 18. Thermal Derating, VOUT = 3.3 V
图 19. Thermal Derating, VOUT = 5 V
1.0
0.5
1.0
0.5
0.0
0.0
-0.5
-0.5
TA = -40°C
TA = 25°C
TA = 85°C
TA = -40°C
TA = 25°C
TA = 85°C
-1.0
1m
-1.0
10m
100m
1
5
3
5
7
9
11
13
15
17
Load (A)
Input Voltage (V)
D005
D006
IOUT = 1A
图 20. Load Regulation
图 21. Line Regulation
5x106
3x106
2x106
1x106
5x105
2x106
1x106
2x105
1x105
5x104
2x104
1x104
5x103
VOUT = 1.0 V
VOUT = 1.8 V
VOUT = 2.5 V
VOUT = 3.3 V
TA = 25°C
TA = -40°C
TA = 85°C
2x103
1x103
0x100
3
1m
10m
100m
1
5
5
7
9
11
13
15
17
Load (A)
Input Voltage (V)
D009
D018
VOUT = 1.8V
IOUT = 1A
图 22. Switching Frequency
图 23. Switching Frequency
版权 © 2017, Texas Instruments Incorporated
15
TPS82150
ZHCSGD2 –JUNE 2017
www.ti.com.cn
No Load
IOUT = 1A
图 25. Input and Output Ripple in PSM Mode
图 24. Input and Output Ripple in PWM Mode
IOUT = 0.5A to 1A,
1A/µs
IOUT = 0A to 1A,
1A/µs
图 27. Load Transient
图 26. Load Transient
No Load
ROUT = 1.8Ω
图 28. Startup without Load
图 29. Startup / Shutdown with Resistance Load
16
版权 © 2017, Texas Instruments Incorporated
TPS82150
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ZHCSGD2 –JUNE 2017
8.3 System Examples
8.3.1 Inverting Power Supply
The TPS82150 can be used as inverting power supply by rearranging external circuitry as shown in 图 30. As the
former GND node now represents a voltage level below system ground, the voltage difference between VIN and
VOUT has to be limited for operation to the maximum supply voltage of 17V (see 公式 8).
space
V + VOUT £ V
IN
INmax
(8)
space
space
VIN
VIN
EN
VOUT
PG
R3
TPS82150
R1
R2
CIN
COUT
FB
SS/TR
GND
CSS
- VOUT
Copyright © 2017, Texas Instruments Incorporated
图 30. Inverting Power Supply Schematic
space
The transfer function of the inverting power supply configuration differs from the buck mode transfer function,
incorporating a Right Half Plane Zero additionally. Therefore the loop stability has to be adapted. More detailed
information is given in TIDUCV2.
版权 © 2017, Texas Instruments Incorporated
17
TPS82150
ZHCSGD2 –JUNE 2017
www.ti.com.cn
9 Power Supply Recommendations
The devices are designed to operate from an input voltage supply range between 3V and 17V. The average
input current of the TPS82150 is calculated as:
space
VOUT ´IOUT
1
IIN
=
´
h
V
IN
(9)
space
Ensure that the power supply has a sufficient current rating for the applications.
10 Layout
10.1 Layout Guidelines
•
TI recommends placing all components as close as possible to the IC. The input capacitor placement
specifically, must be closest to the VIN and GND pins of the device.
•
•
Use wide and short traces for the main current paths to reduce the parasitic inductance and resistance.
To enhance heat dissipation of the device, the exposed thermal pad should be connected to bottom or
internal layer ground planes using vias.
•
Refer to 图 31 for an example of component placement, routing and thermal design.
10.2 Layout Example
space
space
C3
VIN
C1
R2
R1
SS/TR
PG
EN
VIN
GND
VOUT
FB
VOUT
VOUT
GND
C2
图 31. TPS82150 PCB Layout
18
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TPS82150
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ZHCSGD2 –JUNE 2017
10.3 Thermal Consideration
The output current of the TPS82150 needs to be derated when the device operates in a high ambient
temperature or delivers high output power. The amount of current derating is dependent upon the input voltage,
output power, PCB layout design and environmental thermal condition. Care should especially be taken in
applications where the localized PCB temperature exceeds 65°C.
The TPS82150 module temperature must be kept less than the maximum rating of 125°C. Three basic
approaches for enhancing thermal performance are below:
•
•
•
Improve the power dissipation capability of the PCB design.
Improve the thermal coupling of the TPS82150 to the PCB.
Introduce airflow into the system.
To estimate approximate module temperature of TPS82150, apply the typical efficiency stated in this datasheet
to the desired application condition to find the module's power dissipation. Then calculate the module
temperature rise by multiplying the power dissipation by its thermal resistance. For more details on how to use
the thermal parameters in real applications, see the application notes: SZZA017 and SPRA953.
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19
TPS82150
ZHCSGD2 –JUNE 2017
www.ti.com.cn
11 器件和文档支持
11.1 器件支持
11.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
11.1.2 开发支持
11.1.2.1 使用 WEBENCH® 工具定制设计方案
单击此处，使用 TPS82150 器件并借助 WEBENCH® 电源设计器创建定制设计方案。
1. 在开始阶段键入输入电压 (VIN)、输出电压 (VOUT) 和输出电流 (IOUT) 要求。
2. 使用优化器拨盘优化关键设计参数，如效率、封装和成本。
3. 将生成的设计与德州仪器 (TI) 的其他解决方案进行比较。
WEBENCH Power Designer 提供一份定制原理图以及罗列实时价格和组件可用性的物料清单。
在多数情况下，可执行以下操作：
•
•
•
•
运行电气仿真，观察重要波形以及电路性能
运行热性能仿真，了解电路板热性能
将定制原理图和布局方案导出至常用 CAD 格式
打印设计方案的 PDF 报告并与同事共享
有关 WEBENCH 工具的详细信息，请访问 www.ti.com/WEBENCH。
11.2 接收文档更新通知
要接收文档更新通知，请导航至 TI.com 上的器件产品文件夹。请单击右上角的通知我 进行注册，即可收到任意产
品信息更改每周摘要。有关更改的详细信息，请查看任意已修订文档中包含的修订历史记录。
11.3 社区资源
下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，
并且不一定反映 TI 的观点；请参阅 TI 的 《使用条款》。
TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在
e2e.ti.com 中，您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。
设计支持
TI 参考设计支持 可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。
11.4 商标
MicroSiP, DCS-Control, E2E are trademarks of Texas Instruments.
WEBENCH is a registered trademark of Texas Instruments.
11.5 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损
伤。
11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
20
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TPS82150
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ZHCSGD2 –JUNE 2017
12 机械、封装和可订购信息
以下页面包括机械、封装和可订购信息。这些信息是指定器件的最新可用数据。这些数据发生变化时，我们可能不
会另行通知或修订此文档。如欲获取此产品说明书的浏览器版本，请参见左侧的导航栏。
Copyright © 2017, Texas Instruments Incorporated
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TPS82150
ZHCSGD2 –JUNE 2017
www.ti.com.cn
PACKAGE OUTLINE
SIL0008D
MicroSiPTM - 1.53 mm max height
S
C
A
L
E
4
.
0
0
0
MICRO SYSTEM IN PACKAGE
2.9
2.7
A
B
PIN 1 INDEX
AREA
(2.5)
3.1
2.9
PICK AREA
NOTE 3
(2)
1.53 MAX
C
0.08 C
1.1 0.1
SYMM
EXPOSED
THERMAL PAD
(0.1)
TYP
5
4
SYMM
2X
1.9 0.1
1.95
1
8
0.42
0.38
6X 0.65
8X
(45 X0.25)
PIN 1 ID
0.1
C A
C
B
0.05
0.52
0.48
8X
4221520/A 07/2015
MicroSiP is a trademark of Texas Instruments
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Pick and place nozzle 1.3 mm or smaller recommended.
4. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
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Copyright © 2017, Texas Instruments Incorporated
TPS82150
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ZHCSGD2 –JUNE 2017
EXAMPLE BOARD LAYOUT
SIL0008D
MicroSiP TM - 1.53 mm max height
MICRO SYSTEM IN PACKAGE
(1.1)
8X (0.5)
8
1
8X (0.4)
SYMM
(1.9)
(0.75)
6X (0.65)
5
4
SYMM
(2.1)
(
0.2) VIA
TYP
LAND PATTERN EXAMPLE
SOLDER MASK DEFINED
SCALE:20X
0.05 MIN
ALL SIDES
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
(R0.05) TYP
DETAIL
NOT TO SCALE
4221520/A 07/2015
NOTES: (continued)
5. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
www.ti.com
Copyright © 2017, Texas Instruments Incorporated
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TPS82150
ZHCSGD2 –JUNE 2017
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EXAMPLE STENCIL DESIGN
SIL0008D
MicroSiP TM - 1.53 mm max height
MICRO SYSTEM IN PACKAGE
SOLDER MASK EDGE
(R0.05) TYP
8X (0.5)
8X (0.4)
1
(1.04)
8
METAL
TYP
(0.85)
SYMM
(1.05)
6X (0.65)
5
4
SYMM
(2.1)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD
85% PRINTED SOLDER COVERAGE BY AREA
SCALE:30X
4221520/A 07/2015
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
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版权 © 2017, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
1-Sep-2021
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPS82150SILR
TPS82150SILT
ACTIVE
ACTIVE
uSiP
uSiP
SIL
SIL
8
8
3000 RoHS & Green
250 RoHS & Green
NIAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 125
-40 to 125
5S
5S
NIAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
1-Sep-2021
Addendum-Page 2
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