TPS82740B [TI]

具有 360nA Iq 的 200mA 降压转换器模块;


型号：	TPS82740B
厂家：	TEXAS INSTRUMENTS
描述：	具有 360nA Iq 的 200mA 降压转换器模块转换器
文件：	总29页 (文件大小：2649K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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TPS82740A, TPS82740B

ZHCSCJ5A –JUNE 2014–REVISED JUNE 2014

TPS82740x 360nA I_QMicroSIP^TM降压转换器模块，用于低功率应用

1 特性

这款全新的基于 DCS-Control™ 的器件将轻负载效率

范围拓展至 10µA 负载电流以下。它支持高达 200mA

的输出电流。

•

360nA 静态电流典型值

•

10µA 输出电流时的效率高达 90%

引脚可选输出电压，步长 100mV

集成转换率受控负载开关

此器件由可再充电锂离子电池，锂化学电池（例如锂亚

硫酰氯 (Li-SOC12)，锂锰电池 (Li-MnO2)）和两节或

三节碱性电池供电运行。输入电压范围高达 5.5V，也

可实现由 1 个 USB 端口和薄膜太阳能模块供电运行。

高达 200mA 输出电流

2.2V 至 5.5V 的输入电压范围 V_IN

射频 (RF) 友好型 DCS-Control™

低输出电压纹波

用户可通过三个电压选择引脚 (VSEL) 在 1.8V 至 2.5V

(TPS82740A) 和 2.6V 至 3.3V (TPS82740B) 的范围

内以 100mV 的步长选择输出电压。 TPS82740 特有

低输出电压纹波和低噪声。一旦电池电压接近输出电

压（接近 100% 占空比），此器件进入无纹波 100%

模式运行，以防止增加输出电压纹波。在这个情况

下，此器件停止开关，并且输出被连接至输入电压。

自动转换至无纹波 100% 模式

VOUT 和 LOAD 上的放电功能

高度不到 1.1mm 的解决方案

总体解决方案尺寸 < 6.7mm²

小型 2.3mm x 2.9mm MicroSIP™ 封装

2 应用范围

集成的转换率受控负载开关（具有 0.6Ω 的导通电阻典

型值）将已选输出电压配送至一个临时使用的子系统。

•

Bluetooth^®低功耗 (Low Energy)，消费类电子产品

用射频 (RF4CE)，短距低功耗通信协议 (Zigbee)

TPS82740 采用小型 9 焊锡凸点 6.7mm²MicroSiP^TM

封装。

•

可穿戴电子产品

能量采集

器件信息⁽¹⁾

3 说明

产品型号

TPS82740A

TPS82740B

封装

封装尺寸（标称值）

2.30mm x 2.90mm

TPS82740 是业界第一款降压转换器模块，此模块特

有典型值为 360nA 的静态流耗。它是一款用于超低功

率应用的完整 MicroSIP^TM直流/直流降压电源解决方

案。此模块包括开关稳压器、电感器和输入/输出电容

器。将所有需要的无源组件集成在一起可实现仅为

6.7mm²的微型解决方案尺寸。

µSIP

(1) 要了解所有可用封装，请见数据表末尾的可订购产品附录。

4 典型应用

TPS82740

DC/DC Converter

2.2 V to 5.5 V

TPS82740B

OUT

up to 200mA

VIN

C_OUT

C_IN

VOUT

GND

TPS82740 extends

light load efficiency range

down to 10mA output current

Switched Supply

R_ON= 0.6Ω

ENABLE

VSEL1

LOAD

CTRL

VSEL1

VSEL2

VSEL3

VSEL2

VSEL3

Control for

Switched

Supply Rail

Current

DCS-Control^TMtopology

GND

V_IN= 3.6V

V_OUT= 3.3V

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

English Data Sheet: SLVSCE3

TPS82740A, TPS82740B

ZHCSCJ5A –JUNE 2014–REVISED JUNE 2014

www.ti.com.cn

10.2 Functional Block Diagram ..................................... 15

10.3 Feature Description............................................... 15

10.4 Device Functional Modes...................................... 17

11 Application and Implementation........................ 19

11.1 Application Information.......................................... 19

11.2 Typical Application ............................................... 19

12 Power Supply Recommendations ..................... 22

13 Layout................................................................... 22

13.1 Layout Guidelines ................................................. 22

13.2 Layout Example .................................................... 22

13.3 Surface Mount Information.................................... 23

14 器件和文档支持 ..................................................... 24

14.1 文档支持 ............................................................... 24

14.2 商标....................................................................... 24

14.3 静电放电警告......................................................... 24

14.4 术语表 ................................................................... 24

15 机械封装和可订购信息 .......................................... 24

特性.......................................................................... 1

应用范围................................................................... 1

说明.......................................................................... 1

典型应用................................................................... 1

修订历史记录 ........................................................... 2

Device Comparison Table..................................... 3

Pin Configuration and Functions......................... 3

Specifications......................................................... 4

8.1 Absolute Maximum Ratings ..................................... 4

8.2 Handling Ratings ...................................................... 4

8.3 Recommended Operating Conditions...................... 4

8.4 Thermal Information.................................................. 5

8.5 Electrical Characteristics.......................................... 5

8.6 Typical Characteristics.............................................. 6

Parameter Measurement Information ................ 14

10 Detailed Description ........................................... 15

10.1 Overview ............................................................... 15

5 修订历史记录

Changes from Original (June 2014) to Revision A

Page

•

Added 150 mA Typical current specification for I_{LIM_softstart}, Low side MOSFET switch current limit...................................... 6

TPS82740A, TPS82740B

www.ti.com.cn

ZHCSCJ5A –JUNE 2014–REVISED JUNE 2014

6 Device Comparison Table

PACKAGE

MARKING

OUTPUT VOLTAGE SETTINGS

(VSEL1, VSEL2, VSEL3)

PART NUMBER

TPS82740A

TPS82740B

1.8V to 2.5V in 100mV steps

2.6V to 3.3V in 100mV steps

7 Pin Configuration and Functions

MicroSIP™

9 Bump

(TOP VIEW)

VSEL2

(BOTTOM VIEW)

VSEL2

VSEL3

LOAD

VOUT

VSEL1

VSEL3

LOAD

VOUT

VIN

GND

CTRL

CTRL GND

Table 1. Pin Functions

I/O

DESCRIPTION

NAME

VIN

Input voltage supply pin of the module.

Ground terminal.

GND

CTRL

CTRL pin controls the LOAD output pin. With CTRL = low, the LOAD output is disabled. This pin must be

terminated and not left floating.

VOUT

LOAD

OUT

Output voltage pin of the module. An internal load switch is connected between VOUT pin and LOAD pin.

Load switch output pin controlled by the CTRL pin. With CTRL = high, an internal load switch connects the

LOAD pin to the VOUT pin. The LOAD pin allows connect / disconnect other system components to the

output of the DC/DC converter. This pin is pulled to GND with the CTRL pin = low. The LOAD pin features

soft switching. If not used, leave the pin open.

VSEL3

VSEL2

VSEL1

Output voltage selection pins. See Table 2 and Table 3 for V_OUTselection. These pins must be terminated

and can be changed during operation.

High level enables the devices and low level turns the device into shutdown mode. This pin must be

terminated and not left floating.

Table 2. Output Voltage Setting TPS82740A

Device

VOUT

1.8

VSEL3

VSEL2

VSEL1

1.9

2.0

2.1

TPS82740A

2.2

2.3

2.4

2.5

TPS82740A, TPS82740B

ZHCSCJ5A –JUNE 2014–REVISED JUNE 2014

www.ti.com.cn

Table 3. Output Voltage Setting TPS82740B

Device

VOUT

2.6

VSEL3

VSEL2

VSEL1

2.7

2.8

2.9

TPS82740B

3.0

3.1

3.2

3.3

8 Specifications

8.1 Absolute Maximum Ratings⁽¹⁾

Over operating free-air temperature range (unless otherwise noted)

VALUE

UNIT

MIN

–0.3

-40

MAX

(2)

Pin voltage

VIN

EN, CTRL, VSEL1, VSEL2, VSEL3

V_IN+0.3V

3.7

VOUT, LOAD

(3)

Operating ambient temperature range, T_A

Operating junction temperature T_J

°C

-40

125

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings

only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating

conditions is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability.

(2) All voltage values are with respect to network ground terminal GND.

(3) In applications where ambient temperature (T_A) constantly stays above 70°C, the product life time might degrade. MLCC capacitor

reliability and lifetime is depending on temperature and applied voltage conditions. At higher temperatures, MLCC capacitors are subject

to stronger stress. The most critical parameter is the Insulation Resistance (IR) resulting in leakage current.

8.2 Handling Ratings

MIN

–55

MAX

125

UNIT

T_stg

Storage temperature range

°C

Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all

pins⁽¹⁾

2000

V_(ESD)

Electrostatic discharge

Charged device model (CDM), per JEDEC specification

JESD22-C101, all pins⁽²⁾

1000

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. The human body

model is a 100-pF capacitor discharged through a 1.5-kΩ resistor into each pin.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

8.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN NOM

MAX UNIT

V_IN

Supply voltage V_IN

2.2

5.5

200

100

I_OUT+ I_LOAD

Device output current (sum of I_OUTand I_LOAD

)

V_OUTnom+ 0.7V ≤ V_IN≤ 5.5V

_OUTnom≤ V_IN≤ V_OUTnom+0.7V

I_LOAD

C_OUT

C_LOAD

T_J

Load current (current from LOAD pin)

Additional output capacitance connected to VOUT pin (not including LOAD pin)

Capacitance connected to LOAD pin

µF

°C

Operating junction temperature range

-40

T_A

Operating ambient temperature range

TPS82740A, TPS82740B

www.ti.com.cn

ZHCSCJ5A –JUNE 2014–REVISED JUNE 2014

8.4 Thermal Information

TPS82740

THERMAL METRIC⁽¹⁾

µSIP

UNIT

9 PINS

R_θJA

Junction-to-ambient thermal resistance

R_θJC(top)

R_θJB

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

°C/W

ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

ψ_JB

R_θJC(bot)

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

8.5 Electrical Characteristics

V_IN= 3.6V, T_A= –40°C to 85°C, typical values are at T_A= 25°C (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP MAX

UNIT

SUPPLY

V_IN

Input voltage range

2.2

5.5

EN = V_IN, CTRL = GND, I_OUT= 0µA, V_OUT= 1.8V / 2.6V, device not

switching

360 2300

µA

EN = V_IN, I_OUT= 0mA, CTRL = GND, V_OUT= 1.8V device switching

460

500

Operating quiescent EN = V_IN, I_OUT= 0mA, CTRL = GND, V_OUT= 2.6V, device switching

I_Q

current

EN = V_IN, I_OUT= 0mA., CTRL = V_IN,V_OUT= 1.8V, device not

switching

12.5

13.5

EN = V_IN, I_OUT= 0mA., CTRL = V_IN,V_OUT= 2.6V, device not

switching

I_SD

Shutdown current

EN = GND, shutdown current into V_IN

EN = GND, shutdown current into V_IN, T_A= 60°C

Rising V_IN

150

V_{TH_UVLO+}

V_{TH_UVLO-}

Undervoltage

lockout threshold

2.075

1.925

2.15

Falling V_IN

INPUTS EN, CTRL, VSEL 1-3

V_{IH TH}

V_{IL TH}

I_IN

High level input

threshold

2.2V ≤ V_IN≤ 5.5V

1.1

Low level input

threshold

0.4

Input bias Current

T_A= 25°C

T_A= –40°C to 85°C

POWER SWITCHES

High side MOSFET

switch current limit

430

I_LIMF

2.2V ≤ V_IN≤ 5.5V

Low side MOSFET

switch current limit

OUTPUT DISCHARGE SWITCH (VOUT)

MOSFET on-

R_{DSCH_VOUT}

resistance

EN = GND, I_OUT= -10mA into VOUT pin

EN = V_IN, V_OUT= 2V / 2.8V, CTRL = GND

Ω

Bias current into

VOUT pin

T_A= 25°C

660

I_{IN_VOUT}

T_A= –40°C to 85°C

1570

LOAD OUTPUT (LOAD)

High side MOSFET

on-resistance

0.6

1.25

Ω

R_LOAD

I_LOAD= 50mA, CTRL = V_IN, V_OUT= 2.0V / 2.8V, 2.2 V ≤ V_IN≤ 5.5V

CTRL = GND, 2.2V ≤ V_IN≤ 5.5V, I_LOAD= - 10mA

Low side MOSFET

on-resistance

R_{DSCH_LOAD}

V_LOADrise time

Starting with CTRL low to high transition, time to ramp V_LOADfrom

0V to 95%, V_OUT= 1.8V / 2.6V, 2.2V ≤ V_IN≤ 5.5V, I_LOAD= 1mA, T_A

25°C

315

800

µs

t_{Rise_LOAD}

TPS82740A, TPS82740B

ZHCSCJ5A –JUNE 2014–REVISED JUNE 2014

www.ti.com.cn

Electrical Characteristics (continued)

V_IN= 3.6V, T_A= –40°C to 85°C, typical values are at T_A= 25°C (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP MAX

UNIT

AUTO 100% MODE TRANSITION

Auto 100% Mode

170

250

200

340

280

Rising V_IN,100% Mode is left with V_IN= V_OUT+ V_{TH_100+}, max value

at T_J= 85°C

V_{TH_100+}

exit detection

(1)

threshold

Auto 100% Mode

enter detection

110

Falling V_IN, 100% Mode is entered with V_IN= V_OUT+ V_{TH_100-}, max

value at T_J= 85°C

V_{TH_100-}

(1)

threshold

OUTPUT

t_{Startup_delay}

Regulator start up

delay time

From transition EN = low to high until device starts switching

µs

t_Softstart

Softstart time with

reduced switch

current limit

2.2V ≤ V_IN≤ 5.5V, EN = V_IN

400 1200

High side MOSFET

switch current limit

150

200

I_{LIM_softstart}

Reduced switch current limit during softstart

Low side MOSFET

switch current limit

Output voltage

range

Output voltages are selected with pins VSEL1,

VSEL2, VSEL3

TPS82740A

TPS82740B

1.8

2.6

-2.5

–2

2.5

3.3

2.5

I_OUT= 10mA, V_OUT= 1.8V / 2.6V

I_OUT= 100mA, V_OUT= 1.8V / 2.6V

V_OUT= 1.8V / 2.6V, CTRL = V_IN

Output voltage

accuracy

V_VOUT

DC output voltage

load regulation

0.001

%/mA

%/V

DC output voltage

line regulation

V_OUT= 1.8V / 2.6V, CTRL = V_IN, I_OUT= 10 mA, 2.5V ≤ V_IN≤ 5.5V

(1) V_INis compared to the programmed output voltage (V_OUT). When V_IN–V_OUTfalls below V_{TH_100-}, the device enters 100% Mode by

turning the high side MOSFET on. 100% Mode is exited when V_IN–V_OUTexceeds V_{TH_100+}and the device starts switching. The

hysteresis for the 100% Mode detection threshold V_{TH_100+}- V_{TH_100-}is always positive and 50 mV(typ.)

8.6 Typical Characteristics

TABLE OF GRAPHS

FIGURE

Figure 3, Figure 4, Figure 5,

Figure 6

Efficiency

vs Output Current

vs Input Voltage

vs Output curent

Figure 7, Figure 8, Figure 9,

Figure 10

Efficiency

Figure 11, Figure 12, Figure 13,

Figure 14

V_OUT

Output voltage

I_Q

Operating quiescent current

Shutdown current

vs Input voltage

Figure 1

I_SD

Figure 2

Automatic Transition into 100% Mode

Switching frequency

Figure 18, Figure 19, Figure 20

Figure 15, Figure 16, Figure 17

F_SW

vs Output current

Figure 21, Figure 22, Figure 23,

Figure 24, Figure 25, Figure 26,

Figure 27, Figure 28, Figure 29,

Figure 30

Line and Load Transient Performance

AC load regulation performance

LOAD Output Behavior

Figure 31, Figure 32

LOAD

Figure 33, Figure 34, Figure 35

Figure 36, Figure 37, Figure 38,

Figure 39

Input Voltage Ramp up / down

TPS82740A, TPS82740B

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ZHCSCJ5A –JUNE 2014–REVISED JUNE 2014

Typical Characteristics (continued)

1000

200

180

160

140

120

100

T_A= -40C

T_A= 25C

T_A= 60C

T_A= -40C

T_A= 25C

T_A= 60C

T_A= 85C

900

800

T_A= 85C

700

600

500

400

300

200

100

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

Input Voltage V_IN(V)

D019

D020

EN = VIN

CTRL = GND

Device not switching

EN = GND

Figure 1. TPS82740 Quiescent Current I_Q

Figure 2. TPS82740 Shutdown current I_SD

V_IN= 2.7V

V_IN= 3.3V

V_IN= 3.6V

V_IN= 4.2V

V_IN= 5.0V

V_IN= 2.7V

V_IN= 3.3V

V_IN= 3.6V

V_IN= 4.2V

V_IN= 5.0V

0.001

0.01

0.1

100 300

0.001

0.01

0.1

100 300

Output Current (mA)

D008

D009

CTRL = GND

Figure 3. TPS82740A Efficiency V_OUT= 1.8V

Figure 4. TPS82740A Efficiency V_OUT= 2.1V

100

V_IN= 3.0V

V_IN= 3.3V

V_IN= 3.6V

V_IN= 4.2V

V_IN= 5.0V

V_IN= 3.6V

V_IN= 4.2V

V_IN= 5.0V

0.001

0.01

0.1

100 300

0.001

0.01

0.1

100 300

Output Current (mA)

D001

D002

CTRL = GND

Figure 5. TPS82740B Efficiency V_OUT= 2.6V

Figure 6. TPS82740B Efficiency V_OUT= 3.3V

TPS82740A, TPS82740B

ZHCSCJ5A –JUNE 2014–REVISED JUNE 2014

www.ti.com.cn

Typical Characteristics (continued)

100

I_OUT= 1mA

I_OUT= 2mA

I_OUT= 5mA

I_OUT= 10mA

I_OUT= 100mA

I_OUT= 1mA

I_OUT= 10mA

I_OUT= 200mA

I_OUT= 10mA

I_OUT= 100mA

I_OUT= 1mA

I_OUT= 10mA

I_OUT= 200mA

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

Input Voltage V_IN(V)

D010

D011

CTRL = GND

Figure 7. TPS82740A Efficiency V_OUT= 1.8V

Figure 8. TPS82740A Efficiency V_OUT= 2.1V

100

I_OUT= 1mA

I_OUT= 2mA

I_OUT= 5mA

I_OUT= 10mA

I_OUT= 100mA

I_OUT= 1mA

I_OUT= 10mA

I_OUT= 200mA

I_OUT= 10mA

I_OUT= 100mA

I_OUT= 1mA

I_OUT= 10mA

I_OUT= 200mA

2.5

3.0

3.5

4.0

4.5

5.0

5.5

3.5

4.0

4.5

5.0

5.5

Input Voltage V_IN(V)

D004

D003

CTRL = GND

Figure 9. TPS82740B Efficiency V_OUT= 2.6V

Figure 10. TPS82740B Efficiency V_OUT= 3.3V

1.85

1.84

1.83

1.82

1.81

1.80

1.79

1.78

1.77

1.76

1.75

2.16

2.15

2.14

2.13

2.12

2.11

2.10

2.09

2.08

2.07

2.06

2.05

2.04

V_IN= 2.7V

V_IN= 3.3V

V_IN= 3.6V

V_IN= 4.2V

V_IN= 5.0V

V_IN= 2.7V

V_IN= 3.3V

V_IN= 3.6V

V_IN= 4.2V

V_IN= 5.0V

0.001

0.01

0.1

100 300

0.001

0.01

0.1

100 300

Output Current I_OUT(mA)

D012

D013

CTRL = GND

Figure 11. TPS82740A Output voltage V_OUT= 1.8V

Figure 12. TPS82740A Output voltage V_OUT= 2.1V

TPS82740A, TPS82740B

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ZHCSCJ5A –JUNE 2014–REVISED JUNE 2014

Typical Characteristics (continued)

2.67

2.66

2.65

2.64

2.63

2.62

2.61

2.60

2.59

2.58

2.57

2.56

2.55

2.54

2.53

2.52

3.40

3.38

3.36

3.34

3.32

3.30

3.28

3.26

3.24

3.22

3.20

V_IN= 3.3V

V_IN= 3.6V

V_IN= 4.2V

V_IN= 5.0V

V_IN= 3.6V

V_IN= 4.2V

V_IN= 5.0V

0.001

0.01

0.10.2 0.5 1 2 3 5 10 20 50100 300

Output Current I_OUT(mA)

0.001

0.01

0.1

100 300

Output Current I_OUT(mA)

D014

D015

CTRL = GND

Figure 13. TPS82740B Output voltage V_OUT= 2.6V

Figure 14. TPS82740B Output voltage V_OUT= 3.3V

1800

1600

1400

1200

1000

800

600

400

200

1800

1600

1400

1200

1000

800

600

400

200

V_IN= 2.5V

V_IN= 3.0V

V_IN= 3.6V

V_IN= 4.2V

V_IN= 5.0V

V_IN= 2.7V

V_IN= 3.0V

V_IN= 3.6V

V_IN= 4.2V

V_IN= 5.0V

80 100 120 140 160 180 200

Output Current (mA)

80 100 120 140 160 180 200

Output Current (mA)

D016

D017

Figure 15. TPS82740A Switching frequency V_OUT= 1.8V

Figure 16. TPS82740A Switching frequency V_OUT= 2.1V

2.50

1800

I_OUT= 10mA, rising V_IN

I_OUT= 10mA, falling V_IN

I_OUT= 50mA, rising V_IN

I_OUT= 50mA, falling V_IN

I_OUT= 100mA, rising V_IN

I_OUT= 100mA, falling V_IN

2.45

2.40

2.35

2.30

2.25

2.20

2.15

2.10

2.05

2.00

1600

1400

1200

1000

800

600

400

200

V_IN= 3.6V

V_IN= 4.2V

V_IN= 5.0V

2.20

2.25

2.30

2.35

2.40

2.45

2.50

2.55

80 100 120 140 160 180 200

Output Current (mA)

Input Voltage V_IN(V)

D018

D005

Figure 17. TPS82740B switching frequency V_OUT= 3.0V

Figure 18. TPS82740A 100% Mode Transition V_OUT= 2.1V

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Typical Characteristics (continued)

2.90

3.70

3.65

3.60

3.55

3.50

3.45

3.40

3.35

3.30

3.25

3.20

I_OUT= 10mA, rising V_IN

I_OUT= 10mA, falling V_IN

I_OUT= 50mA, rising V_IN

I_OUT= 50mA, falling V_IN

I_OUT= 100mA, rising V_IN

I_OUT= 100mA, falling V_IN

2.85

2.80

2.75

2.70

2.65

2.60

2.55

2.50

2.45

I_OUT= 10mA, falling V_IN

I_OUT= 50mA, rising V_IN

I_OUT= 50mA, falling V_IN

I_OUT= 100mA, rising V_IN

I_OUT= 100mA, falling V_IN

2.45 2.50 2.55 2.60 2.65 2.70 2.75 2.80 2.85 2.90

Input Voltage V_IN(V)

3.20 3.25 3.30 3.35 3.40 3.45 3.50 3.55 3.60 3.65 3.70

Input Voltage V_IN(V)

D006

D007

Figure 19. TPS82740A 100% Mode Transition V_OUT= 2.5V

Figure 20. TPS82740B 100% Mode Transition V_OUT= 3.3V

V_IN= 3.6V

V_OUT= 1.8V

CTRL = GND

Load step at V_OUT

V_IN= 3.6V

V_OUT= 1.8V

CTRL = V_IN

Load step at V_OUT

I_OUT= 0.5mA to 150mA

I_OUT= 50mA to 10mA

Figure 21. TPS82740A Load Transient Response V_OUT= 1.8V

Figure 22. TPS82740A Load Transient Response V_OUT= 1.8V

V_IN= 3.6V

V_OUT= 2.6V

CTRL = V_IN

V_IN= 3.6V

V_OUT= 2.6V

CTRL = GND

Load step at V_OUT

I_OUT= 0.5mA to 150mA

I_OUT= 50mA to 10mA

Figure 23. TPS82740B Load Transient Response V_OUT= 2.6V

Figure 24. TPS82740B Load Transient Response V_OUT= 2.6V

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Typical Characteristics (continued)

V_IN= 3.6V

V_OUT= 1.8V

CTRL = GND

Load step at V_OUT

V_IN= 3.6V

V_OUT= 1.8V

CTRL = V_IN

Load step at V_OUT

0mA to 100mA

1ms rise/fall time

70ms / 10ms

I_OUT= 0mA to 100mA

1ms rise/fall time

70ms / 10ms

Figure 26. TPS82740A Load Transient Response V_OUT= 1.8V

Figure 25. TPS82740A Load Transient Response V_OUT= 1.8V

V_IN= 3.6V

V_OUT= 2.6V

CTRL = GND

Load step at V_OUT

0mA to 100mA

1ms rise/fall time

70ms / 10ms

V_IN= 3.6V

V_OUT= 2.6V

CTRL = V_IN

Load step at V_OUT

0mA to 100mA

1ms rise/fall time

70ms / 10ms

Figure 27. TPS82740B Load Transient Response V_OUT= 2.6V

Figure 28. TPS82740B Load Transient response V_OUT= 2.6V

V_IN= 3.6V / 4.2V

V_OUT= 2.1 V

V_IN= 3.6V / 4.2V

V_OUT= 2.1 V

I_OUT= 100mA

CTRL = GND

I_OUT= 10mA

CTRL = GND

Figure 29. TPS82740A Line Transient Response

I_OUT= 10mA

Figure 30. TPS82740A Line Transient Response

I_OUT= 100mA

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Typical Characteristics (continued)

V_IN= 3.6V

V_OUT= 1.8V

V_OUT= 2.6V

I_OUT= 50mA to 200mA

CTRL = GND

I_OUT= 50mA to 200mA

CTRL = GND

Figure 31. TPS82740A AC Load Sweep V_OUT= 1.8V

Figure 32. TPS82740B AC Load Sweep V_OUT= 2.6V

V_IN= 3.6V

V_OUT= V_LOAD= 1.8 V

I_LOAD= 0 to 50mA

I_OUT= 0mA

V_OUT= V_LOAD= 2.6V

I_LOAD= 0 to 50mA

I_OUT= 0mA

CTRL = V_IN

Figure 33. TPS82740A Load Step at LOAD Output

Figure 34. TPS82740B Load Step at LOAD Output

V_IN= 3.6V

V_OUT= 2.6V

I_OUT= 0mA

V_INramp up/down

0V to 5V in 150ms

V_OUT= 1.8V

R_OUT= 50W

CTRL = GND

I_LOAD= 0mA

C_LOAD= 10mF

controlled

slew rate

V_LOADdischarged

Figure 35. TPS82740B Load Output ON / OFF

Figure 36. TPS82740A Input Voltage Ramp Up / Down

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Typical Characteristics (continued)

V_INramp up/down

0V to 5V in 150ms

V_OUT= 2.6V

V_INramp up/down

0V to 5V in 150ms

V_OUT= 3.3V

R_OUT= 50W

CTRL = GND

R_OUT= 50W

CTRL = GND

100% mode operation

High side MOS-FET turned on

100% mode operation

High side MOS-FET turned on

Figure 37. TPS82740B Input Voltage Ramp Up / Down

Figure 38. TPS82740B Input Voltage Ramp Up / Down

V_INramp up/down

2.8V to 3.7V

V_OUT= 3.0V

R_OUT= 50W

CTRL = GND

High side MOSFET turned on

100% Mode

Exit / Enter

Figure 39. TPS82740B Enter / Exit 100% Mode Operation

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9 Parameter Measurement Information

TPS82740

DC/DC Converter

2.2 V to 5.5 V

OUT

up to 200mA

VIN

VOUT

LOAD

GND

Switched Supply Rail

ENABLE

VSEL1

VSEL2

VSEL3

C_LOAD

VSEL1

VSEL2

VSEL3

10mF

Control for

Switched Supply Rail

CTRL

GND

Measurement Configuration with Passive Components

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10 Detailed Description

10.1 Overview

The TPS82740 is the first fully integrated step down converter module with an ultra low quiescent current

consumption (360nA typ.) while maintaining a regulated output voltage and featuring TI's DCS-Control™

topology. The device extends high efficiency operation to output currents down to a few micro amperes.

10.2 Functional Block Diagram

CTRL

UVLO

Ultra Low Power

Reference V_REF= 1.2V

Softstart

ENABLE

VSEL1

V_OUT

Discharge

VOUT

Load Switch

Slew Rate

Control

Internal

V_FBfeedback

divider

network

(typ. 50MW)

CTRL

Auto 100% Mode

UVLO

Comp

VSEL2

VSEL3

LOAD

Comp

100%

Mode

VIN

Discharge

UVLO

V_{TH_100}

V_{TH_UVLO}

Power Stage

PMOS

Current

Limit Comparator

VIN

Timer

Min. On

UVLO

DCS

Control

VIN

Limit

High Side

VOUT

Min. OFF

VOUT

Control

Logic

Direct Control

& Compensation

Gate Driver

Anti

VOUT

Shoot-Through

V_FB

V_REF

NMOS

Limit

Low Side

Error

amplifier

Main

Comparator

Current

Limit Comparator

GND

10.3 Feature Description

10.3.1 DCS-Control™

TI's DCS-Control™ (Direct Control with Seamless Transition into Power Save Mode) is an advanced regulation

topology, which combines the advantages of hysteretic and voltage mode control. Characteristics of DCS-

Control™ are excellent AC load regulation and transient response, low output ripple voltage and a seamless

transition between PFM and PWM mode operation. DCS-Control™ includes an AC loop which senses the output

voltage (VOUT pin) and directly feeds the information to a fast comparator stage. This comparator sets the

switching frequency, which is constant for steady state operating conditions, and provides immediate response to

dynamic load changes. In order to achieve accurate DC load regulation, a voltage feedback loop is used.

The DCS-Control™ topology supports PWM (Pulse Width Modulation) mode for medium and high load

conditions and Power Save Mode at light loads. During PWM mode, it operates in continuous conduction. The

switching frequency goes up to 1.7MHz with a controlled frequency variation depending on the input voltage. If

the load current decreases, the converter seamlessly enters Power Save Mode to maintain high efficiency down

to very light loads. In Power Save Mode, the switching frequency varies nearly linearly with the load current.

Since DCS-Control™ supports both operation modes within one single building block, the transition from PWM to

Power Save Mode is seamless without effects on the output voltage. The TPS82740 offers both excellent DC

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Feature Description (continued)

voltage and superior load transient regulation, combined with very low output voltage ripple, minimizing

interference with RF circuits. At high load currents, the converter operates in quasi fixed frequency PWM mode

operation and at light loads in PFM (Pulse Frequency Modulation) mode to maintain highest efficiency over the

full load current range. In PFM Mode, the device generates a single switching pulse to ramp up the inductor

current and recharge the output capacitor, followed by a sleep period where most of the internal circuits are

shutdown to achieve the lowest quiescent current. During this time, the load current is supported by the output

capacitor. The duration of the sleep period depends on the load current and the inductor peak current.

During the sleep periods, the quiescent current of the TPS82740 is reduced to 360nA. This low quiescent current

consumption is achieved by an ultra low power voltage reference, an integrated high impedance (typ. 50MΩ)

feedback divider network and an optimized DCS-Control™ block.

10.3.2 LOAD Switch

The LOAD pin can be used to power an additional, temporarily used sub-system. If the CTRL pin is set high, the

LOAD pin is connected to the VOUT pin via an integrated load switch. The load switch is slew rate controlled to

support soft switching and not impacting the regulated output VOUT. If the CTRL pin is set to low, the LOAD pin

is disconnected from the VOUT pin and internally connected to GND by an internal discharge switch. The CTRL

pin can be controlled by a micro controller and must be terminated. With CTRL pin high, the quiescent current is

increased to improve the transient response.

10.3.3 Output Voltage Selection (VSEL1, VSEL2, VSEL3)

The TPS82740 provides an integrated, high impedance (typ. 50MΩ) feedback resistor divider network which is

programmed by the pins VSEL1-3. The TPS82740A supports an output voltage range of 1.8V to 2.5V in 100mV

steps, while the TPS82740B supports an output voltage range from 2.6V to 3.3V in 100mV steps. The output

voltage can be changed during operation and supports a simple dynamic output voltage scaling, shown in

Figure 44. The output voltage is programmed according to Table 2 and Table 3.

10.3.4 Output Discharge Function (VOUT and LOAD)

Both the VOUT pin and the LOAD pin feature a discharge circuit to connect each rail to GND, once they are

disabled. This feature prevents residual charge voltages on capacitors connected to these pins, which may

impact proper power up of the main- and sub-system. With the CTRL pin pulled low, the discharge circuit at the

LOAD pin activates. With the EN pin pulled low, the discharge circuit at the pin VOUT activates.

10.3.5 Internal Current Limit

The TPS82740 integrates a current limit in the high side, as well as in the low side MOSFETs to protect the

device against overload or short circuit conditions. The peak current in the switches is monitored cycle by cycle.

If the high side MOSFET current limit is reached, the high side MOSFET is turned off and the low side MOSFET

is turned on until the current decreases below the low side MOSFET current limit.

Table 4. Load Pin Condition Table

Pin condition

Operating condition

VIN

Remark

LOAD

CTRL

load switch enabled

and slew rate

controlled

Connected

to VOUT

high

> V_UVLO

load switch turned

off

high

low

high or low

high

> V_UVLO

< V_UVLO

Connected

to GND

device and load

switch disabled

device disabled due

to UVLO

high

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10.3.6 CTRL / DVS (Dynamic Voltage Scaling TPS62741)

In TPS62741, the CTRL pin controls beside the load switch as well Dynamic Voltage Scaling. The CTRL pin

selects between two different voltage setting banks. The voltage of each bank are set with the VSEL pins 1-4

according to .

The output LOAD is controlled with the CTRL pin. The pin is internally connected either to VOUT pin or GND and

can be used to power up/down temporarily used external circuits to reduce leakage current consumption of the

system.

10.4 Device Functional Modes

10.4.1 Enable / Shutdown

The TPS82740 is activated when the EN pin is set high. For proper operation, the pin must be terminated and

must not be left floating. With the EN pin set low, the device enters shutdown mode with less than typ. 70nA

current consumption.

10.4.2 Softstart

When the device is enabled, the internal reference is powered up and after the startup delay time t_{Startup_delay}has

expired, the device enters softstart, starts switching and ramps up the output voltage. During softstart, the device

operates with a reduced current limit, I_{LIM_softstart}, of typ. 1/3 of the nominal current limit. This reduced current limit

is active during the time t_Softstart. The current limit is increased to its nominal value, I_LIMF, once this time has

expired or the nominal output voltage is reached.

10.4.3 POWER GOOD OUTPUT (PG)

The Power Good comparator features an open drain output. The PG comparator is active with EN pin set to high

and V_INis above the threshold V_{TH_UVLO+}. It is driven to high impedance once V_OUTtrips the threshold V_{TH_PG+}for

rising V_OUT. The output is pulled to low level once V_OUTfalls below the PG hysteresis, V_{PG_hys}. The output is also

pulled to low level in case the input voltage V_INfalls below the undervoltage lockout threshold V_{TH_UVLO-}or the

device is disabled with EN = low. The power good output (PG) can be used as an indicator for the system to

signal that the converter has started up and the output voltage is in regulation.

Table 5. PG condition table

Pin condition

Operating condition

Remark

hiz

CTRL

high

IOUT / ILOAD

don't care

VIN

VOUT

PG comparator

active, pull up resistor

pulls PG to high

high

> V_UVLO

VOUT > V_{TH_PG+}

PG comparator

active, pull up resistor

pulls PG to high

medium load (>

1mA)

hiz

low

> V_UVLO

VOUT > V_{TH_PG+}

PG comparator

disabled for low Iq

operation, pull up

resistor pulls PG to

high

low

light load (< 1mA)

> V_UVLO

VOUT > V_{TH_PG+}

0mA < IOUT <

100mA

startup, overload or

ramp down

low

high

low

don't care

> V_UVLO

V_IN> 1.2V

< V_UVLO

VOUT < V_{TH_PG-}

VOUT = 0

don't care output disabled

device disabled

device disabled, due

to UVLO

high

don't care output disabled

VOUT not present

Table 6. VOUT Output Discharge Condition Table

VOUT pin

low

VIN condition

1.5V < V_IN< V_UVLO

< V_UVLO

remark

connected to GND, output discharged

high

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remark

Table 6. VOUT Output Discharge Condition Table (continued)

VOUT pin

VIN condition

during regulator start

up, the discharge

switch is enabled and

VOUT pulled to low,

until the regulator

start up time t_Start

expires. During the

softstart time and

later, the discharge

switch is disabled.

hiz, discharge switch disabled

high

> V_UVLO

10.4.4 Automatic Transition into 100% Mode

Once the input voltage comes close to the output voltage, the TPS82740 stops switching and enters 100% duty

cycle operation. It connects the output VOUT via the inductor and the internal high side MOSFET switch to the

input VIN, once the input voltage V_INfalls below the 100% mode enter threshold, V_{TH_100-}. In 100% mode

switching stops eliminating output voltage ripple. Because the output is connected to the input, the output voltage

tracks the input voltage minus the voltage drop across the internal high side switch and the inductor caused by

the output current. Once the input voltage increases and trips the 100% mode exit threshold, V_{TH_100+}, the

TPS82740 turns on and starts switching again. See Figure 40, Figure 18, Figure 19 and Figure 20.

V_IN

V_IN,

V_OUT

100%

Mode

100%

Mode

V_{TH_100+}

V_{TH_100-}

Step Down Operation

V_OUT

tracks V_IN

V_OUT

tracks V_IN

V_UVLO+

V_UVLO-

V_OUT

discharge

t_softstart

Figure 40. Automatic Transition into 100% Mode

TPS82740A, TPS82740B

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ZHCSCJ5A –JUNE 2014–REVISED JUNE 2014

11 Application and Implementation

11.1 Application Information

The device is designed to operate from an input voltage supply range between 2.2V and 5.5V with a maximum

output current of 200mA. Once the input voltage comes close to the output voltage, the DC/DC converter stops

switching and enters 100% duty cycle operation. The integrated slew rate controlled load switch can distribute

the selected output voltage to a temporarily used sub-system. The TPS82740 module operates in PWM mode for

medium and high load conditions and in power save mode at light load currents.

At high load currents, the converter operates in quasi fixed frequency PWM mode operation. The switching

frequency is up to 1.7MHz with a controlled frequency variation depending on the input voltage. If the load

current decreases, the converter seamlessly enters Power Save Mode by varying the switching frequency

linearly to maintain high efficiency over the full load current range. At very light load conditions the device

generates a single switching pulse to ramp up the inductor current and recharge the output capacitor, followed by

a sleep period where most of the internal circuits are shutdown to achieve 360nA quiescent current consumption.

11.2 Typical Application

TPS82740

LCD

Display + Driver

DC/DC Converter

Main Supply

VIN

2.2 V ... 5.5 V

VOUT

GND

ADC

MCU

Control Subsystem

Switched Supply

CTRL

LOAD

ENABLE

VSEL1

VSEL2

VSEL3

VSEL1

VSEL2

VSEL3

Radio

SOC

GND

Acceleration

Sensor

Electronic

Compass

Temperature

Sensor

Example of Implementation in a SOC Based System

11.2.1 Design Requirements

TPS82740 is a complete step-down converter module including all passive components (inductor, input and

output capacitor). For most applications no additional input / output capacitors are required. Use the following

typical application design procedure to select additional external components in case further performance

improvement of the module is desired.

11.2.2 Detailed Design Procedure

11.2.2.1 Input Capacitor Selection

For most applications, the integrated input capacitor at the VIN pin is sufficient.

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Typical Application (continued)

TPS82740 uses a tiny ceramic input capacitor. When a ceramic capacitor is combined with trace or cable

inductance, such as that from a wall adapter, a load step at the output can induce ringing at the VIN pin. This

ringing can couple to the output and be mistaken as loop instability or can even damage the module. In this

circumstance, additional ceramic 'bulk" capacitance, such as electrolytic or tantalum, should be placed between

the input of the module and the power source lead to reduce ringing that occurs between the inductance of the

power source leads and the module.

11.2.2.1.1 Input Buffer Capacitor Selection

In addition to the small ceramic input capacitor a larger buffer capacitor C_Bufis recommended to reduce voltage

drops and ripple voltage. When using battery chemistries like Li-SOCl2, Li-SO2, Li-MnO2, the impedance of the

battery has to be considered. These battery types tend to increase their impedance depending on discharge

status and often can support output currents of only a few mA. Therefore a buffer capacitor is recommended to

stabilize the battery voltage during DC/DC operations e.g. for a RF transmission. A voltage drop on the input of

the TPS82740 during DC/DC operation impacts the advantage of the step down conversion for system power

reduction. Furthermore the voltage drops can fall below the minimum recommended operating voltage of the

device and leads to an early system cut off. Both effects reduce the battery life time. To achieve best

performance and to extract the most energy out of the battery a good procedure is to select the buffer capacitor

value for an voltage drop below 50mVpp during DC/DC operation. The capacitor value strongly depends on the

used battery type, as well the current consumption during a RF transmission as well the duration of the

transmission.

11.2.2.2 Output Capacitor Selection

For most applications, the integrated output capacitor at the VOUT pin is sufficient.

In order to further reduce the output voltage ripple and improve the load transient performance an additional

external output capacitance may be used. For most applications an additional 4.7µF or 10µF capacitor will be

sufficient. Care should be taken that the total effective capacitance present at the output does not exceed 10µF

in order to guarantee loop stability. Ceramic capacitors with low ESR values have the lowest output voltage ripple

and are recommended.

At the LOAD output pin, no additional output capacitor is required. For applications demanding external

capacitance connected to the LOAD pin, the total capacitance should not exceed 10µF.

11.2.3 Application Curves

V_IN= 3.6V

V_OUT= 2.6V

R_OUT= 100W

CTRL = GND

V_OUT= 2.6V

R_OUT= 100W

CTRL = GND

Figure 41. TPS82740B Device Enable and Start up

Figure 42. TPS82740B V_OUTRamp after Enable

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ZHCSCJ5A –JUNE 2014–REVISED JUNE 2014

Typical Application (continued)

V_IN= 3.6V,

V_OUT= 1.8V / 2.5V ramp up / down

I_OUT= 5mA

V_IN= 3.6V, V_OUT= V_{LOAD =}2.6V

CTRL = V_IN

R_OUT= 100W

I_LOAD= 0mA

C_LOAD= 10mF

VSEL 2+3 toggled, VSEL1 = GND

CTRL = GND

Figure 43. TPS82740B V_OUTRamp with activated LOAD

Switch

Figure 44. TPS82740A Dynamic Output Voltage Scaling:

V_OUT= 1.8V / 2.5V

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12 Power Supply Recommendations

The TPS82740 device is a complete and optimized power supply module working within the given

specification range without additional components. Please use the information given in the Application

Information section to connect the input and output circuitry appropriately.

13 Layout

13.1 Layout Guidelines

In making the pad size for the uSiP LGA balls, it is recommended that the layout use a non-solder-mask defined

(NSMD) land. With this method, the solder mask opening is made larger than the desired land area, and the

opening size is defined by the copper pad width. Figure 45 shows the appropriate diameters for a MicroSiP^TM

layout. Figure 46 shows a suggestion for the PCB layout.

13.2 Layout Example

Figure 45. Recommended Land Pattern Image and Dimensions

(5)

(6)

SOLDER PAD

SOLDER MASK

OPENING

COPPER

THICKNESS

STENCIL

COPPER PAD

STENCIL THICKNESS

DEFINITIONS^(1)(2)(3)(4)

OPENING

Non-solder-mask

defined (NSMD)

0.30mm

0.360mm

1oz max (0.032mm)

0.34mm diameter

0.1mm thick

(1) Circuit traces from non-solder-mask defined PWB lands should be 75μm to 100μm wide in the exposed area inside the solder mask

opening. Wider trace widths reduce device stand off and affect reliability.

(2) Best reliability results are achieved when the PWB laminate glass transition temperature is above the operating the range of the

intended application.

(3) Recommend solder paste is Type 3 or Type 4.

(4) For a PWB using a Ni/Au surface finish, the gold thickness should be less than 0.5mm to avoid a reduction in thermal fatigue

performance.

(5) Solder mask thickness should be less than 20 μm on top of the copper circuit pattern.

(6) For best solder stencil performance use laser cut stencils with electro polishing. Chemically etched stencils give inferior solder paste

volume control.

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ZHCSCJ5A –JUNE 2014–REVISED JUNE 2014

GND

LOAD

VOUT

Pin A1

VIN

GND

Figure 46. PCB Layout Suggestion

13.3 Surface Mount Information

The TPS82740 MicroSIP™ module uses an open frame construction for a fully automated assembly process and

provides a large surface area for pick and place operations. See the "Pick Area" in the package drawing.

Package height and weight have been kept to a minimum, allowing MicroSIP™ device handling similar to a 0805

footprint component.

For reflow recommendations, see document J-STD-20 from the JEDEC/IPC standard.

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14 器件和文档支持

14.1 文档支持

14.1.1 相关链接

以下表格列出了快速访问链接。范围包括技术文档、支持与社区资源、工具和软件，以及样片或购买的快速访问。

表 7. 相关链接

部件

产品文件夹

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样片与购买

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TPS82740A

TPS82740B

14.2 商标

DCS-Control, MicroSIP are trademarks of Texas Instruments.

is a registered trademark of ~Bluetooth SIG, Inc..

14.3 静电放电警告

这些装置包含有限的内置 ESD 保护。存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损

伤。

14.4 术语表

SLYZ022 — TI 术语表。

这份术语表列出并解释术语、首字母缩略词和定义。

15 机械封装和可订购信息

以下页中包括机械封装和可订购信息。这些信息是针对指定器件可提供的最新数据。这些数据会在无通知且不对

本文档进行修订的情况下发生改变。欲获得该数据表的浏览器版本，请查阅左侧的导航栏。

PACKAGE OPTION ADDENDUM

www.ti.com

17-Mar-2023

PACKAGING INFORMATION

Orderable Device

Status Package Type Package Pins Package

Eco Plan

Lead finish/

Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

(1)

(2)

(3)

(4/5)

(6)

TPS82740ASIPR

TPS82740ASIPT

TPS82740BSIPR

TPS82740BSIPT

ACTIVE

uSiP

SIP

3000 RoHS & Green

250 RoHS & Green

3000 RoHS & Green

250 RoHS & Green

NIAU

Level-2-260C-1 YEAR

-40 to 85

Samples

NIAU

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

⁽³⁾MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

⁽⁵⁾Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6)

Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

17-Mar-2023

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

17-Mar-2023

TAPE AND REEL INFORMATION

REEL DIMENSIONS

TAPE DIMENSIONS

Reel

Diameter

Cavity

A0 Dimension designed to accommodate the component width

B0 Dimension designed to accommodate the component length

K0 Dimension designed to accommodate the component thickness

Overall width of the carrier tape

P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2

Q3 Q4

Q1 Q2

Q3 Q4

User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

TPS82740ASIPR

TPS82740ASIPT

TPS82740BSIPR

TPS82740BSIPT

uSiP

SIP

3000

250

178.0

9.0

2.5

2.83

2.5

3.1

3.18

3.1

1.35

1.2

4.0

8.0

3000

250

1.35

1.2

2.83

3.18

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

17-Mar-2023

TAPE AND REEL BOX DIMENSIONS

Width (mm)

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

TPS82740ASIPR

TPS82740ASIPT

TPS82740BSIPR

TPS82740BSIPT

uSiP

SIP

3000

250

223.0

194.0

35.0

3000

250

Pack Materials-Page 2

重要声明和免责声明

TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，

不保证没有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担

保。

这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验

证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。

这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。

您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成

本、损失和债务，TI 对此概不负责。

TI 提供的产品受 TI 的销售条款或 ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI 提供这些资源并不会扩展或以其他方式更改

TI 针对 TI 产品发布的适用的担保或担保免责声明。

TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE

邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

TPS82740B [TI]

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