TPS92074 [TI]

具有数字参考控制的非隔离式、降压 PFC LED 驱动器;


型号：	TPS92074
厂家：	TEXAS INSTRUMENTS
描述：	具有数字参考控制的非隔离式、降压 PFC LED 驱动器驱动功率因数校正驱动器
文件：	总25页 (文件大小：882K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

TPS92074

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具有数字基准控制的非隔离、降压功率因数控制器 (PFC) 发光二极管

(LED) 驱动器

查询样品: TPS92074

特性

说明

•

取自 PFC 的受控基准

数字 50/60Hz 同步

恒定 LED 电流运行

单绕组磁性配置

低典型运行电流

快速启动

TPS92074 是一款混合功率因数控制器 (PFC)，此控制

器针对无需相位调光兼容性的 LED 照明解决方案而进

行了优化。此器件使用一个内部、低功耗、数字控制

器来监视转换器已整流交流波形。此控制器和数模转

换器 (DAC) 生成一个已同步三角基准来调节输出电

流。通过在线路周期上允许 LED 电流的变化，并且保

持一个已调节总平均电流，可实现高功率因数解决方

案。

过压保护

反馈短路保护

宽温度运行范围

通过使用一个恒定关闭时间控制，这个解决方案实现了

低组件数量、高效率并自然提供了开关频率的变化。

这个变化创建了一个仿真展频效应，从而简化了转换器

电磁干扰 (EMI) 签名并可使用一个更小的输出滤波

器。

低物料清单 (BOM) 成本和小型印刷电路板 (PCB)

封装尺寸

•

正在申请专利的数字架构

提供 8 引脚小外形尺寸集成电路 (SOIC) 封装和 6

引脚薄小外形晶体管封装 (TSOT)

TPS92074 还包含一些标准特性：电流限制、过压保

护、热关断和 VCC 欠压闭锁，所有这些都采用仅有 6

引脚的封装。

应用范围

•

非相位可调光 LED 灯

灯泡替换

大面积照明

简化的应用图

EMI Filter

LED +

TPS92074

VSEN COFF

GND VCC

ISNS GATE

LED -

V_IN

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

English Data Sheet: SLUSBO7

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This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more

susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

ABSOLUTE MAXIMUM RATINGS⁽¹⁾

All voltages are with respect to GND, –40°C < T_J= T_A< 125°C, all currents are positive into and negative out of the specified

terminal (unless otherwise noted)

VALUE

UNIT

MIN

–0.3

MAX

Input voltage range

Bias and ISNS

Gate

VCC

VSEN, COFF

6.0

2.5

I_Qbias current (non-switching)

ISNS⁽²⁾to Ground

GATE - continuous

GATE - 100 ns

–0.3

–2.5

20.5

Continuous power dissipation

Electrostatic discharge

Internally Limited

Human Body Model (HBM)

750

160

Field Induced Charged Device Model (FICDM)

(3)

Operating junction temperature, T_J

Storage temperature range, T_stg

Lead temperature, soldering, 10s

°C

–65

150

260

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating

Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) ISNS can sustain –2 V for 100 ns without damage.

(3) Maximum junction temperature is internally limited.

THERMAL INFORMATION

TPS92074

SOIC

(D)

TSOT

(DDC)

THERMAL METRIC⁽¹⁾

UNITS

8 PINS

112.3

58.4

52.5

12.5

51.9

6 PINS

165.5

28.8

24.6

0.3

θ_JA

Junction-to-ambient thermal resistance⁽²⁾

Junction-to-case (top) thermal resistance⁽³⁾

Junction-to-board thermal resistance⁽⁴⁾

Junction-to-top characterization parameter⁽⁵⁾

Junction-to-board characterization parameter⁽⁶⁾

Junction-to-case (bottom) thermal resistance⁽⁷⁾

θ_JCtop

θ_JB

°C/W

ψ_JT

ψ_JB

23.8

θ_JCbot

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as

specified in JESD51-7, in an environment described in JESD51-2a.

(3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-

standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.

(4) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB

temperature, as described in JESD51-8.

(5) The junction-to-top characterization parameter, ψ_JT, estimates the junction temperature of a device in a real system and is extracted

from the simulation data for obtaining θ_JA, using a procedure described in JESD51-2a (sections 6 and 7).

(6) The junction-to-board characterization parameter, ψ_JB, estimates the junction temperature of a device in a real system and is extracted

from the simulation data for obtaining θ_JA, using a procedure described in JESD51-2a (sections 6 and 7).

(7) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific

JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.

Spacer

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RECOMMENDED OPERATING CONDITIONS⁽¹⁾

Unless otherwise noted, all voltages are with respect to GND, –40°C < T_J= T_A< 125°C.

MIN

TYP

MAX UNIT

Supply input voltage range VCC

Operating junction temperature

–40

125

°C

(1) Operating Ratings are conditions under which operation of the device is specified and do not imply assured performance limits. For

specified performance limits and associated test conditions, see the Electrical Characteristics table.

ELECTRICAL CHARACTERISTICS

Unless otherwise specified –40°C ≤ T_J= T_A≤ 125°C, V_CC= 14 V, C_VCC= 10 µF C_GATE= 2.2 nF

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

SUPPLY VOLTAGE INPUT (VCC)

I_Q

V_VCCquiescent current

V_VCClow power mode current

Input range

Not switching

1.3

2.5

250

µA

I_{Q_SD}

V_VCC

V_VCC(OVP)

V_CC< V_CC(UVLO)

120

V_CC≤ V_CC(OVP)

Overvoltage protection threshold

V_CC> V_CC(OVP)

V_CCrising

18.0

5.75

20.0

10.5

9.8

6.40

3.3

V_VCC(UVLO)

V_VCC(HYS)

V_VCCUVLO threshold

V_VCCUVLO hysteresis

V_CCfalling

LINE SYNCHRONIZATION

VSEN_TH-Hi

VSEN line detect rising threshold

0.9

1.0

1.1

VSEN_TH-LowVSEN line detect falling threshold

OFF-TIME CONTROL

0.465 0.500 0.540

V_COFF

OFF capacitor threshold

OFF capacitor pull-down resistance

Maximum off-time

1.14

1.20

1.285

R_COFF

t_OFF(max)

280

μs

GATE DRIVER OUTPUT (GATE)

R_GATE(H)

R_GATE(L)

Gate sourcing resistance

Gate sinking resistance

CURRENT SENSE

V_ISNS

V_CL

Average ISNS limit threshold

DAC: 63/127

445

500

1.2

240

280

555

Current limit

Leading edge blanking

Current limit reset delay

ISNS limit to GATE delay

OFF capacitor limit to GATE delay

µs

t_ISNS

t_{COFF_DLY}

THERMAL SHUTDOWN

T_SD

Thermal limit threshold

Thermal limit hysteresis

160

°C

T_HYS

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DEVICE INFORMATION

FUNCTIONAL BLOCK DIAGRAM

VCC

V_VCC

Regulator

VSEN

Filter

Internal

Regulator

V_VCCOVP

V_VCCUVLO

Logic

Standby

Thermal

Shutdown

Standby

0 -V to 1-V (Analog)

PWM

ILIM

ISNS

GATE

200-ns

Delay

1.2 V

Control

Logic

COFF

1.2 V

200-PS

Off-timer

GND

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SOIC (D) PACKAGE

8 PINS

(TOP VIEW)

GND

COFF

VCC

VSEN

ISNS

GATE

TSOT (DDC) PACKAGE

6 PINS

(TOP VIEW)

VSEN

GND

ISNS

COFF

VCC

GATE

PIN DESCRIPTIONS

PIN NUMBERS

NAME

SIOC

(D)

TSOT

(DDC)

I/O

DESCRIPTION

Used to set the converter constant off-time. A current and capacitor connected from the output

to this pin sets the constant off-time of the switching controller.

COFF

Power MOSFET driver pin. This output provides the gate drive for the power switching

MOSFET.

GATE

GND

ISNS

—

Circuit ground connection

LED current sense pin. Connect a resistor from main switching MOSFET source to GND to set

the maximum switching cycle LED current. Connect ISNS to the switching FET source.

Input voltage pin. This pin provides the power for the internal control circuitry and gate driver.

V_CCundervoltage lockout has been implemented with a wide range: 10V rising, 6V falling to

ensure operation with start-up methods that allow elimination of the linear pass device. This

includes using a coupled inductor with resistive start-up.

VCC

—

The line voltage and frequency are detected through this pin and fed to the digital decoder.

Sensing thresholds are 1V rising and 0.5V falling – nominal.

VSEN

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TYPICAL CHARACTERISTICS

Unless otherwise stated, –40°C ≤ T_A= T_J≤ 125°C, V_VCC= 14 V, C_VCC= 10 µF C_GATE= 2.2 nF

1.1630

1.1625

1.1620

1.1615

1.1610

1.1605

1.1600

1400

1200

1000

800

600

400

200

VCC Rising

VCC Falling

−40 −25 −10

20 35 50 65 80 95 110 125

Temperature (°C)

VCC Input Voltage (V)

G000

Figure 1. COFF Threshold Voltage vs Temperature

Figure 2. VCC Input Current vs Vcc Input Voltage

9.84

6.48

9.82

9.80

9.78

9.76

9.74

9.72

9.70

6.46

6.44

6.42

6.40

6.38

6.36

−40 −25 −10

20 35 50 65 80 95 110 125

Temperature (°C)

−40 −25 −10

20 35 50 65 80 95 110 125

Temperature (°C)

G000

Figure 3. Input Voltage (UVLO Rising) vs Junction

Temperature

Figure 4. Input Voltage (UVLO Falling) vs Junction

Temperature

ISNS Mid-Scale Voltage Range (V)

Figure 5. ISNS 0.5V Threshold Distribution

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APPLICATION INFORMATION

The TPS92074 is an AC-DC power factor correction (PFC) controller for LED lighting applications. A hysteretic,

peak current, constant off-time approach implements the conversion.

Rectified AC

Vcc

TPS92074

VSEN COFF

GND

VCC

ISNS GATE

Buck

Buck-Boost

Figure 6. Simplified TPS92074 Schematic

The TPS92074 controls the inductor current by controlling two features: (A) The peak inductor current, and (B)

The cycle off-time. The following items summarize the basics of the switch operation in this hysteretic controller.

•

The main switch Q2 turns on and current ramps in the inductor.

The Q2 current flows through the sense resistor R7. The R7 voltage is compared to a reference voltage at

ISNS. The Q2 on-time ends when the voltage on R7 is equal to a controlled reference voltage and the

inductor current has reached its set peak current level for that switching cycle.

•

Q2 is turned off and a constant off-time timer begins. Voltage begins ramping on C8.

The next cycle begins when the voltage on C8 reaches 1.2 V. This ends the constant off-time and discharges

C8.

•

Capacitor C3 eliminates most of the ripple current seen in the LEDs.

(A) Peak Inductor Current

L-PP

(B)

OFF

(constant)

Time

UDG-12176

Figure 7. Current Regulation Method

The TPS92074 incorporates a patent-pending control methodology to generate the reference for the conversion

stage.

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Initial Start-Up

The TPS92074 is designed to achieve instant turn-on using an external linear regulator circuit. The start-up

sequence is internally controlled by a V_CCunder-voltage lockout (UVLO) circuit. Sufficient headroom has been

incorporated to support the use of an auxiliary winding with start-up linear, resistive or coupled capacitor start-up

methods.

VCC Bias Supply

The TPS92074 can be configured to use a linear regulator with or without the use of an auxiliary winding. Using

a linear regulator to provide V_CCincurs more losses than an auxiliary winding, but has several advantages:

•

allows the use of inexpensive off-the-shelf inductors as the main magnetic

can reduce the size of the required VCC capacitor to as low as 0.1uF

Another consideration when selecting a bias method involves the OVP configuration. Because the feature is

enabled via the VCC pin, an auxiliary winding provides the simplest implementation of output over-voltage

protection.

A typical start-up sequence begins with V_VCCinput voltage below the UVLO threshold and the device operating in

low-power, shut-down mode. The V_VCCinput voltage increases to the UVLO threshold of 9.8V typical. At this

point all of the device features are enabled. The device loads the initial start-up value as the output reference

and switching begins. The device operates until the V_VCClevel falls below the V_CC(UVLO)falling threshold. (6.4V

typical) When V_VCCis below this threshold, the device enters low-power shut-down mode.

Voltage Sense Operation

The VSEN (voltage sense) pin is the only input to the digital controller. The time between the rising edge and the

falling edge of the signal determines converter functions. The pin incorporates internal analog and digital filtering

so that any transition that remains beyond the threshold for more than approximately 150 µs will cause the

device to record a change-of-state.

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Controller

Basic Operation

The controller continuously monitors the line cycle period. Control algorithms use a normalized line period of 256

samples from VSEN fall to VSEN fall and a normalized converter reference control of 127 levels over a range of

0V to 1V .

The two main controller states are:

•

Start-Up

Normal Operation

After the initial start-up period where the reference is a DC level, the reference is changed to a triangular ramp to

achieve a high power factor. The ramp generates gradually over several cycles ensuring the change is

undetectable. The controller maintains the ramp between the rising and falling VSEN signals.

Table 1. Control States and Controlled Reference Values

CONTROLLED REFERENCE VALUE

MODE

LINE DUTY CYCLE

(value / 127 ) X 1 V = reference

Start-up

Any

Typical Average

Typical Ramp Range

Any

Normal Operation

No VSEN

22 to 127

Initial Start-up

Line Synchronization

When the device reaches the turn-on UVLO threshold, the output current reference resets to 0.393 V (50/127)

and switching begins. The controller samples the line for approximately 80 ms (t₁to t₂, Figure 8) to determine

the line frequency and establish the present state of operation. After determining the line frequency, the controller

uses the information to calibrate the internal oscillator. The controller supports line frequencies from 45 Hz to 65

Hz. After determining frequency and duty cycle, the controller enters normal operation.

V_REC

V_VSEN

Controlled Reference

V_ISNS(peak)

V_GATE

Time

t₀t₁

t₂

UDG-12168

Figure 8. Line Synchronization

Triangular Ramp Creation

After the start-up period, the controller creates a triangular ramp that is synchronized to the line and is centered

between rising and falling edges of the VSEN signal as shown in Figure 9.

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Rectified AC

VSEN

Controlled Reference

Time

Figure 9. Controlled Reference Output

At start-up the ramp is created over 127 line cycles (see Figure 10) or approximately 1 second (t₂to t₃≈ 1

second). Because the output level before and after the change is very similar and the change very gradual, it is

impossible for the user to perceive a change in output level. The ramp converts from a DC level to a ramp using

a method that further ensures transparency to the user.

...

V_REC

...

V_VSEN

V_ISNS(peak)

Time

t₂

t₃

Figure 10. Transition Stages of the Controlled Reference during Start-Up

Loss of Voltage Sense

If a circuit malfunction or failure occurs causing the VSEN singal to become too narrow or to be lost completely,

the controller simply sets the reference to a default value 0.33 V (42/127) and waits for the VSEN signal to

return.

Not Using Voltage Sense

A simplified version of the TPS92074 circuit can be implemented by grounding the VSEN signal if minimum

component count and size are essential design criteria. In this configuration, the triangular ramp reference is not

implemented. The output is controlled with a default, static reference of 0.394 V (50/127). If used in conjunction

with an on-time clamp and the appropriate LED stack voltage, power factors (> 0.9) can still be achieved, but

THD is higher without the ramp waveform.

Thermal Shutdown

The TPS92074 includes thermal shutdown protection. If the die temperature reaches approximately 160°C the

device stops switching (GATE pin low). When the die temperature cools to approximately 140°C, the device

resumes normal operation.

If thermal foldback is desired at levels below the device thermal shut down limit, application circuit design

features implement this protection. The most simple of these design features is the addition of a thermistor in the

off-time circuitry.

Thermal Foldback

To implement thermal foldback, adjust the resistance of an existing circuit resistor with the use of an NTC

(negative temperature coefficient) thermistor.

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For example, a resistor combination creating a dominant effect when the thermistor reaches the desired

temperature and resistance can be incorporated by paralleling a thermistor and another resistor like R10 with the

suggested On-Time clamp (see Figure 12. ). This circuit option creates a shorter on-time as the temperature

increases, reducing the output current. The use of a thermistor (NTC or PTC) in these types of circuit

implementations is simple and saves costly added circuitry and additional device pins.

Overvoltage Protection (OVP)

The implementation of overvoltage protection is simple and built-in if using a two-coil magnetic (coupled inductor)

to derive V_CC. If the LED string is opened the auxiliary V_CCrises and reaches the V_CC(OVP)trip point. This action

disables and grounds the gate pin, preventing the converter from switching. The converter remains disabled until

V_CCdrops 0.5 V after a 1 second time-out. If an inductor is used, implement other discrete circuits to disable the

converter.

Output Bulk Capacitor

The required output bulk capacitor, C_BULK, stores energy during the input voltage zero crossing interval and limits

twice the line frequency ripple component flowing through the LEDs. Equation 1 describes the calculation of the

of output capacitor value.

C_BULK

4p´ f_L´R_LED´ V_LED´I_{LED ripple}

(

)

where

•

R_LEDis the dynamic resistance of LED string

I_LED(ripple)is the peak to peak LED ripple current

and f_Lis line frequency

(1)

Compute R_LEDas the difference in LED forward voltage divided by the difference in LED current for a given LED

using the manufacturer’s V_Fvs. I_Fcurve. For an initial estimate, a typical value of 0.25 Ω per LED can be used.

More detail can be found in the Application Report Design Challenges of Switching LED Drivers (AN-1656).

In typical applications, the solution size becomes a limiting factor and dictates the maximum dimensions of the

bulk capacitor. When selecting an electrolytic capacitor, manufacturer recommended de-rating factors should be

applied based on the worst case capacitor ripple current, output voltage and operating temperature to achieve

the desired operating lifetime. It should also be a consideration to provide a minimum load at the output of the

driver to discharge the capacitor after the power is switched off or during LED open circuit failures.

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Design Guidelines

This TPS92074 application design requires the selection of components for the power conversion stage and line

sensing. Output inductor, sense resistor and switching frequency are the key aspects of the power stage design.

Another important consideration is the inclusion of an on-time clamp. The combination of the line voltage going to

zero at each cycle and the hysteretic control method can lead to large increases in current draw at the start and

end of each cycle. The components required for the on-time clamp are very inexpensive and they return results

that make their inclusion a common choice for LED driver designers. This simplified design procedure assumes

the use of an on-time clamp in the design.

UDG-12183

L(ave)

R_SENSEadjusts

the average,

peak inductor

current

The average output current =

the average peak ± ½ the

peak to peak inductor ripple

Peak Inductor Current follows

this Controlled Reference.

I_pk(t) = V_ISNS(t)/R_SENSE

The Inductance (L)

defines 'i

L(P-P)

ûi_L-PP= (V_LED* t_off

)

i_L(ave)= i_Lave(pk)± ûi_L(P-P)

Rectified

Inductor

Current

Ripple

i_Lave(pk)= V_ISNS(ave)

R_SENSE

Time

OFF

Figure 11. TPS92074 Output Current Control

The device uses the controller reference during every switching cycle. This controller reference sets the peak

current through the main switch and sense resistor. The average value of this reference and the inductor ripple

current can be used to calculate the average output current. Also consider the length of time the converter

provides power to the LEDs based on the LED stack voltage. A conversion factor (CF) that accounts for a lower

level of power conversion at the ends of each cycle is used to provide a more accurate sense resistor value. The

lower level of power conversion in these areas also helps to increase the power factor. For the R_SENSEcalculation

use V_ISNS

= 0.433 V (55/127). The CF calculation involves computing the normalized time length of the

(ave)

voltage sense pulse using a formula shown in Equation 3. See the simplified design expressions in Equation 2

through Equation 6. For a more comprehensive approach refer to the TPS92074 Design Spreadsheet.

To calculate R_SENSE, use Equation 2.

ISNS ave

(

)

R_SENSE

´ CF

Di_{L P-P}

(

)

I_LED

(2)

To calculate the conversion factor, use Equation 3.

-1

LED

sin

2 ´ V

RMS

CF = 1-

(3)

(4)

To calculate inductance ripple, use Equation 4.

_LED´ t_OFF

Di_{L P-P}

(

)

To calculate the constant off-time, use Equation 5

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1.2

= ln -

-1 ´ -C

´R

TOFF COFF

(

)

OFF

VCC

(5)

(6)

To calculate the average switching frequency, use Equation 6.

f_SW

t_OFF+ t

´ CF

(

)

OFF

General Approach to Buck and Buck-Boost PFC Design

To maintain a high power factor and low THD, create an input current waveform equivalent to what would be

seen in a purely resistive load. A resistive load (like an incandescent light bulb) can draw power until the line

zero cross. A buck converter driving an LED load can provide power only while the input line is greater than the

LED stack voltage. This situation creates a limitation in the selection of LED stack voltage. Currently in non-LED

load, buck PFC applications, a commonly accepted output voltage that maintains acceptable THD and PFC

levels is one that maintains a 50% conduction angle each line cycle. See the TI Application Report Power Factor

Correction Using the Buck Topology(SLUP264) In practical terms this equates to 90 VDC for a 90 VAC minimum

input. For LED driver solutions this rule can be followed if the goal is simply a power factor ≥0.9. If the goal is

also THD less than 20% then stricter requirements must be followed. In general, designs with an LED stack

voltage beyond 45 V have difficulty achieving < 20% THD. For these solutions, a buck-boost topology should be

used so that the circuit has the capability to draw current from the line below the LED stack voltage.

On-Time Clamp

The use of an on-time clamp ( see Figure 12) provides soft-start and soft-stop functionality to the conversion

during each line cycle. The clamp also allows an opportunity to control the energy in these conversion areas to

optimize THD. For example, reducing the energy conversion in these areas helps to create an input current that

is more sinusoidal in shape. Without it, the current can rise quickly at the start and end of each cycle as the

converter goes in and out of drop-out. Solutions having a power factor ≥0.9 are still achievable, but the design

must use the on-time clamp to obtain very low THD.

TPS92074

ISNS

GATE

R10

R11

D5a

D5b

ISNS

C10

Figure 12. On-time Clamp Circuitry

The circuit uses the gate drive output to generate a ramp. The ramp increases at a rate to reach the current

sense trip point at the desired maximum conduction time. The gate signal, resistor R10 and capacitor C10 create

the ramp. Diode D5b resets the ramp for each switching cycle. Resistor R11 provides an impedance so this

signal can override ISNS.

In the regions at the start and end of a line cycle the current sense reference is controlled to 0.173 V (22/127).

To select an R-C to reach this point in the desired time use Equation 7. A good starting estimate for the

maximum on-time clamp is approximately one-half of t_OFF. For example, choosing 33 nF as the value of

capacitor C10, and assuming V_GATE≈ V_CC, R10 (R_ton(max)) is calculated in Equation 7.

t_OFF

R_{ton max}

(

)

0.173

2´ ln -

-1 ´ -C

ton max

(

)

V_GATE

(7)

TPS92074

ZHCSBJ0 –AUGUST 2013

www.ti.com.cn

Voltage Sense Circuitry and Minimum VSEN Signal Length

If the design topology is a buck converter, select the divider so the falling 0.5-V VSEN threshold is reached when

the rectified AC voltage is at the LED stack voltage. For example, if the LED stack is 20 V and the top resistor is

400 kΩ, the bottom resistor should be 10.25 kΩ to provide a falling VSEN signal at 0.5 V when the rectified AC

reaches 20 V. A 20-V VSEN falling signal corresponds to a 40-V VSEN rising threshold because of the 2:1

hysteresis. These thresholds provide a VSEN signal length of approximately 7.4 ms. This length is adequate to

activate the ramp mode. Regardless of the VSEN connection method used, the divider must ensure an adequate

voltage sense time (t_VSEN> 5.9 ms) to activate the creation of the triangular reference. For example, if a straight

resistor divider ( as shown in Figure 13) is implemented and the design LED stack is more than 42 V, the VSEN

conduction time may not be adequate to ensure use of the ramp reference by the controller.

LED(+)

LED(-)

VSEN

Figure 13. Voltage Sense for Low

Voltage Buck Applications

Figure 14. Voltage Sense for

Buck Applications up to 65V

Figure 15. Voltage Sense for

Buck-Boost Applications

For LED stack voltages between 3 V and 65 V, use an alternate method that senses from LED(–). Because

LED(–) reaches ground each line cycle, the absolute VSEN comparison limits of 0.5 V and 1 V can be used,

providing extra conduction time for the VSEN signal as shown in Figure 14. When using an LED stack, with an

approximate voltage of more than 65-V, use an alternate VSEN methods such as a bridge tap. For buck-boost

applications, implement the circuit shown in Figure 15.

A capacitor on the VSEN pin may be required, depending on operating conditions.

EMI Filtering: AC versus DC side of the rectifier bridge

The TPS92074 requires a minimal amount of EMI filtering to pass conducted and radiated emissions levels to

comply with agency requirements. Applications have been tested with the filter on the AC or DC side of the diode

bridge and have obtained passing results. The use of an R-C snubber to damp filter resonances is strongly

recommended. The EMI filter design involves optimizing several factors and design considerations, including:

•

the use of ‘X’ versus non-X rated filter capacitors

the use of ceramic versus film capacitors

component rating requirements when on the AC or DC side of the diode bridge

snubber time constant and position in the design schematic

filter design choices and audible noise

TPS92074

www.ti.com.cn

ZHCSBJ0 –AUGUST 2013

Application Circuits

TPS92074

VSEN COFF

GND

VCC

ISNS GATE

Figure 16. TPS92074 Buck Topology with AC Side Filter

TPS92074

VSEN COFF

GND

VCC

ISNS GATE

ISNS

Figure 17. TPS92074 Buck-Boost Topology with DC Side Filter

TPS92074

ZHCSBJ0 –AUGUST 2013

www.ti.com.cn

TPS92074

VSEN COFF

GND

VCC

ISNS GATE

ISNS

UDG-12184

Figure 18. TPS92074 Buck-Boost Topology with Resistive Start-up and AUX Supply

TPS92074

VSEN COFF

GND

VCC

ISNS GATE

R_t

0-3V Analog DIM Signal

Figure 19. TPS92074 Buck Topology with Thermal Foldback and Analog Dimming (0 to 100%)

PACKAGE OPTION ADDENDUM

www.ti.com

10-Dec-2020

PACKAGING INFORMATION

Orderable Device

Status Package Type Package Pins Package

Eco Plan

Lead finish/

Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

(1)

(2)

(3)

(4/5)

(6)

TPS92074D

TPS92074DDCR

TPS92074DDCT

TPS92074DR

ACTIVE

SOIC

RoHS & Green

Level-1-260C-UNLIM

-40 to 125

T92074

ACTIVE SOT-23-THIN

DDC

3000 RoHS & Green

250 RoHS & Green

2500 RoHS & Green

NIPDAU

PC5Q

T92074

ACTIVE

SOIC

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

⁽³⁾MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

⁽⁵⁾Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6)

Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

10-Dec-2020

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2

PACKAGE OUTLINE

D0008A

SOIC - 1.75 mm max height

SCALE 2.800

SMALL OUTLINE INTEGRATED CIRCUIT

SEATING PLANE

.228-.244 TYP

[5.80-6.19]

.004 [0.1] C

PIN 1 ID AREA

6X .050

[1.27]

.189-.197

[4.81-5.00]

NOTE 3

.150

[3.81]

4X (0 -15 )

8X .012-.020

[0.31-0.51]

.150-.157

[3.81-3.98]

NOTE 4

.069 MAX

[1.75]

.010 [0.25]

C A B

.005-.010 TYP

[0.13-0.25]

4X (0 -15 )

SEE DETAIL A

.010

[0.25]

.004-.010

[0.11-0.25]

0 - 8

.016-.050

[0.41-1.27]

DETAIL A

TYPICAL

(.041)

[1.04]

4214825/C 02/2019

NOTES:

1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.

Dimensioning and tolerancing per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not

exceed .006 [0.15] per side.

4. This dimension does not include interlead flash.

5. Reference JEDEC registration MS-012, variation AA.

www.ti.com

EXAMPLE BOARD LAYOUT

D0008A

SOIC - 1.75 mm max height

SMALL OUTLINE INTEGRATED CIRCUIT

8X (.061 )

[1.55]

SYMM

SEE

DETAILS

8X (.024)

[0.6]

SYMM

(R.002 ) TYP

[0.05]

6X (.050 )

[1.27]

(.213)

[5.4]

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE:8X

SOLDER MASK

OPENING

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

METAL

EXPOSED

METAL

EXPOSED

METAL

.0028 MAX

[0.07]

.0028 MIN

[0.07]

ALL AROUND

SOLDER MASK

DEFINED

NON SOLDER MASK

DEFINED

SOLDER MASK DETAILS

4214825/C 02/2019

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com

EXAMPLE STENCIL DESIGN

D0008A

SOIC - 1.75 mm max height

SMALL OUTLINE INTEGRATED CIRCUIT

8X (.061 )

[1.55]

SYMM

8X (.024)

[0.6]

SYMM

(R.002 ) TYP

[0.05]

6X (.050 )

[1.27]

(.213)

[5.4]

SOLDER PASTE EXAMPLE

BASED ON .005 INCH [0.125 MM] THICK STENCIL

SCALE:8X

4214825/C 02/2019

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

9. Board assembly site may have different recommendations for stencil design.

www.ti.com

PACKAGE OUTLINE

DDC0006A

SOT-23 - 1.1 max height

SMALL OUTLINE TRANSISTOR

3.05

2.55

1.1

0.7

1.75

1.45

0.1 C

PIN 1

INDEX AREA

4X 0.95

1.9

3.05

2.75

0.5

0.3

0.1

TYP

0.0

0.2

C A B

0 -8 TYP

0.25

GAGE PLANE

SEATING PLANE

0.20

0.12

TYP

0.6

0.3

TYP

4214841/C 04/2022

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. Reference JEDEC MO-193.

www.ti.com

EXAMPLE BOARD LAYOUT

DDC0006A

SOT-23 - 1.1 max height

SMALL OUTLINE TRANSISTOR

SYMM

6X (1.1)

6X (0.6)

SYMM

4X (0.95)

(R0.05) TYP

(2.7)

LAND PATTERN EXAMPLE

EXPLOSED METAL SHOWN

SCALE:15X

METAL UNDER

SOLDER MASK

OPENING

SOLDER MASK

OPENING

METAL

EXPOSED METAL

0.07 MIN

ARROUND

0.07 MAX

ARROUND

NON SOLDER MASK

DEFINED

SOLDER MASK

DEFINED

SOLDERMASK DETAILS

4214841/C 04/2022

NOTES: (continued)

4. Publication IPC-7351 may have alternate designs.

5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com

EXAMPLE STENCIL DESIGN

DDC0006A

SOT-23 - 1.1 max height

SMALL OUTLINE TRANSISTOR

SYMM

6X (1.1)

6X (0.6)

SYMM

4X(0.95)

(R0.05) TYP

(2.7)

SOLDER PASTE EXAMPLE

BASED ON 0.125 THICK STENCIL

SCALE:15X

4214841/C 04/2022

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

7. Board assembly site may have different recommendations for stencil design.

www.ti.com

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邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

TPS92074 [TI]

相关型号：

TPS92074D

TPS92074DDCR

TPS92074DDCT

TPS92074DR

TPS92075

TPS92075D/NOPB

TPS92075DDC/NOPB

TPS92075DDCR/NOPB

TPS92075DR/NOPB

TPS92075_14

TPS92200

TPS92200D1DDCR