TPS92311 [TI]
Off-Line Primary Side Sensing Converter with PFC; 离线式初级侧感应器与PFC
| 型号： | TPS92311 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | Off-Line Primary Side Sensing Converter with PFC |
| 文件： | 总19页 (文件大小：432K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
May 30, 2012
TPS92311
Off-Line Primary Side Sensing Converter with PFC
General Description
Features
The TPS92311 is an off-line converter specifically designed
to drive high power LEDs for lighting applications. Features
include an integrated 3.75Ω 600V power MOSFET, adaptive
constant on-time control, quasi-resonant switching, and ca-
pable of operating in various topologies via mode selection
pins. The TPS92311 is ideally suited for driving 8W LED loads
and below. Power Factor Correction is inherent if the
TPS92311 is operated in the constant on-time mode with an
adaptive algorithm. Resonant switching allows for a reduced
EMI signature and increased system efficiency. Low external
parts count is realized with its simplified and high level of in-
tegration. The control algorithm of TPS92311 adjusts the on
time with reference to the primary side inductor peak current
and secondary side inductor discharge time dynamically, the
response time of which is set by an external capacitor. Other
supervisory features of the TPS92311 include cycle-by-cycle
primary side inductor current limit, VCC under-voltage lock-
out, output over-voltage protection and thermal shutdown.
The TPS92311 is available in 16–pin narrow SOIC package.
Integrated 600V power MOSFET
■
Regulates LED current without secondary side sensing
Adaptive ON-time control with inherent PFC
■
■
■
Critical-Conduction-Mode (CRM) with Zero-Current
Detection (ZCD) for valley switching
Programmable switch turn ON delay
■
■
Programmable Constant ON-Time (COT) and Peak
Current Control
Over-temperature protection
■
Applications
LED Lamps: A19 (E26/27, E14), PAR30/38, GU10
■
■
Solid State Lighting
Typical Application
30188070
FIGURE 1.
© 2012 Texas Instruments Incorporated
301880 SNVS811
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Connection Diagram
Top View
30188002
16–Lead Narrow SOIC package
Ordering Information
Order Number
TPS92311D
Package Type
Package QTY
Supplied As
Rails
Narrow SOIC-16
Narrow SOIC-16
48
TPS92311DR
2500
Tape and Reel
Pin Descriptions
Pin
1, 2, 15, 16
3, 7, 14
4
Name
SW
Description
Application Information
Drain
Internal power MOSFET drain pin
No connection pin
NC
No Connection
ZCD
Zero crossing detection input
The pin senses the voltage of the auxiliary winding for
zero current detection.
5, 12
GND
VIN
Ground
Circuit ground.
6
8
Power supply Input
Compensation network
This pin provides power to the internal control
COMP
Output of the error amplifier. Connect a capacitor from
this pin to ground to set the frequency response of the
LED current regulation loop.
9
DLY
Delay control input
Connect a resistor from this pin to ground to set the delay
between switching ON and OFF periods.
10
11
MODE2
MODE1
Mode selection input 2
Mode selection input 1
Select operating mode for isolated or non-isolated mode.
Select operating mode for peak current mode or constant
ON time.
13
ISNS
Current sense voltage feedback Switch current sensing input.
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Continuous Power Dissipation
ESD Susceptibility:
HBM (Note 3)
Internally Limited
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the Texas Instruments Sales Office/
Distributors for availability and specifications.
±2 kV
-65°C to +150°C
+125°C
Storage Temperature Range
Junction Temperature (TJ-MAX
)
SW to GND
VCC to GND
-0.3V to 600V
-0.3V to 40V
-0.3V to 7V
-0.3V to 7V
-0.3V to 7V
-0.3V to 7V
Maximum Lead Temperature
(Solder and Reflow)
260°C
DLY, COMP, ZCD to GND
ISNS to GND
MODE1 to GND
MODE2 to GND
SW FET Drain Current:
Peak
Operating Conditions
Supply Voltage range VCC
13V to 36V
Junction Temperature (TJ)
-40°C to +125°C
Thermal Resistance (θJA
(Note 6)
)
1.2A
95°C/W
Continuous
Limited by TJ-MAX
Electrical Characteristics VCC = 18V unless otherwise indicated. Typicals and limits appearing in plain type
apply for TA = TJ = +25°C. Limits appearing in boldface type apply over the full Operating Temperature Range. Data sheet minimum
and maximum specification limits are guaranteed by design, test or statistical analysis.
Symbol
Parameter
Conditions
Min
Typ (Note 5)
Max
Units
SUPPLY VOLTAGE INPUT (VCC)
VCC-UVLO
VCC Turn on
threshold
23.4 / 23
25.6
13
27.8 / 29
V
V
VCC Turn off
threshold
11.1 / 10.4
14.7 / 15.7
Hysteresis
12.6
12.5
1.2
2
ISTARTUP
IVCC
Startup Current
VCC = VCC-UVLO–3.0V
Not switching
10
14.75
1.5
µA
mA
mA
Operating supply
current
0.9
65kHz switching
ZERO CROSS DETECT (ZCD)
IZCD
ZCD bais current
VZCD= 5V
0.1
4.3
1
uA
V
VZCD-OVP
ZCD over-voltage
threshold
4.1
4.5
TOVP
Over voltage de-
bounce time
3
cycle
VZCD-ARM
VZCD-TRIG
VZCD-HYS
ZCD Arming
threshold
VZCD = Increasing
VZCD = Decreasing
VZCD-ARM-VZCD-TRIG
1.16
0.48
1.24
0.6
1.3
V
V
V
ZCD Trigger
threshold
0.77
ZCD Hysteresis
0.64
COMPENSATION (COMP)
ICOMP-
Internal reference VCOMP = 2.0V, VISNS = 0V, Measure at
27
µA
current for primary
side current
COMP pin
SOURCE
regulation
gmISNS
VCOMP
ISNS error amp
trans-conductance
100
µmho
V
Δ VISNS to Δ ICOMP @ VCOMP = 2.0V
COMP operating
range
2.0
3.5
DELAY CONTROL (DLY)
VDLY
DLY pin internal
reference voltage
1.21
250
1.23
1.26
V
IDLY-MAX
DLY source current VDLY = 0V
µA
3
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Symbol
Parameter
Conditions
Min
Typ (Note 5)
Max
Units
CURRENT SENSE (ISNS)
VISNS-OCP
Over Current
Detection
Non isolation mode
0.56
0.61
0.68
V
Threshold
VISNS-OCP
Over Current
Detection
Threshold
Isolation mode
3.2
-1
3.4
3.6
1
V
IISNS
Current Sense Bias VISNS = 5V
Current
µA
ns
TOCP
Over current
Detection
Propagation Delay
RSNS = 1K, Measure ISNS pin pulse width
210
660
with VSW = 6V
OUTPUT MOSFET (SW FET)
VBVDS
SW to ISNS
600
V
breakdown voltage
IDS
SW to ISNS
leakage current
(Note 4)
VSW-VISNS = 600V
1.35
µA
RDS
SW to ISNS switch
on resistance
3.75
Ω
TON-MIN
TON-MAX
TOFF-MIN
TOFF-MAX
Minimum ON time
Maximum ON time
Minimum OFF time
330
28
540
44
900
58
ns
µs
µs
µs
1.04
50
1.5
70
1.93
94
Maximum OFF
time
RSNS = 1K, Measure ISNS pull-down
period with VSW = 6V and VZCD = 0V
THERMAL SHUTDOWN
TSD Thermal shutdown (Note 2)
165
20
°C
°C
temperature
Thermal Shutdown
hysteresis
Note 1: Absolute maximum ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions for which the device is intended
to be functional, but device parameter specifications may not be guaranteed. For guaranteed specifications and test conditions, see the Electrical Characteristics.
All voltages are with respect to the potential at the GND pin, unless otherwise specified.
Note 2: Internal thermal shutdown circuitry protects the device from permanent damage. Thermal shutdown engages at TJ = 165°C (typ.) and disengages at TJ
= 145°C (typ).
Note 3: Human Body Model, applicable std. JESD22-A114-C.
Note 4: High voltage devices such as the TPS92311 are susceptible to increased leakage currents when exposed to high humidity and high pressure operating
environments. Users of this device are cautioned to satisfy themselves as to the suitability of this product in the intended end application and take any necessary
precautions (e.g. system level HAST/HALT testing, conformal coating, potting, etc.) to ensure proper device operation.
Note 5: Typical numbers are at 25°C and represent the most likely norm.
Note 6: This RθJA typical value determined using JEDEC specifications JESD51-1 to JESD51-11. However junction-to-ambient thermal resistance is highly
boardlayout dependent. In applications where high maximum power dissipation exists, special care must be paid to thermal dissipation issues during board design.
In high-power dissipation applications, the maximum ambient temperature may have to be derated. Maximum ambient temperature (TA-MAX) is dependent on the
maximum operating junction temperature (TJ-MAX-OP = 125°C), the maximum power dissipation of the device in the application (PD-MAX), and the junction-to ambient
thermal resistance of the part/package in the application (RθJA), as given by the following equation: TA-MAX = TJ-MAX-OP – (RθJA × PD-MAX).
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Typical Performance Characteristics
All curves taken at VCC=18V with configuration in typical application for driving seven power LEDs with ILED=350mA shown in this
datasheet. TA=25°C, unless otherwise specified.
VCC-UVLO vs Temperature
VCC Startup Voltage vs Temperature
15.0
14.5
14.0
13.5
13.0
12.5
12.0
11.5
11.0
28
27
26
25
24
23
22
-50 -25
0
25 50 75 100 125
-50 -25
0
25
50
75 100 125
TEMPERATURE (°C)
TEMPERATURE (°C)
30188030
30188026
30188027
30188040
30188025
30188032
TOFF-MAX vs Temperature
TON-MIN vs Temperature
80
78
76
74
72
70
68
66
64
62
60
600
580
560
540
520
500
480
-50 -25
0
25
50
75 100 125
-50 -25
0
25 50 75 100 125
TEMPERATURE ( °C)
TEMPERATURE (°C)
IVCC-SD vs Temperature
VZCD-OVP vs Temperature
1.50
1.45
1.40
1.35
1.30
1.25
1.20
1.15
1.10
1.05
1.00
5.2
5.0
4.8
4.6
4.4
4.2
4.0
3.8
3.6
-50 -25
0
25 50 75 100 125
-50 -25
0
25 50 75 100 125
TEMPERATURE (°C)
TEMPERATURE (°C)
5
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VZCD-ARM vs Temperature
VZCD-TRIG vs Temperature
1.50
1.45
1.40
1.35
1.30
1.25
1.20
1.15
1.10
1.05
1.00
0.80
0.75
0.70
0.65
0.60
0.56
0.50
0.45
0.40
-50 -25
0
25 50 75 100 125
-50 -25
0
25 50 75 100 125
TEMPERATURE (°C)
TEMPERATURE (°C)
30188028
30188033
30188034
30188029
VISNS-OCP (Isolated Mode) vs Temperature
VISNS-OCP (Non-Isolated Mode) vs Temperature
4.2
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
4.0
3.8
3.6
3.4
3.2
3.0
2.8
2.6
-50 -25
0
25 50 75 100 125
-50 -25
0
25 50 75 100 125
TEMPERATURE (°C)
TEMPERATURE (°C)
30188041
RDS vs Temperature
9
8
7
6
5
4
3
2
1
0
-50 -25
0
25
50
75 100 125
TEMPERATURE (°C)
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Simplified Internal Block Diagram
30188049
FIGURE 2. Simplified Block Diagram
7
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Application Information
The TPS92311 is an off-line convertor specifically designed
to drive LEDs. This device operates in Critical Conduction
Mode (CRM) with adaptive Constant ON-Time control, so that
high power factor can be achieved naturally. The TPS92311-
can be configured as an isolated or non-isolated off-line con-
verter. Please refer to TPS92311 typical schematic Figure 1,
on the front page, in the following discussion. The TPS9231
flyback converter consists of a transformer which includes
three windings LP, LS and LAUX, an internal MOSFET Q1 and
inductor current sensing resistor RISNS. Secondary side com-
ponents are secondary side transformer winding LS, output
diode D3, and output capacitor COUT. An auxiliary winding is
required, and serves two functions. Auxiliary power is devel-
oped from the winding to power the TPS92311 after start-up,
and detect the zero crossing point due to the end of a com-
plete switching cycle. During the on-period, Q1 is turned on,
and current flows through LP, Q1 and RISNS to ground, input
energy is stored in the primary inductor LP. Simultaneously,
the ISNS pin of the device monitors the voltage of the current
sensing resistor RISNS to perform the cycle-by-cycle inductor
current limit function. During the time MOSFET Q1 is off, cur-
rent flow in LP ceases and the energy stored during the on
cycle is released to output and auxiliary circuits. During Q1
off-time current in the secondary winding LScharges the out-
put capacitor COUT through D3 and supplies the LED load.
During Q1 on-time, COUT is responsible to supply load current
to LED load during subsequent on-period. Also during Q1 off-
time current is delivered to the auxiliary winding through D2
and powers the TPS92311. The voltage across LAUX, VLAUX
is fed back to the ZCD pin through a resistor divider network
formed by R2 and R3 to perform zero crossing detection of
VLAUX, which determines the end of the off-period of a switch-
ing cycle. The next on period of a new cycle will be initiated
after an inserted delay of 2 x tDLY. The tDLY is programmable
by a single resistor connecting the DLY pin and ground. The
setting of the delay time, tDLY will be described in a separate
paragraph. During steady state operation, the duration of the
on-period tON can be determined with two different modes: the
Constant On-Time (COT) mode and the Peak Current Mode
(PCM), which are configured by setting the MODE1 and
MODE2 pins. For the COT mode, tON is generated by com-
paring an internal generated saw-tooth waveform with the
voltage on the COMP pin (VCOMP). Since VCOMP is slow vary-
ing, tON is nearly constant within an AC line cycle. For the
PCM, the on-period is terminated when the voltage of the
30188079
FIGURE 3. Primary and Secondary Side Current
Waveforms
Startup Bias and UVLO
During startup, the TPS92311 is powered from the AC line
through R1 and D1 (Figure 1). In the startup state, most of the
internal circuits of the TPS92311 are shut down in order to
minimize internal quiescent current. When VCC reaches the
rising threshold of the VCC-UVLO (typically 25.6V), the
TPS92311 is operating in a low switching frequency mode,
where tON and tOFF are fixed to 1.5μs and 72μs. When VZCD–
is higher than VZCD-ARM, the TPS92311 enters normal
PEAK
operation.
ISNS pin (VISNS) reaches a threshold determined by VCOMP
.
Since the instantaneous input voltage (AC voltage) varies,
tON varies accordingly within an AC line cycle. The duration
of the off-period (tOFF) is determined by the rate of discharging
of the secondary current through the transformer. Also,
where n is the turn ratio of LP and LS. Figure 3 shows the
typical waveforms in normal operation.
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time depends on the drain capacitance of the Q1 and the pri-
mary inductance of the transformer (LP). Such delay time is
set by a single external resistor as described in Delay Setting
section.
During the off-period at steady state, VZCD reaches its maxi-
mum VZCD-PEAK (Figure 3), which is scalable by the turn ratio
of the transformer and the resistor divider network R2 and
R3. It is recommended that VZCD-PEAK is set to 3V during nor-
mal operation.
30188019
FIGURE 5. Switching Node Waveforms
Delay Time Setting
In order to reduce EMI and switching loss, the TPS92311 in-
serts a delay between the off-period and the on-period. The
delay time is set by a single resistor which connects across
the DLY pin and ground, and their relationship is shown in
Figure 6. The optimal delay time depends on the resonance
frequency between LP and the drain to source capacitance of
Q1 (CDS). Circuit designers should optimize the delay time
according to the following equation.
30188089
FIGURE 4. Start up Bias Waveforms
Mode Decoder
The TPS92311 is capable of operating in two control modes
as an isolated topology, Peak Current Mode (PCM) or Con-
stant On-Time (COT). The TPS92311 can also be configured
in a non-isolated topology using COT operation. Depending
on system requirements, the designer will chose between the
two modes of operation. COT mode gives a high power factor,
PCM can achieve a lower output current ripple. COT mode
using a non-isolated topology can achieve a higher efficiency
and good load regulation. The above modes can be selected
by setting the MODE1 and MODE2 pins according to Table
1.
After determining the delay time, tDLY can be implemented by
setting RDLY according to the following equation:
TABLE 1. MODE Configuration
where KDLY = 32MΩ/ns is a constant.
MODE1 MODE2
Mode of operation
OPEN
GND
OPEN
OPEN
GND
COT mode using isolated topology
PCM using isolated topology
OPEN
COT mode using non-isolated
topology
GND
GND
Reserved
Zero Crossing Detection
To minimized the switching loss of the internal power MOS-
FET, a zero crossing detection circuit is embedded in the
TPS92311. VLAUX is AC voltage coupled from VSW by means
of the transformer, with the lower part of the waveform clipped
by DZCD. VLAUX is fed back to the ZCD pin to detect a zero
crossing point through a resistor divider network which con-
sists of R2 and R3. The next turn on time of Q1 is selected
VSW is the minimum, an instant corresponding to a small delay
after the zero crossing occurs. (Figure 5) The actual delay
9
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60
50
40
30
20
10
0
0
400
800
1200 1600 2000
DELAY TIME (ns)
30188039
FIGURE 6. Delay Time Setting
Protection Features
OUTPUT OPEN CIRCUIT PROTECTION
If the LED string is disconnected from the output of the
TPS92311, The output voltage (VLED) increases and thus
VZCD-PEAK increases. When VZCD-PEAK is greater than VZCD-
for 3 continues switching cycles, the Over Voltage Pro-
OVP
tection (OVP) feature is triggered. Switching of Q1 is stopped,
and VCC decreases until it drops below the falling threshold of
VCC-UVLO, the TPS92311 restarts, and re-enter into startup
state (Figure 8).
OUTPUT SHORT CIRCUIT PROTECTION
If the LED string is shorted, VZCD-PEAK drops, and as VZCD-
30188090
drops below VZCD-TRIG, the TPS92311 will enter low
PEAK
switching frequency operation. During low switching frequen-
cy operation, power supplied from LAUX to VCC is not enough
to maintain VCC. If the short remains VCC will drop below the
falling threshold of VCC-UVLO, the TPS92311 will attempt to
restart at this time (Figure 7). When the short is removed the
TPS92311 will restore to steady state operation.
FIGURE 7. Output Short Circuit waveforms
OVER CURRENT PROTECTION
Over Current Protection (OCP) limits the drain current of in-
ternal MOSFET and prevents inductor / transformer satura-
tion. When VISNS reaches a threshold, the OCP is triggered
and the internal MOSFET will turn off immediately. The
threshold is typically 3.4V and 0.64V when the TPS92311 is
using an isolated topology and a non-isolated topology re-
spectively.
THERMAL PROTECTION
Thermal protection is implemented by an internal thermal
shutdown circuit, which activates at 160°C (typically). In this
case, the internal switching power MOSFET will turn off. Ca-
pacitor CVCC will discharge until UVLO. When the junction
temperature of the TPS92311 falls back below 130°C, the
TPS92311 resumes normal operation.
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30188077
FIGURE 8. Auto Restart Operation
11
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where VOS is the maximum switching node overshoot voltage
allowed, in this example, 50V is assumed. As a rule of thumb,
lower turn ratio of transformer can provide a better line regu-
lation and lower secondly side peak current. In here, turn ratio
n = 3.8 is recommended.
Design Example
The following design example illustrates the procedures to
calculate the external component values for the TPS92311
isolated single stage fly-back LED driver with PFC.
Design Specifications:
SWITCHING FREQUENCY
SELECTION
Input voltage range, VAC_RMS = 85VAC – 132VAC
Nominal input voltage, VAC_RMS(NOM) = 110VAC
Number of LED in serial =7
TPS92311 can operate at high switching frequency in the
range of 60kHz to 150kHz. In most off-line applications, with
considering of efficiency degradation and EMC requirements,
the recommended switching frequency range will be 60kHz
to 80kHz. In this design example, switching frequency at
75kHz is selected.
LED current, ILED = 350mA
Forward voltage drop of single LED = 3.0V
Forward voltage of LED stack, VLED = 21V
Key operating Parameters:
Converter minimum switching frequency, fSW = 75kHz
Output rectifier maximum reverse voltage, VD3(MAX) = 100V
Power MOSFET rating, VQ1(MAX) = 600V (3.75Ω)
SWITCHING ON TIME
The maximum power switch on-time, tON depends on the low
line condition of 85VAC. At 85VAC the switching frequency was
chosen at 75kHz. This transformer design will follow the for-
mulae as shown below.
Power MOSFET Output Capacitance, CDS = 37pF (estimat-
ed)
Nominal output power, POUT = 8W
START UP BIAS RESISTOR
During start up, the VCC will be powered by the rectified line
voltage through external resistor, R1. The VCC start up current,
IVCC(SU) must set in the range IVCC(MIN)>IVCC(SU)>ISTARTUP
(MAX) to ensure proper restart operation during OVP fault. In
this example, a value of 0.55mA is suggested. The resistance
of R1 can be calculated by dividing the nominal input voltage
in RMS by the start up current suggested.
So, R1 = 110V/0.55mA = 200KΩ is recommended.
TRANSFORMER PRIMARY
INDUCTANCE
The primary inductance, LP of the transformer is related to the
minimum operating switching frequency fSW, converter output
power POUT, system efficiency η and minimum input line volt-
age VAC_RMS(MIN). For CRM operation, the output power,
POUT can be described by the equation in below.
TRANSFORMER TURN RATIO
The transformer winding turn ratio, n is governed by the in-
ternal MOSFET Q1 maximum rated voltage, (VQ3(MAX)), high-
est line input peak voltage (VAC-PEAK) and output diode
maximum reverse voltage rating (VD3(MAX)). The output diode
rating limits the lower bound of the turn ratio and the internal
power MOSFET rating provide the upper bound of the turn
ratio. The transformer turn ratio must be selected in between
the bounds. If the maximum reverse voltage of D3 (VD3(MAX)
)
is 100V. the minimum transformer turn ratio can be calculated
with the equation in below.
By re-arranging terms, the transformer primary inductance
required in this design example can be calculated with the
equation follows:
In operation, the voltage at the switching node, VSW must be
small than the internal MOSFET maximum rated voltage VQ1
, For reason of safety, 10% safety margin is recom-
m(MeAXn)ded. Hence, 90% of VQ1(MAX) is used in the following
equation.
The converter minimum switching frequency is 75kHz, tON is
5.3µs, VAC_RMS(MIN) = 85V and POUT = 8W, assume the system
efficiency, η = 85%. Then,
From the calculation in above, the inductance of the primary
winding required is 0.81mH.
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12
As a result, R2 is 66kΩ and R3 is 11kΩ. Also, for suppressing
high frequency noise at the ZCD pin, a 15pF capacitor con-
nects the ZCD pin to ground is recommended.
Calculate The Current Sensing
Resistor
After the primary inductance and transformer turn ratio is de-
Auxiliary Winding Vcc Diode
Selection
The VCC diode D2 provides the supply current to the con-
verter, low temperature coefficient , low reverse leakage and
ultra fast diode is recommended.
termined, the current sensing resistor, RISNS can be calculat-
ed.
The resistance for RISNS is governed by the output current and
transformer turn ratio, the equation in below can be used.
Compensation Capacitor And Delay
Timer Resistor Selection
To achieve PFC function with a constant on time flyback con-
verter, a low frequency response loop is required. In most
applications, a 3.3µF CCOMP capacitor is suitable for compen-
sation.
where VREF is fixed to 0.14V internally.
Transformer turn ratio, NP : NS is 3.8 : 1 and ILED = 0.35A
30188071
30188074
FIGURE 9. RISNS Resistor Interface
FIGURE 11. Compensation and DLY Timer connection
The resistor RDLY connecting the DLY pin to ground is used
to set the delay time between the ZCD trigger to power MOS-
FET turn on. The delay time required can be calculated with
the parasitic capacitance at the drain of MOSFET to ground
and primary inductance of the transformer. Equation in below
can be used to find the delay time and Figure 6 in previous
page can help to find the resistance once the delay time is
calculated
30188072
For example, using a transformer with primary inductance
LP = 1mH, and power MOSFET drain to ground capacitor
CDS=37pF, the tDLY can be calculated by the upper equation.
As a result, tDLY=302ns and RDLY is 6.31kΩ. The delay time
may need to change according to the primary inductance of
the transformer. The typical level of output current will shift if
inappropriate delay time is chosen.
FIGURE 10. Auxiliary Winding Interface to ZCD
Auxiliary Winding Interface To ZCD
In Figure 10, R2 and R3 forms a resistor divider which sets
the thresholds for over voltage protection of VLED, VZCD-OVP
and VZCD-PEAK. Before the calculation, we need to set the
voltage of the auxiliary winding, VLAUX at open circuit.
,
Output Flywheel Diode Selection
To increase the overall efficiency of the system, a low forward
voltage schottky diode with appropriate rating should be used.
For example :
Assume the nominal forward voltage of LED stack (VLED) is
21V.
To avoid false triggering ZCDOVP voltage threshold at normal
operation, select ZCDOVP voltage at 1.3 times of the VLED is
typical in most applications. In case the transformer leakage
is higher, the ZCDOVP threshold can be set to 1.5 times of the
Primary Side Snubber Design
The leakage inductance can induce a high voltage spike when
power MOSFET is turned off. Figure 12 illustrate the opera-
tion waveform. A voltage clamp circuit is required to protect
VLED
.
In this design example, open circuit AUX winding OVP voltage
threshold is set to 30V. Assume the current through the AUX
winding is 0.4mA typical.
the power MOSFET. The voltage of snubber clamp (VSN)
must be higher than the sum of over shoot voltage (VOS), LED
open load voltage multiplied by the transformer turn ratio (n).
In this examples, the VOS is 50V and LED maximum voltage,
13
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VLED(MAX) is 30V, transformer turn ratio is 3.8. The snubber
voltage required can be calculated with following equations.
Output Capacitor
The capacitance of the output capacitor is determined by the
equivalent series resistance (ESR) of the LED, RLED and the
ripple current allowed for the application. The equation in be-
low can be used to calculate the required capacitance.
Assume the ESR of the LED stack contains 7 LEDs and is
2.6Ω, AC line frequency fAC is 60Hz.
30188022
In this example, LED current ILED is 350mA and output ripple
FIGURE 12. Snubber Waveform
current is 30% of ILED
:
where n is the turn ratio of the transformer.
Then, COUT = 480μF.
In here, a 470μF output capacitor with 10μF ceramic capacitor
At the same time, sum of the snubber clamp voltage and
VAC peak voltage (VAC_PEAK) must be smaller than the MOS-
FET breakdown voltage (VMOS_BV). By re-arranging terms,
equation in below can be used.
in parallel is suggested.
PCB Layout Considerations
The performance of any switching power supplies depend as
much upon the layout of the PCB as the component selection.
Good layout practices are important when constructing the
PCB. The layout must be as neat and compact as possible,
and all external components must be as close as possible to
their associated pins. High current return paths and signal re-
turn paths must be separated and connect together at single
ground point. All high current connections must be as short
and direct as possible with thick traces. The SW pin of the
internal MOSFET should be connected close to the trans-
former pin with short and thick trace to reduce potential elec-
tro-magnetic interference. For off-line applications, one more
consideration is the safety requirements. The clearance and
creepage to high voltage traces must be complied to all ap-
plicable safety regulations.
In here, snubber clamp voltage, VSN = 250V is recommended.
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14
30188082
FIGURE 13. Isolated topology schematic
30188081
FIGURE 14. Non-isolated topology schematic
15
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Physical Dimensions inches (millimeters) unless otherwise noted
MSOP-16 Pin Package (mm)
For Ordering, Refer to Ordering Information Table
NS Package Number M16A
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16
Notes
17
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Notes
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