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TPS92411DBVT [TI]

适用于 LED 离线交流线性直接驱动的浮动开关，具有低纹波电流 | DBV | 5 | -40 to 150;
TPS92411DBVT
型号： TPS92411DBVT
厂家： TEXAS INSTRUMENTS    TEXAS INSTRUMENTS
描述：

适用于 LED 离线交流线性直接驱动的浮动开关，具有低纹波电流 | DBV | 5 | -40 to 150

开关 驱动
文件： 总32页 (文件大小：2094K)
中文：  中文翻译
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TPS92411, TPS92411P  
ZHCSBQ3B –OCTOBER 2013–REVISED JULY 2014  
TPS92411x 用于对具有低纹波电流的发光二极管 (LED) 进行离线交流线性  
直接驱动的浮动开关  
1 特性  
器件信息(1)  
1
•
•
通过交流电源驱动 LED 的高性能解决方案  
部件号  
封装  
封装尺寸（标称值）  
2.90mm x 1.60mm  
4.89mm x 3.90mm  
用高功率因数、低总谐波失真和低电流纹波简化相  
位可调光 LED 驱动器的设计  
SOT-23 (5)  
SO PowerPAD (8)  
TPS92411，TPS92  
411P  
•
•
•
适用于功率高达 70W 以上的 LED 光源  
输入电压范围：7.5V 至 100V  
(1) 如需了解所有可用封装，请见数据表末尾的可订购产品附录。  
可堆叠 100V，2Ω 金属氧化物半导体场效应晶体管  
(MOSFET) 构造块  
VIN  
DRAIN  
•
受控开关打开和关闭转换最大限度减少了电磁干扰  
(EMI)  
TPS92411  
120 VRMS  
RSET  
RSNS  
•
•
•
•
专用于与 TPS92410 或离散线性稳压器配套使用  
输入欠压保护  
±
+
VS  
输出过压保护 (TPS92411P)  
低 IQ：200µA（典型值）  
VIN  
DRAIN  
VS  
2 应用  
TPS92411  
•
•
•
LED 灯和灯泡  
RSET  
RSNS  
LED 光源  
射灯  
3 说明  
VIN  
DRAIN  
VS  
TPS92411 是一款在离线 LED 照明应用中使用的  
100V 浮动 MOSFET 开关。 该器件与能够实现功率因  
数大于 0.9 的电流稳压器一同使用，从而构建具有低纹  
波电流的 LED 驱动解决方案。 当设计正确时，解决方  
案性能与基于传统反激式降压或升压的交流/直流 LED  
驱动器类似。 此方法无需电感器元件，因此减小了尺  
寸并节约了成本。 TPS92411 开关的受控转换式低频  
操作可产生超低的 EMI。 详细操作，请参见 应用信息  
部分中说明。  
TPS92411  
RSET  
RSNS  
封装选项包括小外形尺寸晶体管 (SOT)23-5 和 PSOP-  
8，这使得用户能够针对小尺寸进行优化，或针对高功  
率进行缩放。 利用 PSOP-8 封装，LED 光源的设计有  
可能高达 70W 或更高。 其他特性包括用于监控器件何  
时具有正常运转所需的足够电压的欠压闭锁 (UVLO) 电  
路，以及过压保护功能 (TPS92411P)。  
1
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not necessarily include testing of all parameters.  
English Data Sheet: SLUSBQ6  
 
 
 
 
 
TPS92411, TPS92411P  
ZHCSBQ3B –OCTOBER 2013–REVISED JULY 2014  
www.ti.com.cn  
目录  
7.3 Feature Description................................................... 9  
7.4 Device Functional Modes........................................ 10  
Application and Implementation ........................ 11  
8.1 Application Information............................................ 11  
8.2 Typical Application .................................................. 12  
Power Supply Recommendations...................... 18  
1
2
3
4
5
6
特性.......................................................................... 1  
应用.......................................................................... 1  
说明.......................................................................... 1  
修订历史记录 ........................................................... 2  
Pin Configuration and Functions......................... 3  
Specifications......................................................... 3  
6.1 Absolute Maximum Ratings ...................................... 3  
6.2 Handling Ratings....................................................... 3  
6.3 Recommended Operating Conditions....................... 4  
6.4 Thermal Information ................................................. 4  
6.5 Electrical Characteristics.......................................... 4  
6.6 Typical Characteristics.............................................. 6  
Detailed Description .............................................. 8  
7.1 Overview ................................................................... 8  
7.2 Functional Block Diagram ......................................... 8  
8
9
10 Layout................................................................... 18  
10.1 Layout Guidelines ................................................. 18  
10.2 Layout Example .................................................... 18  
11 器件和文档支持 ..................................................... 19  
11.1 相关链接................................................................ 19  
11.2 商标....................................................................... 19  
11.3 静电放电警告......................................................... 19  
11.4 术语表 ................................................................... 19  
12 机械封装和可订购信息 .......................................... 19  
7
4 修订历史记录  
Changes from Revision A (May 2014) to Revision B  
Page  
•
已添加 添加了引脚配置和功能部分，处理额定值表、特性描述部分，器件功能模式，应用和实施部分，电源相关建议  
部分，布局部分，器件和文档支持部分以及机械、封装和可订购信息部分............................................................................. 1  
Changes from Original (October 2013) to Revision A  
Page  
•
•
Deleted preview designation for DDA package...................................................................................................................... 3  
Added availablity information for DDA package..................................................................................................................... 3  
2
Copyright © 2013–2014, Texas Instruments Incorporated  
 
TPS92411, TPS92411P  
www.ti.com.cn  
ZHCSBQ3B –OCTOBER 2013–REVISED JULY 2014  
5 Pin Configuration and Functions  
DBV (SOT23-5) PACKAGE  
5 PIN  
DDA (SO-8 Power-Pad) PACKAGE  
8 PIN  
(TOP VIEW)  
(TOP VIEW)  
VIN  
N/C  
1
2
3
4
8
7
6
5
DRAIN  
N/C  
RSET  
VS  
1
2
3
5
4
RSNS  
RSET  
VS  
N/C  
RSNS  
VIN  
DRAIN  
Pin Functions  
PIN  
NO.  
I/O  
O
DESCRIPTION  
NAME  
DDA  
DBV  
DRAIN  
N/C  
N/C  
N/C  
VIN  
8
2
6
7
1
4
4
Drain of the internal switch.  
Not internally connected.  
—
—
3
2
I
Positive power supply for the device.  
VS  
I/O  
Source of the internal switch. This pin is also the device floating ground.  
A resistor connected between the RSET pin and the VIN pin sets the rising  
threshold to open the switch.  
RSET  
RSNS  
3
5
1
5
I/O  
I/O  
A resistor connected between the RSNS pin to system ground senses the VS  
voltage relative to system ground.  
Exposed Themal Pad  
Connect to VS pin directly beneath the device.  
6 Specifications  
6.1 Absolute Maximum Ratings  
All voltages are with respect to VS, –40 °C < TJ = TA ≤ 150 °C. All currents are positive into and negative out of the specified  
terminal (unless otherwise noted).  
MIN  
–0.3  
–0.3  
–40  
MAX  
105  
105  
165  
UNIT  
V
Supply voltage  
VIN  
Switch voltage  
DRAIN  
TJ  
Junction temperature  
ºC  
6.2 Handling Ratings  
MIN  
–65  
MAX  
UNIT  
Tstg  
Storage temperature range  
150  
°C  
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all  
pins(1)  
1
kV  
V
V(ESD)  
Electrostatic discharge  
Charged device model (CDM), per JEDEC specification  
JESD22-C101, all pins(2)  
250  
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.  
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.  
Copyright © 2013–2014, Texas Instruments Incorporated  
3
TPS92411, TPS92411P  
ZHCSBQ3B –OCTOBER 2013–REVISED JULY 2014  
www.ti.com.cn  
6.3 Recommended Operating Conditions  
Over operating free-air temperature range (unless otherwise noted)  
MIN  
7.5  
TYP  
MAX  
UNIT  
V
TPS92411P  
94  
100  
150  
VIN  
TJ  
Input voltage  
TPS92411  
7.5  
Operating junction temperature  
–40  
25  
°C  
6.4 Thermal Information  
TPS92411  
THERMAL METRIC(1)  
DBV  
DDA  
UNIT  
5 PINS  
209.8  
125.2  
38  
8 PINS  
58.6  
72  
θJA  
Junction-to-ambient thermal resistance(2)  
Junction-to-case (top) thermal resistance(3)  
Junction-to-board thermal resistance(4)  
Junction-to-top characterization parameter(5)  
Junction-to-board characterization parameter(6)  
Junction-to-case (bottom) thermal resistance(7)  
θJCtop  
θJB  
39.1  
21.6  
39.1  
15  
°C/W  
ψJT  
15.6  
37.1  
N/A  
ψJB  
θJCbot  
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.  
(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as  
specified in JESD51-7, in an environment described in JESD51-2a.  
(3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specified JEDEC-  
standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.  
(4) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB  
temperature, as described in JESD51-8.  
(5) The junction-to-top characterization parameter, θJT, estimates the junction temperature of a device in a real system and is extracted  
from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7).  
(6) The junction-to-board characterization parameter, θJB, estimates the junction temperature of a device in a real system and is extracted  
from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7).  
(7) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific  
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.  
6.5 Electrical Characteristics  
Unless otherwise specified –40 °C ≤ TJ = TA ≤ 150 °C, (VVIN – VVS) = 30 V, RRSET = RRSNS = Open, all voltages are with  
respect to VS.  
PARAMETER  
INPUT SUPPLY (VIN)  
TEST CONDITIONS  
MIN  
TYP  
MAX  
UNIT  
Rising threshold  
95  
100  
96  
Input overvoltage  
protection  
VIN(ovp)  
TPS92411P Falling threshold  
Hysteresis  
V
4
IQ  
Bias current  
200  
6.5  
370  
400  
7
μA  
V
VIN(uvlo)  
VIN(hys)  
Input undervoltage lockout  
Input UVLO hysteresis  
Rising threshold  
mV  
SWITCH CONTROL (RSNS, RSET)  
IRSNS RSNS threshold current  
VRSNS_OS RSNS offset voltage  
–3.3  
165  
–4  
210  
1.25  
–10  
–20  
–50  
–4.9  
255  
μA  
mV  
V
VRSET  
RSET threshold voltage  
1.2  
1.3  
IRSNS = –20 μA, (VRSET – VVS) = 1.5 V  
–9.3  
–19  
–10.7  
–21  
IRSET  
RSET current  
IRSNS = –40 μA, (VRSET – VVS) = 1.5 V  
IRSNS = –100 μA, (VRSET – VVS) = 1.5 V  
μA  
–47.9  
–52.1  
SWITCH (DRAIN, VS)  
RDS(on) On-resistance  
IDRAIN = 100 mA, TJ = 25°C  
1
2
2.5  
Ω
4
版权 © 2013–2014, Texas Instruments Incorporated  
TPS92411, TPS92411P  
www.ti.com.cn  
ZHCSBQ3B –OCTOBER 2013–REVISED JULY 2014  
Electrical Characteristics (接下页)  
Unless otherwise specified –40 °C ≤ TJ = TA ≤ 150 °C, (VVIN – VVS) = 30 V, RRSET = RRSNS = Open, all voltages are with  
respect to VS.  
PARAMETER  
TEST CONDITIONS  
MIN  
TYP  
MAX  
UNIT  
(VDRAIN – VVS) falling 36 V to 4 V,  
ISW = 100 mA  
1
dv/dt(ON)  
Switch ON slew rate  
V/μs  
(VDRAIN – VVS) = rising 4 V to 36 V,  
ISW = 100 mA  
0.5  
dv/dt(OFF) Switch OFF slew rate  
版权 © 2013–2014, Texas Instruments Incorporated  
5
TPS92411, TPS92411P  
ZHCSBQ3B –OCTOBER 2013–REVISED JULY 2014  
www.ti.com.cn  
6.6 Typical Characteristics  
Unless otherwise stated, –40 °C ≤ TA = TJ ≤ 150 °C, (VVIN – VVS) = 30 V, all voltages are with respect to VS.  
10  
8
10  
8
6
6
4
4
2
2
0
0
−40 −25 −10  
5
20 35 50 65 80 95 110 125 140 155  
Junction Temperature (°C)  
−40 −25 −10  
5
20 35 50 65 80 95 110 125 140 155  
Junction Temperature (°C)  
G000  
G001  
图 1. UVLO vs. Temperature  
图 2. UVLO vs. Temperature  
2
1.8  
1.5  
1.2  
1
0
−2  
−4  
−6  
0.8  
0.5  
0.2  
0
−8  
−10  
−40 −25 −10  
5
20 35 50 65 80 95 110 125 140 155  
−40 −25 −10  
5
20 35 50 65 80 95 110 125 140 155  
Junction Temperature (°C)  
Junction Temperature (°C)  
G002  
G003  
图 3. RSET Threshold vs. Temperature  
图 4. RSNS Threshold Current vs. Temperature  
5
4
3
2
1
0
200  
180  
160  
140  
120  
100  
−40 −25 −10  
5
20 35 50 65 80 95 110 125 140 155  
−40 −25 −10  
5
20 35 50 65 80 95 110 125 140 155  
Junction Temperature (°C)  
Junction Temperature (°C)  
G004  
G005  
图 5. Switch On-Resistance (RDS(on)) vs. Temperature  
图 6. Input Voltage Quiescent Current vs. Temperature  
6
版权 © 2013–2014, Texas Instruments Incorporated  
TPS92411, TPS92411P  
www.ti.com.cn  
ZHCSBQ3B –OCTOBER 2013–REVISED JULY 2014  
Typical Characteristics (接下页)  
Unless otherwise stated, –40 °C ≤ TA = TJ ≤ 150 °C, (VVIN – VVS) = 30 V, all voltages are with respect to VS.  
110  
106  
102  
98  
94  
TPS92411P  
90  
−40 −25 −10  
5
20 35 50 65 80 95 110 125 140 155  
Junction Temperature (°C)  
G006  
图 7. (VVIN – VVS) Overvoltage Threshold vs. Temperature  
版权 © 2013–2014, Texas Instruments Incorporated  
7
TPS92411, TPS92411P  
ZHCSBQ3B –OCTOBER 2013–REVISED JULY 2014  
www.ti.com.cn  
7 Detailed Description  
7.1 Overview  
The TPS92411 is an advanced, floating driver specifically designed for use with a linear regulator in low-power  
offline LED lighting applications. It integrates an on-board 100-V MOSFET switch to shunt LED current as the  
line transitions. As the line transitions through the cycle, the device monitors critical nodes for zero cross at which  
time the internal switch is either opened or shorted to steer the current through or away from the LED stack. The  
TPS92411 does not directly control output power or LED current, it just directs current to the LED stack or  
bypasses the LED stack.  
7.2 Functional Block Diagram  
VIN  
DRAIN  
TPS92411  
5 0Ÿꢀ  
VCC  
VDD  
VDD  
Buffer  
Reference  
RSET  
+
12 V  
±
+
UVLO  
VIN UVLO  
6.5 V/6.13 V  
+
1.25 V  
VS  
±
1x  
1x  
2x  
1x  
VCC  
UVLO  
VS  
2 Ÿꢀ  
1x  
R
S
OV  
210 mV  
Q
+
Set dominant  
+
2 µA  
±
VS  
VS  
RSNS  
VS  
图 8. TPS92411 Block Diagram  
8
版权 © 2013–2014, Texas Instruments Incorporated  
TPS92411, TPS92411P  
www.ti.com.cn  
ZHCSBQ3B –OCTOBER 2013–REVISED JULY 2014  
Functional Block Diagram (接下页)  
VIN  
DRAIN  
TPS92411P  
3.95 0Ÿꢀ  
5 0Ÿꢀ  
OV  
+
VCC  
VDD  
VDD  
Buffer  
Reference  
50 NŸꢀ  
RSET  
+
12 V  
+
±
+
UVLO  
1.25 V  
VCC  
VIN UVLO  
6.5 V/6.13 V  
±
+
1.25 V  
VS  
±
1x  
1x  
2x  
1x  
VS  
VS  
UVLO  
VS  
2 Ÿꢀ  
1x  
210 mV  
R
S
OV  
Q
+
Set dominant  
+
2 µA  
±
VS  
VS  
RSNS  
VS  
图 9. TPS92411P Block Diagram  
7.3 Feature Description  
7.3.1 Overvoltage Protection (OVP)  
Overvoltage protection (OVP) in the TPS92411P version protects the device as well as the LEDs and storage  
capacitor. The OVP is set at approximately 100 V (VVIN – VVS) and closes the internal switch when the threshold  
voltage is reached. For this reason LED stack voltages of 94 V or less are recommended. Higher voltages can  
be used with the TPS92411 version but tolerances must be considered to ensure that the 105 V absolute  
maximum rating is not exceeded.  
7.3.2 Input Undervoltage Lockout (UVLO)  
The TPS92411 includes input UVLO. The UVLO prevents the device from operation until the VIN pin voltage with  
respect to VS exceeds 6.5 V and ensures the device behaves properly when enabled.  
7.3.3 LED Capacitor  
A capacitor is required across each LED stack to provide current to the LEDs during the switch ON time. Refer to  
the available calculator software (SLVC516 for 120-V applications or SLVC517 for 230-V applications) for  
calculating the minimum value required for any particular application. The software calculates the minimum value  
required for a particular application, but best performance is acheived by using as much capacitance as possible  
given size and cost constraints. These design tools also calculate a minimum value for any given current ripple  
percent or flicker index desired for the particular application.  
7.3.4 Blocking Diode  
A blocking diode is required between the drain of the switch (DRAIN) and the anode of the LED stack. This  
prevents the LED capacitor from discharging through the switch during the switch ON time instead allowing it to  
discharge through the LED stack. This diode should be rated for 200 V reverse voltage and capable of forward  
currents as high as the average linear regulator current setting.  
版权 © 2013–2014, Texas Instruments Incorporated  
9
TPS92411, TPS92411P  
ZHCSBQ3B –OCTOBER 2013–REVISED JULY 2014  
www.ti.com.cn  
7.4 Device Functional Modes  
The TPS92411P has 4 functional modes while the TPS92411 has 3:  
7.4.1 Input UVLO  
As described in the previous section the device and internal switch will remain off until VIN is 6.5V or greater with  
respect to VS.  
7.4.2 Operating with Internal Switch ON  
After the device crosses the UVLO threshold the internal switch will turn on and remain on until the voltage at the  
VIN pin exceeds the threshold voltage set by the RSET resistor.  
7.4.3 Operating with Internal Switch OFF  
When the RSET threshold voltage is exceeded on the VIN pin the internal switch will turn off forcing all the  
current to flow through the LEDs and charge the LED capacitor. The switch will remain off until the VS pin drops  
below the threshold voltage set by RSNS or an overvoltage event occurs (TPS92411P only).  
7.4.4 Overvoltage Operation (TPS92411P)  
If an LED fails open or a string voltage exceeding the OVP level is used the device will enter OVP operation. The  
internal switch will close and remain closed until the VIN voltage with respect to the VS pin drops low enough to  
engage normal operation again.  
10  
版权 © 2013–2014, Texas Instruments Incorporated  
TPS92411, TPS92411P  
www.ti.com.cn  
ZHCSBQ3B –OCTOBER 2013–REVISED JULY 2014  
8 Application and Implementation  
8.1 Application Information  
The TPS92411 is an advanced, floating driver specifically designed for use with a linear regulator in low-power  
offline LED lighting applications. It integrates an on-board 100-V MOSFET switch to shunt LED current as the  
line transitions. As the line transitions through the cycle, the device monitors critical nodes for zero cross at which  
time the internal switch is either opened or shorted to steer the current through or away from the LED stack. Use  
the following design procedure to select components for the TPS92411. The following calculators may also be  
used to select components for the TPS92411:  
•
•
•
•
SLVC579 for 120-V applications using the TPS92410  
SLVC580 for 230-V applications using the TPS92410  
SLVC516 for 120-V applications using a discrete linear regulator  
SLVC517 for 230-V applications using a discrete linear regulator  
PSpice and TINA-TI models are also available. The following are typical applications using the TPS92411 for  
both 120-V and 230-V applications using a discrete linear regulator.  
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11  
TPS92411, TPS92411P  
ZHCSBQ3B –OCTOBER 2013–REVISED JULY 2014  
www.ti.com.cn  
8.2 Typical Application  
8.2.1 120-VAC, Phase Dimmable 11.5-W Input with Discrete Linear Regulator  
22 Ÿꢀ  
200 V  
VIN  
DRAIN  
120 VRMS  
1.82 0Ÿꢀ  
1 0Ÿꢀ  
TPS92411  
±
+
RSET  
RSNS  
33 µF  
100 V  
VS  
200 V  
VIN  
DRAIN  
VS  
1.65 0Ÿꢀ  
1 0Ÿꢀ  
TPS92411  
0.22 µF  
250 V  
68 µF  
50 V  
RSET  
RSNS  
0.1 µF  
250 V  
442 Ÿꢀ  
200 V  
VIN  
DRAIN  
VS  
1.43 0Ÿꢀ  
1 0Ÿꢀ  
TPS92411  
120 µF  
25 V  
RSET  
RSNS  
200 NŸꢀ  
499 NŸꢀ  
91 V  
90.9 NŸꢀ  
Q1  
732 NŸꢀ  
2 0Ÿꢀ  
600 V  
2 A  
12 V  
0.01 µF  
0.22 µF  
Q2  
200 mW  
44.2 NŸꢀ  
RCS  
24 Ÿꢀ  
5 NŸꢀ  
1 NŸꢀ  
0.1 µF  
图 10. 120-VAC, Phase Dimmable 11.5-W Input with Discrete Linear Regulator  
8.2.1.1 Design Requirements  
For the 120-V application shown in 图 10 the highest efficiency is obtained by using a high-voltage total LED  
stack to reduce losses in the linear regulator FET. The best current sharing efficiency between stacks can be  
achieved by using the lowest voltage stack at the bottom and making each stack voltage above 2 times the  
voltage of the stack below it. In this example 20-V LEDs are used. This effectively gives the lowest stack a total  
of 20 V, the middle stack a total of 40 V, and the upper stack a total of 80 V. The RSNS resistor is used to set a  
12  
版权 © 2013–2014, Texas Instruments Incorporated  
 
TPS92411, TPS92411P  
www.ti.com.cn  
ZHCSBQ3B –OCTOBER 2013–REVISED JULY 2014  
Typical Application (接下页)  
low voltage point so that when the VS pin voltage falls below this threshold (either from the AC line falling or a  
higher voltage stack switch above it turning OFF) the TPS92411 switch turns ON and bypasses the LEDs. During  
the ON-time, the LEDs are supplied current from the capacitor. The RSET voltage is used to set a threshold to  
detect when the input voltage crosses this threshold it turns OFF the switch and allows the LEDs to conduct  
current from the line and charge the bypass capacitor.  
8.2.1.2 Detailed Design Procedure  
•
•
•
•
Set VRSNS for all three TPS92411 devices at 4 V  
Set VRSET for the bottom stack at 26 V (20 V stack plus 6 V headroom)  
Set VRSET for the middle stack at 46 V (40 V stack plus 6 V headroom)  
Set VRSET for the top stack at 86 V (80 V stack plus 6 V headroom)  
Switching order as the rectified AC line voltage increases is shown in 表 1. 图 11 illustrates when each switch  
turns ON or OFF.  
8.2.1.2.1 Setting the Switching Thresholds (RSNS, RSET)  
The TPS92411 features two threshold settings to allow for proper LED control. The first setting determines when  
the internal switch turns off and allows current to charge the capacitor and flow through the LEDs. The second  
setting determines when the switch turns on to shunt the LEDs and allow the capacitor to supply current. The  
lower switch turn-on threshold (VSNS) should be set first using a resistor (RRSNS) from the RSNS pin to system  
ground. For best efficiency set this threshold between 4 V and 6 V. Then the upper switch turn-off threshold (VVS  
)
can be set using a resistor (RRSET) from the RSET pin to the VIN pin. Set this threshold approximately 6 V to 10  
V above the LED stack voltage (VLED). The RSET threshold should be greater than the LED stack voltage plus  
the value of the RSNS threshold to prevent errant switching. These thresholds can be set with resistance  
calculated using 公式 1 and 公式 2.  
VSNS + 0.21V  
RSNS  
=
IRSNS  
(1)  
(2)  
V
-1.24V ´ 2´R  
)
+ 0.21V  
(
LED  
SNS  
R
=
RSET  
V
VS  
(1)(2)  
表 1. Switching Order on Rising Edge of Rectified 120-VAC  
STACK  
TOP 80-V  
MIDDLE 40-V  
BOTTOM 20-V  
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
(1) 0 denotes switch ON and LEDs bypassed and supplied by the capacitor.  
(2) 1 denotes switch OFF and LEDs conducting from the line, capacitor charging up.  
版权 © 2013–2014, Texas Instruments Incorporated  
13  
 
 
 
TPS92411, TPS92411P  
ZHCSBQ3B –OCTOBER 2013–REVISED JULY 2014  
www.ti.com.cn  
Voltage trip points do not  
include diode drops  
146  
126  
106  
86  
111  
110  
144  
124  
104  
84  
110  
101  
100  
011  
010  
001  
000  
101  
100  
66  
011  
64  
010  
46  
44  
26  
001  
000  
24  
Time  
图 11. Switching Order on Rectified 120-VAC Waveform  
The linear regulator in 图 11 generates a current sense RMS voltage of approximately 2.3 V. The linear regulator  
RMS current is equal to the input current drawn from the AC line. For example, for a 11.5-W input power system  
the input current should be approximately 0.095 A and a 24-Ω resistor should be chosen for RCS. Other input  
power levels (PIN) can be obtained using 公式 3.  
120V  
´ 2.3V  
RMS  
RMS  
R
=
CS  
P
IN  
(3)  
8.2.1.3 Application Curve  
1.00  
0.99  
0.98  
0.97  
0.96  
0.95  
0.94  
0.93  
0.92  
0.91  
0.90  
190  
200  
210  
220  
230  
240  
250  
260  
Input Voltage (VAC)  
C001  
图 12. Power Factor vs. Input Voltage  
14  
版权 © 2013–2014, Texas Instruments Incorporated  
 
 
TPS92411, TPS92411P  
www.ti.com.cn  
ZHCSBQ3B –OCTOBER 2013–REVISED JULY 2014  
8.2.2 230-VAC, Phase Dimmable 16-W Input with Discrete Linear Regulator  
200 V  
1 0Ÿꢀ  
Q3  
200 V  
1 NŸꢀ  
680 pF  
VGS = 4 V  
10 NŸꢀ  
22 µF  
200 V  
68 Ÿꢀ  
VIN  
DRAIN  
TPS92411  
230 VRMS  
2.8 0Ÿꢀ  
1.5 0Ÿꢀ  
0.1 µF  
100 V  
12 V 12 V  
±
+
RSET  
RSNS  
VS  
200 V  
47 µF  
100 V  
VIN  
DRAIN  
VS  
2.67 0Ÿꢀ  
1.5 0Ÿꢀ  
TPS92411  
0.15 µF  
400 V  
RSET  
RSNS  
0.033 µF  
400 V  
550 Ÿꢀ  
200 V  
VIN  
DRAIN  
2.37 0Ÿꢀ  
1.5 0Ÿꢀ  
TPS92411  
100 µF  
50 V  
RSET  
RSNS  
VS  
442 NŸꢀ  
1 0Ÿꢀ  
100 NŸꢀ  
68 V  
100 NŸꢀ  
Q1  
600 V  
2 A  
12 V  
0.022 µF  
0.22 µF  
0.1 µF  
200 mW  
Q2  
RCS  
34.8 Ÿꢀ  
4.99 NŸꢀ  
10 NŸꢀ  
249 NŸꢀ  
图 13. 230-VAC, Phase Dimmable 16-W Input with Discrete Linear Regulator  
8.2.2.1 Design Requirements  
In the 230-V application shown in 图 13, the highest efficiency can be obtained by using a high-voltage total LED  
stack to reduce losses in the linear regulator FET. The best current sharing between stacks can be achieved by  
using the lowest voltage stack at the bottom and making each stack voltage above that two times that of the  
stack below it (as in described in the 120-V application). In this example, very good results can be obtained by  
setting the lowest stack at 40 V, the middle stack at 80 V, and adding a high-voltage cascode FET with the top  
stack and using 160 V. Use the RSNS pin to set a low voltage point so that when the VS pin of the device falls  
版权 © 2013–2014, Texas Instruments Incorporated  
15  
 
TPS92411, TPS92411P  
ZHCSBQ3B –OCTOBER 2013–REVISED JULY 2014  
www.ti.com.cn  
below this threshold (either from the AC line falling or a higher voltage stack switch above it turning OFF) the  
TPS92411 switch turns ON and bypasses the LEDs. During the ON-time, the capacitor supplies current to the  
LEDs. The RSET voltage threshold for a 230-V application is generally set to approximately 8 V to 12 V above  
the LED stack voltage connected across the TPS92411 (for an RSNS voltage of 6 V). This threshold is higher  
than in the typical 120-V application to allow more headroom.  
8.2.2.2 Detailed Design Procedure  
•
•
•
•
Set VRSNS for all three TPS92411 devices at 6 V  
Set VRSET for the bottom stack at 49 V (40 V stack plus 9 V headroom)  
Set VRSET for the middle stack at 89 V (80 V stack plus 9 V headroom)  
Set VRSET for the top stack at 169 V (160 V stack plus 9 V headroom)  
Switching order as the rectified AC line voltage increases is shown in 表 2. 图 14 illustrates when each switch  
turns ON or OFF.  
表 2. Switching Order on Rising Edge of the Rectified 230-VAC Waveform(1)(2)  
STACK  
TOP 160-V  
MIDDLE 80-V  
BOTTOM 40-V  
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
(1) 0 denotes switch ON and LEDs bypassed and supplied by the capacitor.  
(2) 1 denotes switch OFF and LEDs conducting from the line, capacitor charging up.  
Voltage trip points do not  
include diode drops  
289  
249  
209  
169  
129  
89  
111  
110  
286  
246  
206  
166  
126  
86  
110  
101  
100  
011  
010  
001  
000  
101  
100  
011  
010  
001  
000  
49  
46  
Time  
图 14. Switching Order on Rising Edge of the Rectified 230-VAC Waveform  
The linear regulator in 图 14 generates a current sense RMS voltage of 2.44 V. The linear regulator RMS current  
is equal to the input current drawn from the AC line. For example, for a 16-W input power system the input  
current should be approximately 0.07 A and a 34.8-Ω resistor should be chosen for RCS. Other input power levels  
(PIN) can be calculated using 公式 4.  
230V  
´ 2.44V  
RMS  
RMS  
R
=
CS  
P
IN  
(4)  
16  
版权 © 2013–2014, Texas Instruments Incorporated  
 
 
 
TPS92411, TPS92411P  
www.ti.com.cn  
ZHCSBQ3B –OCTOBER 2013–REVISED JULY 2014  
8.2.2.3 Application Curve  
1.00  
0.99  
0.98  
0.97  
0.96  
0.95  
0.94  
0.93  
0.92  
0.91  
0.90  
190  
200  
210  
220  
230  
240  
250  
260  
Input Voltage (VAC)  
C001  
图 15. Power Factor Input Voltage  
版权 © 2013–2014, Texas Instruments Incorporated  
17  
TPS92411, TPS92411P  
ZHCSBQ3B –OCTOBER 2013–REVISED JULY 2014  
www.ti.com.cn  
9 Power Supply Recommendations  
For testing purposes any benchtop adjustable AC power supply with a power rating higher than what is required  
by the circuit is suitable. An example would be an Hewlett Packard 6811B or equivalent. An isolated supply is  
recommended for safety purposes.  
10 Layout  
10.1 Layout Guidelines  
The TPS92411 allows for a simple layout, however some considerations should be taken. The RSET resistor  
should be connected directly between the RSET pin and VIN pin as close to the device as possible. The trace  
between the resistor and the RSET pin should be as short as possible. The trace from the RSNS pin to the  
RSNS resistor should also be as short as possible to minimize parasitic capacitances. The blocking diode should  
be placed between the DRAIN pin and the VIN pin and also located close to the device. Placement of the LED  
capacitor may depend on the physical design of the application, however it should be placed as close to the  
TPS92411 as the design allows to minimize parasitic inductances.  
10.2 Layout Example  
1-RSET 5-RSNS  
System  
GND  
LED-/VS  
2-VS  
3-VIN 4-DRAIN  
To rectified AC or VS of  
TPS92411 above  
LED+  
图 16. Recommended Component Placement (DBV)  
To rectified AC or VS of  
TPS92411 above  
LED+  
1-VIN  
8-DRAIN  
2-NC  
7-NC  
6-NC  
3-RSET  
System  
GND  
LED-/VS  
4-VS  
5-RSNS  
图 17. Recommended Component Placement (DDA)  
18  
版权 © 2013–2014, Texas Instruments Incorporated  
TPS92411, TPS92411P  
www.ti.com.cn  
ZHCSBQ3B –OCTOBER 2013–REVISED JULY 2014  
11 器件和文档支持  
11.1 相关链接  
以下表格列出了快速访问链接。 范围包括技术文档、支持与社区资源、工具和软件，并且可以快速访问样片或购买  
链接。  
表 3. 相关链接  
部件  
产品文件夹  
请单击此处  
请单击此处  
样片与购买  
请单击此处  
请单击此处  
技术文档  
请单击此处  
请单击此处  
工具与软件  
请单击此处  
请单击此处  
支持与社区  
请单击此处  
请单击此处  
TPS92411  
TPS92411P  
11.2 商标  
All trademarks are the property of their respective owners.  
11.3 静电放电警告  
这些装置包含有限的内置 ESD 保护。 存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损  
伤。  
11.4 术语表  
SLYZ022 — TI 术语表。  
这份术语表列出并解释术语、首字母缩略词和定义。  
12 机械封装和可订购信息  
以下页中包括机械封装和可订购信息。 这些信息是针对指定器件可提供的最新数据。 这些数据会在无通知且不对  
本文档进行修订的情况下发生改变。 欲获得该数据表的浏览器版本，请查阅左侧的导航栏。  
版权 © 2013–2014, Texas Instruments Incorporated  
19  
PACKAGE OPTION ADDENDUM  
www.ti.com  
10-Dec-2020  
PACKAGING INFORMATION  
Orderable Device  
Status Package Type Package Pins Package  
Eco Plan  
Lead finish/  
Ball material  
MSL Peak Temp  
Op Temp (°C)  
Device Marking  
Samples  
Drawing  
Qty  
(1)  
(2)  
(3)  
(4/5)  
(6)  
TPS92411DBVR  
TPS92411DBVT  
TPS92411DDA  
ACTIVE  
ACTIVE  
SOT-23  
SOT-23  
DBV  
DBV  
DDA  
DDA  
DBV  
DBV  
DDA  
DDA  
5
5
8
8
5
5
8
8
3000 RoHS & Green  
NIPDAU  
Level-1-260C-UNLIM  
Level-1-260C-UNLIM  
Level-2-260C-1 YEAR  
Level-2-260C-1 YEAR  
Level-1-260C-UNLIM  
Level-1-260C-UNLIM  
Level-2-260C-1 YEAR  
Level-2-260C-1 YEAR  
-40 to 150  
-40 to 150  
-40 to 150  
-40 to 150  
-40 to 150  
-40 to 150  
-40 to 150  
-40 to 150  
PB9Q  
PB9Q  
92411  
92411  
PB8Q  
PB8Q  
250  
75  
RoHS & Green  
RoHS & Green  
NIPDAU  
NIPDAUAG  
NIPDAUAG  
NIPDAU  
ACTIVE SO PowerPAD  
ACTIVE SO PowerPAD  
TPS92411DDAR  
TPS92411PDBVR  
TPS92411PDBVT  
TPS92411PDDA  
TPS92411PDDAR  
2500 RoHS & Green  
3000 RoHS & Green  
ACTIVE  
ACTIVE  
SOT-23  
SOT-23  
250  
75  
RoHS & Green  
RoHS & Green  
NIPDAU  
ACTIVE SO PowerPAD  
ACTIVE SO PowerPAD  
NIPDAUAG  
NIPDAUAG  
92411P  
92411P  
2500 RoHS & Green  
(1) The marketing status values are defined as follows:  
ACTIVE: Product device recommended for new designs.  
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.  
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.  
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.  
OBSOLETE: TI has discontinued the production of the device.  
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance  
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may  
reference these types of products as "Pb-Free".  
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.  
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based  
flame retardants must also meet the <=1000ppm threshold requirement.  
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.  
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.  
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation  
of the previous line and the two combined represent the entire Device Marking for that device.  
Addendum-Page 1  
PACKAGE OPTION ADDENDUM  
www.ti.com  
10-Dec-2020  
(6)  
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two  
lines if the finish value exceeds the maximum column width.  
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information  
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and  
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.  
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.  
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.  
Addendum-Page 2  
PACKAGE MATERIALS INFORMATION  
www.ti.com  
5-Jan-2022  
TAPE AND REEL INFORMATION  
*All dimensions are nominal  
Device  
Package Package Pins  
Type Drawing  
SPQ  
Reel  
Reel  
A0  
B0  
K0  
P1  
W
Pin1  
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant  
(mm) W1 (mm)  
TPS92411DBVR  
TPS92411DBVT  
TPS92411DDAR  
SOT-23  
SOT-23  
DBV  
DBV  
DDA  
5
5
8
3000  
250  
178.0  
178.0  
330.0  
9.0  
9.0  
3.23  
3.23  
6.4  
3.17  
3.17  
5.2  
1.37  
1.37  
2.1  
4.0  
4.0  
8.0  
8.0  
8.0  
Q3  
Q3  
Q1  
SO  
Power  
PAD  
2500  
12.8  
12.0  
TPS92411PDBVR  
TPS92411PDBVT  
TPS92411PDDAR  
SOT-23  
SOT-23  
DBV  
DBV  
DDA  
5
5
8
3000  
250  
178.0  
178.0  
330.0  
9.0  
9.0  
3.23  
3.23  
6.4  
3.17  
3.17  
5.2  
1.37  
1.37  
2.1  
4.0  
4.0  
8.0  
8.0  
8.0  
Q3  
Q3  
Q1  
SO  
Power  
PAD  
2500  
12.8  
12.0  
Pack Materials-Page 1  
PACKAGE MATERIALS INFORMATION  
www.ti.com  
5-Jan-2022  
*All dimensions are nominal  
Device  
Package Type Package Drawing Pins  
SPQ  
Length (mm) Width (mm) Height (mm)  
TPS92411DBVR  
TPS92411DBVT  
TPS92411DDAR  
TPS92411PDBVR  
TPS92411PDBVT  
TPS92411PDDAR  
SOT-23  
SOT-23  
DBV  
DBV  
DDA  
DBV  
DBV  
DDA  
5
5
8
5
5
8
3000  
250  
180.0  
180.0  
366.0  
180.0  
180.0  
366.0  
180.0  
180.0  
364.0  
180.0  
180.0  
364.0  
18.0  
18.0  
50.0  
18.0  
18.0  
50.0  
SO PowerPAD  
SOT-23  
2500  
3000  
250  
SOT-23  
SO PowerPAD  
2500  
Pack Materials-Page 2  
PACKAGE MATERIALS INFORMATION  
www.ti.com  
5-Jan-2022  
TUBE  
*All dimensions are nominal  
Device  
Package Name Package Type  
Pins  
SPQ  
L (mm)  
W (mm)  
T (µm)  
B (mm)  
TPS92411DDA  
TPS92411PDDA  
DDA  
DDA  
HSOIC  
HSOIC  
8
8
75  
75  
517  
517  
7.87  
7.87  
635  
635  
4.25  
4.25  
Pack Materials-Page 3  
GENERIC PACKAGE VIEW  
DDA 8  
PowerPADTM SOIC - 1.7 mm max height  
PLASTIC SMALL OUTLINE  
Images above are just a representation of the package family, actual package may vary.  
Refer to the product data sheet for package details.  
4202561/G  
PACKAGE OUTLINE  
DBV0005A  
SOT-23 - 1.45 mm max height  
S
C
A
L
E
4
.
0
0
0
SMALL OUTLINE TRANSISTOR  
C
3.0  
2.6  
0.1 C  
1.75  
1.45  
1.45  
0.90  
B
A
PIN 1  
INDEX AREA  
1
2
5
(0.1)  
2X 0.95  
1.9  
3.05  
2.75  
1.9  
(0.15)  
4
3
0.5  
5X  
0.3  
0.15  
0.00  
(1.1)  
TYP  
0.2  
C A B  
NOTE 5  
0.25  
GAGE PLANE  
0.22  
0.08  
TYP  
8
0
TYP  
0.6  
0.3  
TYP  
SEATING PLANE  
4214839/G 03/2023  
NOTES:  
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing  
per ASME Y14.5M.  
2. This drawing is subject to change without notice.  
3. Refernce JEDEC MO-178.  
4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not  
exceed 0.25 mm per side.  
5. Support pin may differ or may not be present.  
www.ti.com  
EXAMPLE BOARD LAYOUT  
DBV0005A  
SOT-23 - 1.45 mm max height  
SMALL OUTLINE TRANSISTOR  
PKG  
5X (1.1)  
1
5
5X (0.6)  
SYMM  
(1.9)  
2
3
2X (0.95)  
4
(R0.05) TYP  
(2.6)  
LAND PATTERN EXAMPLE  
EXPOSED METAL SHOWN  
SCALE:15X  
SOLDER MASK  
OPENING  
SOLDER MASK  
OPENING  
METAL UNDER  
SOLDER MASK  
METAL  
EXPOSED METAL  
EXPOSED METAL  
0.07 MIN  
ARROUND  
0.07 MAX  
ARROUND  
NON SOLDER MASK  
DEFINED  
SOLDER MASK  
DEFINED  
(PREFERRED)  
SOLDER MASK DETAILS  
4214839/G 03/2023  
NOTES: (continued)  
6. Publication IPC-7351 may have alternate designs.  
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.  
www.ti.com  
EXAMPLE STENCIL DESIGN  
DBV0005A  
SOT-23 - 1.45 mm max height  
SMALL OUTLINE TRANSISTOR  
PKG  
5X (1.1)  
1
5
5X (0.6)  
SYMM  
(1.9)  
2
3
2X(0.95)  
4
(R0.05) TYP  
(2.6)  
SOLDER PASTE EXAMPLE  
BASED ON 0.125 mm THICK STENCIL  
SCALE:15X  
4214839/G 03/2023  
NOTES: (continued)  
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate  
design recommendations.  
9. Board assembly site may have different recommendations for stencil design.  
www.ti.com  
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