TPS92515AHV-Q1 [TI]
具有集成 NFET 的 65V 汽车类 2A 分流 PWM 可调光 LED 驱动器;
| 型号： | TPS92515AHV-Q1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有集成 NFET 的 65V 汽车类 2A 分流 PWM 可调光 LED 驱动器 驱动 驱动器 |
| 文件： | 总41页 (文件大小：2367K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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TPS92515AHV-Q1
ZHCSIY0 –OCTOBER 2018
具有集成 N 沟道 FET、高侧电流检测和分流 FET PWM 调光功能的
TPS92515AHV-Q1 2A 降压 LED 驱动器
1 特性
此稳压器具有恒定关断时间和峰值电流控制功能。工作
原理十分简单：在基于输出电压的一段关断时间后，即
开始导通时间。达到电感峰值电流阈值后，导通时间立
即结束。TPS92515AHV-Q1 器件可配置为在分流 FET
调光周期的导通和关断时间内保持恒定的峰间纹波。此
周期非常适合在整个分流 FET 调光范围内保持线性响
应。
1
•
符合 AEC-Q100 1 级标准
•
集成 290mΩ（典型值）内部 N 沟道场效应晶体管
(FET)
•
输入电压范围
–
–
TPS92515AHVx：5.5V 至 65V
启动后工作电压低至 5.15V
•
•
•
•
低偏移高侧峰值电流比较器
高达 2A 的恒定平均电流
固有逐周期电流限制
多种调光方法
低失调电压的高侧比较器有助于实现稳态精度。可单独
使用模拟或 PWM 调光技术或者同时使用这两种技术
来调制 LED 电流。其他 特性 包括欠压闭锁 (UVLO)、
宽输入电压操作、固有 LED 开路操作和热关断功能，
其工作温度范围较宽。
–
–
–
10,000:1 分流脉宽调制 (PWM) 调光范围
1000:1 PWM 调光范围
TPS92515AHV-Q1 器件采用热增强型 10 引脚
HVSSOP 封装，提供高电压选件，输入电压范围高达
65V。
200:1 模拟调光范围
•
简单的恒定关断时间控制
–
–
无环路补偿
器件信息(1)
快速瞬态响应
•
•
散热增强型 HVSSOP 封装
器件型号
封装
封装尺寸（标称值）
集成热保护
TPS92515AHV-Q1
HVSSOP (10)
3mm x 3mm
(1) 要了解所有可用封装，请参见数据表末尾的可订购产品附录。
2 应用
简化的降压 LED 驱动器应用
•
汽车照明：LED 开关矩阵 AFS 头灯，DRL，远光
灯/近光灯，雾灯，尾灯，转向信号灯，轮廓灯，售
后市场
TPS92515AHV-Q1
VOUT
6
7
DRN
CSN
SW
5
•
工业照明：工厂自动化、飞行时间 (TOF)、电器、
零售照明、机器视觉检测、紧急出口和/或安全照
明、医用照明、舞台和场地照明
BOOT
GND
4
3
•
•
农业、航海和重工业照明
8
9
VIN
VIN
高对比度分流 FET 调光
PWM
VCC
2
1
10 IADJ
COFF
3 说明
PAD
TPS92515AHV-Q1 是一款包含低电阻 N 沟道
MOSFET 的紧凑型单片开关稳压器。此器件适用于高
亮度 LED 照明 应用 ，满足效率、高带宽、PWM 或模
拟调光和小尺寸方面的要求。
1
本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。 有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确
性和有效性。 在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLUSDG2
TPS92515AHV-Q1
ZHCSIY0 –OCTOBER 2018
www.ti.com.cn
目录
1
2
3
4
5
6
7
特性.......................................................................... 1
9
Application and Implementation ........................ 22
9.1 Application Information............................................ 22
9.2 Typical Application ................................................. 22
9.3 Dos and Don'ts ....................................................... 30
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Device Comparison Table..................................... 3
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
7.1 Absolute Maximum Ratings ...................................... 4
7.2 ESD Ratings ............................................................ 4
7.3 Recommended Operating Conditions....................... 4
7.4 Thermal Information................................................. 4
7.5 Electrical Characteristics........................................... 5
7.6 Typical Characteristics.............................................. 7
Detailed Description .............................................. 9
8.1 Overview ................................................................... 9
8.2 Functional Block Diagram ......................................... 9
8.3 Feature Description................................................. 10
8.4 Device Functional Modes........................................ 21
10 Power Supply Recommendations ..................... 31
10.1 Input Source Direct from Battery........................... 31
10.2 Input Source from a Boost Stage ......................... 31
11 Layout................................................................... 31
11.1 Layout Guidelines ................................................. 31
11.2 Layout Example .................................................... 32
12 器件和文档支持 ..................................................... 33
12.1 文档支持 ............................................................... 33
12.2 接收文档更新通知 ................................................. 33
12.3 社区资源................................................................ 33
12.4 商标....................................................................... 33
12.5 静电放电警告......................................................... 33
12.6 术语表 ................................................................... 33
13 机械、封装和可订购信息....................................... 34
8
4 修订历史记录
日期
修订版本
说明
2018 年 10 月
*
最初发布版本。
2
Copyright © 2018, Texas Instruments Incorporated
TPS92515AHV-Q1
www.ti.com.cn
ZHCSIY0 –OCTOBER 2018
5 Device Comparison Table
MAXIMUM
VOLTAGE (V)
AUTOMOTIVE
QUALIFIED
DEVICE
CONTROL METHOD
TPS92515AHV-Q1
TPS92515-Q1
TPS92515HV
TPS92515
65
42
65
42
75
42
75
42
75
42
75
42
Y
Y
N
N
Y
Y
N
N
Y
Y
N
N
Internal N-channel FET, constant OFF-time
LM3409HV-Q1
LM3409-Q1
LM3409HV
External P-channel FET, constant OFF-time
External P-channel FET, constant OFF-time
LM3409
LM3406HV-Q1
LM3406-Q1
LM3406HV
Internal N-channel FET, controlled ON-time
LM3406
6 Pin Configuration and Functions
DGQ Package
HVSSOP 10-Pin with PowerPAD
Top View
COFF
VCC
1
2
3
4
5
10
9
IADJ
PWM
VIN
GND
BOOT
SW
8
7
CSN
DRN
Thermal Pad
6
Pin Functions
PIN
I/O
DESCRIPTION
NAME
BOOT
COFF
CSN
NO.
4
Connect a ceramic capacitor between BOOT and SW and a diode from VCC to BOOT to power the high-
side FET drive circuitry.
I
I
I
1
Connect a resistor from VOUT, and a capacitor to GND to set the OFF-time.
Current sense negative input. Connect current sense resistor from VIN to CSN for high-side current
sense control.
7
DRN
GND
IADJ
6
3
I
G
I
Internal FET drain. Connect to CSN node
Ground
10
Output current adjust. Connect to an external divider, reference or tie to VCC.
PWM dimming input. Connect to PWM control signal. Output current is pulse-width modulated (PWM)
dimmed from the maximum analog controlled level. Connect to VCC if not used.
PWM
SW
9
5
2
8
I
O
O
Internal FET Source. Connect to output inductor
5-V Regulator Output. Use a decoupling capacitor from VCC to ground. See section on VCC capacitor
selection.
VCC
VIN
I
Connect to input voltage. VIN is also the current sense positive input.
Connect to ground
Thermal pad
—
Copyright © 2018, Texas Instruments Incorporated
3
TPS92515AHV-Q1
ZHCSIY0 –OCTOBER 2018
www.ti.com.cn
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
–0.3
–1.0
–0.3
–0.3
–0.3
–0.3
-0.3
–0.3
–2.0
–40
MAX
UNIT
VIN, DRN, CSN to GND
SW to GND
65.0
65.0
65.0
70.5
5.5
DRN to SW
BOOT to GND
COFF, IADJ, PWM to GND
BOOT to SW
V
5.5
VCC to GND
5.5
VIN to CSN
0.3
(2)
SW to GND, 10-ns transient
Storage temperature, Tstg
150
°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) DRN to SW. Absolute maximum not to be exceeded.
7.2 ESD Ratings
VALUE
±2000
±750
UNIT
Human-body model (HBM), per AEC Q100-002(1)
Charged-device model (CDM), per AEC Q100-011
Electrostatic
discharge
V(ESD)
V
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
5.5
NOM
MAX
65
UNIT
V
VIN
TA
TJ
Input voltage
Operating ambient temperature
Operating junction temperature
–40
–40
125
150
°C
°C
7.4 Thermal Information
TPS92515AHV-
Q1
THERMAL METRIC(1)
UNIT
HVSSOP
10 PINS
56.2
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
44.7
Junction-to-board thermal resistance
32.1
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
1.5
ψJB
31.8
RθJC(bot)
5.3
(1) For more information about traditional and new thermal metrics, see the Semiconductor and device Package Thermal Metrics
application report, SPRA953.
4
Copyright © 2018, Texas Instruments Incorporated
TPS92515AHV-Q1
www.ti.com.cn
ZHCSIY0 –OCTOBER 2018
7.5 Electrical Characteristics
VIN = 40 V, –40°C ≤ TJ ≤ 150°C, VBOOT is referenced to SW pin, unless otherwise specified.
PARAMETER
TEST CONDITION
MIN
TYP
MAX
UNIT
PEAK CURRENT COMPARATOR
VIADJ = VCC
222
205
240
220
0.1
75
257
234
mV
mV
V/V
ns
VCST
VIN– VCSN peak current threshold
VIADJ = 2.2 V
AADJ
tDEL
tLEB
VIADJ to VIN – VCSN threshold gain 0.1 ≤ VIADJ ≤ 2.2 V
CSN pin falling delay
Minimum ON-time
CSN fall to SW fall
130
275
Minimum pulse width
75
195
ns
SYSTEM CURRENTS
Icq
Operating current
Not switching, VIADJ = VVCC
0.85
1.5
mA
INTEGRATED N-Channel MOSFET AND DRIVER
IDRN-SW = 200 mA, VBOOT = 5 V,
TJ = 25°C
290
290
310
500
600
500
650
IDRN-SW = 200 mA, VBOOT = 5 V,
TJ = 150°C
RDS(on)
FET ON-resistance
FET leakage current
mΩ
IDRN-SW = 200 mA, VBOOT = 3.5 V,
TJ = 25°C
IDRN-SW = 200 mA, VBOOT = 3.5 V,
TJ = 150°C
310
10
IDRN-SW(off)
VDRN-SW = 6 V, VSW = 0 V
µA
V
Voltage where gate drive is
disabled
VBOOT-UVLO
VBOOT falling
2.0
2.8
125
100
3.5
VBOOT-UVLO(hys)
IPD(PWM/UVLO)
IPD(BOOT)
IBOOT_Q
BOOT pin UVLO Hysteresis
mV
µA
Pull down from SW when PWM
low.
PWM low, VBOOT = 5 V , VSW = 8 V
130
Pull down from SW when VBOOT
reaches VBOOT-UVLO
PWM high, VBOOT < BOOT-UVLO, VSW
= 8 V
5
7
mA
µA
BOOT pin quiescent current
VBOOT = 5.5 V, 0 V ≤ VSW ≤ 65 V
60
90
VCC/REFERENCE REGULATOR
VCC
Regulated pin voltage
I
VCC(ext) ≤ 500 µA
VCC(ext) ≤ 500 µA
4.8
4.0
5.0
0.1
4.2
5.2
0.2
4.4
V
V
V
VCCDO
VCCUVLO
Drop out voltage
I
VCC undervoltage lockout
Falling threshold, VIN = 10 V
VCC undervoltage lockout
hysteresis
VCCUVLO_hys
0.22
V
IVCC(ILIM)
VINUVLO
VINUVLO_hys
OFF-TIMER
VOFT
VCC regulator current limit
VIN UVLO Falling Threshold
VIN UVLO Hysteresis
VCC shorted to GND
14
4.65
150
19
4.90
190
23
5.15
225
mA
V
mV
OFF-time threshold
COFF threshold
0.95
1.00
68
1.05
120
V
tD(off)
COFF to SW rising delay
ns
µs
tOFF(max)
Maximum OFF-time
230
PWM/UVLO (Enable)
IPWM(uvlo) PWM/UVLO pin current
VPWM(uvlo)
VPWM(uvlo) = 5.5 V
PWM pin rising
10
nA
V
PWM/UVLO pin threshold
PWM/UVLO pin hysteresis
0.95
50
1.0
1.05
150
Difference between rising and falling
threshold
VPWM(uvlo-hys)
100
mV
PWM pin rising to SW pin rising
PWM pin falling to SW pin falling
VPWM(uvlo) = 2 V
75
100
–20
130
170
–15
ns
ns
μA
tPWM(uvlo)
PWM/UVLO pin delay
IPWM(uvlo-hys)
PWM/UVLO hysteresis current
–25
Copyright © 2018, Texas Instruments Incorporated
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TPS92515AHV-Q1
ZHCSIY0 –OCTOBER 2018
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Electrical Characteristics (continued)
VIN = 40 V, –40°C ≤ TJ ≤ 150°C, VBOOT is referenced to SW pin, unless otherwise specified.
THERMAL SHUTDOWN
TSD
Thermal shutdown temperature
Thermal shutdown hysteresis
175
10
°C
TSD(hyst)
6
Copyright © 2018, Texas Instruments Incorporated
TPS92515AHV-Q1
www.ti.com.cn
ZHCSIY0 –OCTOBER 2018
7.6 Typical Characteristics
TJ = TA = 25°C unless otherwise specified.
225
245
244
243
242
241
240
239
238
237
236
235
Randomly sampled devices
Randomly sampled devices
224
223
222
221
220
219
218
217
216
215
214
213
212
-40 -20
0
20
40
60
80 100 120 140
-40 -20
0
20
40
60
80 100 120 140
Junction Temperature (èC)
Junction Temperature (èC)
D001
D001
VIADJ = 2.2 V
VIN = 40 V
VIADJ = VCC
VIN = 40 V
Figure 1. VCST vs. Junction Temperature
Figure 2. VCST vs. Junction Temperature
5.1
5.09
5.08
5.07
5.06
5.05
5.04
5.03
5.02
5.01
5
4.99
4.98
4.97
4.96
4.95
1.004
1.002
1
IVCC= 0mA
IVCC=4mA
0.998
0.996
0.994
0.992
0.99
Vin=6
Vin=40
Vin=65
-40 -20
0
20
40
60
80 100 120 140 160
-40 -20
0
20
40
60
80 100 120 140 160
Junction Temperature (oC)
Junction Temperature (oC)
D021
D011
Figure 3. VCC vs. Junction Temperature
Figure 4. VOFF vs. Junction Temperature
74
73.5
73
72.5
72
71.5
71
70.5
70
69.5
69
68.5
68
67.5
67
66.5
88
86
84
82
80
78
76
74
72
70
-40 -20
0
20
40
60
80 100 120 140 160
-40 -20
0
20
40
60
80 100 120 140 160
Junction Temperature (oC)
Junction Temperature (oC)
D012
D013
VIN = 40 V
VIN = 6 V
Figure 5. CSN Pin Falling Delay Time vs. Junction
Temperature
Figure 6. Off-Time Delay vs. Junction Temperature
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ZHCSIY0 –OCTOBER 2018
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Typical Characteristics (continued)
TJ = TA = 25°C unless otherwise specified.
1.05
1.03
1.01
0.99
0.97
0.95
0.93
0.91
0.89
0.87
205
202.5
200
197.5
195
ILED
Efficiency (%)
192.5
190
187.5
185
182.5
180
Vin=6
Vin=40
Vin=65
177.5
175
-40 -20
0
20
40
60
80 100 120 140 160
30
35
40
45
50
55
60
65
Junction Temperature (oC)
VIN
D014
D015
VLED = 22 V
VIADJ=2.4 V
RSENSE = 0.196 Ω
Figure 7. Leading-Edge Blanking Time vs. Junction
Temperature
Figure 8. EVM Configuration Result
1.04
1.02
1
1.04
1.02
1
ILED (Amps)
Efficiency
ILED (Amps)
Efficiency
0.98
0.96
0.94
0.92
0.98
0.96
0.94
0.9
30
31
32
33
34
35
36
37
38
39
40
38
40
42
44
46
48
50
VIN (V)
VIN (V)
D017
D016
VLED = 13 V
VIADJ=2.4 V
RSENSE = 0.196 Ω
VLED = 35 V
VIADJ=2.4 V
RSENSE = 0.196 Ω
Figure 10. EVM Configuration Result
Figure 9. EVM Configuration Result
8
Copyright © 2018, Texas Instruments Incorporated
TPS92515AHV-Q1
www.ti.com.cn
ZHCSIY0 –OCTOBER 2018
8 Detailed Description
8.1 Overview
The TPS92515AHV-Q1 is an internal N-channel MOSFET (monolithic NFET) hysteric control, buck regulator.
Hysteretic operation allows a high control bandwidth and is ideal for shunt FET and LED matrix applications
(series LED switched network). The high-side differential current sense with low adjustable threshold voltage via
a 10:1 divider, provides an excellent method for regulating output current while maintaining high system
efficiency. The device uses a controlled OFF-time (COFT) architecture to allow the converter to operate in both
continuous conduction mode (CCM) and discontinuous conduction mode (DCM) with no external control loop
compensation, and provides an inherent cycle-by-cycle current limit.
The adjustable current sense threshold provides the capability for analog dimming the LED current over the full
range and the PWM dimming input allows for high-frequency PWM dimming control requiring no external
components. Configuration options allow for easy implementation of external shunt FET dimming. See also the
OFF-Timer, Shunt FET Dimming or Shunted Output Condition section.
The device does not internally limit the maximum attainable average LED current. It does have a thermal limit
based on the maximum junction temperature. The maximum junction temperature is a function of the system
operating points (efficiency, ambient temperature, thermal management), component choices, and switching
frequency. This functionality allows the device to provide constant currents up to 1 A in a wide variety of
applications and up to 2 A in a smaller sub-set of applications. This simple regulator contains all the features
necessary to implement a high-efficiency, versatile, high-performance LED driver.
8.2 Functional Block Diagram
R
VIN
+
IADJ
VCC
+
+
R
2.4 V
CSN
10 R
DRN
LEB
Thermal
Shutdown
VCCUVLO
VCC
Regulator
T
T
Thermal
Shutdown
Gate
Internal
N-channel FET
20 µA
+
5 kΩ
SW
PWM
Control
Logic
Boot
1.0 V
UVLO
BOOT
COFF
+
5 mA
100 µA
1.0 V
Gate
250-µs (max)
off-time
VCCUVLO
PWM
GND
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TPS92515AHV-Q1
ZHCSIY0 –OCTOBER 2018
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8.3 Feature Description
8.3.1 General Operation
The TPS92515AHV-Q1 operates using a peak-current, constant OFF-time as described in Figure 11. Two states
dictate the high-side FET control. The switch remains on until the programmed peak current is reached. The
device controls the peak current by monitoring the voltage across the sense resistor. When the voltage drop is
higher than the programmed threshold, the peak current is reached, and the switch is turned OFF, which begins
the OFF-time period. A capacitor on the COFF pin is then charged through a resistor connected to the output.
When the COFF pin voltage reaches the 1-V (typical) threshold, the OFF-time ends. The COFF pin capacitor
resets and the main switch turns ON, and the next cycle begins.
The average output current
VIADJ and RSENSE
adjust
the peak inductor
current
The Inductance
(L) and tOFF define
equals the peak minus half
the peak to peak inductor
ripple
DI
L-PP
ILave = ILED = IL-Peak œ (ûIL-PP / 2)
ûIL-PP = (VLED * tOFF ) / L
IL-Peak = [ VIADJ /10 ] / RSENSE
t
t
t
OFF
ON
Figure 11. Hysteretic Operation
Although commonly referred to as constant OFF-time, it is the output votage that determines the OFF-time. This
connection ensures constant peak-to-peak ripple. To maintain a constant ripple over various input and output
voltages, the converter OFF-time becomes shorter or longer resulting in a change in frequency. If the input
voltage and output voltage are relatively constant, the frequency also remains constant. If either the input voltage
or the output voltage changes, the frequency changes. For a fixed input voltage, the device operates at the
maximum frequency at 50% duty cycle and the frequency reduces as the duty cycle becomes shorter or longer.
A graphical representation is shown in Figure 12. For a fixed output voltage (VLED), the frequency is always the
maximum at the highest input voltage as shown in Figure 13.
10
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ZHCSIY0 –OCTOBER 2018
Feature Description (continued)
0
V /2
IN
Maximum
65
Output Voltage (V)
Input Voltage (V)
Fixed input voltage
Fixed LED voltage
Figure 12. Frequency vs LED Output Voltage
Figure 13. Frequency vs Input Voltage (VIN
)
Because the OFF-time is proportional to the output voltage, it is possible to illustrate how VLED can be removed
from the output current equation. When VLED >> VOFT , the output ripple can be defined as shown in Equation 1.
ΔIL-PP = (VLED x dt)/L
where
•
dt is defined by the OFF-timer
(1)
(2)
.
COFF(1V) COFFROFF(1V)
Cdv
dt =
=
=
i
VLED
»
…
ÿ
V
LED Ÿ
ROFF
⁄
Substitute dt in Equation 1 to create Equation 3.
»
ÿ
COFFROFF(1V)
VLED …
Ÿ
⁄
VLED
L
COFFROFF(1V)
L
Vdt VLEDdt
DIL-PP
=
=
=
=
L
L
(3)
(4)
V
IADJ
COFFROFF(1V)
2 L
10
RSENSE
ILED
=
-
When VLED >≈ 10 V, use the ILED calculation Equation 4. The Detailed Design Procedure section describes a
design example that uses the more detailed equation. A VLED > 10 V ensures a linear charging ramp below 1 V.
If VLED <≈10 V, use Equation 5 that considers the exponential charging characteristic.
»
ÿ
Ÿ
Ÿ
Ÿ
Ÿ
»
ÿ
Ÿ
»
ÿ
Ÿ
»
ÿ
Ÿ
VOFT
VLED
V
»
…
…
…
ÿ
Ÿ
Ÿ
Ÿ
⁄
… VLED -ROFFCOFF ln 1-
…
IADJ
…
…
…
…
…
…
…
⁄ Ÿ
⁄
⁄
10
RSENSE
ILED
=
-
2L
Ÿ
⁄
(5)
Because the control method relies on thresholds to control the main switch, offsets and delays must also be
considered when examining the output accuracy. The ILED equation can be expanded to include these error
sources as shown in Equation 6. ILED equations include several passive components, so it is important to
consider the tolerance of each component. The VCST_Offset parameter is the variation in the VCST threshold
between the typical and maximum or minimum values as defined in the Electrical Characteristics table.
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Feature Description (continued)
»
ÿ
Ÿ
»
ÿ
Ÿ
»
ÿ
Ÿ
»
ÿ
Ÿ
VOFT
VLED
V
»
…
…
…
ÿ
Ÿ
Ÿ
Ÿ
⁄
… VLED -ROFFCOFF ln 1-
+ t
…
…
IADJ
…
D(OFF) Ÿ
…
ê V
(
)
+
CST _Offset
…
…
…
…
(V - VLED)(tDEL
)
⁄ Ÿ
⁄
⁄
10
IN
ILED
=
-
Ÿ
Ÿ
RSENSE
L
2L
Ÿ
⁄
(6)
8.3.2 Current Sense Comparator
A comparator, two resistors and a current source create a peak current detection circuit block. See the
Functional Block Diagram for details. A current source controlled by VIADJ draws a current across a resistor in
series with a comparator, forcing a proportional offset. The resistor in the current source (10 R) and in series with
the comparator (R) are sized with a 10:1 ratio. This ratio allows for a practical voltage range of operation for the
IADJ pin and maintains a small current sense voltage for low losses and less impact on efficiency.
The ON cycle begins with the offset in place via IADJ across the resistor R at the VIN pin. When the current rises
enough to create a voltage across the sense resistor to match the offset, the comparator trips. The end of the
ON-time period starts an OFF-time cycle.
Trace resistance can have an impact on accuracy, be careful when routing the traces to VIN and CSN from the
sense resistor. Because the sense resistor value is typically in milli-ohms, use a short kelvin connection to CSN
and place the sense resistor as close as possible to VIN.
8.3.3 OFF Timer
The converter OFF-time is controlled via the COFF pin. The output voltage charges a capacitor to 1 V through a
resistor creating a delay. Deriving the OFF-time from the output voltage creates a ramp representing the inductor
current. If the output voltage cannot be used, another voltage fixed source may be implemented to create a truly
constant OFF-time. However, this configuration reduces output current accuracy. When the device is first
enabled (when VCC rises above the VCC undervoltage lockout threshold) the pull-down on the COFF pin is
disabled, allowing a voltage to build up on the COFF capacitor. At the same time, the maximum off timer begins.
If the voltage source is sufficiently above the 1-V threshold, the ramp becomes linear and approximates the
inductor current. If the 1-V nominal COFF threshold is reached, or the COFF capacitor charge time duration is
greater than tOFF(max) (maximum OFF-time timer expires), a switching cycle starts.
The timer reaches the maximum OFF-time during start-up when the output is completely discharged or when
shunt FET dimming and the shunt FET shunts the output for the required period.
Equation 7 calculates ROFF for a desired OFF-time.
tOFF
ROFF
=
»
ÿ
Ÿ
⁄
»
ÿ
VOFT
VLED
-COFF ln 1-
…
…
Ÿ
⁄
(7)
8.3.4 OFF-Timer, Shunt FET Dimming or Shunted Output Condition
The OFF-time is derived from the output voltage to create a constant inductor ripple. A constant inductor ripple
ensures linearity when dimming. When the dimming method selected requires the output to be shorted, (shunt
FET or Switched Matrix approach) it is necessary to derive the OFF-time ramp from an alternate source. When
the output is shunted, the output voltage becomes very low and possibly less than the 1 V OFF-timer threshold
voltage. If this occurs, the off timer is not able to trip and the OFF-time reaches the maximum OFF-time before
the switch is turned on again. The system is able to operate in this mode, but constant inductor current ripple and
linear shunt-FET dimming is not possible. To avoid this situation, VCC can be used as a parallel source to
charge the COFF capacitor and maintain a constant ripple even when the output is shorted. This ensures precise
dimming linearity. Refer to Figure 14 for connection information.
It is not recommended to apply power to the OFF-timer circuitry while the VIN pin is not powered. The device
includes an internal diode between the COFF pin and the VCC pin. If the COFF pin receives power with no input
voltage (VIN) applied, VCC pin voltage could inadvertently be pulled up and cause the device to attempt
operation. This attempt could negatively affect the application if this operation is not desired.
12
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Feature Description (continued)
Selecting the value for ROFF2 is a two-step process.
The first step is to compute the OFF-time required when the output is shunted (tOFF-Shunt).
DILpk-pk ìL
tOFF-Shunt
=
VSHUNT + (0.7)
where
•
VSHUNT is the output voltage when the shunt device or LED Matrix device is ON
(8)
(9)
The second steps is to compute ROFF2 using (tOFF-Shunt).
-tOFF-Shunt
ROFF2
=
»
ÿ
Ÿ
»
…
ÿ
1
COFF ìln 1-
…
Ÿ
⁄
VCC
…
Ÿ
⁄
The value of ROFF1 becomes the previously calculated value of ROFF
.
The result of these calculations produce an inductor current that maintains the same DC value when shunted or
when not shunted as shown in Figure 15.
ROFF1
1
2
3
4
5
COFF
VCC
ROFF2
COFF
GND
BOOT
SW
VLED
Ch1: PWM Signal
Time: 400 µs/div
Ch4: Inductor current
No Output Capacitor
Figure 14. Shunt Dimming COFF Connection
8.3.5 Internal N-channel MOSFET
Figure 15. Shunt FET Dimming with Optimized
Inductor Current
Integrated in the TPS92515AHV-Q1 is a low on-resistance (RDS(on)) N-channel MOSFET. The resistance
specified in the Electrical Characteristics table for the drive voltage and temperature is important to consider
because the actual on-resistance for a given operating point affects efficiency and the transition point into drop-
out when operating at high currents. A sensing element for thermal shutdown circuitry has been located close to
the internal FET to better assist in part protection.
8.3.5.1 Drop-Out
The TPS92515AHV-Q1 can operate safely even when the input voltage enters the drop-out region. As VIN
approaches VLED, ΔIL-PP falls to a level much lower than during normal operation. Because the average output
current is based on Equation 10, as ΔIL-PP becomes smaller, the average current tends to increase. The amount
of increase depends on the value of ΔIL-PP used in the design. If drop-out performance is a concern, performance
can be improved by lowering the ΔIL-PP design parameter.
ILED= ILPEAK – (ΔIL-PP/2)
(10)
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Feature Description (continued)
8.3.6 VCC Internal Regulator and Undervoltage Lockout (UVLO)
The device incorporates a linear regulator to generate the 5-V (typ) VCC voltage. The VCC output voltage is
monitored to implement undervoltage lockout (UVLO) protection. The UVLO thresholds are fixed and cannot be
adjusted. The device has been designed to supply current for the device operation as well as additional power
for external circuitry. If a 5-V rail is required in an application, the device can allow up to 500 µA to be drawn in
addition to the device load. A capacitance of 1 µF or ≥ 10× the BOOT capacitance to a maximum of 10 µF is
recommended.
The device requires adequate input decoupling in order to lower ΔVIN-PP ripple for the best VCC supply voltage
performance. ΔVIN-PP must not exceed 10% of the input voltage VIN or 2 V, whichever is lower.
8.3.7 Analog Adjust Input
The analog adjust pin (IADJ) provides the reference for the peak current trip point. Through the use of an internal
10:1 divider, a wider range and finer control of the peak current sense threshold is created. For example,
applying 2.2 V to the IADJ pin creates a 220-mV, peak-current-sense trip point. The lower sense voltage also
lowers the power (V2/R) losses at the sense resistor. There is a practical lower limit to the IADJ pin voltage
choice due to circuit non-idealities. For example, using VIADJ = 0.5 V results in a sense voltage of 50 mV, which
does not allow accurate operation.
8.3.7.1 IADJ Pin Clamp
The IADJ pin incorporates an internal 2.4-V clamp. An area of inaccuracy in the clamp knee point voltage
requires the designer to consider how to mitigate this situation when selecting an IADJ pin voltage. The most
accurate method is to apply 2.2 V to the IADJ pin, which allows it to remain below the clamp knee-point voltage
area. If an accurate, external, 2.2-V (or lower) reference is not available, use the next most accurate control
method which is the internal clamp. The least accurate method uses a resistor divider on the VCC pin. The
Analog and PWM Dimming - Normalized Results and Comparison section includes measured analog dimming
results.
14
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Feature Description (continued)
8.3.7.2 IADJ Pin Clamp Characteristic
Figure 16 shows the clamping characterization. Figure 28 shows an application measurement. The translation is
straightforward, with the exception of the knee-point voltage area. For voltages ≤2.2 V, the internal VIN to CSN
peak current sense voltage equals VIADJ/10. For voltages ≥ 2.4 V the voltage equals 240 mV. For the area 2.2 ≤
VIADJ≤ 2.4 the voltage approximates VIADJ/10, but varies slightly more than the other regions of operation.
240
220
Lower Limit of
Knee
100
1
2.2
3
5.5
VIADJ (V)
Figure 16. IADJ Pin Internal Clamp Characteristic
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Feature Description (continued)
8.3.7.3 Analog Adjust (IADJ Pin) Control Methods
This section describes several analog adjust (IADJ) control methods configurations.
Table 1. IADJ Pin Connection Schematics
FIGURE
Figure 17
IADJ PIN CONNECTION
IADJ pin tied directly to the VCC pin using the internal 2.4-V clamp.
Figure 18
Figure 19
Figure 20
Figure 21
Figure 22
IADJ pin tied through a voltage divider to the VCC pin allowing a lower peak current sense voltage
IADJ pin tied through a resistor and thermistor divider, implementing thermal foldback function.
IADJ pin is connected to a micro controller. A GPI/GPIO is connected to a filter to create an analog adjust voltage.
IADJ pin connection to implement a soft-start sequence
IADJ pin is connected to a precision reference. This configuration yields the highest accuracy.
.
TPS92515
VCC
TPS92515
2 VCC
2
10 IADJ
10 IADJ
Figure 17.
Figure 18.
TPS92515
TPS92515
2
VCC
2
VCC
10 IADJ
10 IADJ
µC supplied
Figure 19.
Figure 20.
TPS92515
TPS92515
2
VCC
2 VCC
10 IADJ
External
Reference
10 IADJ
Figure 21.
Figure 22.
8.3.7.4 IADJ Control Method Notes
•
•
Connecting the IADJ pin directly to VCC is simple and is the most accurate stand-alone implementation.
Using a resistor divider circuit can lower the sense voltage and improve efficiency if the converter output
currents are high. The trade-off is an increased variation in the peak trip voltage. Note that there are also
practical limitations to how low the sense voltage can be and maintain a reasonable accuracy.
16
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•
The simple thermal foldback method sizes the divider to set the IADJ voltage above 2.4 V. This method uses
the internal clamp when thermal foldback is not required and sets the IADJ voltage below 2.4 V when
foldback is required. Match the temperature characteristic of the thermistor to the second resistor in the
divider. As an alternative, use a positive temperature coefficient (PTC) thermistor as the upper resistor in the
divider.
•
By using a micro-controller to control the timing output, the duty cycle can be controlled and the voltage can
be filtered and connected to the IADJ pin. Use a filter pole of 1/10th the micro-controller control pin output
switching frequency, or use R ≈ 1 kΩ and C ≈ 4.7 µF as a starting point.
•
•
Simply add a capacitor to the IADJ pin and size the R-C constant to produce the desired soft-start time.
Consider the maximum current is reached when VIADJ = 2.4 V.
To get the highest accuracy, use an external, high-precision reference and power it from the TPS92515AHV-
Q1 VCC if required. A 1% or 2% Zener diode, TL431 device, or an existing precision reference circuit can be
used.
8.3.8 Thermal Protection
The TPS92515AHV-Q1 device incorporates thermal protection circuitry. If the TPS92515AHV-Q1 thermal pad is
not soldered, or not soldered correctly, the device reaches the thermal shutdown temperature prematurely. Use
X-ray inspection or some other means to verify the device thermal pad soldering to ensure correct assembly.
Two internal sensing elements ensure proper temperature measurement across the die. One sensing element is
located near the internal FET. The other sensing element is located near the VCC regulator. Power dissipation the
FET and internal regulator contribute the most to device temperature rise.
When the device temperature reaches the thermal shut-down level at the FET sense point, the high-side FET
and internal regulator become disabled and switching stops. When thermal shut-down temperature is reached at
the regulator sense point, the VCC regulator becomes disabled, and switching stops when VCC falls below the
VCCUVLO level. In both cases, after the device lowers 10°C (typical) from the trip temperature, normal operation
resumes.
8.3.8.1 Maximum Output Current and Junction Temperature
As with all power converter controllers and regulators, practical limits to specification maximums must be
considered for each application. For example, it is not possible to operate the TPS92515AHV-Q1 with a
switching frequency of 1 MHz, output current of 2 A, at an ambient temperature of 125°C and stay within
operating limits. Conversion factors and environment must be considered. This section describes two conversion
scenarios with different operating conditions that can result in approximately the same junction temperature. In
each case all of the power loss factors combine to develop the device junction temperature.
Figure 24 describes a design with half the output current and a lower switching frequency compared to that
shown in Figure 23. However, the design shown in Figure 24 has a higher ambient temperature, higher VIN and
an additional external VCC load, resulting in similar junction temperature. Table 2 lists trade-offs and impact on
temperature. In general, applications requiring high current (2 A) or a high switching frequency (> 1 MHz) provide
reduced maximum ambient temperature levels.
VccEXT
fSW
ILED
fSW
VIN
TA
VIN
TA
ILED
ILED = 500 mA
fSW = 300 kHz
VIN = 60 V
TA = 125°C
External VCC load = 500 µA
ILED = 1 A
VIN = 14 V
TA = 85°C
fSW = 500 kHz
Figure 23. Power Balanced
Figure 24. Power Unbalanced
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Table 2. Device Junction Temperature Factors
FACTOR
AFFECT ON TEMPERATURE AND TRADE-OFFS
TA
Ambient temperature
An increase in the ambient temperatre increases the junction temperature by the same amount.
A higher input voltage results in more power developed across the internal regulator resulting in
higher internal losses. A higher voltage often yields a larger step-down conversion and lower
efficiency.
VIN
Input voltage
A higher LED output current results in higher power (I2R) losses in current carrying elements like the
internal MOSFET.
ILED
LED current
Current used to supply additional loads external to the TPS92515AHV-Q1 device draw from the
internal regulator. More external current results in an increased junction temperature. When an
external source supplies the BOOT current internal power dissipation decreases.
IVCC(ext)
External VCC current
Each time the internal FET is turned ON and OFF, current must flow from VCC to the gate driver.
The current drawn by a switching gate approximately equals the gate charge times the switching
frequency. Power loss associated with the switching edge transitions also increase with frequency.
fSW
Switching frequency
Efficiency
Switching conversions requiring difficult conversions (small duty cycles) have higher overall losses.
These losses increase the overall temperature of the application and the device temperature.
η
8.3.9 Junction Temperature Relative Estimation
The dominant power loss factors predict the junction temperature. These equations offer an estimate of device
temperature for the use of considering different conversion scenarios. By adding the losses and using the device
thermal impedance, a temperature can be predicted. In this case we consider losses internal to the device:
Conduction loss in the MOSFET, an estimate of switching losses and Icq losses.
»
ÿ
+ (IGate + Icq) * V * QJA + TA
LOSSSW IN
TJ-Estimate = P
+ P
LOSSCOND
⁄
(11)
By expanding the terms an estimate can be calculated using Equation 12. Equation 12 is a good prediction in a
design and layout similar to the orderable EVM. If other sources of heat rise are located near the TPS92515AHV-
Q1 the device temperature also rises accordingly.
»
…
…
ÿ
»
…
…
ÿ
Ÿ
»
ÿ
VLED
-9
2x 0.6 x
0.5 x V x ILED x 60E-9x fSW ) x 1.2 + (3E x f +1E-3) * V
x 56.2 + T
»
+
ÿ
»
ÿ
TJ-Estimate
=
I
Ÿ
(
)
… LED
Ÿ
⁄
IN
SW
IN
Ambient
⁄
⁄
V
Ÿ
⁄
IN
Ÿ
⁄
(12)
8.3.10 BOOT and BOOT UVLO
The TPS92515AHV-Q1 contains circuitry to ensure proper operation of the internal MOSFET. Typically a
capacitor tied to the switchnode (SW pin) and a diode connected to the VCC supply powers the BOOT pin. Each
time the diode conducts current, a path is created from the VCC pin to charge the BOOT capacitor. The
connection allows the BOOT capacitor to float with the switch-node voltage and internal FET source. Anytime the
main switching diode conducts current, the switch-node falls to a diode drop below ground. This creates a path
for the boot capacitor to be charged in approximately 150 ns or less. A typical BOOT capacitance of 0.1 µF can
maintain the ON-state of the FET for approximately 5 ms. This timing allows conversion duty-cycles of >> 99%.
Anytime the BOOT voltage reaches a level that does not allow proper FET turn-on, the high-side FET turns off.
Although the internal VCC regulator typically supplies power to the BOOT drive circuitry, that power can be
supplied by a suitable external source. Use this configuration to save power dissipation in the device and to
lower the junction temperature. Ensure the external source does not exceed 5 V and that it can supply an
adequate average current equal to or greater than 3 × 10-9 × fSW
.
8.3.10.1 Start-Up, BOOT-UVLO and Pre-Charged Condition
If a pre-charge condition occurs (a voltage exists on the output at turn-on) a resulting undervoltage lockout of the
BOOT pin activates an internal, 5-mA (typical) pulldown. The pulldown reduces the time required to bring the
output voltage low enough to charge the BOOT capacitor and begin operation. The device activates this strong
pulldown any time undervoltage lockout of the BOOT pin occurs. However, in most situations the diode turn-on
does most of the work to lower the switch node voltage. The pulldown does not act as a synchronous FET.
18
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ZHCSIY0 –OCTOBER 2018
Internal
N-FET
DRN
SW
Gate
BOOT
UVLO
BOOT
VCC
5 mA
100 µA
VCCUVLO
PWM
Figure 25. BOOT and PWM Pull-Downs
8.3.11 PWM (UVLO and Enable)
If PWM dimming or ON/OFF control is not needed in the application, tie the PWM pin to the VCC pin.
Use the PWM pin for PWM dimming. Use a signal above 1 V (typical) and below 900 mV (typical) when
measured at the PWM pin. Standard PWM frequency ranges can also be used (100 Hz to 2 kHz). Higher
frequencies can cause the delays from PWM to gate turn ON and turn OFF to limit the achievable duty cycle.
For example, the PWM to gate delay (turn on + turn off ≈ 100 ns) and the time to slew the switchnode up and
down (approximately 100 ns) total approximately 200 ns.
For example, if a 10 kHz PWM frequency is desired having a period of 100 μs, the minimum duty cycle is 200
ns/100 μs = 0.2%. This is sometimes referred to as 500:1 dimming. As the PWM signal width becomes smaller,
the converter ON and OFF time are eventually controlled by the PWM input signal directly. For example, if the
PWM ON-time is shorter than the converter natural demanded ON-time, the PWM signal itself becomes the
control signal for the high-side switch. The PWM pin activates a weak pulldown, as shown in Figure 25. Because
the PWM pin also controls UVLO (undervoltage lockout and device enable), when pulled low it is necessary to
ensure the output is 100% OFF. The high-side FET driver has a small leakage path to the output. Although very
small (<<100 μA), the LEDs can glow if the current was not eliminated. The device activates the 100-μA (typical)
pulldown circuitry and it remains ON while PWM is low. This activation ensures that the LED emits no light.
8.3.11.1 Using PWM for UVLO (Undervoltage Lockout) Protection
When the PWM pin exceeds the 1-V (typical) threshold, the device activates a 100-mV (typical) fixed hysteresis
and an adjustable hysteresis based on an internal current source (IPWM(uvlo-hys)). This functionality provides noise
immunity to the PWM control and adjustability to the UVLO hysteresis. The two thresholds can be designed as
described in the UVLO Programming Resistors section.
8.3.11.1.1 UVLO Programming Resistors
The value of resistors R2 and R3 establish the undervoltage lockout level as shown in Figure 26. Include a small
level of capacitance (approximately 0.1 µF) at the UVLO pin for noise immunity. If the application does not
require drop-out operation (operation when VIN approximates VLED) program a UVLO level allows no switching to
occur until there is adequate input voltage available.
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POR
VIN
R2
20 ꢀA
PWM
5 kΩ
+
1.0 V
R3
Figure 26. UVLO Programming Resistors
Select the desired amount of voltage hysteresis and the desired turn-ON threshold (VIN-RISE_THRESHOLD). Because
of the small amount of fixed-voltage hysteresis and fixed-hysteresis current, some combinations of turn-ON and
turn-OFF thresholds are not possible. If the calculation results in values that are zero or negative, the
combinations selected are not possible. Choose a turn-ON point and an amount of voltage hysteresis (VHYST).
Use Equation 13 and Equation 14 to calculate R3 and R2.
»
IN-RISE_ THRESHOLD ÿ
VHYST - 0.1 x V
⁄
R3 =
»
ÿ
-1
IN-RISE_ THRESHOLD
20
m
A x
V
⁄
(13)
(14)
»
ÿ
-1 x R3
R2 = V
IN-RISE_ THRESHOLD
⁄
8.3.11.2 Using PWM for Digitally Controlled Enable
If using the PWM pin as to provide and enable function, ensure the signal edge rate is adequate (< 100 ns) when
measured at the device PWM pin to prevent the device from turning ON and turning OFF when the level
transitions through the 1-V threshold region. If the edge is too slow or if the high level is not adequately above
the 1-V threshold, a small capacitor may be required on the PWM pin to avoid multiple turn-ON and turn-OFF
cycles when passing through this region.
8.3.11.3 UVLO: VIN, VCC and BOOT UVLO
The TPS92515AHV-Q1 contains 3 internal under voltage lock-outs which must be satisfied for the device to
operate: VIN UVLO ensures adequate voltage to power the high-side comparator. VCC UVLO ensures internal
rails are adequate for the device to function, and BOOT UVLO ensures proper high-side FET operation and
smooth dropout operation. All of the UVLO's operate independently and automatically. Under normal operation
they do not require any specific user attention.
8.3.11.4 Analog and PWM Dimming - Normalized Results and Comparison
When the PWM applied signal is less than the switching cycle period and falls during an OFF-time it has no
impact on the current for that cycle as the switch is already OFF. This situation can be avoided by increasing the
switching frequency. Shunt FET PWM dimming avoids this issue. Current adjustment that maintains a constant
ripple when shunted (see the OFF-Timer, Shunt FET Dimming or Shunted Output Condition section), creates a
linear relation to the PWM shunt FET duty cycle and the average output current. Shunt FET PWM dimming can
out-perform PWM dimming as characterized in Figure 27 through Figure 29, but is more complicated to
implement.
Another impact on linearity can occur when using the analog dimming function. Discontinuous conduction mode
(DCM) occurs when the inductor current reaches 0 A during each cycle,. When the device enters DCM, the
output current is no longer the peak current minus half the ripple. The linear range can be extended by lowering
the ripple, ΔIL-PP. If the system is being digitally controlled, the applied IADJ pin voltage can be adjusted when it
is known the DCM operation occurs. In either case, a lower limit is eventually reached when the measured peak
threshold voltage is approximately < 50 mV. At this point, the offset error becomes a significant portion of the
peak current trip point voltage being measured.
20
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1
0.1
1.1
1
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
0.01
0.001
0.0001
1E-5
1E-6
1E-7
1E-8
30% Ripple
12% Ripple
Ideal
IDEAL
PWM, L=47mH. Fsw=228kHz Fpwm=200Hz
PWM, L=47mH. Fsw=390kHz, Fpwm=200Hz
PWM, L=100mH. Fsw=390kHz, Fpwm=200Hz
PWM, L=100mH. Fsw=800kHz, Fpwm=500Hz
Shunt FET. L=47mH Fsw=350kHz Fpwm=500Hz
5E-10
1
2 3 5 710 20 50 100
1000
10000
100000
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
Applied Dimming Signal Ratio [x:1]
VIADJ (V)
D021
DADIM
VLED = 15 V
VIN = 55 V
Figure 27. PWM Dimming Performance with Shunt Dim
Comparison
Figure 28. Analog Dimming Performance
2
1
0.7
0.5
0.3
0.2
30% Ripple
12% Ripple
Ideal
0.1
0.07
0.05
0.03
0.02
0.01
0.007
0.005
0.003
0.002
DCMäCCM
0.001
0.020.03 0.05
0.1
0.2 0.3 0.5 0.7
VIADJ (V)
1
2
3
4 5
DADLG
VLED = 15 V
VIN = 55 V
Figure 29. Analog Dimming Performance (Log Scale)
8.4 Device Functional Modes
This device has no additional functional modes.
Copyright © 2018, Texas Instruments Incorporated
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Be sure to
validate and test the design implementation to confirm system functionality.
9.1 Application Information
This section presents a simplified design process using the TPS92515AHV-Q1 buck current regulator for an LED
driver with the following specifications:
•
•
•
•
Buck converter topology
Input voltage: 65 V
Output voltage: 22 V (7 LEDs)
Output current 1 A
Use the following design procedure to select component values for this and similar buck applications.
9.2 Typical Application
VCC
VIN
65 V (max)
TPS92515
COFF IADJ 10
R10
R12
1
2
3
4
5
VIN
C6
C10
VCC
GND
BOOT
SW
R2
R3
C7
PWM
VIN
9
8
7
6
ROFF1
D4
C8
C5
C1
LED+
CSN
DRN
R5
L1
C9
D1
PAD
Copyright © 2016, Texas Instruments Incorporated
Figure 30. TPS92515AHV-Q1 BUCK LED Driver
9.2.1 General Design Procedure
This procedure includes the fundamental design equations required for a TPS92515AHV-Q1 buck converter
design.
9.2.1.1 Calculating Duty Cycle
Start with an efficiency of n estimation of 0.9.
VLED
D =
V x n
IN
where
•
VOUT = VLED
(15)
9.2.1.2 Calculate OFF-Time Estimate
Equation 16 uses the switching period T to derive the OFF-time (tOFF) .
22
Copyright © 2018, Texas Instruments Incorporated
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Typical Application (continued)
1
tOFF
=
x 1-D
» ÿ
⁄
fSW
derived from:
•
•
T = [tOFF + tON ]= [tOFF+ (D × T)] and
T = 1/fSW
(16)
9.2.1.3 Calculate OFF-Time Resistor ROFF
Select a COFF between 100 pF and 1 nF. The preferred value is 470 pF. The EC table specifies the OFF-time
threshold (VOFT) at 1 V.
tOFF
ROFF
=
VOFT
VLED
»
ÿ
⁄
»
ÿ
-COFF ln 1-
⁄
(17)
9.2.1.4 Calculate the Minimum Inductance Value
Where ΔIL-PP is in Amperes. For example, a 1-A solution with 20% inductor ripple: set ΔIL-PP = 0.2A
VLED x tOFF
L =
DIL-PP
(18)
When selecting the inductor, ensure the ratings for both peak and average current are adequate. Equation 19
calculates the peak inductor current.
V
»
…
IADJ ÿ
Ÿ
10
⁄
ILPEAK=
RSENSE
(19)
9.2.1.5 Calculate the Sense Resistance
Always use the highest VIADJ voltage the application allows without exceeding 5.5 V. The device clamps any
higher value to a level 2.4 V. See also the Analog Adjust Input for details.
V
»
…
IADJ ÿ
Ÿ
10
⁄
RSENSE
=
DI
»
L-PP ÿ
2
⁄
ILED
+
(20)
9.2.1.6 Calculate Input Capacitance
NOTE
Input voltage ripple (ΔVIN-PP) must not exceed 10% of the input voltage (VIN) or 2 V,
whichever is lower.
For example, VIN = 50 V, 50 x 0.1 = 5 V; the maximum ΔVIN-PP remains 2 V.
»
…
ÿ
1
ILED
x
- tOFF Ÿ
fSW
⁄
CIN-MIN
=
DV
IN-PP
(21)
9.2.1.7 Calculate Output Capacitance
Because current is being regulated and is continuous, no output capacitance is required to supply the load and
maintain output voltage. This regulation helps when designing a high-frequency PWM dimming on the LED load.
When no output capacitor is used, the same design calculations for ΔIL-PP also apply to ΔILED-PP
.
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Typical Application (continued)
A capacitor placed in parallel with the LED load can be used to reduce ΔILED-PP while keeping the same average
current through both the inductor and the LED load. With an output capacitor, the inductance can be lowered,
making the magnetic smaller and less expensive. Alternatively, the circuit can be run at lower frequency with the
same inductor value, improving the efficiency and increasing the maximum allowable average output voltage. A
parallel output capacitor is also useful in applications where the inductor or input voltage tolerance is poor.
Adding a capacitor that reduces ΔILED-PP to well below the target provides headroom for changes in inductance or
VIN that might otherwise push the maximum ΔILED-PP too high.
Figure 31. Calculating Dynamic Resistance rD from LED Characteristics.
Determine the output capacitance by establishing the desired ΔILED-PP and the LED dynamic resistance, rD.
Calculate the dynamic resistance as the slope of the LED exponential DC characteristic at the nominal operating
point as shown in Figure 31. Simply dividing the forward voltage by the forward current at the nominal operating
point results in an incorrect value that is between 5 times and 10 times too high. Calculate total dynamic
resistance for a string of n LEDs connected in series as the dynamic resistance of one device multiplied by n.
Use Equation 22 and Equation 23 to estimate ΔILED-PP when using a parallel capacitor:
DIL-PP
1
DILED-PP
=
and ZC =
rD
2p
fSWCO
1+
ZC
(22)
(23)
DIL-PP - DI
LED-PP ÿ
»
⁄
CO=
DILED-PP
2p
f
r
SW ÿ
D
»
⁄
24
Copyright © 2018, Texas Instruments Incorporated
TPS92515AHV-Q1
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Typical Application (continued)
9.2.2 Design Requirements
Table 3 shows the design parameters for an example Buck LED driver application.
Table 3. Design Parameters
PARAMETER
INPUT CHARACTERISTICS
TEST CONDITIONS
MIN
TYP
MAX UNIT
VIN
Input voltage range
Input UVLO setting
30
65
4
65
29
V
V
VULVO
VUVLO-HYST Input UVLO hysteresis
OUTPUT CHARACTERISTICS
VFLED
n
LED forward voltage
Number of LEDs in series
Output voltage
3.14159
7
V
VLED
ILED
PMAX
LED+ to LED–
22
V
mA
W
Output current
1000
22
Maximum output power
25
SYSTEMS CHARACTERISTICS
ΔILEDpk-pk
ΔILpk-pk
ΔVIN-PP
fSW
LED current ripple
Inductor current ripple
Input voltage ripple
Switching frequency
10%
45%
2
V
580
kHz
9.2.3 Detailed Design Procedure
This procedure describes the fundamental component selections for the design specifications noted in
Equation 17.
9.2.3.1 Calculating Duty Cycle
Solve for D: VOUT = VLED. Assume a target efficiency of 90%. (η = 0.9)
VLED
22
D =
=
= 0.37 = 37%
V x n 65 x 0.9
IN
(24)
9.2.3.2 Calculate OFF-Time Estimate
Equation 25 uses the switching period T to derive the OFF-time (tOFF) .
1
1
tOFF
=
x 1-D =
x 1-.376 = 1.076 ms
» ÿ
»
ÿ
⁄
⁄
fSW
580kHz
where
•
•
T = tOFF+ tON
tOFF+ (D x T), and T = 1/fSW
(25)
9.2.3.3 Calculate OFF-Time Resistor ROFF
Select a COFF between 100 pF and 1 nF. The preferred value is 470 pF. The EC table specifies the OFF-time
threshold (VOFT) at 1 V.
tOFF
1.076
m
ROFF
=
=
= 49212W
VOFT
VLED
1
»
ÿ
⁄
»
ÿ
-470p ln 1-
»
ÿ
»
22 ÿ
⁄
-COFF ln 1-
⁄
⁄
(26)
9.2.3.4 Calculate the Inductance Value
this example uses a 1-A solution with 45% inductor ripple. Set ΔIL-PP = 0.45A
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TPS92515AHV-Q1
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VLED x tOFF 22 x 1.076
m
L =
=
= 52mH
DIL-PP
1.0 x .45
where
•
ΔIL-PP is in A
(27)
When selecting an inductor ensure the ratings for both peak and average current are adequate. It is best to
select an inductance value of at least the calculated value or higher. For example, most cases use 56 µH or 68
µH given the 52 µH calculation. However, in this example size and efficiency are a concern and the application
allows for the use of an output capacitor. Because a value of 52 µH not close to any common values, and output
capacitance is allowed, 47 µH is selected. 47 µH has a lower winding resistance (DCR) for the same case size.
9.2.3.5 Calculate the Sense Resistance
Always use the highest VIADJ voltage that the application allows. Do not exceed 5.5 V. A value higher than 2.4 V
is clamped to 2.4 V. Refer back to Analog Adjust Input for details.
V
2.4
10
»
…
IADJ ÿ
»
…
ÿ
⁄
Ÿ
Ÿ
10
⁄
RSENSE
=
=
= 0.196W
DI
0.45
2
»
L-PP ÿ
»
ÿ
⁄
⁄
ILED
+
1.0 +
2
(28)
9.2.3.6 Calculate Input Capacitance
NOTE
Inductor ripple current (ΔVIN-PP) must not exceed 10% of the input voltage (VIN) or 2 V,
whichever is lower.
For example, VIN = 65 V, 65 x 0.1 = 6.5 V; the maximum ΔVIN-PP remains 2 V.
»
…
ÿ
1
1
»
…
ÿ
ILED
x
- tOFF Ÿ
1 x
-1.076m
Ÿ
⁄
fSW
580k
⁄
CIN-MIN
í
í
í 324nF
DV
2
IN-PP
(29)
9.2.3.7 Verify Peak Current for Inductor Selection
When selecting in inductor consider these three specifications.
•
•
•
the required inductance
the average current rating
the peak current rating
Equation 30calculates the peak current rating
V
2.4
10
»
…
IADJ ÿ
»
…
ÿ
⁄
Ÿ
Ÿ
10
⁄
ILPEAK=
=
= 1.22A
RSENSE
.196W
(30)
26
Copyright © 2018, Texas Instruments Incorporated
TPS92515AHV-Q1
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ZHCSIY0 –OCTOBER 2018
9.2.3.8 Calculate Output Capacitance
Figure 32. Calculating Dynamic Resistance (rD) from LED Specifications
Solve for rD, using the slope of the tangent line, then multiply by the number of LEDs.
3.83 - 3.63
1.5 - 0.6
rD =
= .0222W x 7 = 1.55W
(31)
Substitute the value of rD with other parameters to solve for the required minimum output capacitor to meet the
required LED ripple current level:
DIL-PP - DI
LED-PP ÿ
0.45 - 0.15
ÿ
»
»
⁄
⁄
CO=
=
í 354 nF
DILED-PP
2p
f
r
0.15 2p 580k 1.55
»
SW ÿ
» ÿ
D
⁄
⁄
(32)
9.2.3.9 Calculate UVLO Resistance Values
Consider the rising threshold of VIN to be 29 V and the hysteresis to be 4 V, calculate R2 and R3 to create the
desired operation:
»
IN-RISE_ THRESHOLD ÿ
VHYST - 0.1 x V
4 - 0.1 x 29
»
ÿ
⁄
⁄
R3 =
=
= 1964W
20mA x 29 -1
»
ÿ
» ÿ
20
m
A x
V
IN-RISE_ THRESHOLD -1
⁄
⁄
(33)
(34)
»
ÿ
-1 x R = 29 -1 x 1964 = 54.9kW
» ÿ
3
R2 = V
IN-RISE_THRESHOLD
⁄
⁄
The final schematic is shown in Figure 33 and performance curves in the Application Curves section:
Copyright © 2018, Texas Instruments Incorporated
27
TPS92515AHV-Q1
ZHCSIY0 –OCTOBER 2018
www.ti.com.cn
VCC
VIN
65 V (max)
R10
100 kΩ
TPS92515
COFF IADJ 10
1
2
3
4
5
VIN
R2
COFF
470 pF
DNP
DNP
VCC
GND
BOOT
SW
54.9 kΩ
1 mF
PWM
VIN
9
8
7
6
ROFF1
49 kΩ
D4
R3
CIN
0.1 mF
2 kΩ
L1
47 µH
RSENSE
0.196 Ω
CIN
2.2 mF
CSN
DRN
0.1 mF
LED+
CO
1 mF
D1
PAD
Copyright © 2016, Texas Instruments Incorporated
Figure 33. Application Schematic
9.2.4 Application Curves
Buck LED driver example: VOUT = 22 V (7 LEDs), IOUT = 1 A
100
96
92
88
84
80
76
72
68
64
60
1.2
1.17
1.14
1.11
1.08
1.05
1.02
0.99
0.96
0.93
0.9
Efficiency
ILED
Ch1: SW Voltage; Ch2: VIN Ripple Voltage (AC Coupled);
Ch3: ILED-PP; Ch4: Inductor current;
Time: 1 µs/div
30
35
40
45
VIN (V)
50
55
60
65
Figure 35. Normal Operation
D0068
VLED = 22 V
IOUT = 1.0 A
Figure 34. Efficiency and Output Current vs. Input Voltage
28
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TPS92515AHV-Q1
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ZHCSIY0 –OCTOBER 2018
Ch1: SW Voltage; Ch2: VIN (DC Coupled);
Ch4: Inductor current; UVLO designed limit attained.
Time: 1 ms/div
Ch1: SW Voltage; Ch2: VIN (DC Coupled);
Ch4: Inductor current; UVLO designed limit attained.
Time: 1 ms/div
Figure 36. Startup Transient
Figure 37. Shut-Down Transient
Ch1: SW Voltage; Ch2: VIN (DC Coupled);
Ch4: Inductor current;
Ch1: SW Voltage; Ch2: PWM pin;
Ch4: Inductor current;
Time: 8 µs/div
Time: 10 µs/div
Figure 38. First 15 SW Node Pulses at Turn-On
Figure 39. PWM Dimming: 250Hz, 0.25% Duty Cycle
Copyright © 2018, Texas Instruments Incorporated
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TPS92515AHV-Q1
ZHCSIY0 –OCTOBER 2018
www.ti.com.cn
Ch1: SW Voltage; Ch2: PWM pin;
Ch4: Inductor current;
Time: 10 µs/div
Ch1: SW Voltage; Ch2: PWM pin;
Ch4: Inductor current;
Time: 1 ms/div
Figure 40. PWM Dimming: 250Hz, 1% Duty Cycle
Figure 41. PWM Dimming: 250Hz, 50% Duty Cycle
Ch1: PWM Signal
Ch4: Inductor current; ΔIL-PP Maintained
Time: 20 µs/div
Figure 42. Shunt FET Dimming - Optimized Inductor
Current Waveform
Ch1: PWM Signal
Ch4: Inductor current; OFF-time reaching Maximum OFF-Time
Time: 400 µs/div
Figure 43. Shunt FET Dimming - Non-Optimized Inductor
Current
9.3 Dos and Don'ts
Dos
Don'ts
Check soldering of thermal pad in production
Check device case and junction temperature during and after
prototyping of any solution.
30
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TPS92515AHV-Q1
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ZHCSIY0 –OCTOBER 2018
10 Power Supply Recommendations
The TPS92515AHV-Q1 can operate via two main input source options:
•
•
from the battery directly
from the output of a boost stage
Make sure that either application meets the input voltage ripple requirements. The input ripple must go no higher
than 10% of the input voltage to a maximum of 2 V.
10.1 Input Source Direct from Battery
The TPS92515AHV-Q1 can operate directly from a battery. The device ratings are such that load dump and
other battery voltage excursions do not exceed the ratings of the device. When the battery voltage drops, no
device damage occurs, and the device recovers in a controlled manner. The BOOT UVLO protection allows duty
cycles over 99%.
10.2 Input Source from a Boost Stage
The TPS92515AHV-Q1 maximum input voltage of 65 V makes it a suitable second stage buck regulator for a
variety of applications and LED output configurations. For an average LED forward voltage of 3.5 V, and allowing
for some headroom below the 65-V maximum input, the TPS92515AHV-Q1 can successfully control up to 17
LEDs connected in series.
11 Layout
11.1 Layout Guidelines
The performance of any switching converter depends as much upon the layout of the PCB as it does on the
component selection. Follow these simple guidelines to maximize noise rejection and minimize the generation of
EMI within the circuit.
Figure 44 shows a sample layout and the associated current loops.
•
Discontinuous currents are the type of current most likely to generate EMI. Be careful when routing these
paths.
–
The main path for discontinuous current contains the input capacitor (CIN), the recirculating diode (D1), the
internal MOSFET (DRN pin to SW pin), and the sense resistor (RSENSE) shown as LOOP2. Make LOOP2
as small as possible.
–
Make the connections between all three components short and thick to minimize parasitic inductance. In
particular, the switch node (where L1, D1 and the SW pin connect, shown as LOOP1). Make them large
enough to connect the components without producing excessive heat from the current it carries.
•
The IADJ, COFF, CSN and VIN pins are all high-impedance control inputs, therefore minimize the loops
containing these high impedance nodes. The most sensitive loop contains the sense resistor (RSENSE) Place
the sense resistor as close as possible to the CSN and VIN pins to maximize noise rejection.
•
•
•
Place the OFF-time capacitor (connected from the COFF pin to ground) close to the COFF and GND pins to
maximize noise rejection.
External resistors (if used) bias the IADJ pin. Place them close to the IADJ and GND pins and use a small
capacitor to decouple.
In some applications the LED load can be far away (several inches or more) from the device, or on a
separate PCB connected by a wiring harness. When an output capacitor is used and the LED load is large or
separated from the main converter, place the output capacitor close to the LEDs to reduce the effects of
parasitic inductance on the AC impedance of the capacitor.
Copyright © 2018, Texas Instruments Incorporated
31
TPS92515AHV-Q1
ZHCSIY0 –OCTOBER 2018
www.ti.com.cn
11.2 Layout Example
Minimize discontinuous current loops
Components close to Device
Ground plane + thermal vias
GND
LOOP1
TPS92515
1
10
PWM
GND
COFF
IADJ
ILED
2
3
4
5
9
8
7
6
VCC
PWM
D1
CIN
GND
BOOT
SW
VIN
VIN
CSN
Kelvin Connection to
RSENSE
LED+
DRN
DAP
LOOP2
Figure 44. TPS92515AHV-Q1 Layout Example
32
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TPS92515AHV-Q1
www.ti.com.cn
ZHCSIY0 –OCTOBER 2018
12 器件和文档支持
12.1 文档支持
12.1.1 相关文档
12.1.1.1 相关链接
下表列出了快速访问链接。类别包括技术文档、支持与社区资源、工具和软件，以及申请样片或购买产品的快速链
接。
表 4. 相关链接
器件
产品文件夹
请单击此处
样片与购买
请单击此处
技术文档
工具与软件
请单击此处
支持和社区
请单击此处
TPS92515AHV-Q1
请单击此处
12.2 接收文档更新通知
要接收文档更新通知，请导航至 TI.com.cn 上的器件产品文件夹。单击右上角的通知我进行注册，即可每周接收产
品信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
12.3 社区资源
下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，
并且不一定反映 TI 的观点；请参阅 TI 的 《使用条款》。
TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在
e2e.ti.com 中，您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。
设计支持
TI 参考设计支持 可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。
12.4 商标
E2E is a trademark of Texas Instruments.
12.5 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损
伤。
12.6 术语表
SLYZ022 — TI 术语表。
这份术语表列出并解释术语、缩写和定义。
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TPS92515AHV-Q1
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13 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且
不会对此文档进行修订。如需获取此数据表的浏览器版本，请查阅左侧的导航栏。
34
版权 © 2018, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPS92515AHVQDGQRQ1
TPS92515AHVQDGQTQ1
ACTIVE
ACTIVE
HVSSOP
HVSSOP
DGQ
DGQ
10
10
2500 RoHS & Green
250 RoHS & Green
NIPDAUAG
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 125
-40 to 125
1NIX
1NIX
NIPDAUAG
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Addendum-Page 2
GENERIC PACKAGE VIEW
DGQ 10
3 x 3, 0.5 mm pitch
PowerPADTM HVSSOP - 1.1 mm max height
PLASTIC SMALL OUTLINE
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224775/A
www.ti.com
PACKAGE OUTLINE
DGQ0010E
PowerPADTM - 1.1 mm max height
S
C
A
L
E
3
.
7
0
0
PLASTIC SMALL OUTLINE
C
5.05
4.75
TYP
SEATING PLANE
PIN 1 ID
AREA
A
0.1 C
8X 0.5
10
1
3.1
2.9
NOTE 3
2X
2
5
6
0.27
0.17
10X
3.1
2.9
1.1 MAX
0.08
C A
B
B
NOTE 4
0.23
0.13
TYP
SEE DETAIL A
EXPOSED
THERMAL PAD
4
5
0.25
GAGE PLANE
2.1
1.9
0.15
0.05
0.7
0.4
8
0 - 8
1
DETAIL A
TYPICAL
1.83
1.63
4221816/A 08/2015
PowerPAD is a trademark of Texas Instruments.
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-187, variation BA-T.
www.ti.com
EXAMPLE BOARD LAYOUT
DGQ0010E
PowerPADTM - 1.1 mm max height
PLASTIC SMALL OUTLINE
(2.2)
NOTE 9
(1.83)
SOLDER MASK
OPENING
SOLDER MASK
DEFINED PAD
SEE DETAILS
10X (1.45)
10X (0.3)
1
10
(1.3)
TYP
(2.1)
SOLDER MASK
OPENING
SYMM
(3.1)
NOTE 9
8X (0.5)
6
5
(R0.05) TYP
SYMM
METAL COVERED
BY SOLDER MASK
(
0.2) TYP
VIA
(1.3) TYP
(4.4)
LAND PATTERN EXAMPLE
SCALE:15X
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
METAL
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4221816/A 08/2015
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
8. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
numbers SLMA002 (www.ti.com/lit/slma002) and SLMA004 (www.ti.com/lit/slma004).
9. Size of metal pad may vary due to creepage requirement.
www.ti.com
EXAMPLE STENCIL DESIGN
DGQ0010E
PowerPADTM - 1.1 mm max height
PLASTIC SMALL OUTLINE
(1.83)
BASED ON
0.125 THICK
STENCIL
10X (1.45)
10X (0.3)
1
10
(2.1)
SYMM
BASED ON
0.125 THICK
STENCIL
8X (0.5)
5
6
(R0.05) TYP
SEE TABLE FOR
SYMM
(4.4)
DIFFERENT OPENINGS
FOR OTHER STENCIL
THICKNESSES
METAL COVERED
BY SOLDER MASK
SOLDER PASTE EXAMPLE
EXPOSED PAD
100% PRINTED SOLDER COVERAGE BY AREA
SCALE:15X
STENCIL
THICKNESS
SOLDER STENCIL
OPENING
0.1
2.05 X 2.35
1.83 X 2.1 (SHOWN)
1.67 X 1.92
0.125
0.150
0.175
1.55 X 1.77
4221816/A 08/2015
NOTES: (continued)
10. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
11. Board assembly site may have different recommendations for stencil design.
www.ti.com
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