TPS92682QRHMRQ1 [TI]
具有 SPI 的双通道恒压恒流控制器 | RHM | 32 | -40 to 125;
| 型号： | TPS92682QRHMRQ1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有 SPI 的双通道恒压恒流控制器 | RHM | 32 | -40 to 125 控制器 开关 |
| 文件： | 总97页 (文件大小：4918K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPS92682-Q1
SLUSCX8B – MARCH 2019 – REVISED JULY 2020
TPS92682-Q1 Dual-Channel Constant-Voltage and Constant-Current Controller
with SPI Interface
The device is programmable to operate in constant-
voltage (CV) or constant-current (CC) modes.
1 Features
•
•
AEC-Q100 grade 1 qualified
Functional Safety-Capable
In CV mode, TPS92682-Q1 can be programmed to
operate as two independent or dual-phase Boost
voltage regulators. The output voltage can be
programmed using an external resistor voltage
divider, and a SPI-programmable 8-bit DAC.
– Documentation available to aid functional safety
system design
Wide input voltage range: 4.5 V to 65 V
± 4% LED current accuracy over –40°C to 150°C
junction temperature range
•
•
In CC mode, the device is designed to support dual
channel step-up or step-down LED driver topologies.
LED current can be independently modulated using
analog or PWM dimming techniques. Analog dimming
with over 28:1 range is obtained using a
programmable 8-bit DAC. PWM dimming of LED
current is achieved either by directly modulating the
PWM input pins with the desired duty cycle, or using a
SPI-programmable 10-bit PWM counter. The optional
PDRV gate driver output can be used to drive an
external P-Channel series MOSFET.
•
•
SPI communication interface
SPI programmable features:
– Spread spectrum for improved EMI
– Soft-start timing
– ILED current and output voltage settings
– Current limit, overvoltage, fault-timer
– Single versus dual phase
– CV and CC mode configuration
Dual channel peak-current-mode (PCM) controller
Low input offset rail-to-rail current sense amplifier
Analog dimming
External series FET PWM dimming with integrated
P-channel driver interface
– Over 1000:1 PWM dimming range
Open-drain fault flag indicator per channel
Up to 1-MHz programmable switching frequency
with external clock synchronization capability
Comprehensive programmable fault protection
circuitry
•
•
•
•
The TPS92682-Q1 incorporates an advanced SPI-
programmable diagnostic and fault protection
mechanism including: cycle-by-cycle current limit,
output overvoltage and undervoltage protection, ILED
overcurrent protection, and thermal warning. The
device also includes an open-drain fault indicator
output per channel.
•
•
The TPS92682-Q1 includes an LH pin, when pulled
high, initiates the limp home (LH) condition. In LH
mode, the device uses a separate set of SPI-
programmed registers.
•
•
Wettable flank with VQFN package
Device Information
2 Applications
PART NUMBER
TPS92682-Q1
PACKAGE (1)
VQFN (32)
HTSSOP (32)
BODY SIZE (NOM)
5.0 mm x 5.0 mm
11.0 mm x 6.1 mm
•
•
•
Automotive forward lighting
Emergency vehicles
General lighting
TPS92682-Q1
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
3 Description
The TPS92682-Q1 is a dual-channel, peak current-
mode controller with SPI communication interface.
VBAT
VOUT1
VIN
ISP1
GATE1
EN
VDD
VBAT
PWM1
VCC
PWM2
SSN
TPS92682
PGND
SCK
SPI
LH
GATE2
MISO
MOSI
ISP2
VOUT2
FAULT1
FAULT2
Typical Application
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS92682-Q1
SLUSCX8B – MARCH 2019 – REVISED JULY 2020
www.ti.com
Table of Contents
1 Features............................................................................1
2 Applications.....................................................................1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
Pin Functions.................................................................... 4
6 Specifications.................................................................. 5
6.1 Absolute Maximum Ratings........................................ 5
6.2 ESD Ratings............................................................... 5
6.3 Recommended Operating Conditions.........................5
6.4 Thermal Information....................................................6
6.5 Electrical Characteristics.............................................7
6.6 Typical Characteristics.............................................. 11
7 Detailed Description......................................................15
7.1 Overview...................................................................15
7.2 Functional Block Diagram.........................................15
7.3 Feature Description...................................................18
7.4 Device Functional Modes..........................................31
7.5 Programming............................................................ 35
7.6 TPS92682 Registers.................................................37
8 Application and Implementation..................................53
8.1 Application Information General Design
Considerations............................................................ 53
8.2 Application Information CC Mode............................. 54
8.3 Typical Application CV Mode.................................... 60
8.4 Typical Application CC Mode....................................67
8.5 Typical Application CV Mode.................................... 76
9 Power Supply Recommendations................................81
10 Layout...........................................................................82
10.1 Layout Guidelines................................................... 82
10.2 Layout Example...................................................... 82
11 Device and Documentation Support..........................84
11.1 Receiving Notification of Documentation Updates..84
11.2 Support Resources................................................. 84
11.3 Trademarks............................................................. 84
11.4 Electrostatic Discharge Caution..............................84
11.5 Glossary..................................................................84
12 Mechanical, Packaging, and Orderable
Information.................................................................... 84
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (August 2019) to Revision B (May 2020)
Page
•
•
•
•
Added functional safety bullet to the Section 1 ..................................................................................................1
Updated the numbering format for tables, figures and cross-references throughout the document...................1
Added HTSSOP package...................................................................................................................................3
Added DAP package thermal information...........................................................................................................6
Changes from Revision * (March 2019) to Revision A (August 2019)
Page
•
Changed from Advance Information to Production Data ................................................................................... 1
Copyright © 2020 Texas Instruments Incorporated
2
Submit Document Feedback
Product Folder Links: TPS92682-Q1
TPS92682-Q1
SLUSCX8B – MARCH 2019 – REVISED JULY 2020
www.ti.com
5 Pin Configuration and Functions
VIN
EN
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
ISN1
ISP1
PWM1
PWM2
SSN
GATE1
VCC
Thermal
Pad
PGND
GATE2
ISP2
SCK
MISO
MOSI
ISN2
9
10 11 12 13 14 15 16
(Not to scale)
Figure 5-1. RHM Package 32-Pin VQFN with PowerPAD Top View
PGND
VCC
1
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
GATE2
ISP2
2
GATE1
ISP1
3
ISN2
4
FB2/OV2
CSP2
CSN2
PDRV2
COMP2
FLT2/SYNC
FLT1
ISN1
5
FB1/OV1
CSP1
CSN1
PDRV1
COMP1
AGND
VDD
6
7
Thermal
Pad
8
9
10
11
12
13
14
15
16
LH
MOSI
RT
MISO
VIN
SCK
EN
SSN
PWM1
PWM2
Figure 5-2. DAP Package 32-Pin TSSOP with PowerPAD Top View
Copyright © 2020 Texas Instruments Incorporated
Submit Document Feedback
3
Product Folder Links: TPS92682-Q1
TPS92682-Q1
SLUSCX8B – MARCH 2019 – REVISED JULY 2020
www.ti.com
Pin Functions
PIN
I/O (1)
DESCRIPTION
VQFN HTTSOP
NAME
NO.
NO.
AGND
30
11
10
P
Signal ground
Connect to an integral or integral-proportional compensation network to ensure stability for
channel-1.
COMP1
29
12
I/O
Connect to an integral or integral-proportional compensation network to ensure stability for
channel-2.
COMP2
25
I/O
CSN1
CSN2
CSP1
CSP2
EN
27
14
26
15
2
8
I
I
I
I
I
High-side current sense amplifier input (–) for channel-1
High-side current sense amplifier input (–) for channel-2
High-side current sense amplifier input (+) for channel-1
High-side current sense amplifier input (+) for channel-2
Hardware enable. Pull this pin low to enter shutdown.
27
7
28
15
Connect using a resistor divider to VOUT1 to set OVP threshold (and VOUT in CV mode) for
channel-1.
FB1/OV1
FB2/OV2
FLT1
25
16
10
11
6
I/O
I/O
O
Connect using a resistor divider to VOUT2 to set OVP threshold (and VOUT in CV mode) for
channel-2.
29
23
24
Open-drain fault output for channel-1 (or both channels if PIN-11 is programmed to be
SYNC).
FLT2/
SYNC
I/O
Dual function pin (programmable) either open-drain fault output for channel-2 or SYNC input
GATE1
GATE2
22
19
3
I/O
I/O
Channel-1 gate driver output for external N-channel FET
Channel-2 gate driver output for external N-channel FET
32
Switch current sense input (-) for channel-1. Connect to the GND connection of the external
switch-current sense resistor.
ISN1
ISN2
ISP1
ISP2
24
17
23
18
5
30
4
I
I
I
I
Switch current sense input (-) for channel-2. Connect to the GND connection of the external
switch-current sense resistor.
Switch current sense input (+) for channel-1. Connect to external switch current sense
resistor between N-channel FET and ground.
Switch current sense input (+) for channel-2. Connect to external switch current sense
resistor between N-channel FET and ground.
31
LH
9
7
22
20
21
9
I
O
I
Digital input, when set high, the device enters the limp home mode.
SPI slave data output
MISO
MOSI
PDRV1
PDRV2
PWM1
PWM2
PGND
RT
8
SPI slave data input
28
13
3
I/O
I/O
I
Channel-1 P-channel gate driver. Connect to gate of external series P-channel FET switch.
Channel-2 P-channel gate driver. Connect to gate of external series P-channel FET switch.
Connect to external PWM signal to enable PWM dimming for channel-1.
Connect to external PWM signal to enable PWM dimming for channel-2.
Power ground
26
16
17
1
4
I
20
32
6
P
I/O
I
13
19
18
2
Set internal clock frequency by connecting a resistor to ground
SPI clock input
SCK
SSN
5
I
SPI chip select input
VCC
21
31
1
P
P
P
7.5-V low-dropout regulator output
VDD
12
14
5-V LDO output
VIN
High-voltage input (65 V) to internal LDO
(1) I = input, O = output, P = power
Copyright © 2020 Texas Instruments Incorporated
4
Submit Document Feedback
Product Folder Links: TPS92682-Q1
TPS92682-Q1
SLUSCX8B – MARCH 2019 – REVISED JULY 2020
www.ti.com
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1) (2)
MIN
–0.3
MAX
65
UNIT
V
VIN, EN, CSPx, CSNx
CSPx to CSNx (3)
–0.3
0.3
8.8
5.5
5.5
5.5
8.8
5.5
VCSP
5.5
4
V
ISPx, ISNx
Input voltage
–0.3
V
SSN, SCK, MOSI, LH, RT, FLTx
–0.3
V
FBx/OVx
PWMx
–0.3
V
–0.3
V
VCC, GATEx
VDD
–0.3
V
–0.3
V
Output voltage(4)
PDRV
VCSP –8.8
–0.3
V
MISO
V
COMPx
–0.3
V
IGATE, (pulsed < 20 ns)
IPDRV, (pulsed < 10 µs)
IGATE (pulse < 20 ns)
IDDRV (pulse < 10 µs)
500
50
mA
mA
mA
mA
°C
°C
Source current
Sink current
500
50
Operating junction temperature, TJ
Storage temperature, Tstg
–40
150
165
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages are with respect to GND unless otherwise noted
(3) Continuous sustaining voltage
(4) All output pins are not specified to have an external voltage applied.
6.2 ESD Ratings
VALUE
±2000
±500
UNIT
Human-body model (HBM), per AEC Q100-002, all pins(1)
Charged-device model (CDM), per AEC Q100-011
Electrostatic
discharge
V(ESD)
V
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
6.5
NOM
MAX
UNIT
V
VIN
Supply input voltage
14
65
VIN, crank
VCSP, VCSN
fSW
Supply input, battery crank voltage
Current sense common mode voltage (1)
Switching frequency
4.5
V
0
60
700
V
100
0.8×fCLK
0.1
kHz
Hz
kHz
°C
fSYNC
FSS
Synchronization frequency range, vs fCLK set by RT
Spread-spectrum modulation frequency
Operating ambient temperature
1.2×fCLK
10
TA
–40
125
(1) For current sense common mode voltage below 6.5 V, PFET dimming may not be applied
Copyright © 2020 Texas Instruments Incorporated
Submit Document Feedback
5
Product Folder Links: TPS92682-Q1
TPS92682-Q1
www.ti.com
UNIT
SLUSCX8B – MARCH 2019 – REVISED JULY 2020
6.4 Thermal Information
TPS92682-Q1
THERMAL METRIC(1)
RHM (VQFN) DAP (HTSSOP)
32 PINS
31.2
21.9
12.1
0.2
32 PINS
27.3
18.7
9.7
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
0.2
ψJB
12.0
2.3
9.6
RθJC(bot)
2.1
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
Copyright © 2020 Texas Instruments Incorporated
6
Submit Document Feedback
Product Folder Links: TPS92682-Q1
TPS92682-Q1
SLUSCX8B – MARCH 2019 – REVISED JULY 2020
www.ti.com
6.5 Electrical Characteristics
–40°C < TJ < 150°C, VIN= 14V, VIADJDACx = 0xDF, CVCC = 1μF, CVDD = 1μF, CCOMP = 2.2nF, RCS = 100mΩ, RT
= 50kΩ, VPWM = 5V, no load on GATE and PDRV, DIV=4 (unless otherwise noted)
PARAMETER
INPUT VOLTAGE (VIN)
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VEN = 0 V, VCSP = VCSN = VPDRV = 0
V
10
10.5
2.3
IIN-SHDN
Input shutdown current
µA
VEN = 0 V, VCSP = 14 V
Software EN1 and EN2 = 0, VPWM1
VPWM2 = 0 V
=
IIN-STBY
IIN-SW
Input standby current
mA
mA
VCC=7.5V, CGATEx = 1nF, Both
channels are switching
Supply switching current
10
VCC BIAS SUPPLY
VCC rising threshold,
VVIN = 8 V
4.5
4.1
4.9
V
V
VCCUVLO
Supply under-voltage protection
VCC falling threshold,
VVIN = 8 V
3.7
Hysteresis
411
7.5
mV
V
VCC(REG)
IVCC(LIMIT)
VCCDO
VCC regulation voltage
VCC current limit
No load
7
8
VVCC = 0 V
40
mA
mV
VCC LDO dropout voltage
IVCC = 30 mA, VVIN = 4.5 V
300
5
475
VDD BIAS SUPPLY
VDD(REG)
VDD regulation voltage
No load
4.85
2.58
30
5.25
4.1
V
V
VDD(POR-RISE)
VDD(POR-FALL)
VDDDO
VDD rising threshold
VDD falling threshold
VDD LDO dropout voltage
VDD current limit
VVIN = 5 V
VVIN = 5 V
V
IVDD = 15 mA, VVIN = 4.5 V
VVDD = 0 V
400
50
mV
mA
IVDD(LIMIT)
39
ENABLE INPUT
VEN
EN voltage threshold
EN pin hysteresis
1.12
1.21
100
5
1.3
V
Difference between rising and falling
threshold
VEN-HYS
mV
µA
IEN
EN PIN input bias current
VEN = 14 V
OSCILLATOR
RT = 200kΩ, DIV=4
RT = 50kΩ, DIV=4
85
100
400
1
115
460
kHz
kHz
V
fSW
Switching frequency
RT PIN voltage
340
VRT
SPREAD SPECTRUM DAC
DACDT-BITs
DACDT-MAX
DACDT-MIN
GATE DRIVER
RGH
Internal DAC resolution
8
Bits
V
DAC maximum voltage
DAC minimum voltage
1.156
855
mV
Driver pull-up resistance
IGATE = –10 mA
IGATE = 10 mA
5.1
4.1
11.2
10.5
Ω
Ω
RGL
Driver pull-down resistance
SWITCH CURRENT SENSE and ILIMIT
ILIM threshold PWM = LOW
VPWMx= 0 V, CHxILIM = XX
VPWMx= 5 V, CHxILIM = 11
VPWMx= 5 V, CHxILIM = 10
VPWMx= 5 V, CHxILIM = 01
VPWMx= 5 V, CHxILIM = 00
649
228
132
82
711
253
769
277
171
119
93
mV
mV
mV
mV
mV
VILIM(THR)
151
ILIM threshold PWM = HIGH
100.6
75.2
57
Copyright © 2020 Texas Instruments Incorporated
Submit Document Feedback
7
Product Folder Links: TPS92682-Q1
TPS92682-Q1
SLUSCX8B – MARCH 2019 – REVISED JULY 2020
www.ti.com
PARAMETER
TEST CONDITIONS
CHxLEB = 0
MIN
TYP
75
MAX
UNIT
ns
tIS(BLANK)
Leading edge blanking
CHxLEB = 1
150
86
ns
tILIMIT(DELAY)
ISx to GATEx delay
ns
PWM COMPARATOR
DMAX
Maximum duty cycle
90
%
mV
µA
Difference between CH1 and CH2
PWM comparator offset
VLVx-Delta
ILVx
–17.5
17.5
IS level shift bias current
No slope compensation added
40
Turn-off propagation delay from
input of PWM comp. to gate
output
TPWM-Delta
100
ns
ns
Difference between CH1 and CH2
PWM comp. propagation delay
TPWMDEL-Delta
–30
30
CURRENT SENSE AMPLIFIER (CSP, CSN)
VCSP(CM) = 14 V, IADJDAC = 0×FF
VCSP(CM) = 14V, IADJDAC = 0x95
VCSP(CM) = 14V, IADJDAC = 0×0F
165.8
96.5
172.7
100.8
10.3
179.6
104.5
mV
mV
mV
V(CSP-CSN)x
Current Sense REG Voltage
Current sense unity gain
bandwidth
CS(BW)
GCS
K(OCP)
K(UC)
500
14
kHz
V/V
V/V
V/V
Current Sense Gain = VIADJ/V(CSP-
VCS = 150 mV, VCSP = 60 V
K(OCP) = V(OCP-THR)/VIADJ
K(UC) = V(UC-THR)/VIADJ
CSN)
Ratio of over-current detection
threshold to VIADJ
1.41
1.53
0.5
1.66
Ratio of under-current detection
threshold to VIADJ
ICSP(BIAS)
ICSN(BIAS)
SSDAC
CSP bias current
CSN bias current
VCSP = VCSN = VPDRV = 14 V
VCSP = VCSN = VPDRV = 14 V
59
59
µA
µA
DACSS-BITs
DACSS-FS
CALDAC
Internal DAC resolution
DAC full scale voltage
8
Bits
V
2.8
Switch current sense calibration
DAC
DACCAL-BITs
DACCAL-RES
3
Bits
mV
Offset-per-Bit applied to the switch
current sense
2.5
FAULT FLAG ( FLTx)
R( FLT)
Open-drain pull down resistance
36
Ω
VIADJDAC
DACADJ-BITs
DACADJ-FS
Internal DAC resolution
DAC full scale voltage
8
Bits
V
2.32
2.4
2.48
ERROR AMPLIFIER (COMP)
HG = 0
HG = 1
122
914
gM
Transconductance
µA/V
µA
IADJx = 0×95, V(CSP-CSN) = 0 V, HG =
0
129
777
129
783
ICOMP(SRC)
COMP source current capacity
COMP sink current capacity
IADJx = 0×95, V(CSP-CSN) = 0 V, HG =
1
IADJx = 0×00, V(CSP-CSN) = 0.1 V, HG
= 0
ICOMP(SINK)
µA
IADJx = 0×00, V(CSP-CSN) = 0.1 V, HG
= 1
Copyright © 2020 Texas Instruments Incorporated
8
Submit Document Feedback
Product Folder Links: TPS92682-Q1
TPS92682-Q1
SLUSCX8B – MARCH 2019 – REVISED JULY 2020
www.ti.com
PARAMETER
TEST CONDITIONS
Gain = –3 dB, HG = 0
MIN
TYP
5
MAX
UNIT
EA(BW)
Error amplifier bandwidth
MHz
Gain = –3 dB, HG = 1
1
VCOMP(RST)
RCOMP(DCH)
VCOMP reset voltage
100
248
mV
Ω
COMPx discharge FET RDSON
COMP1 to COMP2 short path
resistance
RCOMP(DIFF)
300
Ω
SLOPEDAC
DACSLP-FS
VFB
DAC full scale voltage
0.36
V
VFBERR
VFBBIAS
OVDAC
Regulation voltage error
–4
4
%
VFB pin pull up bias current
200
nA
OV limit threshold, 0%
OV limit threshold, 2.5%
OV limit threshold, 5%
OV limit threshold, 7.5%
OV limit threshold, 10%
OV limit threshold, 12.5%
OV limit threshold, 15%
OV limit threshold, 20%
OV hysteresis current
CHxOVDAC = 000
CHxOVDAC = 001
CHxOVDAC = 010
CHxOVDAC = 011
CHxOVDAC = 100
CHxOVDAC = 101
CHxOVDAC = 110
CHxOVDAC = 111
1.2
1.237
1.268
1.299
1.329
1.36
1.27
V
V
V
V
VOV(THR)
V
1.391
1.422
1.483
20.5
V
V
V
IOV-HYS
UV (Output Under Voltage)
11.5
40
28.5
67
µA
VUV(THR)
Under voltage protection threshold
Under voltage blanking period
53.2
5
mV
µs
tUV(BLANK)
DIGITAL INPUTs (PWMx, SYNC, FS, SSN, SCK, MOSI)
IBIAS
Input bias current
Falling threshold
Rising threshold
Except PWM inputs
1
µA
V
VTINPUT-FALL
VTINPUT-RISE
PWM INPUT (PWM)
0.7
1.85
V
RPWM(PD)
tDLY(RISE)
tDLY(FALL)
PWM pull-down resistance
10
MΩ
ns
PWM rising to PDRV delay
PWM falling to PDRV delay
CPDRV = 1 nF
CPDRV = 1 nF
235
222
ns
PFET GATE DRIVE
VPDRV(OFF)
VPDRV(ON)
IPDRV(SINK)
RPDRV
PDRV off-state voltage
VCSP = 14 V
14
7.34
29
V
V
PDRV on-state voltage
PDRV sink current
VCSP = 14 V
VCSP – VPDRV = 5 V, pulsed < 100 µs
VCSP – VPDRV = 0 V, pulsed < 100 µs
mA
Ω
PDRV pull up resistance
83.5
SPI INTERFACE
VOL-MISO
Output low voltage threshold
I(MISO) = 10 mA
0.25
25
V
Ω
RDS-MISO
CMISO
10
pF
Falling edge of SSN to 1st SCK rising
edge
tSS-SU
tSS-H
tSS-HI
tSCK
SSN setup time
SSN hold time
500
250
ns
ns
Falling edge of 16th SCK to SSN
rising edge
Time SSN must remain high between
transactions
SSN high time
SCK period
1
µs
ns
Clock period
500
Copyright © 2020 Texas Instruments Incorporated
Submit Document Feedback
9
Product Folder Links: TPS92682-Q1
TPS92682-Q1
SLUSCX8B – MARCH 2019 – REVISED JULY 2020
www.ti.com
PARAMETER
TEST CONDITIONS
Clock duty cycle
MIN
40
TYP
MAX
UNIT
%
DSCK
SCK duty cycle
MOSI setup time
MOSI hold time
60
tMOSI-SU
tMOSI-H
MOSI valid to rising edge SCK
MOSI valid after rising edge SCK
125
140
ns
ns
Time to tristate MISO after SSN rising
edge
tMISO-HIZ
tMISO-HL
MISO tristate time
110
320
320
ns
ns
Time to place valid "0" on MISO after
falling SCK edge.
MISO valid high-to-low
Time to tri-state MISO after falling
SCK edge. tRC is the time added by
the application total capacitance and
resistance.
tMISO-LH
MISO valid low-to-high
320+tRC
320
ns
ns
TZO-HL
MISO drive time high-to-low
SSN Falling Edge to MISO Falling
Copyright © 2020 Texas Instruments Incorporated
10
Submit Document Feedback
Product Folder Links: TPS92682-Q1
TPS92682-Q1
SLUSCX8B – MARCH 2019 – REVISED JULY 2020
www.ti.com
6.6 Typical Characteristics
TA = 25°C free air, VIN = 14 V, DIV = 2 (CHxDIV = 0x00) unless otherwise specified
7.54
7.53
7.52
7.51
7.5
5.02
5.01
5
4.99
4.98
4.97
4.96
4.95
7.49
7.48
7.47
7.46
7.45
7.44
-50 -30 -10
10
30
50
70
90
110 130 150
-50 -30 -10
10
30
50
70
90
110 130 150
Junction Temperature (oC)
Junction Temperature (oC)
VCC_
VDD_
IVCC = 20 mA
IVDD = 20 mA
Figure 6-1. Regulated VCC Voltage vs Junction
Temperature
Figure 6-2. Regulated VDD Voltage vs Junction
Temperature
450
400
350
300
250
200
150
51
50.5
50
49.5
49
48.5
48
47.5
47
-50
-30
-10
10
30
50
70
90
110 130 150
-50 -30 -10
10
30
50
70
90
110 130 150
Junction Temperature (oC)
Junction Temperature (oC)
VCC_
VCC_
VIN = 4.5 V, IVCC = 30 mA
Figure 6-4. VCC Current Limit vs Junction
Temperature
Figure 6-3. VCC Dropout Voltage vs Junction
Temperature
1.01
1.006
1.002
0.998
0.994
0.99
4.6
4.55
4.5
4.45
4.4
4.35
4.3
4.25
4.2
4.15
4.1
4.05
4
Rising
Falling
3.95
3.9
-50 -30 -10
10
30
50
70
90 110 130 150
-50 -30 -10
10
30
50
70
90
110 130 150
Junction Temperature (oC)
Junction Temperature (oC)
VRT_
VCC_
Figure 6-6. RT Pin Voltage vs Junction
Temperature
Figure 6-5. VCC UVLO Threshold vs Junction
Temperature
Copyright © 2020 Texas Instruments Incorporated
Submit Document Feedback
11
Product Folder Links: TPS92682-Q1
TPS92682-Q1
SLUSCX8B – MARCH 2019 – REVISED JULY 2020
www.ti.com
402
401.5
401
201
200.8
200.6
200.4
200.2
200
400.5
400
199.8
199.6
199.4
199.2
199
399.5
399
398.5
398
-50 -30 -10
10
30
50
70
90 110 130 150
-50 -30 -10
10
30
50
70
90 110 130 150
Junction Temperature (oC)
Junction Temperature (oC)
FSW_
FSW_
RT = 50 kΩ, CHxDIV = 01
RT = 100 kΩ, CHxDIV = 01
Figure 6-7. Switching Frequency vs Junction
Temperature
Figure 6-8. Switching Frequency vs Junction
Temperature
90.6
90.4
90.2
90
252
251
250
249
248
247
89.8
89.6
89.4
89.2
89
-50 -30 -10
10
30
50
70
90
110 130 150
-50
-30
-10
10
30
50
70
90
110 130 150
Junction Temperature (oC)
Junction Temperature (oC)
DMAX
ILIM
RT = 50 kΩ, CHxDIV = 01
CHxILIM = 11
Figure 6-9. Maximum Duty Cycle vs Junction
Temperature
Figure 6-10. ISP Current Limit Threshold vs
Junction Temperature
100.6
100.4
100.2
100
1.236
1.232
1.228
1.224
1.22
99.8
99.6
99.4
99.2
99
1.216
-50 -30 -10
10
30
50
70
90 110 130 150
-50 -30 -10
10
30
50
70
90 110 130 150
Junction Temperature (oC)
Junction Temperature (oC)
ILIM
VOV_
CHxILIM = 01
CHxOV = 000
Figure 6-11. ISP Current Limit Threshold vs
Junction Temperature
Figure 6-12. Over Voltage Protection Threshold vs
Junction Temperature
Copyright © 2020 Texas Instruments Incorporated
12
Submit Document Feedback
Product Folder Links: TPS92682-Q1
TPS92682-Q1
SLUSCX8B – MARCH 2019 – REVISED JULY 2020
www.ti.com
1.49
20.8
20.6
20.4
20.2
20
1.485
1.48
1.475
1.47
19.8
19.6
19.4
1.465
1.46
-50 -30 -10
10
30
50
70
90 110 130 150
-50 -30 -10
10
30
50
70
90
110 130 150
Junction Temperature (oC)
Junction Temperature (oC)
VOV_
IOV_
CHxOV = 111
Figure 6-14. OVP Hysteresis Current vs Junction
Temperature
Figure 6-13. Over Voltage Protection Threshold vs
Junction Temperature
62
61.5
61
62
61.5
61
60.5
60
60.5
60
59.5
59
59.5
59
58.5
58
58.5
58
-50 -30 -10
10
30
50
70
90
110 130 150
-50 -30 -10
10
30
50
70
90
110 130 150
Junction Temperature (oC)
Junction Temperature (oC)
CSP_
CSN_
VCSP = 14 V
VCSN = 14 V
Figure 6-15. CSP Pin Input Bias Current vs
Junction Temperature
Figure 6-16. CSN Pin Input Bias Current vs
Junction Temperature
2.408
2.406
2.404
2.402
2.4
1.408
1.406
1.404
1.402
1.4
2.398
2.396
2.394
2.392
1.398
1.396
1.394
1.392
-50 -30 -10
10
30
50
70
90 110 130 150
-50 -30 -10
10
30
50
70
90 110 130 150
Junction Temperature (oC)
Junction Temperature (oC)
VIAD
VIAD
CHxIADJ = FF (hex)
CHxIADJ = 95 (hex)
Figure 6-17. VIADJ Voltage vs Junction
Temperature
Figure 6-18. VIADJ Voltage vs Junction
Temperature
Copyright © 2020 Texas Instruments Incorporated
Submit Document Feedback
13
Product Folder Links: TPS92682-Q1
TPS92682-Q1
SLUSCX8B – MARCH 2019 – REVISED JULY 2020
www.ti.com
173
172.5
172
102
101.5
101
171.5
171
100.5
100
170.5
170
99.5
99
169.5
169
98.5
98
-50 -30 -10
10
30
50
70
90 110 130 150
-50 -30 -10
10
30
50
70
90 110 130 150
Junction Temperature (oC)
Junction Temperature (oC)
VCSP
VCSP
CHxIADJ = FF (hex)
CHxIADJ = 95 (hex)
Figure 6-19. V(CSP – VCSN) Voltage vs Junction
Temperature
Figure 6-20. V(CSP – VCSN) Voltage vs Junction
Temperature
1.51
1.505
1.5
1000
800
600
400
200
0
1.495
1.49
-50 -30 -10
10
30
50
70
90 110 130 150
20
30 40 50 6070 100
200 300
500 700 1000
Junction Temperature (oC)
Resistance RT (kW)
KOCP
FSW_
CHxIADJ = 95 (hex)
Figure 6-22. Channel Switching Frequency FSW vs
RT Resistance
Figure 6-21. Over Current Protection Gain vs
Junction Temperature
Copyright © 2020 Texas Instruments Incorporated
14
Submit Document Feedback
Product Folder Links: TPS92682-Q1
TPS92682-Q1
SLUSCX8B – MARCH 2019 – REVISED JULY 2020
www.ti.com
7 Detailed Description
7.1 Overview
The TPS92682-Q1 device is an automotive-grade two-channel controller with Serial Peripheral Interface (SPI)
interface, ideally suited for exterior lighting applications. The device is optimized to achieve high-performance
solutions and features all of the functions necessary to implement LED drivers based on step-up or step-down
power converter topologies with a small form-factor at a lower cost.
The two channels of the TPS92682-Q1 device can be configured independently as CC (constant current) or CV
(constant voltage) mode. The device implements fixed-frequency peak current mode control to achieve
regulation and fast dynamic response. Each channel can be configured as boost, boost-to-battery, SEPIC, or
other converter topologies.
In CC mode, the integrated low offset and rail-to-rail current sense amplifier provide the flexibility required to
power a single string consisting of 1 to 20 series connected LEDs while maintaining 4% current accuracy over
the operating temperature range. The LED current regulation threshold is set by the analog adjust input
CHxIADJ register over 28:1 dimming range. The TPS92682-Q1 incorporates an internal 10-bit counter for the
PWM dimming function for each channel. The PWM width and frequency are programmable through the SPI
registers. Alternatively, the device can also be configured to implement direct PWM dimming based on the duty
cycle of the external PWM signal connected to PWM1 or PWM2 pins for channel-1 or channel-2, respectively.
The internal PWM signals control the GATEx and PDRVx outputs, which control the external N-channel
switching FETs and P-channel dimming FETs connected in series with LED strings.
The TPS92682-Q1 can be configured in CV mode. In this mode, the device regulates the voltage connected to
the FBx/OVx pins to an internal programmable reference voltage, set by the CHxIADJ register. In CV mode, the
TPS92682-Q1 can be used as the first stage of a two-stage LED driver in an ECU (electronic control unit) of an
exterior lighting application. The device can also be configured to operate in two-phase mode, where the
switching frequencies of the two channels are phase-shifted by 180° and the channel-1 compensation loop,
including COMP1 and the FB1/OV1, is shared between the two channels.
The TPS92682-Q1 incorporates an enhanced programmable fault feature. A selected number of faults, including
ILIMIT (cycle-by-cycle current limit), OV (output Overvoltage), UV (output Undervoltage), and OC (LED
Overcurrent), can be programmed to be latched faults, or automatically re-start the channel when the fault is
cleared and after a programmed timer is expired. In addition, the TPS92682-Q1 includes open-pin faults for the
FBx, ISNx, and RT pins. Other fault and diagnostic features include Thermal Shutdown (TSD), Thermal Warning
(TW), LED Undercurrent (UC), and POR. Each channel includes an active-low fault pin ( FLT) that is pulled low
when a fault occurs. For each fault, there is an associated fault read-bit in the register map that can be read
through SPI communication interface. For a complete list of the fault and diagnostic features, refer to Section
7.3.16.
The TPS92682-Q1 includes a limp home (LH) function that is initiated when the LH pin is set high. In LH mode,
the operation of the device is set by the LH registers. The LH registers are programmed upon initialization of the
device. To exit the LH mode, the LH pin must be set low and the LH bit in the CFG1 register must be written to
“0”.
The TPS92682-Q1 device has numerous enhanced programmable features that can be accessed through the 4-
wire SPI bus. The SPI bus consists of four signals: SSN, SCK, MOSI, and MISO. The SSN, SCK, and MOSI pins
are TTL inputs into the device.
7.2 Functional Block Diagram
The block diagram below shows the associated blocks for channel-1. Channel-2 has a similar configuration.
Copyright © 2020 Texas Instruments Incorporated
Submit Document Feedback
15
Product Folder Links: TPS92682-Q1
TPS92682-Q1
SLUSCX8B – MARCH 2019 – REVISED JULY 2020
www.ti.com
5V LDO
VDD
TSD
TW
POR
Thermal
Limit
POR
VIN
7.5V LDO
VCC
UVLO
EN
UVLO
CH1_Gate
CH1_s
EN
CH1_MAXD
PWM1
GATE1
PGND
S
Q
1
0
1
0
R
Dominant
CH1_Clk100p
CH1_MAXD
Power_FLT
R
RT OPEN
RT_Open
CH1_MAXD_EN
POR
RT
CH1_Clk10p
CH1_Clk100p
CSP1
OSCILLATOR
Clk_M
FMDAC
DAC
Dither
CH1_s
Dither_EN
SYNC
PWM1
CH1&2_Clk100p
CH1&2_Clk10p
CHx_Islope
CH1_EN
CH1&2_CLK
CH1&2_DIV
Slope Gen. &
MAX Duty
100%
10%
PDRV1
Power_FLT
CH1_nPDRV
CH1&2_ISLP
Clk10p
Clk100p
VDD
PWM1
PWM1
PWM1
0
CH1_OV_EN
CH1_close_comp_n
CH1_close_comp
R
Q
R
Dominant
1
CH1_Duty
S
VDD
+
CH1_OV
INT_PWM
CH1_PWM_O
œ
1.23V
ref
0
CH1_OVDAC
DAC
OV
0
1
CH2_comp
2PH
100mV
+
CH1_EAref
CH1_complow
1
œ
CH1_CV
CH1_comp
CH1_close_comp
COMP1
CH1_UV
5ms
Delay
FB1/OV1
œ
Power_FLT
+
CH1_VFB
50mV
CH1_PD_comp
CH1_PD_O
CH1_IADJ
DAC1
IADJ
CH1_Islope
VDD
CH1_close_comp
CH1_OC
CH1_UC
10ms
Filter
CH1_LBSEL
CH1_EAref
OC/UC
SENSE
(150%/50%)
+
CH1_Duty
gM
CH1_close_comp
œ
+
CH1_EA_FB
LEB
CH1_Gate
CSP1
CSN1
œ
CH1_HG
+
CH1_Isense
x14
0
œ
CH1_comp
CH1_VFB
1
CH1_PD_O
CH1_close_comp
CH1_CV
DAC
SS1
FLT1
CH1_SSDAC
ISP1
ISN1
0
1
+
CH1_ILIMIT
CH1_FAULT
CH2_FAULT
CH1_FILT1
œ
SYNC_EN
SYNC
CH1_close_comp_n
TSD
BG_NOK
UVLO
SYNC/FLT2
Power_FLT
CH1ILIM
20mA
VDD
POR
CH1_IS_OPEN
Copyright © 2020 Texas Instruments Incorporated
16
Submit Document Feedback
Product Folder Links: TPS92682-Q1
TPS92682-Q1
SLUSCX8B – MARCH 2019 – REVISED JULY 2020
www.ti.com
VDD
CH1&2_IADJ
CH1&2ILIM
CH1&2_PWM
Clk_M
CH1&2_ISLP
CH1&2_OVDAC
CH1&2_SSDAC
CH1&2_DIV
FMDAC
DIGITAL
BLOCK
CH1&2_IS_OPEN
CH1&2_OV
CH1&2_UV
CH1&2_OC
CH1&2_UC
CH1&2_ILIMIT
CH1&2_complow
POR
CH1&2_LBSEL
CH1&2_FILT1
RSVD
AGND
TW
RSVD
RTOP
CH1&2_HG
LH
CH1&2_EN
CH1&2_CLK
CH1&2_OVEN
CH1&2_UV_EN
CH1&2_OC_EN
CH1&2_FBO_EN
CH1&2_PWM_O
CH1&2_PD_comp
INT_PWM
LH
LH
CH1&2_nPDRV
2PH
CH1&2_CV
CH1&2_MAXD_EN
CH1&2_FAULT
SYNC_EN
MISO
DITHER_EN
MOSI
SSN
SCK
MOSI
SSN
SCK
MISO
SPI
Interface
Copyright © 2020 Texas Instruments Incorporated
Submit Document Feedback
17
Product Folder Links: TPS92682-Q1
TPS92682-Q1
SLUSCX8B – MARCH 2019 – REVISED JULY 2020
www.ti.com
7.3 Feature Description
The TPS92682-Q1 device implements a fixed frequency Peak Current Mode (PCM) control. In PCM, the
switching cycle starts with a rising edge of the clock. The switching cycle ends when the sensed switch current,
ViSW (added with VSLOPE), exceeds the compensator voltage, VCOMP. As shown in Figure 7-1 and Figure 7-2, a
transconductance gM error amplifier generates an error signal by comparing the feedback signal and the
reference voltage, VREF. The resulting error current generates the compensator voltage VCOMP, through a
compensator impedance, connected to the COMPx pin.
For stability at high duty cycle and better noise immunity, a compensation ramp VSLOPE is added to the sensed
switch current ViSW
.
VIN
L
RCS
CHxCLK
S
Q
R
Dominant
GATEx
COUT
R
RIS
VSLOPE
PWM
Comp
ViSW
+
S
ISPx
œ
EA
Amp
CS
Amp
VCOMP
VREF
CSPx
CSNx
+
gM
+
œ
œ
COMPx
CCOMP
Figure 7-1. PCM Control in CC Mode
VOUT
VIN
L
RFB2
CHxCLK
GATEx
S
Q
R
Dominant
COUT
R
RIS
RFB1
VSLOPE
PWM
Comp
ViSW
ISPx
+
S
œ
EA
Amp
VCOMP
VREF
+
gM
FBx
œ
COMPx
CCOMP
Figure 7-2. PCM Control in CV Mode
Copyright © 2020 Texas Instruments Incorporated
18
Submit Document Feedback
Product Folder Links: TPS92682-Q1
TPS92682-Q1
SLUSCX8B – MARCH 2019 – REVISED JULY 2020
www.ti.com
VCOMP
VSLOPE
ViSW
DTSW
TSW
Figure 7-3. PCM Control and Ramp Compensation
7.3.1 Device Enable
The TPS92682-Q1 can be enabled or disabled by the EN pin or the software enable bits. When EN pin is pulled
low, the device enters shutdown state, where the quiescent current of the device is decreased to IIN-SHDN. In
shutdown state, the internal regulators are turned off and the registers are reset. When the voltage on the enable
pin is increased above the voltage threshold of VEN, the two channels can be enabled. In addition to the EN pin,
there are two enable bits for the two channels of the TPS92682-Q1 as shown in Table 7-2. In order for each
channel to be turned on, the associated CHxEN bit must be set to "1" in Section 7.6.1.
In addition to the EN pin and the CHxEN bits, the PWMx signals (hardware or software) must be set high and the
associated CHxIADJ must be set to a value greater than eight (refer to Section 7.6.8) in order for the associated
channel to be turned on.
7.3.2 Internal Regulator and Undervoltage Lockout (UVLO)
The device incorporates 65-V input voltage rated linear regulators to generate the 7.5-V (typical) VCC bias
supply, the 5-V (typical) VDD supply, and other internal reference voltages. The device monitors the VCC output
to implement UVLO protection. Operation is enabled when VCC exceeds the 4.5-V (typ) threshold and is
disabled when VCC drops below the 4.1-V (typical) threshold. The UVLO comparator provides a hysteresis to
avoid chatter during transitions. The UVLO thresholds are internally fixed and cannot be adjusted. An internal
current limit circuit is implemented to protect the device during VCC pin short-circuit conditions. The VCC supply
powers the internal circuitry and the N-channel gate driver outputs, GATEx. Place a bypass capacitor in the
range of 2.2 μF to 4.7 μF across the VCC output and GND to ensure proper operation. The regulator operates in
dropout when input voltage VIN falls below 7.5 V. The VCC is a regulated output of the internal regulator and is
not recommended to be driven with an external power supply.
The internal VDD regulator is used to generate supply voltage for various internal analog and digital circuits. The
supply current is internally limited to protect the device from output overload and short-circuit conditions. Place a
bypass capacitor in the range of 2.2 μF to 4.7 μF across the VDD output to GND to ensure proper operation. The
POR circuit of the device is placed at the output of the VDD regulator. The POR rise and fall thresholds are
provided in Section 6.5.
7.3.3 Oscillator
The internal clock frequency of the TPS92682-Q1 device is programmable by a single external resistor,
connected between the RT pin and the GND. The relationship between the resistor RT and the internal main
clock (CLKM) frequency is shown in Equation 1 and Figure 6-22.
1012
fCLKM
=
12.5ìRT
(1)
The relationship between the channel clock, CHxCLK (or the channel switching frequency fSW), and fCLKM is
shown in Section 7.6.4. TI recommends a switching frequency setting between 100 kHz to 700 kHz for best
efficiency and for optimal performance over input and output voltage operating range. Operation at higher
switching frequencies requires careful selection of N-channel MOSFET characteristics as well as detailed
analysis of switching losses.
Copyright © 2020 Texas Instruments Incorporated
Submit Document Feedback
19
Product Folder Links: TPS92682-Q1
TPS92682-Q1
SLUSCX8B – MARCH 2019 – REVISED JULY 2020
www.ti.com
To use the synchronization functionality of the TPS92682-Q1, the SYNCEN bit shown in Table 7-3 must be set to
"1", and a square wave signal with the desired fCLKM frequency must be applied to the SYNC pin.
RT
RT
Oscillator
CLKM
SYNC
fSYNC
Figure 7-4. TPS92682 SYNC Function
7.3.4 Spread Spectrum Function
The main clock of the TPS92682-Q1, CLKM, is generated using an internal ramp generator as shown in Figure
7-5. The internal ramp, RAMPCLKM, is compared with a reference voltage of VOSCREF to reset the ramp at the
end of the clock period, TCLKM. When the reference voltage VOSCREF is constant (1 V), the main clock
frequency is fixed. The frequency modulation of the main clock is achieved using an internal 8-bit digital counter
DAC, and by modulating the reference voltage as shown in Figure 7-6. Both modulation frequency, FM, and the
modulation magnitude, ΔFM, are programmable in Section 7.6.6.
VDD
RampCLKM
1V
1V
Ref
Ref
+
0
+
œ
RampRESET
œ
VOSCREF
1
8-Bit
1V DFM
DAC &
Counter
RT
RT
Figure 7-5. Internal Ramp for CLKM Generation
1/FM
DFm
1 V
RampCLKM
TCLKM
Figure 7-6. Internal Ramp Waveform
To achieve maximum attenuation in average-EMI scan, set a modulation frequency of FM ranging from 100 Hz to
1.2 kHz. A low modulating frequency has a small impact on the quasi-peak EMI scan. Set the modulation
frequency to 10 KHz or higher to achieve attenuation for quasi-peak EMI measurements. A modulation
Copyright © 2020 Texas Instruments Incorporated
20
Submit Document Feedback
Product Folder Links: TPS92682-Q1
TPS92682-Q1
SLUSCX8B – MARCH 2019 – REVISED JULY 2020
www.ti.com
frequency higher than the receiver resolution bandwidth (RBW) of 9 kHz impacts only the quasi-peak EMI scan
and has little impact on the average EMI measurement. The TPS92682-Q1 device simplifies EMI compliance by
providing the means to tune the modulation frequency, FM, and modulation magnitude, ΔFM, based on the
measured EMI signature.
Equation 2 shows the relation between the channel switching frequency, fSW, and the desired modulation
frequency FM.
DIV ì fSW
FM =
FMFREQ
(2)
In Equation 2, DIV is the division factor between CLKM and the CHxCLK provided in Section 7.6.4, and FMFREQ is
the division factor given in Section 7.6.6.
The output of the FM 8-bit digital counter always resets and starts from 1 V when a register write is performed to
Section 7.6.6.
7.3.5 Gate Driver
The TPS92682-Q1 contains an N-channel gate driver that switches the output GATEx between VCC and GND. A
peak source and sink current of 500 mA allows controlled slew-rate of the MOSFET gate and drain voltages,
limiting the conducted and radiated EMI generated by switching.
The gate driver supply current, ICC(GATE), depends on the total gate drive charge (QG) of the MOSFET and the
operating frequency of the converter, fSW, ICC(GATE) = QG × fSW. Select a MOSFET with a low gate charge
specification to limit the junction temperature rise and switch transition losses.
It is important to consider a MOSFET threshold voltage when operating in the dropout region (input voltage VIN
is below the VCC regulation level). TI recommends a logic level device with a threshold voltage below 5 V when
the device is required to operate at an input voltage less than 7 V.
7.3.6 Rail-to-Rail Current Sense Amplifier
The internal rail-to-rail current sense amplifier measures the average LED current based on the differential
voltage drop between the CSPx and CSNx inputs over a common mode range of 0 V to 65 V. The differential
voltage, V(CSPx-CSNx), is amplified by a voltage-gain factor of 14 and is connected to the negative input of the
transconductance error amplifier. Accurate LED current feedback is achieved by limiting the cumulative input
offset voltage (represented by the sum of the voltage-gain error, the intrinsic current sense offset voltage, and
the transconductance error amplifier offset voltage) over the recommended common-mode voltage and
temperature range.
An optional common-mode (CFCM) or differential mode (CFDM) low-pass filter implementation, as shown in Figure
7-7, can be used to filter the effects of large output current ripple, and switching current spikes caused by diode
reverse recovery. TI recommends a filter resistance in the range of 10 Ω to 100 Ω to limit the additional offset
caused by amplifier bias current mismatch to achieve the best accuracy and line regulation.
RFS
CSPx
+
x14
CFDM
CHxIsense
RCS
RFS
œ
CSNx
CFCM
CFCM
Figure 7-7. Current Sense Amplifier
Copyright © 2020 Texas Instruments Incorporated
Submit Document Feedback
21
Product Folder Links: TPS92682-Q1
TPS92682-Q1
SLUSCX8B – MARCH 2019 – REVISED JULY 2020
www.ti.com
7.3.7 Transconductance Error Amplifier
As shown in Figure 7-8, the internal transconductance error amplifier generates an error signal proportional to
the difference between the internal programmable 8-bit CHxIADJ-DAC (Section 7.6.8) and the feedback signal.
The feedback signal is the sensed current CHxIsense in CC mode, or the sense output voltage, CHxVFB, in CV
mode. The gain gM of the error amplifier is programmable through the CHx_HG bit in Section 7.6.2. The gain
values for CHx_HG = 0 or 1 are provided in Section 6.5. Based on the value of CHx_CV bit in Table 7-4, either
CHxIsense or CHxVFB is connected to the input of the error amplifier. Therefore, the TPS92682-Q1 device either
operates in CV or CC mode.
The output of the error amplifier is connected to an external compensation network to achieve closed-loop LED
current (CC), or output voltage (CV) regulation. In most LED driver applications, a simple integral compensation
circuit consisting of a capacitor connected from COMPx output to GND provides a stable response over a wide
range of operating conditions. TI recommends a capacitor value between 10 nF and 100 nF as a good starting
point. To achieve higher closed-loop bandwidth, a proportional-integral compensator, consisting of a series
resistor and a capacitor network connected across the COMPx output and GND, is required. Section 8 includes
a summarized detailed design procedure.
COMPx
CHx_comp
œ
CHx_complow
100mV
500 W
+
CHx_PD_comp
0 œ 2.4V
8-Bit
DAC
CHx_IADJ
CHx_close_comp
Transconductance
Error Amp
EAREF
CSPx
+
gM
+
x14
œ
œ
CHx_Isense
CHx_VFB
EAFB
RCS
0
1
CHx_HG
CSNx
VDD
0 œ 2.8V
8-Bit
DAC
CHx_CV
0.2mA
CHx_SSDAC
CH1_FBO_EN
FBx
RFB1
VOUTx
RFB2
Figure 7-8. Feedback Connection to the Error Amplifier
7.3.8 Switch Current Sense
Figure 7-9 shows the simplified block diagram of the switch current sense circuitry. The ISPx input pin monitors
the main MOSFET current to implement peak current mode control. The GATEx output duty cycle is derived by
comparing the peak switch current, measured by the RIS resistor, to the internal CHx_COMP voltage threshold.
An internal slope signal, CHx_ISLOPE, is added to the measured sense voltage to prevent sub-harmonic
oscillations for duty cycles greater than 50%.
An internal leading-edge blanking (LEB) is applied to the switch current sense at the beginning of each switching
cycle by shunting the ISPx input to the ISNx (GND connection of the RIS) for the duration of the LEB time. The
LEB circuit prevents unwanted duty cycle termination due to MOSFET switching-current spike at the beginning
of the new switching cycle. The LEB time can be set to 150 ns or 75 ns (typical) using the CHxLEB bit set in
Table 7-5. For additional noise suppression, connect an external low-pass RC filter with resistor values ranging
from 100 Ω to 500 Ω and a 1000-pF capacitor across RIS.
Copyright © 2020 Texas Instruments Incorporated
22
Submit Document Feedback
Product Folder Links: TPS92682-Q1
TPS92682-Q1
SLUSCX8B – MARCH 2019 – REVISED JULY 2020
www.ti.com
Cycle-by-cycle current limit is accomplished by a separate internal comparator. The current limit threshold is set
based on the status of internal PWM signal and the CHxILIM setting. The current limit threshold is set to a value
programmed in the CHxILIM in Table 7-17 when PWM signal is high. The current limit threshold is set to 700 mV
(typical) when PWM signal is low. In CC mode, the transition between the two thresholds in conjunction with the
slope compensation and the error amplifier circuit allows for higher inductor current immediately after the PWM
transition, to improve LED current transient response in PWM dimming.
The device immediately terminates the GATEx and PDRVx outputs when the sensed voltage at the ISPx input
exceeds the current limit threshold. For more detail on the cycle-by-cycle current limit, refer to Section 7.3.16.
VDD
CHx_Gate
CHxLEB
CHx_Islope
LEB
75ns/150ns
20mA
CHx_close_comp
+
CHx_DUTY
comp
œ
CHx_COMP
5kW
CHx_ISW
ISPx
+
CHx_ILIMIT
comp
CHx_ILIM
RIS
œ
ILIM_DAC
CHx_PWM
ISNx
Figure 7-9. Switch Current Sense and Current Limit
7.3.9 Slope Compensation
Switching converters with peak current mode control are subject to subharmonic oscillation for duty cycles
greater than 50%. To avoid instability, the control scheme adds an artificial ramp to the sensed switch current
(shown in Figure 7-9). The required slope of the artificial ramp depends on the input voltage, VIN, output voltage,
VO, inductor L, and switch current sense resistor RIS. The TPS92682-Q1 device provides a programmable slope
compensation with seven levels of slope magnitude to simplify and enhance the performance of common
switching converter topologies, such as boost, boost-to-battery, and SEPIC. The slope magnitude can be
programmed through CHxISLP in Section 7.6.5. Section 8 includes calculations for the choice of correct slope
magnitude for a given application.
7.3.10 ILED Setting in CC Mode
In CC mode, as shown in Figure 7-8, the voltage across the LED current sense resistor, V(CSP–CSN), is regulated
to the output of the programmable 8-bit CHxIADJ-DAC, scaled by the current sense amplifier voltage gain of 14.
The LED current can be linearly adjusted by writing a different value to the CHxIADJ register. The 8-bit DAC
output can be set in the range of 85 mV (CHxIADJ = 9) to 2.4 V (CHxIADJ = 255). The associated channel is
turned off for CHxIADJ ≤ 8.
7.3.11 Output Voltage Setting in CV Mode
In CV mode, as shown in Figure 7-8, the voltage at the FBx pin (output voltage divider) is regulated to the output
of the programmable 8-bit CHxIADJ-DAC. The FBx voltage can be adjusted in the range of 85 mV (CHxIADJ =
9) to 2.4 V (CHxIADJ = 255). The associated channel is turned off for CHxIADJ ≤ 8.
Copyright © 2020 Texas Instruments Incorporated
Submit Document Feedback
23
Product Folder Links: TPS92682-Q1
TPS92682-Q1
SLUSCX8B – MARCH 2019 – REVISED JULY 2020
www.ti.com
7.3.12 PWM Dimming
As shown in Figure 7-10, the TPS92682-Q1 device incorporates both internal and external PWM dimming. To
select between external or internal PWM dimming, the INTPWM bit in Section 7.6.2 must be set to "0" or "1",
respectively. If internal PWM dimming operation is selected, the state of the PWMx pins do not have any effect
on the operation of the device. For external PWM dimming, apply a square-wave signal to the PWMx pin with the
rising and falling thresholds provided in Section 6.5. The LED current modulates based on the duty cycle of the
external PWM signal, DPWM(EXT)
.
PWMxINT PWMxINT
PWMx
0
1
CHx_close_comp
R
Q
CHxPWM_dig
R
Dominant
S
INT_PWM
CHx_Duty
Figure 7-10. PWM Dimming Circuit
To use internal PWM dimming, the INTPWM bit in Section 7.6.2 must be set to "1". The TPS92682-Q1 device
incorporates a 10-bit PWM counter for each channel. The duty cycle of the internal PWM can be set using a 10-
bit value in the CHxPWML and CHxPWMH registers. Because CHxPWM is a 10-bit value, a PWM duty cycle
update can require two SPI writes, one to the CHxPWMH and another to the CHxPWML register. To prevent
transferring incoherent values, the contents of the two registers transfer to the CHxPWM counter only upon the
write to the CHxPWML register. Therefore, for an update to the PWM duty cycle, it is recommended
consecutively writing to CHxPWMH first and CHxPWML second. In addition, in order to avoid corrupting the
progress of the current PWM duty cycle, the update from the CHxPWM registers to the CHxPWM counter occurs
two PWMCLK before the end of each PWM period (at the count of 1022).
Due to synchronization of the external PWM with internal clock, when switching from external PWM to internal
PWM, a glitch for the total of one PWM period can be observed in the output.
The clock to the 10-bit PWM counter is related to the main clock, CLKM, by a division factor set by a 3-bit value
in Section 7.6.10. The relation between the PWMCLK and PWM frequency with CLKM frequency are shown in
Equation 3 and Equation 4.
fCLKM
PWMCLK
=
PWMDIV
(3)
(4)
PWMCLK
PWMFREQ
=
1024
For example, if the CLKM frequency is set to fCLKM = 800 kHz and PWMDIV = 001 (division value of 2), the PWM
frequency is PWMFREQ ≈ 390 Hz.
The phase between the internal PWM dimming for the two channels can be set to 180° if the PWMPH bit in
Section 7.6.2 is set to 0. For PWMPH = 1, there is zero phase shift between the internal 10-bit PWM counters of
the two channels.
The PWM signal controls the GATEx and PDRVx outputs. If PWMxINT is set low, the associated channel is
turned off, the COMPx pin is disconnected from the error amplifier, and the PDRVx output is set to VCSP to
maintain the charge on the compensation network and output capacitors. On the rising edge of the PWMxINT, the
GATEx and PDRVx outputs are enabled to ramp the inductor current to the previous steady-state value. The
COMPx pin connects to the error amplifier only when the switch current sense voltage VISPx exceeds the
COMPx voltage, CHx_comp. This connection immediately forces the converter into steady-state operation with
minimum LED current overshoot. When dimming is not required, connect the PWMx pins to the VDD pin. An
internal pull-down resistor sets the PWM inputs to logic-low and disables the device when the pins are
disconnected or left floating, and the INTPWM bit in Section 7.6.2 is set to the default value of "0".
Copyright © 2020 Texas Instruments Incorporated
24
Submit Document Feedback
Product Folder Links: TPS92682-Q1
TPS92682-Q1
SLUSCX8B – MARCH 2019 – REVISED JULY 2020
www.ti.com
7.3.13 P-Channel FET Gate Driver Output
The PDRVx output is a function of the internal PWM signal and is capable of sinking and sourcing up to 50 mA
of peak current to control a high-side series connected P-channel dimming FET. The PDRV switches between
VCSP and (VCSP – 7 V) is based on the status of the PWM signal to completely turn off and turn on the external
P-channel dimming FET. In CC mode, a series dimming FET is required to achieve high contrast ratio since it
ensures fast rise and fall times of the LED current in response to the PWM input. Without any dimming FET, the
rise and fall times are limited by the inductor slew rate and the closed-loop bandwidth of the system. In CC
mode, leave the PDRVx pin unconnected if not used. In CV mode, the PDRVx together with CSPx and CSNx
pins can be connected to GND to limit the shutdown current. The PDRVx can also be disabled by setting the
CHxPDRVEN bit in Table 7-3 to zero.
7.3.14 Soft Start
The soft start feature helps the regulator gradually reach the steady-state operating point, thus reducing start-up
stresses and current surges. The device clamps the COMPx pin to the output of the SSDAC plus the threshold
voltage of a P-FET, until the LED current or the output voltage approaches the regulation threshold. The soft
start is controlled with an 8-bit DAC which ramps from 0 V to 2.8 V during start-up of an associated channel. The
rate of the soft-start ramp (or the ramp time) can be controlled by programming the clock of the internal digital
ramp counter. The clock of the digital ramp counter is related to the associated channel clock (switching
frequency fSW) by:
CHxCLK
SSCLK
=
SSxDIV
(5)
The SSxDIV is a division factor provided in Section 7.6.7. For example, if the channel switching frequency is set
to 400 kHz, the soft-start ramp time can be programmed between 1.3 ms and 64 ms. It is important to note that
the ramp time is the time for the SSDAC output to ramp from 0 V to 2.8 V (digital ramp counter to count from 0 to
255), but the controller can reach the regulation point before the ramp is completed.
COMPx
CHx_comp
500 W
CHx_EAref
CCOMP
+
gM
œ
CHx_EA_FB
CHx_HG
8-Bit
DAC
CHx_SSDAC
0 œ 2.8V
Figure 7-11. Soft-Start Circuit
When programming the soft-start ramp, It is essential to ensure that the soft-start ramp time is longer than the
time required to charge the output capacitor.
To initiate the soft-start ramp, the PWM signal (internal or external) must be set high. If PWM dimming occurs
during the soft-start period, the digital ramp counter holds the ramp value when PWM = LOW, and re-starts the
ramp from the last ramp value when PWM = HIGH. Figure 7-12 shows an example of this feature.
Copyright © 2020 Texas Instruments Incorporated
Submit Document Feedback
25
Product Folder Links: TPS92682-Q1
TPS92682-Q1
SLUSCX8B – MARCH 2019 – REVISED JULY 2020
www.ti.com
255
219
2.8 V
146
SSDAC
73
0
0 V
PWM
Figure 7-12. Soft-start Period During PWM Dimming
7.3.15 Two-Phase Operation
The TPS92682-Q1 device can be programmed in two-phase mode by setting the 2PH bit to "1" in Section 7.6.2.
In two-phase mode, the CH1_comp is internally connected to the CH2_comp with 500 Ω (max) of resistance. In
this case, the error amplifier of channel-2 is disabled and only the error amplifier of channel-1 connects to both
COMP1 and COMP2 pins. TI recommends that external compensators be connected to both COMP1 and
COMP2 pins, and that these two pins be shorted together externally.
Two-phase mode uses only the channel-1 soft-start DAC and controls both phases. To generate the channel
clocks, only the division factor for the channel-1, programmed in Section 7.6.4, is used. The two channel clocks
(switching frequency fSW) are the same and are 180° out-of-phase.
In two-phase mode, in the case of internal PWM, only CH1PWM is used for both channels. When external PWM
is used, it is recommended to short both PWMx pins together and use only one PWM signal for both channels.
A selected number of the faults (CH2_OV, CH2_UV, CH2_OC, and CH2_UC) have no effect in the operation of
two-phase mode. For more detail about faults and diagnostics in TPS92682-Q1, refer to Section 7.3.16.
7.3.15.1 Current Sharing In Two-Phase
In two-phase operation, the current sharing between the two phases depends on the mismatch between the
current sense circuitry of the two channels. The TPS92682-Q1 incorporates a feature and a register setting to
improve the current sharing in two-phase operation. Table 7-40 includes three bits of calibration settings,
CHxCAL2:0, which introduce an offset of 0 to 17.5 mV (with a resolution of 2.5 mV) to the channel switch current
sense voltage. The calibration offset can be used to compensate for the mismatch offset between the two
channels.
The following procedure is recommended for offset calibration between the two phases in a CV two-phase
design:
•
•
•
•
In two-phase CV, Comp1 and Comp2 pins are connected together.
Configure the registers for the application and turn on the two-phase converter.
Set the load at the output of the two-phase converter to half of the maximum load in the application.
Set CH2GOFF = 1 and CH1GOFF = 0 in Table 7-40. This setting turns off channel-2. Measure the COMP
voltage as shown in Figure 7-13 and record the measurement as VCOMP1
Set the CH1GOFF = 1 and CH2GOFF = 0 in Table 7-40. This setting turns off channel-1. Measure the COMP
voltage and record the measurement as VCOMP2
The difference between the two measurements, ΔVOFST = VCOMP1 – VCOMP2, is the offset mismatch between
the two phases.
By setting a similar offset voltage through CHxCAL bits, the mismatch can be corrected (offset must be set in
CH2CAL if VCOMP1 > VCOMP2, and in CH1CAL if VCOMP1 < VCOMP2).
At the end of the procedure, set both CH1GOFF and CH2GOFF bits to zero.
.
•
•
•
•
.
Copyright © 2020 Texas Instruments Incorporated
26
Submit Document Feedback
Product Folder Links: TPS92682-Q1
TPS92682-Q1
SLUSCX8B – MARCH 2019 – REVISED JULY 2020
www.ti.com
10k
10k
CHF1
V
COMP1
TPS92682-Q1
COMP2
CCOMP
RCOMP
CHF2
Figure 7-13. Current Sharing Calibration Setup
7.3.16 Faults and Diagnostics
The TPS92682-Q1 includes a comprehensive configurable faults and diagnostics feature. Table 7-1 shows the
list of the faults and diagnostics. A selected number of the faults (UVLO, RTOPEN, TW, TSD, and POR) are
shared between the two channels.
As shown in Table 7-1, a selected number of the faults can be enabled or disabled using FLT EN-bits in the
FEN1 and FEN2 registers. The rest of the faults and diagnostics feature are always enabled and operational.
All the faults and diagnostics features, except FBOPEN, TSD, and UVLO, have an associated Fault-Read-bit in
the FLT1 and FLT2 registers. Upon occurrence of the fault, the associated Fault-Read-bit is set in the register
map. Reading these registers clears the bits that are set if the condition no longer exists. The clearing of the
Fault-Read-bits happens at the end of the SPI transfer read response, not at the end of the read command.
Although FBOPEN fault does not have a dedicated Fault-Read-bit, this fault sets the OV-fault read bit.
In TPS92682-Q1, the OV, UV, ILIM, and OC faults can be configured to be a non-latched fault in Section 7.6.22.
If a fault is configured as non-latched, upon occurrence of the fault, the associated channel turns off. The
channel performs a soft start after expiration of a configurable fault timer and when the fault is cleared. In latched
fault condition, the associated channel is turned off and remains off until the channel enable-bits are re-
programmed in Section 7.6.1.
Table 7-1. TPS92682 Faults and Diagnostics
FAULT OR
DIAGNOS.
ENABLE
FTIMER
F-PIN
TRIGGER LATCH
DISABLE
LIST
DESCRIPTION
Output over voltage fault
FLT EN-BIT FLT R-BIT
OV
UV
Fault
Fault
Fault
Fault
Fault
Diagnos.
Fault
Fault
Fault
Yes
Yes
Yes
No
Yes
Yes
Yes
No
No
Yes
Yes
No
Yes
No
No
No
No
Yes
Yes
Yes
No
Yes
Yes
Yes
No
Output under voltage fault
Cycle/Cycle switch current limit
Input under voltage lockout
ILED over current
ILIM
UVLO
OC
Yes
No
Yes
Yes
Yes
Yes
No
Yes
No
Yes
No
UC
ILED under current
ISNOPEN ISNx open pin fault
Yes
No
Yes
Yes
Yes
No
RTOPEN
FBOPEN
RT open pin fault
No
FB pin open pin fault
Yes
No
Copyright © 2020 Texas Instruments Incorporated
Submit Document Feedback
27
Product Folder Links: TPS92682-Q1
TPS92682-Q1
www.ti.com
DISABLE
SLUSCX8B – MARCH 2019 – REVISED JULY 2020
FAULT OR
DIAGNOS.
ENABLE
FTIMER
F-PIN
LIST
DESCRIPTION
FLT EN-BIT FLT R-BIT
TRIGGER LATCH
TW
Thermal warning at 150°C (typ.)
Thermal shutdown
Diagnos.
Fault
No
No
No
Yes
No
No
No
No
No
No
No
No
TSD
POR
Yes
Yes
Power On Reset
Fault
Yes
As shown in Table 7-1, all faults, except UVLO, UC, and TW, set the active low fault pins, FLT1 and FLT2. Figure
7-14 shows the functionality of the fault pins. SYNC/ FLT2 is a dual function pin. When the SYNCEN bit in
Section 7.6.1 is set to "1", SYNC/ FLT2 is an input pin and a square wave signal with the desired fCLKM
frequency must be applied to this pin. In this case, faults on both channels are ORed and applied to the FLT1
pin.
FLT1
0
CH1_FAULT
1
CH2_FAULT
SYNC_EN
SYNC/FLT2
SYNC
Figure 7-14. Fault PINs
7.3.16.1 Main Fault Timer (MFT)
For each channel of the TPS92682-Q1, there is a 14-bit counter that implements a main fault timer. The timer
can be programmed by a 4-bit value for each channel in Section 7.6.17. The MFT time can be set to a value
between 1000 and 16383 times the input clock period. The input clock of the MFT is the channel clock, CHxCLK
(the switching frequency fSW). For example, for a channel with a switching frequency of fSW = 400 kHz, the timer
can be programmed from 2.5 to 41 ms.
Only UV and OC faults can trigger the MFT. When either of these two faults are enabled as a non-latched fault,
the fault event turns off the channel and triggers the MFT. The associated channel is turned back on by a soft-
start process when the MFT count is completed and the fault is cleared.
7.3.16.2 OV Fault
If CHxOVEN is set to "1" in Section 7.6.20, the output over voltage fault is enabled. When VFBx exceeds the
threshold voltage OVTHR, the CHx_OV fault is set high and turns off the associated channel. The OVTHR voltage
is set by OV_DAC; OVTHR = VFBREF × OV%, where OV% is provided in Section 7.6.23. The VFBREF in CC mode
is set to 1.228 V (typical), and in CV mode, is set to the output of the CHxIADJ register. When CHx_OV is high,
OVTHR is set to VFBREF and a 20 µA hysteresis current is applied to the feedback resistor divider. For the boost
converter with the output voltage sensing according to Figure 7-15, VOUT must decrease to a level shown in
Equation 6 for the CHx_OV to be cleared.
RFB1 + RFB2
RFB1
VO
Ç
ì VFBREF -I20m ìRFB2
(6)
Copyright © 2020 Texas Instruments Incorporated
28
Submit Document Feedback
Product Folder Links: TPS92682-Q1
TPS92682-Q1
SLUSCX8B – MARCH 2019 – REVISED JULY 2020
www.ti.com
20mA
VDD
CHx_OV_EN
VDD
CHx_OV
+
OV
OVTHR
VOUT
0.2mA
œ
CHx_CV
1.23V
ref
CHx_OVDAC
VFBREF
DAC
OV
0
0
RFB2
FBx/OVx
1
CHx_EAref
1
œ
UV
5ms
Delay
+
RFB1
CHx_UV
50mV
CHx_VFB
CHx_close_comp
Figure 7-15. OV and UV Faults
If the CHxOVFL bit is set to "1" in Section 7.6.22, the OV fault is configured as a latched fault and the associated
channel turns off with the rising edge of CHx_OV. The channel can be turned on again only by re-setting the
CHxEN bit in Section 7.6.1.
For CHxOVFL = 0, the OV fault is a non-latched fault. In this case, the associated channel turns off when the OV
fault occurs, but the channel goes through a restart and soft-start ramp when CHx_OV goes low. Figure 7-16
shows a non-latched OV situation for a converter in CV mode, where the output voltage (VFBx) is regulated to
VFBREF in normal condition.
CHx is
Soft-Start
off
OVTHR
VFBREF
VFBx
VFBREF œ
I20m x (RFB1||RFB2)
CHx_OV
Figure 7-16. Non-latched OV Fault in CV Mode
7.3.16.3 UV Fault
If CHxUVEN is set to "1" in Section 7.6.20, the output under voltage fault is enabled. Figure 7-15 shows when
VFBx decreases below the UVTHR of 50 mV (typ.), CHx_UV is set high and turns off the associated channel. If the
CHxUVFL bit is set to "1" in Section 7.6.22, the UV fault is configured as a latched fault and the associated
channel turns off and remains off with the rising edge of CHx_UV. The channel can be turned on again only by
re-setting the CHxEN bit to "1". For CHxUVFL = 0, the UV fault is a non-latched fault. In this case, the
associated channel turns off when a UV fault occurs, but the channel goes through a restart and soft-start ramp
when CHx_UV is cleared and the MFT is expired.
The UV fault is disabled during the soft-start ramp if the CHxRFEN bit is set to "0" in Section 7.6.20.
7.3.16.4 ILIM Fault
Figure 7-9 shows that the cycle-by-cycle switch current limit is achieved by comparing the sensed switch current
with a programmable ILIM threshold and terminating the duty cycle when VISPx ≥ VILIM(THR). The ILIMTHR can be
set using a 2-bit value in Section 7.6.15. If CHxILIMEN is set to zero in Section 7.6.21, the ILIM fault is disabled.
However, the cycle-by-cycle current limit is always active as long as the sensed switch current exceeds ILIMTHR
.
If CHxILIMEN is set to "1", the ILIM fault is enabled, and it can be set as a latched or non-latched fault. There is
an ILIM event counter for each channel that counts the number of ILIM fault events. When the ILIM event
Copyright © 2020 Texas Instruments Incorporated
Submit Document Feedback
29
Product Folder Links: TPS92682-Q1
TPS92682-Q1
SLUSCX8B – MARCH 2019 – REVISED JULY 2020
www.ti.com
counter reaches a programmed value, the associated channel is turned off. The maximum number of ILIM fault
events can be set using a 2-bit CHxILIMCNT in Section 7.6.15. The ILIM event counter is reset every 100-
CHxCLK cycles to prevent transients and non-real faults, resulting in an unwanted channel disable.
If CHxILIMFL is set to "1" in Section 7.6.22, the ILIM event is set to a latched fault. The associated channel is
turned off and remains off when the ILIM event counter reaches the programmed value. The channel can be
turned on again only by re-setting the CHxEN bit to "1" in Section 7.6.1.
For CHxILIMFL = 0, the ILIM fault is a non-latched fault. When the ILIM event counter reaches the programmed
value, the associated channel is turned off and an ILIM fault timer, IFT, is triggered. The associated channel is
turned back on by a soft-start ramp when the ILIM fault timer count is completed and the output of the ILIM event
counter is cleared. The ILIM fault timer can be programmed using a 2-bit value CHxIFT in Section 7.6.16. The
IFT time can be set to a value between four and 32 cycles of the input clock. The input clock of the IFT is the
channel clock, CHxCLK (the switching frequency fSW). For example, for a channel with a switching frequency of
fSW = 400 kHz, the timer can be programmed from 10 to 80 µs.
Figure 7-17 shows the simplified functional block diagram of the ILIM fault. Figure 7-18 shows the progress of
the cycle by cycle current limit, the ILIM event counter (IFEC), the ILIM Fault Timer (IFT), and the restart of the
channel for a non-latched ILIM fault.
S
R
Q
IFEC
Counter
R
IFT
Timer
CHx_ILIMIT
IFT_done
CHx
Disable
0
1
CLR
IFEC_rst
100 Count
CHxILIMFL
From SS
state-machine
CHx_CLK
Figure 7-17. ILIM Fault Diagram
Soft-Start is
initiated
VCOMPx
ILIM
IL
ILIM Event Counter
(IFEC) is counting
GATEx
IFEC reaches
max. count
IFECCNT
ILIM
Fault
ILIM Fault Signal
IFT active
Figure 7-18. ILIM Fault
The ILIM fault in CV mode is disabled during the soft-start ramp if the CHxRFEN bit is set to "0" in Section
7.6.20.
As stated before, it is important to note that the cycle-by-cycle switch current limit is always active even if the
ILIM fault is disabled.
7.3.16.5 UVLO
For details on the UVLO fault, refer to Section 7.3.2.
Copyright © 2020 Texas Instruments Incorporated
30
Submit Document Feedback
Product Folder Links: TPS92682-Q1
TPS92682-Q1
SLUSCX8B – MARCH 2019 – REVISED JULY 2020
www.ti.com
7.3.16.6 ILED Over Current (OC)
When CHxOCEN is set to "1" in Section 7.6.21, the ILED overcurrent fault is enabled, and the voltage across the
current sense inputs (CSPx and CSNx) is monitored. The device sets the OC fault signal when the voltage at the
output of the current sense amplifier exceeds the regulation set point VIADJ by 50%. The OC fault threshold is
calculated as follows:
V
IADJ
V CSPx-CSNx = 1.5ì
(
)
14
(7)
If the CHxOCFL bit is set to "1" in Section 7.6.22, the OC fault is configured as a latched fault and the associated
channel turns off and remains off with the rising edge of CHx_OC. The channel can be turned on again only by
re-setting the CHxEN bit to "1" in Section 7.6.1. For CHxOCFL = 0, the OC fault is a non-latched fault. In this
case, the associated channel turns off when an OC fault occurs, but the channel goes through a restart and soft-
start ramp when CHx_OC is cleared and the MFT is expired.
7.3.16.7 ILED Undercurrent (UC)
The ILED Undercurrent (UC) is a diagnostic feature and not a fault event. Therefore, the UC event sets the fault
read bits in the FLT2 register only, and does not have any effect on the operation of the associated channel or
trigger the fault pins.
The device sets the UC event when the voltage at the output of the current sense amplifier decreases by 50%
from the regulation set point VIADJ. The UC threshold is calculated as follows:
V
IADJ
V CSPx-CSNx = 0.5ì
(
)
14
(8)
When PWM dimming, the UC fault read bit might be set during the time when PWM is low.
7.3.16.8 ISNOPEN, FBOPEN, and RTOPEN Faults
The device can detect open pin fault on ISNx, FBx, and RT pins. If any of these pins are opened during
operation, the device turns off the associated channel (or both channels for RT open pin). The channels can be
turned on again only by re-setting the CHxEN bits high and if the faults are removed.
7.3.16.9 TW and TSD
The thermal warning (TW) bit is set in the FLT1 Register when the junction temperature exceeds 150°C (typ).
The TW event is a diagnostic feature and not a fault event. As a result, TW does not have any effect on the
operation of the device.
Internal thermal shutdown (TSD) circuitry is implemented to protect the controller in the event the junction
temperature exceeds a value of 175°C. In the event of TSD, the controller is forced into a shutdown mode,
disabling the internal regulator. This feature is designed to prevent overheating and damage to the device.
7.3.16.10 COMPx Pull-Down and Comp-Low signal
As shown in Figure 7-8, an internal switch pulls down the COMPx pin when there is a fault. The Comp-Pull-
Down discharges the compensator capacitors, such that the converter start-up always begins from a known
state.
The converter does not start unless the COMPx voltage decreases below 100 mV (when CHx_complow goes
high).
7.4 Device Functional Modes
The TPS92682-Q1 operates in the functional modes shown in Figure 7-19.
Copyright © 2020 Texas Instruments Incorporated
Submit Document Feedback
31
Product Folder Links: TPS92682-Q1
TPS92682-Q1
SLUSCX8B – MARCH 2019 – REVISED JULY 2020
www.ti.com
POR
POR
Mode
CLKM exists
LH = High
CLKM exists
LH = Low
LH = High
Limp
Home
Normal
Operation
LH = Low
& LH-bit = 0
Figure 7-19. TPS92682 Functional Mode
7.4.1 POR Mode
Upon POR, all the register settings are reset to their default values and both channels are turned off. The device
enters functional modes if the main clock, CLKM, is active.
7.4.2 Normal Operation
In Normal operation mode, the registers can be programmed and the channels can be turned on. To operate in
this mode, the LH pin must be low. The state machine for this mode is shown in Figure 7-20 and Figure 7-21.
•
•
State 0: After POR, all the registers are reset to their default values, and the two channels are off.
State 1 (CHx_EN-BIT = 0): In this state, the device registers are ready to be programmed. Read FLT1 and
FLT2 registers to clear all the fault read bits and the PC bit. Set the FPINRST bit in the EN register in order
for the fault pins to be cleared. All the initializations must be completed before turning on the channels. The
device stays in state-1 unless the condition of CHx_IADJ > 8 is met.
•
•
State 2 (CHx_EN-BIT = 1): The device advances to state-2 when the CHx_EN bit is set to "1". In this state, all
the necessary conditions for initiating the soft-start ramp are checked. The CHx_complow signal and
CHx_PWM are high, and the condition of CHx_IADJ > 8 is met. If a latched fault occurs in this state, the
CHx_comp pin is pulled low, the CHx_EN bits are set to zero and the device returns to state-1. For a non-
latched fault, the device remains in this mode until the fault is removed.
State 3 (SSDAC_RAMP): The SSDAC_RAMP state begins when all the conditions for the soft-start ramp
initialization are met. In this state, the soft-start ramp DAC increments only when CHx_PWM is high. For
CHx_PWM = LOW, the ramp is held constant. The DAC ramp re-starts the increment from the previous value
at the next PWM dimming cycle, and when CHx_PWM = HIGH. If a latched-fault occurs in this state, the
CHx_comp pin is pulled low, the CHx_EN bit is set to zero, and the device returns to state-1. For a non-
latched fault, the associated channel is turned off, the CHx_comp pin is pulled low and the device returns to
state-2. At the end of the soft-start ramp, read the FLT1 and FLT2 registers and set the FPINRST bit in the
EN register in order for the fault read-bits and the fault pins to be cleared.
Copyright © 2020 Texas Instruments Incorporated
32
Submit Document Feedback
Product Folder Links: TPS92682-Q1
TPS92682-Q1
SLUSCX8B – MARCH 2019 – REVISED JULY 2020
www.ti.com
0
POR
POR
Reset: CHx_SSDAC,
CHx_EN, CHx_PFETDRV,
CHx_ramp_done
Set: CHx_PD_comp
CHx_FPIN
CHx_EN-BIT=0
Reset: CHx_EN, CHx_PFETDRV,
CHx_ramp_done, CHx_SSDAC
1
Set: CHx_PD_comp
NO
PC-bit cleared?
YES
Reset: CHx_EN-BIT
YES
YES
CHx_Latch_FLT?
NO
Set: CHx_FPIN
CHx_NonLatch_FLT?
NO
Set: CHx_FPIN
YES
NO
CHx_IADJ≤8?
NO
2 3
CHx_EN-BIT=1?
YES
2
Figure 7-20. Operational Mode, States 0 and 1
Copyright © 2020 Texas Instruments Incorporated
Submit Document Feedback
33
Product Folder Links: TPS92682-Q1
TPS92682-Q1
SLUSCX8B – MARCH 2019 – REVISED JULY 2020
www.ti.com
1
1
2
CHx_EN-BIT=1
Reset: CHx_EN, CHx_PFETDRV,
CHx_ramp_done, CHx_SSDAC
Set: CHx_PD_comp
Reset: CHx_EN-BIT
Set: CHx_FPIN
YES
CHx_Latch_FLT?
NO
YES
YES
Set: CHx_FPIN
CHx_NonLatch_FLT?
NO
CHx_IADJ≤8?
NO
NO
CHx_EN-BIT=1?
YES
NO
(CHx_PWM_active
&& CHx_complow)?
YES
1
3
SSDAC_RAMP
Reset: CHx_PD_comp
Reset: CHx_EN-BIT
Set: CHx_FPIN
YES
CHx_Latch_FLT?
NO
YES
YES
Set: CHx_FPIN
CHx_NonLatch_FLT?
NO
CHx_IADJ≤8?
NO
NO
CHx_EN-BIT=1?
YES
NO
CHx_PWM_active?
YES
YES
CHx_ssdac==255?
NO
Set: CHx_ramp_done
Increment SS-DAC
Reset: CHx_ramp_done
Set: CHx_EN
Figure 7-21. Operational Mode, States 2 and 3
Copyright © 2020 Texas Instruments Incorporated
34
Submit Document Feedback
Product Folder Links: TPS92682-Q1
TPS92682-Q1
SLUSCX8B – MARCH 2019 – REVISED JULY 2020
www.ti.com
7.4.3 Limp Home
The TPS92682-Q1 device enters the limp home (LH) mode, when the LH pin is pulled high (VDD, or logic level
voltage). In LH mode, the device sets the operation of the device based on the SPI programmable LH-registers
(register addresses 0x17 to 0x24). The LH-registers should be programmed during initialization of the device. To
exit the LH mode, the LH pin must be pulled low, and the LH bit in Section 7.6.2 must be written to "0". The LH
bit is set to "1" when the LH pin is pulled high. Writing a value of "1" to the LH bit does not have any effect and
does not change the operation of the device.
7.5 Programming
The programming of the TPS92682-Q1 registers can be performed through a serial interface communication.
The 4-wire control interface in the TPS92682-Q1 device is compatible with the Serial Peripheral Interface (SPI)
bus. A Micro-Controller-Unit (MCU) can write to and read from the device registers to configure the channel
operation and enable or disable a specific channel.
7.5.1 Serial Interface
The SPI bus consists of four signals: SSN, SCK, MOSI, and MISO. The SSN, SCK, and MOSI pins are TTL
inputs into the TPS92682-Q1 while the MISO pin is an open-drain output. The SPI bus can be configured for
both star-connect and daisy chain hardware connections.
A bus transaction is initiated by the MCU creating a falling edge on SSN. While SSN is low, the input data
present on the MOSI pin is sampled on the rising edge of SCK, with MS-bit first. The output data is asserted on
the MISO pin at the falling edge of the SCK. Figure 7-22 shows the data transition and sampling edges of SCK.
SSN
15
16
1
2
3
4
SCK
MOSI
MISO
D15
D14
D13
D12
D1
D0
D15
D14
D13
D12
D1
D0
Figure 7-22. SPI DATA Format
A valid transfer requires a non-zero integer multiple of 16 SCK cycles (16, 32, 48, and so forth). If SSN is pulsed
low and no SCK pulses are issued before SSN rises, a SPI error is reported. Similarly, if SSN is raised before
the 16th rising edge of SCK, the transfer is aborted and a SPI error is reported. If SSN is held low after the 16th
falling edge of SCK and additional SCK edges occur, the data continues to flow through the TPS92682-Q1 shift
register and out of the MISO pin. When SSN transitions from low-to-high, the internal digital block decodes the
most recent 16 bits that were received prior to the SSN rising edge.
SSN must transition to high after a multiple of 16 SCK cycles for a transaction to be valid and does not set the
SPI error bit. In the case of a write transaction, the TPS92682-Q1 logic performs the requested operation when
SSN transitions high. In the case of a read transaction, the read data is output during the next frame, regardless
of whether a SPI error has occurred.
The data bit on MOSI is shifted into an internal 16-bit shift register (MS-bit first) while data is simultaneously
shifted out of the MISO pin. While SSN is high (bus idle), MISO is tri-stated by the open-drain driver. While SSN
is low, MISO is driven according to the 16-bit data pattern being shifted out based on the prior received
command. At the falling edge of the SSN, to begin a new transaction, MISO is driven with the MS-bit of the
outbound data, and is updated on each subsequent falling edge of SCK.
7.5.2 Command Frame
The command frames are the only defined frame-format that are sent from master to slave on MOSI. A
command frame can be either a read command or a write command. A Command frame consists of a CMD bit,
Copyright © 2020 Texas Instruments Incorporated
Submit Document Feedback
35
Product Folder Links: TPS92682-Q1
TPS92682-Q1
SLUSCX8B – MARCH 2019 – REVISED JULY 2020
www.ti.com
six bits of ADDRESS, a PARITY bit (odd parity), and eight bits of DATA. The format of the Command frame is
shown in Figure 7-23. The bit sequence is as follows:
1. The COMMAND bit (CMD). CMD = 1 means the transfer is a write command; CMD = 0 means it is a read
command.
2. Six bits of ADDRESS (A5..A0)
3. The PARITY bit (PAR). This bit is set by the following equation: PARITY = XNOR(CMD, A5..A0, D7..D0).
4. Eight bits of DATA (D7..D0). For read commands, the DATA bits must be set to zero.
Both the Read and the Write Command follow the Command frame format.
SSN
SCK
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
C
M
D
P
A
R
A
5
A
4
A
3
A
2
A
1
A
0
D
7
D
D
D
D
D
D
D
MOSI
6
5
4
3
2
1
0
Figure 7-23. Command Frame Format
7.5.3 Response Frame
There are three possible response frame formats: Read Response, Write Response, and Write Error/POR.
These formats are further described below.
7.5.3.1 Read Response Frame Format
The Read Response has the following format:
1. The SPI Error bit (SPE)
2. Four reserved bits (always ‘1100’)
3. The RT Open Fault bit (RTO)
4. The Power-Cycled bit (PC)
5. The Thermal Warning bit (TW)
6. Eight bits of DATA (D7..D0)
This is shown in Figure 7-24. This frame is sent out by the TPS92682-Q1 following a read command.
SSN
SCK
1
2
1
3
1
4
0
5
0
6
7
8
9
10 11 12 13 14 15 16
S
P
E
R
T
O
P
C
T
D
7
D
D
D
D
D
D
D
MISO
W
6
5
4
3
2
1
0
Figure 7-24. Read Response Frame Format
7.5.3.2 Write Response Frame Format
The Write Response frame has the following format:
1. The SPI Error bit (SPE)
2. The COMMAND bit (CMD)
3. Six bits of ADDRESS (A5..A0)
4. Eight bits of DATA (D7..D0)
This is shown in Figure 7-25. This frame is sent out following a write command if the previously received frame
was a write command and no SPI Error occurred during that frame.
Copyright © 2020 Texas Instruments Incorporated
36
Submit Document Feedback
Product Folder Links: TPS92682-Q1
TPS92682-Q1
SLUSCX8B – MARCH 2019 – REVISED JULY 2020
www.ti.com
The data and address bits in the write response are the data and address that were sent in the previous write
command.
SSN
SCK
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
S
P
E
C
M
D
A
5
A
4
A
3
A
2
A
1
A
0
D
7
D
D
D
D
D
D
D
MISO
6
5
4
3
2
1
0
Figure 7-25. Write Response Frame Format
7.5.3.3 Write Error/POR Frame Format
The Write Error/POR frame is simply a ‘1’ in the MSB, followed by all zeroes (see Figure 7-26). This frame is
sent out by the TPS92682-Q1 internal digital block during the first SPI transfer following power-on reset, or
following a write command with a SPI Error.
SSN
SCK
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
MISO
Figure 7-26. Write Error/POR
7.5.4 SPI Error
The TPS92682-Q1 device records a SPI Error if any of the following conditions occur:
•
•
•
The SPI command has a non-integer multiple of 16 SCK pulses.
Any of the DATA bits during a read command are non-zero.
There is a parity error in the previously received command.
If any of these conditions are true, the TPS92682 sets the SPE bit high in the next response frame. A write
command with a SPI Error (not 16-bit aligned or bad parity) does NOT write to the register being addressed.
Similarly, a read command to FLT1 or FLT2 does not clear any active fault bits in those registers if the command
has a SPI Error.
7.6 TPS92682 Registers
The SPI-accessible registers are 8-bits wide and exist in a 6-bit-addressable register array (0x00 through 0x3F).
The registers in the TPS92682 device contain programmed information and operating status. Upon power-up the
registers are reset to their default values. Writes to unlisted addresses are not permitted and may result in
undesired operation. Reads of unlisted addresses return the zero value.
Reserved bits (“RSVD”) must be written with ‘0’ values when writing. Registers are read/write unless indicated in
the description of the register. Table 7-2 lists the TPS92682 register map.
Table 7-2. TPS92682 Register Map
ADDR
00h
REGISTER
EN
D7
D6
D5
D4
D3
D2
D1
D0
DEFAULT
00111100
00000000
CH2MAXD CH1MAXD CH2PDRV CH1PDRV
FPINRST SYNCEN
CH2EN
CH1EN
CH1CV
EN
2PH
EN
LH
EN
EN
01h
02h
03h
04h
CFG1
CFG2
PWMPH
CH2LEB
RSVD
INTPWM
CH1LEB
RSVD
CH2HG
CH2FILT1
CH1HG
RSVD
CH2CV
RSVD
RSVD
RSVD
RSVD
CH1FILT1 00000000
SWDIV
ISLOPE
RSVD
CH2DIV1:0
RSVD
CH1DIV1:0
00000000
01010101
RSVD
CH2ISLP2:0
CH1ISLP2:0
Copyright © 2020 Texas Instruments Incorporated
Submit Document Feedback
37
Product Folder Links: TPS92682-Q1
TPS92682-Q1
SLUSCX8B – MARCH 2019 – REVISED JULY 2020
www.ti.com
ADDR
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
REGISTER
FM
D7
D6
D5
D4
D3
D2
FMFREQ3:0
CH1SS3:0
D1
D0
DEFAULT
00000101
01110111
00000000
00000000
00000001
00000000
00000000
00000000
00000000
00001111
00001010
10011001
read
RSVD
RSVD
FMMAG1:0
SOFTSTART
CH1IADJ
CH2IADJ
PWMDIV
CH1PWML
CH1PWMH
CH2PWML
CH2PWMH
ILIM
CH2SS3:0
CH1IADJ7:0
CH2IADJ7:0
RSVD RSVD
CH1PWM7:0
RSVD RSVD
CH2PWM7:0
RSVD RSVD
CH2ILIM1:0
CH2IFT1:0
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
PWMDIV2:0
RSVD
CH1PWM9:8
RSVD
CH2PWM9:8
CH1ILIM1:0
CH1IFT1:0
CH2ILIMCNT1:0
CH1ILIMCNT1:0
IFT
RSVD
RSVD
RSVD
RSVD
MFT
CH2MFT3:0
CH1MFT3:0
CH1OV CH2UV
CH1ILIM CH2ISO
FLT1
RTO
RSVD
PC
TW
CH2OV
CH2ILIM
CH1UV
CH1ISO
12h
FLT2
CH2UC
CH1UC
CH2OC
CH1OC
read
CH2FBOE CH1FBOE
13h
14h
FEN1
FEN2
CH2RFEN CH1RFEN
OVOPT RSVD
CH2ILIMF CH1ILIMF
CH2OVEN CH1OVEN CH2UVEN CH1UVEN 00111100
N
N
CH2ILIME CH1ILIME
CH1ISOE
N
CH2OCEN CH1OCEN
CH2ISOEN
00001111
N
N
15h
16h
17h
FLATEN
OV
CH2OCFL CH1OCFL CH2OVFL CH1OVFL CH2UVFL CH1UVFL 00000000
CH2OV2:0 RSVD CH1OV2:0 00100010
L
L
RSVD
LHPWMP LHINTPW LHCH2MA LHCH1MA LHCH2PD LHCH1PD
LHCFG
LHCH2EN LHCH1EN 00111100
H
M
XDEN
XDEN
RVEN
RVEN
18h
19h
LHCH1IADJ
LHCH2IADJ
LHCH1IADJ7:0
00000000
00000000
LHCH2IADJ7:0
LHCH1PWM7:0
LHCH1PWM
L
1Ah
1Bh
1Ch
1Dh
00000000
LHCH1PWM
H
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
LHCH2PWM7:0
RSVD RSVD
RSVD
RSVD
RSVD
LHCH1PWM9:8
LHCH2PWM9:8
00000000
00000000
00000000
LHCH2PWM
L
LHCH2PWM
H
1Eh
1Fh
20h
LHILIM
LHIFT
LHCH2ILIMCNT1:0
RSVD RSVD
LHCH2MFT3:0
LHCH2RF LHCH1RF LHCH2FB LHCH1FB LHCH2OV LHCH1OV LHCH2UV LHCH1UV
LHCH1ILIMCNT1:0
LHCH2ILIM1:0
LHCH1ILIM1:0
00001111
00001010
10011001
RSVD RSVD
LHCH2IFT1:0
LHCH1IFT1:0
LHMFT
LHCH1MFT3:0
21h
22h
23h
LHFEN1
LHFEN2
00111100
00001111
EN
EN
OEN
LHCH2OC LHCH1OC LHCH2ILI LHCH1ILI LHCH2ISO LHCH1ISO
EN EN MEN MEN EN EN
OEN
EN
EN
EN
EN
RSVD
RSVD
LHCH2ILI LHCH1ILI LHCH2OC LHCH1OC LHCH2OV LHCH1OV LHCH2UV LHCH1UV
LHFLATEN
00000000
00100010
MFL
MFL
FL
FL
FL
FL
FL
FL
24h
25h
26h
LHOV
CAL
RSVD
LHCH2OV2:0
RSVD
LHCH1OV2:0
CH2CAL2:0
CH2GOFF
CH1CAL2:0
CH1GOFF 00000000
00000000
RESET
RESET7:0
In the following sub-sections the descriptions of different registers in Table 7-2 are provided.
Copyright © 2020 Texas Instruments Incorporated
38
Submit Document Feedback
Product Folder Links: TPS92682-Q1
TPS92682-Q1
SLUSCX8B – MARCH 2019 – REVISED JULY 2020
www.ti.com
7.6.1 EN Register
EN is the channel enable register. This register contains bits associated with the enabling of channels and
several channel-related functions.
Table 7-3. EN Register
ADDR
00h
REGISTER
EN
D7
D6
D5
CH2MAX CH1MAX CH2PDRV CH1PDRV
DEN DEN EN EN
D4
D3
D2
D1
D0
DEFAULT
FPINRST SYNCEN
CH2EN
CH1EN
00111100
•
•
FPINRST:
Setting this bit to one resets both fault pins, if there are no active faults in the system. Note that this bit is
write-only. Any reads of this register return 0 in the FPINRST bit location.
SYNCEN:
0: SYNC input is disabled.
1: SYNC input is enabled.
CHxMAXDEN:
•
•
•
0: Maximum duty cycle for the associated channel is disabled.
1: Maximum duty cycle for the associated channel is enabled.
CHxPDRVEN:
0: The associated channel PFET driver is disabled.
1: The associated channel PFET driver is enabled.
CHxEN:
0: The associated channel is disabled.
1: The associated channel is enabled. SPI writes of ‘1’ to these bits are blocked if the PC bit in the FLT1
register is high.
7.6.2 CFG1 Register
Configuration register 1
Table 7-4. CFG1 Register
ADDR
01h
REGISTER
CFG1
D7
D6
D5
D4
D3
D2
D1
D0
DEFAULT
PWMPH INTPWM
2PH
LH
CH2HG
CH1HG
CH2CV
CH1CV
00000000
•
•
•
•
PWMPH:
0: Phase shift of 180° between internal PWM signals
1: Zero phase shift between internal PWM signals
INTPWM:
0: External PWM inputs are used.
1: Internal PWM inputs are used.
2PH:
0: Single phase, two-channel configuration
1: Dual phase configuration
LH:
This bit is latched high when the LH pin is set high. The LH bit remains high until this bit is written back to
zero through SPI (the LH pin cannot set this bit to zero). If the LH bit is high, the LH registers are used to
Copyright © 2020 Texas Instruments Incorporated
Submit Document Feedback
39
Product Folder Links: TPS92682-Q1
TPS92682-Q1
SLUSCX8B – MARCH 2019 – REVISED JULY 2020
www.ti.com
control the logic instead of the normal registers. The part comes out of LH mode when LH pin is pulled low
and the LH bit is written to 0.
It is recommended that the LH bit always be written with a ‘1’ during normal programming. This will ensure
that a true limp-home event triggered by LH pin is captured.
•
•
CHxHG:
0: The error-amp of the associated channel is set to low gain.
1: The error-amp of the associated channel is set to high gain.
CHxCV:
0: The associated channel is set in CC mode.
1: The associated channel is set in CV mode.
7.6.3 CFG2 Register
Configuration register 2
Table 7-5. CFG2 Register
ADDR
02h
REGISTER
CFG2
D7
D6
D5
D4
D3
D2
D1
D0
DEFAULT
CH2LEB
CH1LEB
RSVD
RSVD
CH2FILT1
RSVD
RSVD
CH1FILT1 00000000
•
•
CHxLEB:
0: Short Leading Edge Blanking
1: Long Leading Edge Blanking
CHxFILT1: ILIM comparator filter
7.6.4 SWDIV Register
SWDIV register holds the divider value associated with dividing down the main clock to generate the channel
clocks (switching frequency fSW).
Table 7-6. SWDIV Register
ADDR
03h
REGISTER
SWDIV
D7
D6
D5
D4
D3
D2
D1
D0
DEFAULT
RSVD
RSVD
RSVD
RSVD
CH2DIV1:0
CH1DIV1:0
00000000
•
CHxDIV:
00: Division = 2. CHxCLK = fCLKM / 2
01: Division = 4. CHxCLK = fCLKM / 4
10: Division = 8. CHxCLK = fCLKM / 8
11: Division = 8. CHxCLK = fCLKM / 8
7.6.5 ISLOPE Register
ISLOPE register programs the slope compensation ramp magnititude.
Table 7-7. ISLOPE Register
ADDR
04h
REGISTER
ISLOPE
D7
D6
D5
D4
D3
D2
D1
D0
DEFAULT
RSVD
CH2ISLP2:0
RSVD
CH1ISLP2:0
01010101
•
CHxISLP:
000: VSLP(PK) = 0 mV
001: VSLP(PK) = 50 mV
010: VSLP(PK) = 100 mV
Copyright © 2020 Texas Instruments Incorporated
40
Submit Document Feedback
Product Folder Links: TPS92682-Q1
TPS92682-Q1
SLUSCX8B – MARCH 2019 – REVISED JULY 2020
www.ti.com
011: VSLP(PK) = 150 mV
100: VSLP(PK) = 200 mV
101: VSLP(PK) = 250 mV
110: VSLP(PK) = 300 mV
111: VSLP(PK) = 350 mV
7.6.6 FM Register
FM contains the Frequency Modulation configuration bits.
Table 7-8. FM Register
ADDR
05h
REGISTER
FM
D7
D6
D5
D4
D3
D2
D1
D0
DEFAULT
RSVD
RSVD
FMMAG1:0
FMFREQ3:0
00000101
•
•
The CLKM frequency is varied by a percentage defined by FMMAG:
00: Frequency modulation is disabled.
01: The modulation magnitude is set to ±3.75%.
10: The modulation magnitude is set to ±7.5%.
11: The modulation magnitude is set to ±15%.
The FMFREQ programs a division factor applied to CLKM that sets the frequency modulation:
0000: FM frequency is 1÷4096 of CLKM frequency.
0001: FM frequency is 1÷3584 of CLKM frequency.
0010: FM frequency is 1÷3072 of CLKM frequency.
0011: FM frequency is 1÷2560 of CLKM frequency.
0100: FM frequency is 1÷2048 of CLKM frequency.
0101: FM frequency is 1÷1536 of CLKM frequency.
0110: FM frequency is 1÷1024 of CLKM frequency.
0111: FM frequency is 1÷512 of CLKM frequency.
1000: FM frequency is 1÷256 of CLKM frequency.
1001: FM frequency is 1÷128 of CLKM frequency.
1010: FM frequency is 1÷64 of CLKM frequency.
1011: FM frequency is 1÷32 of CLKM frequency.
1100: FM frequency is 1÷16 of CLKM frequency.
1101: FM frequency is 1÷8 of CLKM frequency.
1110: Frequency modulation is disabled.
1111: Frequency modulation is disabled.
7.6.7 SOFTSTART Register
The SOFTSTART register determines the division factor to be applied to the input clock of the soft-start 8-bit
ramp counter.
Copyright © 2020 Texas Instruments Incorporated
Submit Document Feedback
41
Product Folder Links: TPS92682-Q1
TPS92682-Q1
SLUSCX8B – MARCH 2019 – REVISED JULY 2020
www.ti.com
Table 7-9. SOFTSTART Register
ADDR
06h
REGISTER
D7
D6
D5
D4
D3
D2
D1
D0
DEFAULT
SOFTSTART
CH2SS3:0
CH1SS3:0
01110111
•
CHxSS:
0000: Soft-start is disabled.
0001: Division factor = 2
0010: Division factor = 4
0011: Division factor = 6
0100: Division factor = 8
0101: Division factor = 12
0110: Division factor = 16
0111: Division factor = 20
1000: Division factor = 26
1001: Division factor = 32
1010: Division factor = 38
1011: Division factor = 46
1100: Division factor = 54
1101: Division factor = 64
1110: Division factor = 80
1111: Division factor = 100
If 2PH is set to '1', only CH1 parameter is used.
7.6.8 CH1IADJ Register
CH1IADJ register programs the 8-bit IADJ DAC for the channel-1. If CH1IADJ ≤ 8, channel-1 is turned off. The
DAC output can be set from 85 mV (code 9) to 2.4 V (code 255).
Table 7-10. CH1IADJ Register
ADDR
07h
REGISTER
CH1IADJ
D7
D6
D5
D4
D3
D2
D1
D0
DEFAULT
CH1IADJ7:0
00000000
7.6.9 CH2IADJ Register
CH2IADJ register programs the 8-bit IADJ DAC for the channel 2. If CH2IADJ ≤ 8, channel-2 is turned off. The
DAC output can be set from 85 mV (code 9) to 2.4 V (code 255).
Table 7-11. CH2IADJ Register
ADDR
08h
REGISTER
CH2IADJ
D7
D6
D5
D4
D3
D2
D1
D0
DEFAULT
CH2IADJ7:0
00000000
If 2PH is set to '1', only CH1 parameter is used.
7.6.10 PWMDIV Register
PWMDIV register sets the clock divider for the internal PWM generator block.
Copyright © 2020 Texas Instruments Incorporated
42
Submit Document Feedback
Product Folder Links: TPS92682-Q1
TPS92682-Q1
SLUSCX8B – MARCH 2019 – REVISED JULY 2020
www.ti.com
Table 7-12. PWMDIV Register
ADDR
09h
REGISTER
PWMDIV
D7
D6
D5
D4
D3
D2
D1
D0
DEFAULT
RSVD
RSVD
RSVD
RSVD
RSVD
PWMDIV2:0
00000001
•
PWMDIV:
000: PWMCLK = CLKM ÷ 1
001: PWMCLK = CLKM ÷ 2
010: PWMCLK = CLKM ÷ 3
011: PWMCLK = CLKM ÷ 4
100: PWMCLK = CLKM ÷ 5
101: PWMCLK = CLKM ÷ 6
110: PWMCLK = CLKM ÷ 7
111: PWMCLK = CLKM ÷ 8
7.6.11 CH1PWML Register
CH1PWML register sets the eight LSBs of the PWM-width on a 10-bit counter for channel-1.
Table 7-13. CH1PWML Register
ADDR
0Ah
REGISTER
CH1PWML
D7
D6
D5
D4
D3
D2
D1
D0
D0
D0
D0
DEFAULT
CH1PWM7:0
00000000
7.6.12 CH1PWMH Register
CH1PWMH register sets the two MSBs of the PWM-width on a 10-bit counter for channel-1.
Table 7-14. CH1PWMH Register
ADDR
0Bh
REGISTER
CH1PWMH
D7
D6
D5
D4
D3
D2
D1
DEFAULT
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
CH1PWM9:8
00000000
7.6.13 CH2PWML Register
CH2PWML register sets the eight LSBs of the PWM-width on a 10-bit counter for channel-2.
Table 7-15. CH2PWML Register
ADDR
0Ch
REGISTER
CH2PWML
D7
D6
D5
D4
D3
D2
D1
DEFAULT
CH2PWM7:0
00000000
7.6.14 CH2PWMH Register
CH2PWMH register sets the two MSBs of the PWM-width on a 10-bit counter for channel-2.
Table 7-16. CH2PWMH Register
ADDR
0Dh
REGISTER
CH2PWMH
D7
D6
D5
D4
D3
D2
D1
CH2PWM9:8
DEFAULT
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
00000000
7.6.15 ILIM Register
ILIM register configures the ILIM event counter and the VILIM(THR) of channel-1 and channel-2.
Copyright © 2020 Texas Instruments Incorporated
Submit Document Feedback
43
Product Folder Links: TPS92682-Q1
TPS92682-Q1
SLUSCX8B – MARCH 2019 – REVISED JULY 2020
www.ti.com
Table 7-17. ILIM Register
ADDR
0Eh
REGISTER
ILIM
D7
D6
D5
D4
D3
D2
D1
D0
DEFAULT
CH2ILIMCNT1:0
CH1ILIMCNT1:0
CH2ILIM1:0
CH1ILIM1:0
00001111
ILIM event counter counts the number of ILIM fault events before disabling the associated channel completely or
initiating the ILIM Fault Timer.
•
CHxILIMCNT:
00: ILIM event counter threshold = 1
01: ILIM event counter threshold = 4
10: ILIM event counter threshold = 16
11: ILIM event counter threshold = 32
•
The current limit threshold voltage of the associated channel is set by CHxILIM:
00: VILIM(THR) = 75 mV
01: VILIM(THR) = 100 mV
10: VILIM(THR) = 150 mV
11: VILIM(THR) = 250 mV
7.6.16 IFT Register
ILIM Fault Timer register, IFT, determines the maximum count value of a 6-bit counter used for the ILIM Fault
Timer. The clock for the ILIM Fault Timer is the CHxCLK
.
Table 7-18. IFT Register
ADDR
0Fh
REGISTER
IFT
D7
D6
D5
D4
D3
D2
D1
D0
DEFAULT
RSVD
RSVD
RSVD
RSVD
CH2IFT1:0
CH1IFT1:0
00001010
•
CHxIFT:
00: ILIM Fault Timer maximum count = 4
01: ILIM Fault Timer maximum count = 8
10: ILIM Fault Timer maximum count = 16
11: ILIM Fault Timer maximum count = 32
If 2PH is set to '1', only CH1 parameters are used and only ILIM Fault Timer 1 is active. In this case, ILIM Fault
Timer 1 affects both channels.
7.6.17 MFT Register
Main Fault Timer register, MFT, determines the maximum count value of a 14-bit counter, used for the Main Fault
Timer. The clock for the MFT is the CHxCLK
.
Table 7-19. MFT Register
ADDR
10h
REGISTER
MFT
D7
D6
D5
D4
D3
D2
D1
D0
DEFAULT
CH2MFT3:0
CH1MFT3:0
10011001
•
CHxMFT:
0000: Main Fault Timer maximum count = 0 (Main Fault Timer is disabled)
0001: Main Fault Timer maximum count = 1000
0010: Main Fault Timer maximum count = 1500
Copyright © 2020 Texas Instruments Incorporated
44
Submit Document Feedback
Product Folder Links: TPS92682-Q1
TPS92682-Q1
SLUSCX8B – MARCH 2019 – REVISED JULY 2020
www.ti.com
0011: Main Fault Timer maximum count = 2000
0100: Main Fault Timer maximum count = 2500
0101: Main Fault Timer maximum count = 3000
0110: Main Fault Timer maximum count = 3500
0111: Main Fault Timer maximum count = 4000
1000: Main Fault Timer maximum count = 5000
1001: Main Fault Timer maximum count = 6000
1010: Main Fault Timer maximum count = 7000
1011: Main Fault Timer maximum count = 8000
1100: Main Fault Timer maximum count = 10000
1101: Main Fault Timer maximum count = 12000
1110: Main Fault Timer maximum count = 14000
1111: Main Fault Timer maximum count = 16383
If 2PH is set to '1', only CH1 parameters are used and only Fault Timer 1 is active. In this case, Fault Timer 1
affects both channels.
7.6.18 FLT1 Register (read only)
FLT1 register bits are set if a selected fault shown in Table 7-20 occurs. Reading this register clears the bits that
are set, if the associated faults no longer exist. Note that the clearing of the bits happens at the end of the read
response SPI transfer, not at the end of the read command SPI transfer.
Table 7-20. FLT1 Register
ADDR
11h
REGISTER
FLT1
D7
D6
D5
D4
D3
D2
D1
D0
DEFAULT
RTO
RSVD
PC
TW
CH2OV
CH1OV
CH2UV
CH1UV
read
•
•
RTO: RT pin is open.
PC: Power Cycled bit; This bit is set at power up and upon POR. The PC bit must be cleared before the soft-
start DAC state machine can progress and the channels can be turned on.
TW: Thermal Warning bit
CHxOV: Output overvoltage fault (CH2OV is disabled if 2PH is set to '1').
CHxUV: Output undervoltage fault (CH2UV is disabled if 2PH is set to '1').
•
•
•
7.6.19 FLT2 Register (read only)
FLT2 register bits are set if a selected fault shown in Table 7-21 occurs. Reading this register clears the bits that
are set, if the associated faults no longer exist. Note that the clearing of the bits happens at the end of the read
response SPI transfer, not at the end of the read command SPI transfer.
Table 7-21. FLT2 Register
ADDR
12h
REGISTER
FLT2
D7
D6
D5
D4
D3
D2
D1
D0
DEFAULT
CH2UC
CH1UC
CH2OC
CH1OC
CH2ILIM CH1ILIM
CH2ISO
CH1ISO
read
•
•
•
•
CHxUC: CHx output current less than 0.5 times of the set value (CH2UC is disabled if 2PH is set to '1').
CHxOC: CHx output current more then 1.5 times of the set value (CH2OC is disabled if 2PH is set to '1').
CHxILIM: ILIM bit is only set after CHxILIMCNT counter has reached the programmed value.
CHxISO: Open pin detection on ISN pins
Copyright © 2020 Texas Instruments Incorporated
Submit Document Feedback
45
Product Folder Links: TPS92682-Q1
TPS92682-Q1
SLUSCX8B – MARCH 2019 – REVISED JULY 2020
www.ti.com
7.6.20 FEN1 Register
Fault Enable-1 register, FEN1, determines which of the faults shown in Table 7-22 are enabled. If a fault enable
is set to '1', it is enabled and it will affect the operation of the associated channel. The faults that are disabled will
not affect the CHx fault pin output.
Table 7-22. FEN1 Register
ADDR
13h
REGISTER
FEN1
D7
D6
D5
D4
D3
D2
D1
D0
DEFAULT
CH2FBOE CH1FBOE
CH2RFEN CH1RFEN
CH2OVEN CH1OVEN CH2UVEN CH1UVEN 00111100
N
N
•
Ramp Fault Enable, CHxRFEN:
0: Disables the CHxUV fault from affecting channel operation before or during the Soft-Start ramp. In CV
mode, CHx ILIM neither triggers the IFT, nor turns off the channel before or during the Soft-start ramp. Note
that the cycle-by-cycle current limit is still active.
1: All the enabled faults are active before or during the Soft-start ramp.
•
•
•
CHxFBOEN: if set to '1', FB pin open fault is enabled. There are no associated fault read bits for this fault.
CHxOVEN: if set to '1', output overvoltage fault is enabled. CH2OV fault is disabled if 2PH bit is set to '1'.
CHxUVEN: if set to '1', output undervoltage fault is enabled. CH2UV fault is disabled if 2PH bit is set to '1'.
If 2PH is set to '1', only CH1 parameter is used.
7.6.21 FEN2 Register
Fault Enable-2 register, FEN2, determines which of the faults shown in Table 7-23 are enabled. If a fault enable
is set to '1', it is enabled and it will affect the operation of the associated channel. The faults that are disabled will
not affect the CHx fault pin output.
Table 7-23. FEN2 Register
ADDR
14h
REGISTER
FEN2
D7
D6
D5
D4
D3
D2
D1
D0
DEFAULT
CH2OCE CH1OCE CH2ILIME CH1ILIME CH2ISOE CH1ISOE
OVOPT
RSVD
00001111
N
N
N
N
N
N
•
OVOPT: if set to '1', the OV fault is only captured by the analog block and the digital state machine is not
affected by the overvoltage fault.
•
•
•
CHxOCEN: if set to '1', output overcurrent fault is enabled.
CHxILIMEN: if set to '1', ILIM fault is enabled.
CHxISOEN: if set to '1', ISN open pin fault is enabled.
If 2PH is set to '1', only CH1 parameter is used.
7.6.22 FLATEN Register
Fault Latch Enable register, FLATEN, determines which of the faults shown in Table 7-24 are latched faults. A
latched fault turns off the channel. In this case, to turn the channel back on, the CHxEN should be set to '1' in
Table 7-3 through a SPI write command.
Table 7-24. FLATEN Register
ADDR
15h
REGISTER
FLATEN
D7
D6
D5
D4
D3
D2
D1
D0
DEFAULT
CH2ILIMF CH1ILIMF
CH2OCFL CH1OCFL CH2OVFL CH1OVFL CH2UVFL CH1UVFL 00000000
L
L
•
•
•
•
CHxILIMFL: if set to '1', ILIM fault is set to a latched fault.
CHxOCFL: if set to '1', output overcurrent fault is set to a latched fault.
CHxOVFL: if set to '1', output overvoltage fault is set to a latched fault.
CHxUVFL: if set to '1', output undervoltage fault is set to a latched fault.
Copyright © 2020 Texas Instruments Incorporated
46
Submit Document Feedback
Product Folder Links: TPS92682-Q1
TPS92682-Q1
SLUSCX8B – MARCH 2019 – REVISED JULY 2020
www.ti.com
If 2PH is set to '1', only CH1 parameter is used.
7.6.23 OV Register
CHxOV programs a 3-bit DAC to set the OV threshold relative to the VFBREF
Table 7-25. OV Register
.
ADDR
16h
REGISTER
OV
D7
D6
D5
D4
D3
D2
D1
D0
DEFAULT
RSVD
CH2OV2:0
RSVD
CH1OV2:0
00100010
•
CHxOV:
000: OVTHR = VFBREF×(1.000)
001: OVTHR = VFBREF×(1.025)
010: OVTHR = VFBREF×(1.050)
011: OVTHR = VFBREF×(1.075)
100: OVTHR = VFBREF×(1.100)
101: OVTHR = VFBREF×(1.125)
110: OVTHR = VFBREF×(1.150)
111: OVTHR = VFBREF×(1.200)
If 2PH is set to '1', only CH1 parameter is used.
7.6.24 LHCFG Register
LHCFG is the Limp-Home Configuration register. The settings in this register are applied when LH pin is set
high.
Table 7-26. LHCFG Register
ADDR
17h
REGISTER
LHCFG
D7
D6
D5
D4
D3
D2
D1
D0
DEFAULT
LHPWMP LHINTPW LHCH2MA LHCH1MA LHCH2PD LHCH1PD
LHCH2EN LHCH1EN 00111100
H
M
XDEN
XDEN
RVEN
RVEN
•
•
•
•
•
LHPWMPH:
0: Phase shift of 180° between internal PWM signals
1: Zero phase shift between internal PWM signals
LHINTPWM:
0: External PWM inputs are used.
1: Internal PWM inputs are used.
LHCHxMAXDEN:
0: Maximum duty cycle for the associated channel is disabled.
1: Maximum duty cycle for the associated channel is enabled.
LHCHxPDRVEN:
0: The associated channel PFET driver is disabled.
1: The associated channel PFET driver is enabled.
LHCHxEN:
0: The associated channel is disabled.
1: The associated channel is enabled.
If 2PH is set to '1', only CH1 parameter is used.
Copyright © 2020 Texas Instruments Incorporated
Submit Document Feedback
47
Product Folder Links: TPS92682-Q1
TPS92682-Q1
SLUSCX8B – MARCH 2019 – REVISED JULY 2020
www.ti.com
7.6.25 LHCH1IADJ Register
LHCH1IADJ register programs the 8-bit IADJ DAC for channel-1. The settings in this register are applied when
LH pin is set high. If LHCH1IADJ ≤ 8, the channel-1 is turned off. The DAC output can be set from 85 mV (code
9) to 2.4 V (code 255).
Table 7-27. LHCH1IADJ Register
ADDR
18h
REGISTER
LHCH1IADJ
D7
D6
D5
D4
D3
D2
D1
D0
DEFAULT
LHCH1IADJ7:0
00000000
7.6.26 LHCH2IADJ Register
LHCH2IADJ register programs the 8-bit IADJ DAC for channel-2. The settings in this register are applied when
LH pin is set high. If LHCH2IADJ ≤ 8, the channel-2 is turned off. The DAC output can be set from 85 mV (code
9) to 2.4 V (code 255).
Table 7-28. LHCH2IADJ Register
ADDR
19h
REGISTER
LHCH2IADJ
D7
D6
D5
D4
D3
D2
D1
D0
DEFAULT
LHCH2IADJ7:0
00000000
If 2PH is set to '1', only CH1 parameter is used.
7.6.27 LHCH1PWML Register
LHCH1PWML register sets the eight LSBs of the PWM-width on a 10-bit counter for channel-1. The settings in
this register are applied when LH pin is set high.
Table 7-29. LHCH1PWML Register
ADDR
1Ah
REGISTER
D7
D6
D5
D4
D3
D2
D1
D0
DEFAULT
LHCH1PWML
LHCH1PWM7:0
00000000
7.6.28 LHCH1PWMH Register
LHCH1PWMH register sets the two MSBs of the PWM-width on a 10-bit counter for channel-1. The settings in
this register are applied when LH pin is set high.
Table 7-30. LHCH1PWMH Register
ADDR
1Bh
REGISTER
D7
D6
D5
D4
D3
D2
D1
D0
DEFAULT
LHCH1PWMH
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
LHCH1PWM9:8
00000000
7.6.29 LHCH2PWML Register
LHCH2PWML register sets the eight LSBs of the PWM-width on a 10-bit counter for channel-2. The settings in
this register are applied when LH pin is set high.
Table 7-31. LHCH2PWML Register
ADDR
1Ch
REGISTER
D7
D6
D5
D4
D3
D2
D1
D0
DEFAULT
LHCH2PWML
LHCH2PWM7:0
00000000
If 2PH is set to '1', only CH1 parameter is used.
7.6.30 LHCH2PWMH Register
LHCH2PWMH register sets the two MSBs of the PWM-width on a 10-bit counter for channel-2. The settings in
this register are applied when LH pin is set high.
Copyright © 2020 Texas Instruments Incorporated
48
Submit Document Feedback
Product Folder Links: TPS92682-Q1
TPS92682-Q1
SLUSCX8B – MARCH 2019 – REVISED JULY 2020
www.ti.com
Table 7-32. LHCH2PWMH Register
ADDR
1Dh
REGISTER
D7
D6
D5
D4
D3
D2
D1
D0
DEFAULT
LHCH2PWMH
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
LHCH2PWM9:8
00000000
If 2PH is set to '1', only CH1 parameter is used.
7.6.31 LHILIM Register
LHILIM register configures the ILIM event counter and the VILIM(THR) of channel-1 and channel-2. The settings in
this register are applied when LH pin is set high.
Table 7-33. LHILIM Register
ADDR
1Eh
REGISTER
LHILIM
D7
D6
D5
D4
D3
D2
D1
D0
DEFAULT
LHCH2ILIMCNT1:0
LHCH1ILIMCNT1:0
LHCH2ILIM1:0
LHCH1ILIM1:0
00001111
LHILIM-counter counts the number of ILIM fault events before disabling the associated channel completely or
initiating the ILIM Fault Timer.
•
LHCHxILIMCNT:
00: ILIM event counter threshold = 1
01: ILIM event counter threshold = 4
10: ILIM event counter threshold = 16
11: ILIM event counter threshold = 32
•
The current limit threshold voltage of the associated channel is set by LHCHxILIM:
00: VILIM(THR) = 75 mV
01: VILIM(THR) = 100 mV
10: VILIM(THR) = 150 mV
11: VILIM(THR) = 250 mV
7.6.32 LHIFT Register
LHIFT register determines the maximum count value of a 6-bit counter used for the ILIM Fault Timer. The clock
for the ILIM Fault Timer is the CHxCLK. The settings in this register are applied when LH pin is set high.
Table 7-34. LHIFT Register
ADDR
1Fh
REGISTER
LHIFT
D7
D6
D5
D4
D3
D2
D1
D0
DEFAULT
RSVD
RSVD
RSVD
RSVD
LHCH2IFT1:0
LHCH1IFT1:0
00001010
•
LHCHxIFT:
00: ILIM Fault Timer maximum count = 4
01: ILIM Fault Timer maximum count = 8
10: ILIM Fault Timer maximum count = 16
11: ILIM Fault Timer maximum count = 32
If 2PH is set to '1', only CH1 parameters are used and only ILIM Fault Timer 1 is active. In this case, ILIM Fault
Timer-1 affects both channels.
7.6.33 LHMFT Register
LHMFT register determines the maximum count value of a 14-bit counter, used for the Main Fault Timer. The
clock for the MFT is the CHxCLK. The settings in this register are applied when LH pin is set high.
Copyright © 2020 Texas Instruments Incorporated
Submit Document Feedback
49
Product Folder Links: TPS92682-Q1
TPS92682-Q1
SLUSCX8B – MARCH 2019 – REVISED JULY 2020
www.ti.com
Table 7-35. LHMFT Register
ADDR
20h
REGISTER
LHMFT
D7
D6
D5
D4
D3
D2
D1
D0
DEFAULT
LHCH2MFT3:0
LHCH1MFT3:0
10011001
•
LHCHxMFT:
0000: Main Fault Timer maximum count = 0 (Main Fault Timer is disabled)
0001: Main Fault Timer maximum count = 1000
0010: Main Fault Timer maximum count = 1500
0011: Main Fault Timer maximum count = 2000
0100: Main Fault Timer maximum count = 2500
0101: Main Fault Timer maximum count = 3000
0110: Main Fault Timer maximum count = 3500
0111: Main Fault Timer maximum count = 4000
1000: Main Fault Timer maximum count = 5000
1001: Main Fault Timer maximum count = 6000
1010: Main Fault Timer maximum count = 7000
1011: Main Fault Timer maximum count = 8000
1100: Main Fault Timer maximum count = 10000
1101: Main Fault Timer maximum count = 12000
1110: Main Fault Timer maximum count = 14000
1111: Main Fault Timer maximum count = 16383
If 2PH is set to '1', only CH1 parameters are used and only Fault Timer 1 is active. In this case, Fault Timer 1
affects both channels.
7.6.34 LHFEN1 Register
LHFEN1 register determines which of the faults shown in Table 7-36 are enabled. If a fault enable is set to '1', it
is enabled and it will affect the operation of the associated channel. The faults that are disabled will not affect the
CHx fault pin output. The settings in this register are applied when LH pin is set high.
Table 7-36. LHFEN1 Register
ADDR
21h
REGISTER
LHFEN1
D7
D6
EN
D5
D4
D3
D2
EN
D1
EN
D0
EN
DEFAULT
LHCH2RF LHCH1RF LHCH2FB LHCH1FB LHCH2OV LHCH1OV LHCH2UV LHCH1UV
00111100
EN
OEN
OEN
EN
•
•
LHCHxRFEN:
0: Disables the CHxUV fault from affecting channel operation before or during the Soft-start ramp. In CV
mode, CHx ILIM neither triggers the IFT, nor turns off the channel before or during the Soft-start ramp. Note
that the cycle-by-cycle current limit is still active.
1: All the enabled faults are active before or during the Soft-start ramp.
LHCHxFBOEN: if set to '1', FB pin open fault is enabled. There are no associated fault read bits for these
faults.
•
•
LHCHxOVEN: if set to '1', output overvoltage fault is enabled. CH2OV fault is disabled if 2PH bit is set to '1'.
LHCHxUVEN: if set to '1', output undervoltage fault is enabled. CH2UV fault is disabled if 2PH bit is set to '1'.
If 2PH is set to '1', only CH1 parameter is used.
Copyright © 2020 Texas Instruments Incorporated
50
Submit Document Feedback
Product Folder Links: TPS92682-Q1
TPS92682-Q1
SLUSCX8B – MARCH 2019 – REVISED JULY 2020
www.ti.com
7.6.35 LHFEN2 Register
LHFEN2 register determines which of the faults shown in Table 7-37 are enabled. If a fault enable is set to '1', it
is enabled and it will affect the operation of the associated channel. The faults that are disabled will not affect the
CHx fault pin output. The settings in this register are applied when LH pin is set high.
Table 7-37. LHFEN2 Register
ADDR
22h
REGISTER
LHFEN2
D7
D6
D5
LHCH2OC LHCH1OC LHCH2ILI LHCH1ILI LHCH2IS LHCH1IS
EN EN MEN MEN OEN OEN
D4
D3
D2
D1
D0
DEFAULT
RSVD
RSVD
00001111
•
•
•
LHCHxOCEN: if set to '1', output overcurrent fault is enabled.
LHCHxILIMEN: if set to '1', ILIM fault is enabled.
LHCHxISOEN: if set to '1', ISN open pin fault is enabled.
If 2PH is set to '1', only CH1 parameter is used.
7.6.36 LHFLATEN Register
LHFLATEN register determines which of the faults shown in Table 7-38 are latched faults. A latched fault turns
off the channel. In this case, to turn on the channel back on, the CHxEN should be set to '1' in Table 7-3 through
a SPI write command. The settings in this register are applied when LH pin is set high.
Table 7-38. LHFLATEN Register
ADDR
23h
REGISTER
LHFLATEN
D7
D6
D5
D4
D3
D2
FL
D1
FL
D0
FL
DEFAULT
LHCH2ILI LHCH1ILI LHCH2OC LHCH1OC LHCH2OV LHCH1OV LHCH2UV LHCH1UV
MFL
00000000
MFL
FL
FL
FL
•
•
•
•
LHCHxILIMFL: if set to '1', ILIM fault is set to a latched fault.
LHCHxOCFL: if set to '1', output overcurrent fault is set to a latched fault.
LHCHxOVFL: if set to '1', output overvoltage fault is set to a latched fault.
LHCHxUVFL: if set to '1', output undervoltage fault is set to a latched fault.
If 2PH is set to '1', only CH1 parameter is used.
7.6.37 LHOV Register
LHCHxOV register programs a 3-bit DAC to set the OV threshold relative to the VFBREF. The settings in this
register are applied when LH pin is set high.
Table 7-39. LHOV Register
ADDR
24h
REGISTER
LHOV
D7
D6
D5
D4
D3
D2
D1
D0
DEFAULT
RSVD
LHCH2OV2:0
RSVD
LHCH1OV2:0
00100010
•
LHCHxOV:
000: OVTHR = VFBREF × (1.000)
001: OVTHR = VFBREF × (1.025)
010: OVTHR = VFBREF × (1.050)
011: OVTHR = VFBREF × (1.075)
100: OVTHR = VFBREF × (1.100)
101: OVTHR = VFBREF × (1.125)
110: OVTHR = VFBREF × (1.150)
111: OVTHR = VFBREF × (1.200)
Copyright © 2020 Texas Instruments Incorporated
Submit Document Feedback
51
Product Folder Links: TPS92682-Q1
TPS92682-Q1
SLUSCX8B – MARCH 2019 – REVISED JULY 2020
www.ti.com
If 2PH is set to '1', only CH1 parameter is used.
7.6.38 CAL Register
The CAL register includes calibration bits for the switch current sense circuitry.
Table 7-40. CAL Register
ADDR
25h
REGISTER
CAL
D7
D6
D5
D4
D3
D2
D1
D0
DEFAULT
CH2CAL2:0
CH2GOFF
CH1CAL2:0
CH1GOFF 00000000
CHxCAL: Each channel has three calibration bits, which adds 2.5 mV of offset per bit (2.5 mV to 17.5 mV) to the
switch current sense voltage threshold. The calibration bits can decrease the offset mismatch between the
switch current sense of the two channels and improve the current sharing in two phase applications.
CHxGOFF: This bit turns off the associated channel, when set to "1".
•
7.6.39 RESET Register
Writing 0xC3 to the RESET register resets all writable registers to their default values. This register is write-only
and reads from this register return 0. Note that a RESET command does not reset the PC bit in Table 7-20 to its
power-on default value of '1'.
Table 7-41. RESET Register
ADDR
26h
REGISTER
RESET
D7
D6
D5
D4
D3
D2
D1
D0
DEFAULT
RESET7:0
00000000
Copyright © 2020 Texas Instruments Incorporated
52
Submit Document Feedback
Product Folder Links: TPS92682-Q1
TPS92682-Q1
SLUSCX8B – MARCH 2019 – REVISED JULY 2020
www.ti.com
8 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes. Customers should validate and test their design
implementation to confirm system functionality.
8.1 Application Information General Design Considerations
The TPS92682-Q1 can be configured both in CC and CV mode. In both cases, the following general design
procedures are applicable.
8.1.1 Switching Frequency, fSW
To set the switching frequency for each channel, refer to Section 7.3.3.
8.1.2 Duty Cycle Considerations
The switch duty cycle, D, defines the converter operation and is a function of the input and output voltages. In
steady state, the duty cycle is derived using the expression:
Boost:
VO - V
VO
IN
D =
(9)
Buck-Boost:
VO
D =
VO + V
IN
(10)
The minimum duty cycle, DMIN, and maximum duty cycle, DMAX, are calculated by substituting maximum input
voltage, VIN(MAX), and the minimum input voltage, VIN(MIN), respectively in the previous expressions. The
minimum duty cycle achievable by the device is determined by the leading edge blanking period and the
switching frequency. The maximum duty cycle is limited by the internal oscillator to 90% (typ) to allow for
minimum off-time. It is necessary for the operating duty cycle to be within the operating limits of the device to
ensure closed-loop regulation over the specified input and output voltage range.
8.1.3 Main Power MOSFET Selection
The power MOSFET is required to sustain the maximum switch node voltage, VSW, and switch RMS current
derived based on the converter topology. TI recommends a drain voltage VDS rating of at least 10% greater than
the maximum switch node voltage to ensure safe operation.
The worst case MOSFET RMS current for Boost and Buck-Boost topology depends on the maximum output
power, PO(MAX), and is calculated as follows:
≈
’
PO(MAX)
V
IN(MIN)
IQ(RMS)
=
ì ∆1-
÷
÷
◊
∆
V
VO(MAX)
IN(MIN)
«
(11)
Select a MOSFET with low total gate charge, Qg, to minimize gate drive and switching losses.
8.1.4 Rectifier Diode Selection
A Schottky diode (when used as a rectifier) provides the best efficiency due to its low forward voltage drop and
near-zero reverse recovery time. TI recommends a diode with a reverse breakdown voltage, VD(BR), greater than
or equal to MOSFET drain-to-source voltage, VDS, for reliable performance. It is important to understand the
Copyright © 2020 Texas Instruments Incorporated
Submit Document Feedback
53
Product Folder Links: TPS92682-Q1
TPS92682-Q1
SLUSCX8B – MARCH 2019 – REVISED JULY 2020
www.ti.com
leakage current characteristics of the Schottky diode, especially at high operating temperatures as it impacts the
overall converter operation and efficiency.
The diode power rating and package is selected based on the calculated current, the ambient temperature and
the maximum allowable temperature rise.
8.1.5 Switch Current Sense Resistor
The switch current sense resistor, RIS, is used to implement peak current mode control and to set the peak
switch current limit. The value of RIS is selected to protect the main switching MOSFET under fault conditions.
RIS can be calculated based on peak inductor current, IL(PK), and switch current limit threshold, VILIM(THR)
.
V
ILIM(THR)
RIS
=
1.2ìIL(PK)
(12)
In Equation 12, 20% margin is considered for transient conditions.
GATEx
100 W
ISPx
1 nF
RIS
ISNx
Figure 8-1. IS Input Filter
The use of a 1-nF and 100-Ω low-pass filter is optional. The recommended filter resistor value is less than 500 Ω
to limit its influence on the internal slope compensation signal.
8.1.6 Slope Compensation
The magnitude of internal artificial ramp, VSLP, is set by the ISLOPE register shown in Table 7-7. The slope of
the artificial ramp is VSLP / TSW, where TSW is the switching period. Equation 13 shows a choice of VSLP, which is
sufficient for the stability of the Boost or Buck-Boost topologies over the entire range of duty-cycle D. In practice,
slightly smaller VSLP can be selected for a given application. The value of VSLP in Equation 13 is determined by
the inductor, L, the switch current sense resistor, RIS, output voltage, VO, and the switching period, TSW
.
VO
VSLP
í
ìRIS ì TSW
2ìL
(13)
8.1.7 Soft Start
As described in Section 7.3.14, the ramp can be programmed using Section 7.6.7. The soft-start time, tSS, is the
time for the internal digital ramp to complete the 256 counts (from 0-V to 2.8-V typ). Program the SOFTSTART
Register with a SSxDIV that is found using Equation 14. The maximum time, tSS, for each channel is related to
the maximum value of SSxDIV in Table 7-9.
tSS ì fSW
256
SSxDIV
í
(14)
8.2 Application Information CC Mode
The TPS92682-Q1 controller, when configured in CC mode, is suitable for implementing step-up or step-down
LED driver topologies including BOOST, BUCK-BOOST, SEPIC, and so forth. This section presents the design
process for the BOOST and BUCK-BOOST converters. The expressions derived for the BUCK-BOOST topology
can be altered to select components for a 1:1 coupled-inductor SEPIC converter. The design procedure can be
easily adapted for FLYBACK and similar converter topologies.
Copyright © 2020 Texas Instruments Incorporated
54
Submit Document Feedback
Product Folder Links: TPS92682-Q1
TPS92682-Q1
SLUSCX8B – MARCH 2019 – REVISED JULY 2020
www.ti.com
LED1+
LED1-
Q3
RCS1
RFB12
RFB11
CCOMP1
29
CVDD
31
VIN
RT
32
30
28
27
26
25
COUT1
CVIN
1
2
24
VIN
EN
ISN1
RIS1
CVCC
RIS2
23
22
21
20
EN
VPWM1
ISP1
GATE1
VCC
D1
VIN
3
4
PWM1
PWM2
Q1
L1
VPWM2
TPS92682-Q1
PGND
5
6
7
8
L2
SSN
Q2
19
18
GATE2
ISP2
SCK
D2
CIN
SPI
COUT3
MISO
MOSI
17
ISN2
DAP
COUT2
9
10
VDD
11 12
13
CCOMP2
14
15
16
VDD
LH
RFLT1
FAULT1
FAULT2
RFLT2
Q4
RCS2
RFB22
RFB21
Q5
LED2+
LED2-
Figure 8-2. Two-Channel LED Driver, BOOST, and BUCK-BOOST Topology (CC mode)
8.2.1 Inductor Selection
The choice of inductor sets the continuous conduction mode (CCM) and discontinuous conduction mode (DCM)
boundary condition. Therefore, one approach of selecting the inductor value is by deriving the relationship
between the output power corresponding to CCM-DCM boundary condition, PO(BDRY), and inductance, L. This
approach ensures CCM operation in battery-powered LED driver applications that are required to support
different LED string configurations with a wide range of programmable LED current set points. The CCM-DCM
boundary condition can be estimated either based on the lowest LED current and the lowest output voltage
requirements for a given application or as a fraction of maximum output power, PO(MAX)
.
PO(BDRY) Ç ILED(MIN) ì VO(MIN)
(15)
(16)
PO(MAX)
PO(MAX)
Ç PO(BDRY)
Ç
4
2
Boost:
Copyright © 2020 Texas Instruments Incorporated
Submit Document Feedback
55
Product Folder Links: TPS92682-Q1
TPS92682-Q1
SLUSCX8B – MARCH 2019 – REVISED JULY 2020
www.ti.com
V2
V
≈
’
IN
IN
L =
ì 1-
∆
÷
◊
2ìPO(BDRY) ì fSW
VO
«
(17)
Buck-Boost:
1
L =
2
≈
∆
«
’
÷
◊
1
1
2ìPO(BDRY) ì fSW
ì
+
VO
V
IN
(18)
Select an inductor with a saturation current rating greater than the peak inductor current, IL(PK), at the maximum
operating temperature.
Boost:
≈
’
PO(MAX)
V
V
IN(MIN)
IN(MIN)
IL(PK)
=
+
ì∆1-
÷
÷
◊
∆
V
2ìL ì fSW
VO(MAX)
IN(MIN)
«
(19)
Buck-Boost:
≈
’
VO(MIN) ì V
1
+
1
IN(MIN)
IL(PK) = PO(MAX) ì∆
÷ +
÷
∆
VO(MIN)
V
2ìL ì fSW ì V
+ V
IN(MIN)
O(MIN)
IN(MIN)
«
◊
(20)
8.2.2 Output Capacitor Selection
The output capacitors are required to attenuate the discontinuous or large ripple output current, and achieve the
desired peak-to-peak LED current ripple, ΔiLED(PP). The capacitor value depends on the total series resistance of
the LED string, rD, and the switching frequency, fSW.The capacitance required for the target LED ripple current
can be calculated based on following equations.
Boost:
≈
’
ILED(MAX)
V
IN(MIN)
COUT
=
ì∆1-
÷
÷
◊
∆
DiLED(PP) ì fSW ìrD
VO(MAX)
«
(21)
Buck-Boost:
COUT
ILED(MAX) ì VO(MIN)
=
DiLED(PP) ì fSW ìrD(MIN) ì V
+ V
O(MIN)
IN(MIN)
(22)
When choosing the output capacitors, it is important to consider the ESR and the ESL characteristics as they
directly impact the LED current ripple. Ceramic capacitors are the best choice due to their low ESR, high ripple
current rating, long lifetime, and good temperature performance. When selecting ceramic capacitors, it is
important to consider the derating factors associated with higher temperature and the DC bias operating
conditions. TI recommends an X7R dielectric with voltage rating greater than maximum LED stack voltage. An
aluminum electrolytic capacitor can be used in parallel with ceramic capacitors to provide bulk energy storage.
The aluminum capacitors must have necessary RMS current and temperature ratings to ensure prolonged
operating lifetime. The minimum allowable RMS output capacitor current rating, ICOUT(RMS), can be approximated
as:
Boost and Buck-Boost:
Copyright © 2020 Texas Instruments Incorporated
56
Submit Document Feedback
Product Folder Links: TPS92682-Q1
TPS92682-Q1
SLUSCX8B – MARCH 2019 – REVISED JULY 2020
www.ti.com
DMAX
ICOUT RMS = ILED
ì
(
)
1- DMAX
(23)
8.2.3 Input Capacitor Selection
The input capacitor, CIN, reduces the input voltage ripple and stores energy to supply input current during input
voltage or PWM dimming transients. The series inductor in the Boost and SEPIC topologies provides continuous
input current and requires a smaller input capacitor to achieve desired input voltage ripple, ΔvIN(PP). The Buck-
Boost and Flyback topologies have discontinuous input current and require a larger capacitor to achieve the
same input voltage ripple. Based on the switching frequency, fSW, and the maximum duty cycle, DMAX, the input
capacitor value can be calculated for each channel as follows:
Boost:
≈
’
V
V
IN(MIN)
IN(MIN)
CIN
=
ì ∆1-
÷
÷
◊
8ìL ì fS2W ì DvIN(PP)
Buck-Boost:
CIN
∆
VO(MAX)
«
(24)
PO(MAX)
=
fSW ì DvIN(PP) ì V
IN(MIN)
(25)
X7R dielectric-based ceramic capacitors are the best choice due to their low ESR, high ripple current rating, and
good temperature performance. For applications using PWM dimming, TI recommends large bulk capacitors in
addition and in parallel to the ceramic capacitors to minimize the voltage deviation due to large input current
transients generated in conjunction with the rising and falling edges of the LED current.
Decouple the VIN pin with a 0.1-µF ceramic capacitor, placed as close as possible to the device, and optionally
in series with a 10-Ω resistor to create a 160-kHz low-pass filter.
VIN
RVIN
VIN
CVIN
Figure 8-3. VIN Filter
8.2.4 Programming LED Current
The LED current can be programmed to match the LED string configuration by writing an 8-bit value to Section
7.6.8 and Section 7.6.9. Equation 26 shows the relation between the programmed LED current ILED, the register
CHxIADJ, and the LED current sense resistor, RCS
.
CHxIADJì 2.4
14ìRCSx ì 255
ILED
=
(26)
8.2.5 Feedback Compensation
The loop gain T(s) is the product of the converter transfer function Givc(s) (Equation 27) and the feedback
transfer function Gc(s).
Using a first-order approximation, the converter transfer function can be modeled as a single pole created by the
output capacitor and the LED string dynamic resistance, rD. In the boost and buck-boost topologies, the transfer
function has a right half-plane zero created by the inductor, and the DC output current ILED. The ESR of the
output capacitor is neglected in this analysis.
Copyright © 2020 Texas Instruments Incorporated
Submit Document Feedback
57
Product Folder Links: TPS92682-Q1
TPS92682-Q1
SLUSCX8B – MARCH 2019 – REVISED JULY 2020
www.ti.com
≈
∆
«
≈
∆
«
’
s
1-
1+
÷
Ù
iLED
wZ
◊
’
÷
◊
Givc s =
( )
= Go ì
Ù
vCOMP
s
wP
(27)
Table 8-1 summarizes the expression for the small-signal model parameters.
Table 8-1. Small-Signal Model Parameters for CC Operation
DC GAIN (G0)
POLE FREQUENCY (ωP)
ZERO FREQUENCY (ωZ)
2
1-D ì V
(
)
VO
+ rD ìILED
(
)
O
VO ì 1-D
(
)
Boost
RIS
ì
V
+
rD ìILED
VO ìrD ì COUT
(
)
L ìILED
O
2
1- D ì V
(
V
)
VO
+ DìrD ìILED
(
)
O
VO ì 1-D
(
)
Buck-Boost
RIS
ì
+
DìrD ìILED
VO ìrD ìCOUT
(
)
DìL ìILED
O
The feedback transfer function includes the current sense resistor and the loop compensation of the
transconductance amplifier. A compensation network at the output of the error amplifier is used to configure loop
gain and phase characteristics. A simple capacitor, CCOMP, from COMPx to GND (as shown in Figure 8-4)
provides integral compensation and creates a pole at the origin. Alternatively, a network of RCOMP, CCOMP, and
CHF, shown in Figure 8-5, can be used to implement Proportional-Integral (PI) compensation to create a pole at
the origin, a low-frequency zero, and a high-frequency pole.
The feedback transfer function is defined as follows.
Feedback transfer function with integral compensation:
Ù
vCOMP 14ì gM ìRCS
GC s = -
( )
=
Ù
iLED
sìCCOMP
(28)
(29)
Feedback transfer function with proportional integral compensation:
Ù
vCOMP
1+ sìRCOMP ìCCOMP
(
)
14ì gM ìRCS
sì C + CHF
GC s = -
( )
=
ì
Ù
iLED
≈
’
(
)
≈
∆
«
’
÷
◊
CCOMP ìCHF
COMP
1+ sìR
ì
∆
∆
÷
÷
COMP
CCOMP + CHF
«
◊
Copyright © 2020 Texas Instruments Incorporated
58
Submit Document Feedback
Product Folder Links: TPS92682-Q1
TPS92682-Q1
SLUSCX8B – MARCH 2019 – REVISED JULY 2020
www.ti.com
CHx_comp
CHx_comp
COMPx
COMPx
RCOMP
CCOMP
CHF
gM
gM
CCOMP
0 œ 2.4V
8-Bit
DAC
0 œ 2.4V
CHx_IADJ
CHx_IADJ
8-Bit
DAC
CHxEAREF
CHxEAREF
ILED
ILED
CSPx
CSPx
+
x14
œ
+
x14
RCS
RCS
CHx_Isense
CHx_Isense
œ
CSNx
CSNx
Figure 8-4. Integral Compensator
Figure 8-5. Proportional Integral Compensator
The pole at the origin minimizes output steady-state error. High bandwidth is achieved with the PI compensator
by introducing a phase lead using a low-frequency zero. Use the following expressions to calculate the
compensation network.
•
BOOST and BUCK-BOOST with an Integral Compensator:
20ì gM ìRCS ìG0
CCOMP
=
wP
(30)
•
BOOST and BUCK-BOOST with a Proportional-Integral Compensator:
14ì gM ìRCS ìG0
CCOMP
=
wP ì wZ
(31)
(32)
CCOMP
100
CHF
<
1
RCOMP
=
wP ìCCOMP
(33)
The above compensation values are calculated to provide reasonable phase margin (> 45°) and bandwidth. In
practice, the above values can be modified for desired dynamic performance (for example: PWM dimming rise/
fall-time or overshoot/undershoot).
8.2.6 Overvoltage and Undervoltage Protection
In BOOST and SEPIC topologies, the Overvoltage threshold is programmed using a resistor divider, RFBx1 and
RFBx2, from the output voltage VO to GND. If the LEDs are referenced to a potential other than GND, as in the
BUCK-BOOST, the output voltage is sensed and translated to ground by using a PNP transistor and level-shift
resistors, as shown in Figure 8-2 for the channel-2. The Overvoltage turnoff threshold, VO(OV), is:
Boost:
≈
∆
«
’
÷
◊
RFB1 + RFB2
RFB1
VO OV = VOV THR
ì
(
)
(
)
(34)
Buck and Buck-Boost:
Copyright © 2020 Texas Instruments Incorporated
Submit Document Feedback
59
Product Folder Links: TPS92682-Q1
TPS92682-Q1
SLUSCX8B – MARCH 2019 – REVISED JULY 2020
www.ti.com
RFB2
VO OV = VOV THR) ì
+ 0.7
(
)
(
RFB1
(35)
In CC mode, VOV(THR) = 1.24 V (typ), when CHxOV register is set to 000.
The Overvoltage hysteresis, VOV(HYS), is:
VOV HYS = IOV HYS ìRFB2
(36)
where
IOV(HYS) is 20 µA (typ.)
•
The corresponding undervoltage fault threshold, VO(UV), is:
RFB1 + RFB2
RFB1
VO UV = 0.05ì
(
)
(37)
8.2.7 Series P-Channel MOSFET Selection
In the applications with PWM dimming, the device requires a P-channel MOSFET placed in series with the LED
load. Select a P-channel MOSFET with gate-to-source voltage rating of 10 V or higher and with a drain-to-source
breakdown voltage rating greater than the output voltage. Ensure that the drain current rating of the P-channel
MOSFET exceeds the programmed LED current by at least 10%.
It is important to consider the FET input capacitance and on-resistance as it impacts the accuracy and efficiency
of the LED driver. TI recommends a FET with lower input capacitance and gate charge to minimize the errors
caused by rise and fall times when PWM dimming at low duty cycles is applied.
8.3 Typical Application CV Mode
The TPS92682-Q1 controller, when configured in CV mode, is suitable for implementing step-up voltage
regulator topologies including BOOST, SEPIC, and so forth. The device can also be configured in two-phase
mode for efficiency optimization and reduced input and output current ripple. This section presents the design
process for the BOOST voltage regulator. The design procedure can be easily adapted for other converter
topologies, like 1:1 coupled-inductor SEPIC converter.
Copyright © 2020 Texas Instruments Incorporated
60
Submit Document Feedback
Product Folder Links: TPS92682-Q1
TPS92682-Q1
SLUSCX8B – MARCH 2019 – REVISED JULY 2020
www.ti.com
VOUT1
CCOMP1
29
VIN
RT
RFB11
26
CVDD
31
RFB12
25
32
30
28
27
COUT1
CVIN
1
2
24
VIN
EN
ISN1
RIS1
CVCC
RIS2
23
22
21
20
EN
ISP1
GATE1
VCC
D1
VDD
VIN
3
4
PWM1
PWM2
Q1
L1
TPS92682-Q1
PGND
5
6
7
8
L2
SSN
Q2
19
18
GATE2
ISP2
CIN
SCK
D2
SPI
MISO
MOSI
17
ISN2
DAP
COUT2
9
10
VDD
11 12
13
CCOMP2
14
15
16
RFB21
VDD
RFB22
LH
RFLT1
VOUT2
FAULT1
FAULT2
RFLT2
Figure 8-6. Two-Channel BOOST Voltage Regulator (CV mode)
Copyright © 2020 Texas Instruments Incorporated
Submit Document Feedback
61
Product Folder Links: TPS92682-Q1
TPS92682-Q1
SLUSCX8B – MARCH 2019 – REVISED JULY 2020
www.ti.com
COMP
CCOMP
VOUT
VIN
RT
RFB1
26
CVDD
31
RFB2
25
32
30 29
28
27
COUT
CVIN
1
2
24
VIN
EN
ISN1
RIS1
CVCC
RIS2
23
22
21
20
EN
ISP1
GATE1
VCC
D1
D2
VDD
3
4
PWM1
PWM2
Q1
VIN
L2
TPS92682-Q1
PGND
5
6
7
8
SSN
Q2
19
18
GATE2
ISP2
L1
SCK
CIN
SPI
MISO
MOSI
17
ISN2
DAP
9
10
VDD
11 12
CCOMP
13
14
15
16
VDD
LH
RFLT1
FAULT1
FAULT2
COMP
RFLT2
Figure 8-7. Two-Phase BOOST Voltage Regulator (CV mode)
8.3.1 Inductor Selection
The choice of the inductors in CV BOOST is highly dependent on the efficiency and the form-factor targets. One
parameter that affects these specifications is the desired inductor current ripple. A common first choice for the
inductor current ripple, ΔiL-PP, is 50% of the nominal inductor current IL.
V ì V - V
(
)
IN
O
IN
L =
DiL-PP ì VO ì fSW
(38)
where
M = VO / VIN
•
BOOST voltage regulators can be configured to operate in Discontinuous Conduction Mode (DCM) to achieve
higher efficiency at light load. The condition to operate in DCM versus CCM are shown in Equation 39 and
Equation 40:
CCM Operation:
V2 ì V - V
(
)
IN
O
IN
PO >
2ì VO ìL ì fSW
(39)
DCM Operation:
Copyright © 2020 Texas Instruments Incorporated
62
Submit Document Feedback
Product Folder Links: TPS92682-Q1
TPS92682-Q1
SLUSCX8B – MARCH 2019 – REVISED JULY 2020
www.ti.com
V2 ì V - V
(
)
IN
O
IN
PO Ç
2ì VO ìL ì fSW
(40)
8.3.2 Output Capacitor Selection
The output capacitors are required to attenuate the discontinuous output current of the BOOST converter, as
well as decreasing the output voltage undershoot and overshoot during load transient. The capacitance required
for the target output peak-to-peak ripple is provided in the following equations:
For one-phase operation:
≈
’
V
IOUT(MAX)
IN(MIN)
COUT = ∆1-
֓
÷
∆
VO(MAX)
DvO-PP ì fSW
«
◊
(41)
For two-phase operation, fSW in Equation 41 must be substituted with twice of the switching frequency.
When choosing the output capacitors, it is important to consider the ESR and the ESL characteristics as they
directly impact the output voltage ripple. Ceramic capacitors are the best choice due to their low ESR, high ripple
current rating, long lifetime, and good temperature performance. When selecting ceramic capacitors, it is
important to consider the derating factors associated with higher temperature and the DC bias operating
conditions. TI recommends an X7R dielectric with voltage rating greater than maximum output voltage, VOUT. An
aluminum electrolytic capacitor can be used in parallel with ceramic capacitors to provide bulk energy storage.
The aluminum capacitors must have necessary RMS current and temperature ratings to ensure prolonged
operating lifetime. The minimum allowable RMS output capacitor current rating, ICOUT(RMS), can be approximated
as:
DMAX
ICOUT RMS = IOUT
ì
(
)
1- DMAX
(42)
8.3.3 Input Capacitor Selection
The input capacitors for one-phase CV BOOST can be obtained in the same way found in Equation 24 for CC
mode.
For two-phase operation, the input capacitor can be obtained as shown in Equation 43.
≈
’
V
V
IN(MIN)
IN(MIN)
CIN
=
ì∆1-
÷
÷
◊
8ì(L / 2)ì(2xfSW )2 ì DvIN(PP)
∆
VO(MAX)
«
(43)
8.3.4 Programming Output Voltage VOUT
The output voltage VOUT can be programmed using the feedback resistors and by writing an 8-bit value to
Section 7.6.8 and Section 7.6.9. Equation 44 shows the relationship between the programmed VOUT, the register
CHxIADJ, and the feedback resistors.
≈
’
÷
◊
RFB2
RFB1
CHxIADJì 2.4
255
VOUT = 1+
ì
∆
«
(44)
8.3.5 Feedback Compensation
The loop gain T(s) is the product of the converter transfer function GVVC(s) and the feedback transfer function
GC(s). The TPS92682-Q1 device, when configured as a BOOST voltage regulator, is normally followed by a
second stage switching converter, which acts as a power sink load. In this case, the converter transfer function,
GVVC(s), can be approximated as shown in Equation 45. The GVVC(s) has a low frequency pole, ωP1, and a high
frequency pole, ωP2, when the converter operates in CCM. In DCM, ωP2 can be ignored. In a BOOST topology,
the transfer function has a right half-plane zero.
Copyright © 2020 Texas Instruments Incorporated
Submit Document Feedback
63
Product Folder Links: TPS92682-Q1
TPS92682-Q1
SLUSCX8B – MARCH 2019 – REVISED JULY 2020
www.ti.com
≈
’
÷
◊
s
1-
∆
«
Ù
vo
wZ
Gvvc s =
( )
= Go ì
Ù
vCOMP
≈
∆
«
’ ≈
’
÷
◊
s
s
1+
ì 1+
÷ ∆
wP1
wP2
◊ «
(45)
Table 8-2 summarizes the expressions for the small-signal model parameters of a BOOST converter operating in
CCM or DCM.
Table 8-2. Small-Signal Model Parameters for CV BOOST
BOOST
TOPOLOGY
G0
ωP1
ωP2
ωZ
Fm ì VO2
IN + Fm ìFv ì VO2
V2
IN
≈
’
V
V
IN
Fm ì VO
L
IN
ì∆
∆
+ Fv ÷
CCM
Fm ì VO2
÷
RIS
ì
V
VO ìCOUT
PO ìL
«
◊
V
IN ìIO
ì V - V ìC
O
2ì
V - V ì V
O IN O
(
)
pì fSW
DCM
∞
VO
(
)
VIN ì VC
IN
OUT
In Table 8-2, Fm is the compensation ramp gain, Fv is the VO feedback gain, IO is the DC output current, and VC
is the DC compensation voltage. In a BOOST topology:
RIS
Fm
=
VSLP
(46)
(47)
V2
IN
Fv =
2ìL ì fSW ì VO2
2ìI ì V - V
≈
∆
«
’
(
)
ì
Lì fSW
Fm ì V
O
O
IN
VC = RIS
ì
+1
÷
◊
Lì fSW
IN
(48)
The feedback transfer function includes the voltage divider gain (HFB = RFB1 / (RFB1 + RFB2)) and the
transconductance amplifier gain. A compensation network at the output of the error amplifier is used to configure
loop gain and phase characteristics. In CV BOOST application, a Proportional-Integral (PI) compensation is
recommended. A network of RCOMP, CCOMP, and CHF, shown in Figure 8-8, can be used to implement PI
compensation to create a pole at the origin, a low-frequency zero, and a high-frequency pole.
The feedback transfer function is defined as follows.
Feedback transfer function with proportional integral compensation:
Ù
vCOMP
1+ sìRCOMP ìCCOMP
(
)
gM ìHFB
sì C + CHF
GC s = -
( )
=
ì
Ù
vO
≈
’
(
)
≈
∆
«
’
÷
◊
CCOMP ìCHF
CCOMP + CHF
COMP
1+ sìR
ì
∆
∆
÷
÷
COMP
«
◊
(49)
Copyright © 2020 Texas Instruments Incorporated
64
Submit Document Feedback
Product Folder Links: TPS92682-Q1
TPS92682-Q1
SLUSCX8B – MARCH 2019 – REVISED JULY 2020
www.ti.com
CHx_comp
COMPx
RCOMP
vC
gM
CHF
CCOMP
0 œ 2.4V
8-Bit
DAC
CHx_IADJ
VO
RFB2
CHxEAREF
FBx
RFB1
Figure 8-8. Proportional Integral Compensator
The pole at the origin minimizes output steady-state error. High bandwidth is achieved with the PI compensator
by introducing a phase lead using a low-frequency zero.
PI compensator component values can be found by selecting a reasonable bandwidth and phase-margin. It is
recommended to select a bandwidth of ωC smaller than the RHP zero ωZ by a factor of KC in the range of 5 to
10. Assuming ωC = ωZ / KC and ωC >> ωP1:
wZ
RCOMP
=
KC ì gM ìG0 ìHFB ì wP1
(50)
The compensator zero, generated by the RCOMP and CCOMP is recommended to be placed far below the
bandwidth ωC and above ωP1 to provide adequate phase-margin. It is recommended to set the low-frequency
zero of the compensator as follows:
1
= KP ì wP1
CCOMP ìRCOMP
(51)
where
•
KP is a factor in the range of 1 to 5
From Equation 51 and Equation 52, CCOMP can be found.
CCOMP
CHF
<
100
(52)
8.3.6 Overvoltage and Undervoltage Protection
In CV mode, the output Overvoltage level is set in Section 7.6.23 as a percentage above the programmed
regulated value of VOUT
.
The Overvoltage hysteresis, VOV(HYS), is:
VOV HYS = IOV HYS ìRFB2
(53)
where
IOV(HYS) is 20 µA (typ.)
•
Copyright © 2020 Texas Instruments Incorporated
Submit Document Feedback
65
Product Folder Links: TPS92682-Q1
TPS92682-Q1
SLUSCX8B – MARCH 2019 – REVISED JULY 2020
www.ti.com
The corresponding undervoltage fault threshold, VO(UV), is:
RFB1 + RFB2
RFB1
VO UV = 0.05ì
(
)
(54)
Copyright © 2020 Texas Instruments Incorporated
66
Submit Document Feedback
Product Folder Links: TPS92682-Q1
TPS92682-Q1
SLUSCX8B – MARCH 2019 – REVISED JULY 2020
www.ti.com
8.4 Typical Application CC Mode
Figure 8-9 shows the schematic for a dual channel, high-side current sense, Boost and Buck-Boost LED driver with PFET dimming. In this application,
the Channel-1 of the device is configured as Boost and the Channel-2 as Buck-Boost.
Figure 8-9. CC Mode LED Driver, BOOST, and Buck-Boost
Copyright © 2020 Texas Instruments Incorporated
Submit Document Feedback
67
Product Folder Links: TPS92682-Q1
TPS92682-Q1
SLUSCX8B – MARCH 2019 – REVISED JULY 2020
www.ti.com
8.4.1 CC Boost Design Requirements
Table 8-3 shows the design parameters for the boost LED driver application.
Table 8-3. Design Parameters
PARAMETER
INPUT CHARACTERISTICS
VIN Input voltage range
OUTPUT CHARACTERISTICS
TEST CONDITIONS
MIN
7
TYP
MAX
18
UNIT
V
14
VF(LED)
NLED
VO
LED forward voltage
Number of LEDs in series
Output voltage
2.8
33.6
3.2
12
3.6
V
LED+ to LED–
38.4
350
4%
3
43.2
550
V
ILED
Output current
mA
RRilED
rD
LED current ripple ratio
LED string resistance
Maximum output power
PWM dimming frequency
Ω
W
PO(MAX)
fPWM
25
400
8
Hz
SYSTEMS CHARACTERISTICS
PO(BDRY)
Output power at CCM-DCM boundary
W
condition
ΔvIN(PP)
VO(OV)
VOV(HYS)
fDM
Input voltage ripple
20
50
mV
V
Output Overvoltage protection threshold
Output Overvoltage protection hysteresis
Dither Modulation Frequency
Switching frequency
2.4
V
400
600
Hz
kHz
fSW
400
8.4.2 CC Boost Detailed Design Procedure
In the following section, the detailed design procedure for the CC BOOST LED driver is provided.
8.4.2.1 Calculating Duty Cycle
From Equation 9 and the input and output characteristics in Table 8-3, you can solve for DTYP, DMAX, and DMIN
.
•
•
•
DTYP = 0.64
DMAX = 0.84
DMIN = 0.46
8.4.2.2 Setting Switching Frequency
For the default division factor of 2 in Section 7.6.4 and from Equation 1, the RT value for fSW = 400 kHz can be
obtained:
1012
RT
=
12.5ìSW DIVìfSW
(55)
RT = 100 kΩ
8.4.2.3 Setting Dither Modulation Frequency
The dither modulation frequency can be set using the Section 7.6.6 in Equation 2. For the dither modulation
frequency of less than 600 Hz, the FMFREQ must be set to 0101, which corresponds to a division factor of 1536
and sets FM = 521 Hz.
Copyright © 2020 Texas Instruments Incorporated
68
Submit Document Feedback
Product Folder Links: TPS92682-Q1
TPS92682-Q1
SLUSCX8B – MARCH 2019 – REVISED JULY 2020
www.ti.com
8.4.2.4 Inductor Selection
The inductor is selected to meet the CCM-DCM boundary power requirement, PO(BDRY). In most applications,
PO(BDRY) is set to be 1/3 of the maximum output power, PO(MAX). The inductor value is calculated for typical input
voltage, VIN(TYP), and output voltage, VO(TYP). From Equation 17, the inductor L is calculated to be:
L ≥ 19.5 µH
The value of L = 22 µH is selected for this application.
Ensure that the inductor saturation current rating is greater than 1.2 × IL(PK) found from Equation 19:
IL(PK) = 3.9 A
8.4.2.5 Output Capacitor Selection
The specified peak-to-peak LED current ripple, ΔiLED(PP), is:
ΔiLED(PP) = RRiLED × ILED(MAX) = 22 mA
The output capacitance required to achieve the target LED current ripple can be obtained from Equation 21. The
resulting capacitance value is calculated to be: COUT ≥ 18.4 µF.
Four 4.7-µF 100-V ceramic capacitors are used in parallel to achieve a combined required output capacitance.
8.4.2.6 Input Capacitor Selection
The input capacitor is required to reduce switching noise conducted through the input terminal and to reduce the
input impedance of the LED driver. Equation 24 is used to calculate the required capacitance of CIN ≥ 10 µF to
limit peak-to-peak input voltage ripple, ΔvIN(PP), to 20 mV.
Two 4.7-µF, 50-V ceramic capacitors are used in parallel to achieve the combined input capacitance of 9.4 µF.
As shown in Figure 8-9, an additional 33-µF 50-V electrolytic capacitor and more ceramic capacitors are also
used at the input terminal to further decrease the overshoot and undershoot of VIN during PWM dimming.
8.4.2.7 Main N-Channel MOSFET Selection
Ensure that the MOSFET ratings exceed the maximum output voltage and RMS switch current.
VDS = VO(OV) × 1.1 = 55 V
The maximum RMS switch current can be found from Equation 11 to be 3.9 A.
An N-channel MOSFET with a voltage rating of 100 V and a current rating of more than 4 A is required for this
design.
8.4.2.8 Rectifier Diode Selection
Select a diode with a reverse breakdown voltage, VD(BR), greater than or equal to MOSFET drain-to-source
voltage, VDS, for reliable performance.
The DC current rating of the diode rectifier for the Boost LED driver must be greater than ILED(MAX)
.
8.4.2.9 Setting ILED and Selecting RCS
The LED current can be programmed by writing an 8-bit value to Section 7.6.8, and as described in Section
8.2.4.
The value of the current sense resistor, RCS, can be selected to result in the ILED(MAX) for the maximum
programmed value of 255 in the CHxIADJ register.
2.4
RCS
=
14ìILED(MAX)
(56)
Substituting ILED(MAX) = 0.55 A in Equation 56 results in RCS = 0.31 Ω. A current sense value of 0.3 Ω is selected
for this design.
Copyright © 2020 Texas Instruments Incorporated
Submit Document Feedback
69
Product Folder Links: TPS92682-Q1
TPS92682-Q1
SLUSCX8B – MARCH 2019 – REVISED JULY 2020
www.ti.com
8.4.2.10 Setting Switch Current Limit
As shown in Equation 12, the switch current limit is determined by the switch current sense resistor, RIS, and the
switch current threshold. For VILIM(THR) = 250 mV and 1.2 × IL(PK) = 4.7 A, RIS ≤ 53 mΩ. A standard sense
resistor of RIS = 40 mΩ is selected for this application.
8.4.2.11 Slope Compensation
The recommended slope compensation magnitude can be obtained from Equation 13, VSLP ≥ 100 mV.
The VSLP can be programmed in Section 7.6.5. The ISLOPE =011 is selected, which corresponds with VSLP
=
150 mV.
8.4.2.12 Compensator Parameters
Proportional-Integral Compensator is selected for this design. The initial compensator component values can be
obtained from Equation 31, Equation 32, and Equation 33.
CCOMP = 33 nF
CHF = 3.3 nF
RCOMP = 715 Ω
It is be noted that the above compensator components are fine-tuned to provide improved transient performance
in PWM dimming.
8.4.2.13 Overvoltage Protection
The output Overvoltage level is programmed using a resistor divider, RFB2 and RFB1, from the output voltage, VO,
to GND. RFB2 can be calculated from the VOV(HYS) = 2.4 V and Equation 36:
RFB2 = 120 kΩ
RFB1 can be calculated from Equation 34 and the required value of VO(OV) = 50 V:
RFB1 = 3 kΩ
8.4.2.14 Series P-Channel MOSFET Selection
In applications with PWM dimming, the device requires a P-channel MOSFET placed in series with the LED
load. Select a P-channel MOSFET with a gate-to-source voltage rating of 10 V or higher and with a drain-to-
source breakdown voltage rating greater than the output voltage. Ensure that the drain current rating of the P-
channel MOSFET exceeds the programmed LED current by at least 10%. It is important to consider the FET
input capacitance and on-resistance as it impacts the accuracy and efficiency of the LED driver. TI recommends
a FET with lower input capacitance and gate charge to minimize the errors caused by rise and fall times when
PWM dimming at low duty cycles is applied.
8.4.3 CC Buck-Boost Design Requirements
Buck-Boost LED drivers provide the flexibility needed in applications, where the load voltage (LED string voltage)
maybe less or more than the input battery voltage or the application supports multiple LED load configurations.
For such applications, it is necessary to modify the design procedure presented to account for the wider range of
output voltage and LED current specifications. Table 8-4 shows the design parameters for the Buck-Boost (BtB)
LED driver application.
Table 8-4. Design Parameters
PARAMETER
INPUT CHARACTERISTICS
VIN Input voltage range
OUTPUT CHARACTERISTICS
TEST CONDITIONS
MIN
TYP
MAX
UNIT
V
7
14
18
VF(LED)
NLED
LED forward voltage
2.8
3
3.2
6
3.6
9
V
Number of LEDs in series
Copyright © 2020 Texas Instruments Incorporated
70
Submit Document Feedback
Product Folder Links: TPS92682-Q1
TPS92682-Q1
SLUSCX8B – MARCH 2019 – REVISED JULY 2020
www.ti.com
PARAMETER
Output voltage
TEST CONDITIONS
LED+ to LED–
MIN
8.4
TYP
19.2
500
MAX
32.4
1200
UNIT
V
VO
ILED
Output current
200
mA
RRilED
rD
LED current ripple ratio
LED string resistance
Maximum output power
PWM dimming frequency
7.5%
1.5
0.8
2.3
12
Ω
W
PO(MAX)
fPWM
400
3.5
Hz
SYSTEMS CHARACTERISTICS
PO(BDRY)
Output power at CCM-DCM boundary
W
condition
ΔvIN(PP)
VO(OV)
VOV(HYS)
fDM
Input voltage ripple
100
40
3
mV
V
Output Overvoltage protection threshold
Output Overvoltage protection hysteresis
Dither Modulation Frequency
Switching frequency
V
400
600
Hz
kHz
fSW
400
8.4.4 CC Buck-Boost Detailed Design Procedure
In the following section, the detailed design procedure for the CC Buck-Boost LED driver is provided.
8.4.4.1 Calculating Duty Cycle
From Equation 10 and the input and output characteristics in Table 8-4, you can solve for DTYP, DMAX, and DMIN
.
DTYP = 0.58
DMAX = 0.82
DMIN = 0.32
8.4.4.2 Setting Switching Frequency
The RT value that sets the internal clock is calculated from Equation 55 in Section 8.4.2. For the default division
factor of 2 in Section 7.6.4, the value for fSW = 400 kHz can be obtained.
8.4.4.3 Setting Dither Modulation Frequency
Frequency modulation is shared between both channels of the TPS92682-Q1. As a result, the same frequency
modulation is applied to both Boost and Buck-Boost LED drivers.
8.4.4.4 Inductor Selection
The inductor is selected to meet the CCM-DCM boundary power requirement, PO(BDRY). Typically, the boundary
condition is set to enable CCM operation at the lowest possible operating power. The inductor value is calculated
for typical input voltage, VIN(TYP), and output voltage, VO(TYP). From Equation 18, the inductor L is calculated to
be:
L = 23.4 µH
The value of L = 22 µH is selected for this application.
Ensure that the inductor saturation current rating is greater than the 1.2 × IL(PK) found from Equation 20:
IL(PK) = 3.4 A
8.4.4.5 Output Capacitor Selection
The specified peak-to-peak LED current ripple, ΔiLED(PP), is:
ΔiLED(PP) = RRiLED × ILED(MAX) = 90 mA
The output capacitance required to achieve the target LED current ripple can be obtained from Equation 22. The
resulting capacitance value is calculated to be COUT ≥ 24.2 µF.
Copyright © 2020 Texas Instruments Incorporated
Submit Document Feedback
71
Product Folder Links: TPS92682-Q1
TPS92682-Q1
SLUSCX8B – MARCH 2019 – REVISED JULY 2020
www.ti.com
Five 4.7-µF 100-V ceramic capacitors are used in parallel to achieve a combined required output capacitance.
8.4.4.6 Input Capacitor Selection
The input capacitor is required to reduce switching noise conducted through the input terminal and to reduce the
input impedance of the LED driver. Equation 25 is used to calculate the required capacitance of CIN ≥ 43 µF to
limit peak-to-peak input voltage ripple, ΔvIN(PP), to 100 mV.
Four 10-µF, 50-V ceramic capacitors are used in parallel to achieve a combined input capacitance of 40 µF. As
shown in Figure 8-9, an additional 33-µF 50-V electrolytic capacitor and more ceramic capacitors are also used
at the input terminal to further decrease the overshoot and undershoot of VIN during PWM dimming.
8.4.4.7 Main N-Channel MOSFET Selection
Maximum transistor voltage rating must exceed the following:
VDS = 1.2 × (VO(OV) + VIN(MAX)) = 70 V
The maximum RMS switch current can be found from Equation 11 to be 2.3 A.
An N-channel MOSFET with a voltage rating of 100 V and a current rating of more than 3 A is required for this
design.
8.4.4.8 Rectifier Diode Selection
Select a diode with a reverse breakdown voltage, VD(BR), greater than or equal to MOSFET drain-to-source
voltage, VDS, for reliable performance.
The DC current rating of the diode rectifier for the Buck-Boost LED driver must be greater than ILED(MAX)
.
8.4.4.9 Setting ILED and Selecting RCS
The LED current can be programmed by writing an 8-bit value to Section 7.6.9, and as described in Section
8.2.4.
The value of the current sense resistor, RCS, can be selected to result in the ILED(MAX) for the maximum
programmed value of 255 in the CHxIADJ register.
Substituting ILED(MAX) = 1.2 A in Equation 56 results in RCS = 0.14 Ω. A current sense value of 0.1 Ω is selected
for this design.
8.4.4.10 Setting Switch Current Limit
As shown in Equation 12, the switch current limit is determined by the switch current sense resistor, RIS, and the
switch current threshold. For VILIM(THR) = 250 mV and 1.2 × IL(PK) = 4 A, RIS ≤ 62 mΩ. A standard sense resistor
of RIS = 60 mΩ is selected in this design.
8.4.4.11 Slope Compensation
The recommended slope compensation magnitude can be obtained from Equation 13, VSLP ≥ 100 mV.
The VSLP can be programmed in Section 7.6.5. The ISLOPE =011 is selected, which corresponds with VSLP
=
150 mV.
8.4.4.12 Compensator Parameters
An integral compensator can be selected for this design. The CCOMP can be calculated from Equation 30
CCOMP = 100 nF
A proportional integral compensator can be used to achieve higher bandwidth and improved transient
performance. However, it is necessary to experimentally tune the compensator parameters over the entire
operating range to ensure stable operation.
8.4.4.13 Overvoltage Protection
The output Overvoltage level is programmed using RFB2 and RFB1. RFB2 can be calculated from the VOV(HYS) = 3
V and Equation 36:
Copyright © 2020 Texas Instruments Incorporated
72
Submit Document Feedback
Product Folder Links: TPS92682-Q1
TPS92682-Q1
SLUSCX8B – MARCH 2019 – REVISED JULY 2020
www.ti.com
RFB2 = 150 kΩ
RFB1 can be calculated from Equation 35 and the required value of VO(OV) = 40 V:
RFB1 = 4.75 kΩ
8.4.5 PWM Dimming Consideration
A 60-V, 2-A P-channel FET is used to achieve series FET PWM dimming.
Copyright © 2020 Texas Instruments Incorporated
Submit Document Feedback
73
Product Folder Links: TPS92682-Q1
TPS92682-Q1
SLUSCX8B – MARCH 2019 – REVISED JULY 2020
www.ti.com
8.4.6 Application Curves
The following waveform curves are for the Boost and the Buck-Boost LED drivers. Channel-1 of the TPS92682-
Q1 is configured as a Boost LED driver and the Channel-2 as a Buck-Boost.
CH1: Boost ILED
current
CH2: Buck-Boost
ILED current
CH3: Boost LED+
voltage (12×LED)
CH4: Buck-Boost
LED+ voltage
(3×LED)
CH1: Boost ILED
current
CH2: Buck-Boost
ILED current
CH3: Boost LED+
voltage (12×LED)
CH4: Buck-Boost
LED+ voltage
(3×LED)
Figure 8-11. PWM Dimming Transient with FM
Figure 8-10. PWM Dimming Transient
CH1: Boost ILED current
CH2: Boost switch current CH3: Boost LED+ voltage
sense voltage (12xLED)
CH2: Buck-Boost ILED
current
CH4: Buck-Boost switch
current sense voltage
CH3: Buck-Boost LED+
voltage (3×LED)
Figure 8-12. Boost PWM Dimming, Switch Current
Figure 8-13. Buck-Boost PWM Dimming, Switch
Current
CH1: Boost ILED
current
CH2: Buck-Boost
ILED current
CH3: Boost LED+
voltage (12×LED)
CH4: Buck-Boost
LED+ voltage
(6×LED)
CH1: Boost ILED current
CH3: Boost LED+ voltage CH4: COMP1-PIN voltage
(12×LED)
Figure 8-15. Boost LED Open Fault
Figure 8-14. Buck-Boost PWM Dimming, Switch
Current
Copyright © 2020 Texas Instruments Incorporated
74
Submit Document Feedback
Product Folder Links: TPS92682-Q1
TPS92682-Q1
SLUSCX8B – MARCH 2019 – REVISED JULY 2020
www.ti.com
CH3: FB2/OV2 PIN voltage
CH4: COMP2 PIN voltage
CH2: Buck-Boost ILED
current
CH3: FB2/OV2 PIN
voltage
CH4: Buck-Boost VSW
voltage
Figure 8-16. Buck-Boost LED Open Fault
Figure 8-17. Buck-Boost LED Open Fault
CH2: Buck-Boost ILED
current
CH3: Buck-Boost LED+
voltage
CH4: Buck-Boost VSW
voltage
CH1: Boost ILED current
CH3: Boost LED+ voltage CH4: Boost VSW voltage
Figure 8-19. Buck-Boost Output Short Fault
Figure 8-18. Boost Output Short Fault
12×LED, ILED = 560 mA
6×LED, ILED = 700 mA
Figure 8-20. Boost Conducted EMI Scan with FM
Figure 8-21. Buck-Boost Conducted EMI Scan with
FM
Copyright © 2020 Texas Instruments Incorporated
Submit Document Feedback
75
Product Folder Links: TPS92682-Q1
TPS92682-Q1
SLUSCX8B – MARCH 2019 – REVISED JULY 2020
www.ti.com
8.5 Typical Application CV Mode
Figure 8-22 shows the schematic for a two-phase Boost Constant Voltage (CV) regulator.
Figure 8-22. CV Mode Two-Phase BOOST
Copyright © 2020 Texas Instruments Incorporated
76
Submit Document Feedback
Product Folder Links: TPS92682-Q1
TPS92682-Q1
SLUSCX8B – MARCH 2019 – REVISED JULY 2020
www.ti.com
8.5.1 CV Design Requirements
Table 8-5 shows the design parameters for the CV two-phase boost.
Table 8-5. Design Parameters
PARAMETER
INPUT CHARACTERISTICS
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VIN
Input voltage range
Maximum input current
8
14
28
10
V
A
IIN(MAX)
OUTPUT CHARACTERISTICS
VO
Output voltage
50
V
A
IO(MAX)
PO(MAX)
Maximum output current
Maximum output power
2
100
W
SYSTEMS CHARACTERISTICS
PR
Peak Ratio: peak to average inductor current
1.4
at POUT(MAX), IL(PK)/IL
ΔvIN(PP)
ΔvOUT(PP)
VO(OV)
VOV(HYS)
fDM
Input voltage ripple
10
50
55
2.0
mV
mV
V
Output voltage ripple
Output Overvoltage protection threshold
Output Overvoltage protection hysteresis
Dither Modulation Frequency
Switching frequency
V
400
600
Hz
kHz
fSW
200
8.5.2 Detailed Design Procedure
In the following section, the detailed design procedure for the two-phase CV Boost is provided.
8.5.2.1 Calculating Duty Cycle
From Equation 9 and the input and output characteristics in Table 8-5, you can solve for DTYP, DMAX, and DMIN
.
DTYP = 0.72
DMAX = 0.84
DMIN = 0.44
8.5.2.2 Setting Switching Frequency
Assuming the division factor of 4 in Section 7.6.4 and from Equation 1, the RT value for the fSW = 200 kHz can
be obtained:
1012
RT
=
12.5ìSW DIVìfSW
(57)
RT = 100 kΩ
8.5.2.3 Setting Dither Modulation Frequency
The dither modulation frequency can be set using the Section 7.6.6 in Equation 2. For the dither modulation
frequency of less than 600 Hz, the FMFREQ must be set to 0101, which corresponds to a division factor of 1536
and sets FM = 521 Hz.
8.5.2.4 Inductor Selection
The inductor is selected to meet the peak-to-peak inductor current ripple at POUT(MAX). The inductor current
ripple, ΔiL-PP, can be obtained from the PR = IL(PK) / IL at POUT(MAX)
:
Copyright © 2020 Texas Instruments Incorporated
Submit Document Feedback
77
Product Folder Links: TPS92682-Q1
TPS92682-Q1
SLUSCX8B – MARCH 2019 – REVISED JULY 2020
www.ti.com
PO(MAX)
DiL-PP = 2ì PR -1 ì
(
)
V
IN
(58)
In Equation 58, it is important to note that the POUT(MAX) is the maximum output power per phase, 50 W in this
design.
The value of ΔiL-PP is calculated for typical input voltage, VIN(TYP). From Equation 38, the inductor L is calculated
to be:
L ≥ 17 µH
The value of L = 15 µH is selected for this application.
Ensure that the inductor saturation current rating is greater than 1.1 × IL(PK) = 6.5 A (IL(PK) is calculated with 90%
CV BOOST efficiency assumption).
8.5.2.5 Output Capacitor Selection
The output capacitors are required to attenuate the discontinuous output current of the BOOST converter, as
well as decreasing the output voltage undershoot and overshoot during load transient. The total required output
capacitor, COUT, can be found from Equation 41, where fSW is replaced with 2 × 200 kHz = 400 kHz for two-
phase operation.
COUT ≥ 84 µF
10 × 4.7-µF, 100-V ceramic capacitors are used in parallel, at the output of each phase, to achieve a combined
required output capacitance. It is important to note that the CV Boost output capacitor also plays an important
role in decreasing the output undershoot and overshoot voltage during load transient.
8.5.2.6 Input Capacitor Selection
The input capacitor is required to reduce switching noise conducted through the input terminal and to reduce the
input impedance of the CV Boost. Equation 43 is used to calculate the required capacitance of CIN ≥ 70 µF to
limit peak-to-peak input voltage ripple, ΔvIN(PP), to 10 mV.
Eight 10-µF, 50-V ceramic capacitors are used in parallel to achieve a combined input capacitance of 80 µF. As
shown in Figure 8-22, an additional 33-µF, 50-V electrolytic capacitor and a 1-µH inductor are also used at the
input terminal. The electrolytic capacitor is used to further decrease overshoot and undershoot during load
transient. The input inductor is used to decrease the switching noise and improve EMI performance.
8.5.2.7 Main N-Channel MOSFET Selection
Ensure that the MOSFET ratings exceed the maximum output voltage and RMS switch current.
VDS = VO(OV) × 1.1 = 61 V
The maximum RMS switch current can be found from Equation 11, where PO(MAX) is replaced by half of the total
maximum output power for two-phase operation.
An N-channel MOSFET with a voltage rating of 100 V and a current rating of more than 7 A is required for this
design.
8.5.2.8 Rectifier Diode Selection
Select a diode with a reverse breakdown voltage, VD(BR), greater than or equal to MOSFET drain-to-source
voltage, VDS, for reliable performance.
The DC current rating of the diode rectifier for the Boost LED driver must be greater than half of the total output
current, IO(MAX) = 2 A.
8.5.2.9 Programming VOUT
The output voltage VOUT can be programmed using the feedback resistors and by writing an 8-bit value to
Section 7.6.8 and Section 7.6.9. Equation 26 shows the relation between the programmed VOUT, the register
CHxIADJ, and the feedback resistors.
Copyright © 2020 Texas Instruments Incorporated
78
Submit Document Feedback
Product Folder Links: TPS92682-Q1
TPS92682-Q1
SLUSCX8B – MARCH 2019 – REVISED JULY 2020
www.ti.com
It is recommended to set the ratio of the feedback resistors RFB2 / RFB1 such that for the maximum CHxIADJ =
255, VOUT does not increase above the maximum desired limit (for example, VO(LIM) = 60 V).
In this design for VO(LIM) = 60 V, RFB2 / RFB1 = 24.
In this design, CHxIADJ is set to the value of 212 to achieve VO = 50 V, for the RFB2 / RFB1 = 24.
8.5.2.10 Setting Switch Current Limit
As shown in Equation 12, the switch current limit is determined by the switch current sense resistor, RIS, and the
switch current threshold. For VILIM(THR) = 100 mV and IL(PK) = 6 A, RIS ≤ 16 mΩ. A standard sense resistor of RIS
= 10 mΩ is selected for this application.
The maximum power loss introduced by RIS can be found from Equation 59, to be 0.45 W.
2
PRIS-Loss = RIS ì I
Q(RMS)
(59)
8.5.2.11 Slope Compensation
The recommended slope compensation magnitude can be obtained from Equation 13, VSLP ≥ 100 mV.
In CV mode for RIS values smaller than 20 mΩ, it is recommended to use VSLP ≥ 250 mV for better noise
immunity.
The VSLP can be programmed in Section 7.6.5. The ISLOPE =101 is selected, which corresponds with VSLP
=
250 mV.
8.5.2.12 Compensator Parameters
Proportional-Integral Compensator is selected for this design. The compensator component can be obtained
from Equation 50, Equation 51 and Equation 52:
CCOMP = 33 nF
CHF = 100 pF
RCOMP = 15 kΩ
It is noted that the above compensator components are fine-tuned to provide improved load transient
performance.
8.5.2.13 Overvoltage Protection
In CV mode, the output Overvoltage level is set in Section 7.6.23 as a percentage above the programmed
regulated value of VOUT. For VO(OV) = 55 V, Section 7.6.23 is set to 10%, which corresponds with CHxOV = 100.
RFB2 can be calculated from the VOV(HYS) = 2 V and from Equation 53:
RFB2 = 100 kΩ
RFB1 can be calculated from the ratio of RFB2 / RFB1 = 24, found in the VOUT setting.
RFB1 = 4.12 kΩ
Copyright © 2020 Texas Instruments Incorporated
Submit Document Feedback
79
Product Folder Links: TPS92682-Q1
TPS92682-Q1
SLUSCX8B – MARCH 2019 – REVISED JULY 2020
www.ti.com
8.5.3 Application Curves
The following waveform curves are for the two-phase CV Boost.
CH1: Phase-1 VSW CH2: Phase-2 VSW CH3: CV Boost
voltage
voltage
VOUT
CH2: IOUT, 0.2 A to 2 A
transient
CH3: CV Boost VOUT
Figure 8-23. Normal Operation, POUT = 50 W
Figure 8-24. Load Transient
CH1: VCOMP1 pin CH3: CV Boost VOUT
CH1: VCOMP1 pin CH3: CV Boost VOUT
Figure 8-25. Start-up, SOFTSTART = 0111
Figure 8-26. Start-up, SOFTSTART = 1111
Figure 8-27. CV Conducted EMI Scan, fSW = 100
kHz
Figure 8-28. CV Conducted EMI Scan, fSW = 200
kHz
Copyright © 2020 Texas Instruments Incorporated
80
Submit Document Feedback
Product Folder Links: TPS92682-Q1
TPS92682-Q1
SLUSCX8B – MARCH 2019 – REVISED JULY 2020
www.ti.com
9 Power Supply Recommendations
This device is designed to operate from an input voltage supply range between 4.5 V and 65 V. The input can be
a car battery or another pre-regulated power supply. If the input supply is located more than a few inches from
the TPS92682-Q1 device, additional bulk capacitance or an input filter can be required in addition to the ceramic
bypass capacitors to address noise and EMI concerns.
Copyright © 2020 Texas Instruments Incorporated
Submit Document Feedback
81
Product Folder Links: TPS92682-Q1
TPS92682-Q1
SLUSCX8B – MARCH 2019 – REVISED JULY 2020
www.ti.com
10 Layout
10.1 Layout Guidelines
•
The performance of the switching regulator depends as much on the layout of the PCB as the component
selection. Following a few simple guidelines maximizes noise rejection and minimizes the generation of EMI
within the circuit.
•
Discontinuous currents are the most likely to generate EMI. Therefore, take care when routing these paths.
The main path for discontinuous current in the device using a buck regulator topology contains the input
capacitor, CIN, the recirculating diode, D, the N-channel MOSFET, Q1, and the sense resistor, RIS. In the
TPS92682-Q1 device using a boost regulator topology, the discontinuous current flows through the output
capacitor COUT, diode, D, N-channel MOSFET, Q1, and the current sense resistor, RIS. When using a buck-
boost regulator topology, implement the layout of both input and output loops carefully. Make sure that these
loops are as small as possible. In order to minimize parasitic inductance, ensure that the connection between
all the components are short and thick. In particular, make the switch node (where L, D, and Q1 connect) just
large enough to connect the components. To minimize excessive heating, large copper pours can be placed
adjacent to the short current path of the switch node.
•
Route the CSP and CSN together with kelvin connections to the current sense resistor with traces as short as
possible. If needed, use common mode and differential mode noise filters to attenuate switching and diode
reverse recovery noise from affecting the internal current sense amplifier.
•
•
Because the COMPx, ISPx, ISNx, and FBx pins are all high-impedance inputs that may couple external
noise, ensure that the loops containing these nodes are minimized whenever possible.
In some applications, the LED or LED array can be far away from the TPS92682-Q1 device, or on a separate
PCB connected by a wiring harness. When an output capacitor is used and the LED array is large or
separated from the rest of the regulator, place the output capacitor close to the LEDs to reduce the effects of
parasitic inductance on the AC impedance of the capacitor.
•
The TPS92682-Q1 has an exposed thermal pad to aid power dissipation. Adding several vias under the
exposed pad helps conduct heat away from the device. The junction-to-ambient thermal resistance varies
with application. The most significant variables are the area of copper in the PCB and the number of vias
under the exposed pad. The integrity of the solder connection from the device exposed pad to the PCB is
critical. Excessive voids greatly decrease the thermal dissipation capacity.
10.2 Layout Example
Figure 10-1 shows a layout example for a CC boost LED driver, which is connected to the channel-1 of the
TPS92682-Q1.
Copyright © 2020 Texas Instruments Incorporated
82
Submit Document Feedback
Product Folder Links: TPS92682-Q1
TPS92682-Q1
SLUSCX8B – MARCH 2019 – REVISED JULY 2020
www.ti.com
VIN
GND
LED+
LED-
VIN
EN
ISN1
ISP1
PWM1
PWM2
SSN
GATE1
VCC
PGND
GATE2
ISP2
SCK
GATE2
ISP2
MISO
MOSI
ISN2
FB2/OV2
CSP2
CSN2
PDRV2
Figure 10-1. CC Boost Layout Example
Copyright © 2020 Texas Instruments Incorporated
Submit Document Feedback
83
Product Folder Links: TPS92682-Q1
TPS92682-Q1
SLUSCX8B – MARCH 2019 – REVISED JULY 2020
www.ti.com
11 Device and Documentation Support
11.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
11.2 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
11.3 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
11.5 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2020 Texas Instruments Incorporated
84
Submit Document Feedback
Product Folder Links: TPS92682-Q1
PACKAGE OPTION ADDENDUM
www.ti.com
22-Feb-2021
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPS92682QDAPRQ1
ACTIVE
HTSSOP
DAP
32
2000 RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 125
TPS92682Q
TPS92682QRHBRQ1
TPS92682QRHMRQ1
PREVIEW
ACTIVE
VQFN
VQFN
RHB
RHM
32
32
2000 RoHS & Green
3000 RoHS & Green
NIPDAU
Level-3-260C-168 HR
Level-3-260C-168 HR
-40 to 125
-40 to 125
92682Q
NIPDAUAG
TPS
92682Q
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
22-Feb-2021
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
22-Jul-2020
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS92682QDAPRQ1 HTSSOP
TPS92682QRHMRQ1 VQFN
DAP
32
32
2000
3000
330.0
330.0
24.4
12.4
8.8
5.3
11.8
5.3
1.8
1.1
12.0
8.0
24.0
12.0
Q1
Q2
RHM
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
22-Jul-2020
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TPS92682QDAPRQ1
TPS92682QRHMRQ1
HTSSOP
VQFN
DAP
32
32
2000
3000
367.0
367.0
367.0
367.0
45.0
35.0
RHM
Pack Materials-Page 2
PACKAGE OUTLINE
RHM0032C
VQFNP - 0.9 mm max height
SCALE 3.000
PLASTIC QUAD FLATPACK - NO LEAD
5.1
4.9
B
A
0.05
0.00
(0.09)
PIN 1 ID
5.1
4.9
DETAIL A
DETAIL
SCALE 20.000
A
TYPICAL
(
4.75)
(0.15)
(0.15)
DETAIL
B
S
C
A
L
E
2
0
.
0
0
0
DETAIL B
TYPICAL
C
0.9 MAX
SEATING PLANE
0.08 C
(0.2)
SEE DETAIL A
3.2 0.1
SYMM
SEE DETAIL B
4X (45 X 0.6)
9
16
8
17
EXPOSED
THERMAL PAD
SYMM
33
4X
3.5
1
24
28X 0.5
0.30
0.18
32X
25
PIN 1 ID
(OPTIONAL)
32
0.1
C B A
C
0.5
32X
0.05
0.3
4224724/A 12/2018
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
RHM0032C
VQFNP - 0.9 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(
3.2)
(1.13) TYP
(0.785)
TYP
32
25
32X (0.6)
1
24
32X (0.25)
(0.785) TYP
SYMM
33
(1.13) TYP
(4.8)
28X (0.5)
17
8
(
0.2) VIA
TYP
9
16
SYMM
(4.8)
(R0.05)
TYP
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
0.05 MIN
ALL AROUND
0.05 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
EXPOSED METAL
EXPOSED METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4224724/A 12/2018
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
RHM0032C
VQFNP - 0.9 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
SYMM
(1.13 TYP)
32
25
32X (0.6)
1
24
32X (0.25)
(R0.05)
TYP
(1.13)
TYP
SYMM
33
(4.8)
28X (0.5)
17
8
METAL
TYP
9
16
9X ( 0.93)
(4.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 33:
75% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:18X
4224724/A 12/2018
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
GENERIC PACKAGE VIEW
DAP 32
8.1 x 11, 0.65 mm pitch
PowerPADTM TSSOP - 1.2 mm max height
PLASTIC SMALL OUTLINE
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4225303/A
www.ti.com
PACKAGE OUTLINE
TM
DAP0032F
PowerPAD TSSOP - 1.2 mm max height
S
C
A
L
E
1
.
5
0
0
PLASTIC SMALL OUTLINE
8.3
7.9
TYP
A
PIN 1 ID AREA
30X 0.65
32
1
11.1
10.9
NOTE 3
2X
9.75
16
B
17
0.30
32X
0.19
6.2
6.0
0.1 C
0.1
C A B
SEATING PLANE
(0.15) TYP
C
SEE DETAIL A
4.11
3.29
EXPOSED
THERMAL PAD
0.25
4.06
3.16
1.2 MAX
GAGE PLANE
0.75
0.50
0.15
0.05
2X (0.9)
NOTE 5
0 - 8
2X (0.15)
NOTE 5
DETAIL A
TYPICAL
4226056/A 07/2020
PowerPAD is a trademark of Texas Instruments.
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. Reference JEDEC registration MO-153.
5. Features may differ and may not be present.
www.ti.com
EXAMPLE BOARD LAYOUT
TM
DAP0032F
PowerPAD TSSOP - 1.2 mm max height
PLASTIC SMALL OUTLINE
(5.2)
NOTE 9
SOLDER MASK
DEFINED PAD
(4.11)
32X (1.5)
SYMM
SEE DETAILS
1
32
32X (0.45)
30X (0.65)
(11)
NOTE 9
SYMM
(4.06)
(1.2 TYP)
(R0.05) TYP
(
0.2) TYP
VIA
16
17
(0.65) TYP
(1.3) TYP
(7.5)
METAL COVERED
BY SOLDER MASK
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
METAL UNDER
SOLDER MASK
SOLDER MASK
METAL
SOLDER MASK
OPENING
OPENING
EXPOSED METAL
EXPOSED METAL
0.05 MIN
ALL AROUND
0.05 MAX
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
NOT TO SCALE
4226056/A 07/2020
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
8. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
numbers SLMA002 (www.ti.com/lit/slma002) and SLMA004 (www.ti.com/lit/slma004).
9. Size of metal pad may vary due to creepage requirement.
www.ti.com
EXAMPLE STENCIL DESIGN
TM
DAP0032F
PowerPAD TSSOP - 1.2 mm max height
PLASTIC SMALL OUTLINE
(4.11)
BASED ON
0.125 THICK
STENCIL
32X (1.5)
1
32
32X (0.45)
30X (0.65)
(4.06)
BASED ON
SYMM
0.125 THICK
STENCIL
SEE TABLE FOR
DIFFERENT OPENINGS
FOR OTHER STENCIL
THICKNESSES
17
16
METAL COVERED
BY SOLDER MASK
SYMM
(7.5)
SOLDER PASTE EXAMPLE
EXPOSED PAD
100% PRINTED SOLDER COVERAGE BY AREA
SCALE:8X
STENCIL
THICKNESS
SOLDER STENCIL
OPENING
0.1
4.60 X 4.54
4.11 X 4.06 (SHOWN)
3.75 X 3.71
0.125
0.15
0.175
3.47 X 3.43
4226056/A 07/2020
NOTES: (continued)
10. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
11. Board assembly site may have different recommendations for stencil design.
www.ti.com
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you
permission to use these resources only for development of an application that uses the TI products described in the resource. Other
reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third party
intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims, damages,
costs, losses, and liabilities arising out of your use of these resources.
TI’s products are provided subject to TI’s Terms of Sale (https:www.ti.com/legal/termsofsale.html) or other applicable terms available either
on ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s
applicable warranties or warranty disclaimers for TI products.IMPORTANT NOTICE
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2021, Texas Instruments Incorporated
相关型号：
©2020 ICPDF网 联系我们和版权申明