TPS9901TPZPRQ1 [TI]
用于汽车外部照明的 DLP® 系统管理与照明控制器
| PZP | 100 | -40 to 105;
| 型号： | TPS9901TPZPRQ1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 用于汽车外部照明的 DLP® 系统管理与照明控制器 | PZP | 100 | -40 to 105 控制器 |
| 文件： | 总52页 (文件大小：3005K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPS99001-Q1
DLPS133A – JUNE 2019 – REVISED JANUARY 2021
TPS99001-Q1 System Management Controller
1 Features
3 Description
•
•
Qualified for automotive applications
The TPS99001-Q1 system management controller is
part of the DLP5531-Q1 chipset, which also includes
the DLPC230-Q1 DMD display controller.
AEC-Q100 qualified with the following results:
– Temperature grade 2: –40°C to 105°C ambient
operating temperature
– Device HBM ESD classification level 2
– Device CDM ESD classification level C4B
Automotive system management device for DLP®
products:
An integrated DMD high-voltage regulator supplies
DMD mirror reference voltages, meeting the required
tight tolerances. The power supply sequencer and
monitor provide robust coordination of power-up and
power-down events for the entire chipset.
•
– Advanced power monitoring, sequencing, and
protection circuits
– Two die temperature monitors, MCU external
watchdog timer, clock frequency monitor
– SPI port with parity, checksum, and password
register protection
– Second SPI port for independent system
monitoring
On-chip DMD mirror voltage regulators
– Generates +16-V, +8.5-V and –10-V DMD
control voltages
The TPS99001-Q1 controller integrates a 12-bit ADC
as one of the core components of the control system.
The ADC is capable of automatic sampling up to 63
events per video frame.
Advanced system status monitoring circuits provide
real-time visibility into display sub-system operational
condition, including two processor watchdog circuits,
two die temperature monitors, comprehensive supply
monitoring for overvoltage and undervoltage
detection, checksum and password register protection
with byte-level parity on SPI bus transactions, and
other built-in test functions.
•
•
12-bit ADC with up to 63 time sequence samples
per frame
Device Information (1)
2 Applications
PART NUMBER
PACKAGE
BODY SIZE (NOM)
TPS99001-Q1
HTQFP (100)
14.00 mm × 14.00 mm
•
Automotive advanced lighting applications (high
resolution headlight)
Adaptive driving beam (ADB)
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
•
Typical Standalone System
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS99001-Q1
DLPS133A – JUNE 2019 – REVISED JANUARY 2021
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Table of Contents
1 Features............................................................................1
2 Applications.....................................................................1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications................................................................ 10
6.1 Absolute Maximum Ratings...................................... 10
6.2 ESD Ratings............................................................. 10
6.3 Recommended Operating Conditions.......................11
6.4 Thermal Information..................................................11
6.5 Electrical Characteristics - Analog to Digital
Converter.....................................................................12
6.6 Electrical Characteristics - Voltage Regulators.........13
6.7 Electrical Characteristics - Temperature and
Voltage Monitors..........................................................14
6.8 Electrical Characteristics - Current Consumption..... 15
6.9 Power-Up Timing Requirements...............................16
6.10 Power-Down Timing Requirements........................ 18
6.11 Timing Requirements - Sequencer Clock................20
6.12 Timing Requirements - Host / Diagnostic Port
7.1 Overview...................................................................23
7.2 Functional Block Diagram.........................................24
7.3 Feature Description...................................................24
7.4 Device Functional Modes..........................................31
7.5 Register Maps...........................................................33
8 Application and Implementation..................................36
8.1 Application Information............................................. 36
8.2 Typical Applications.................................................. 36
9 Power Supply Recommendations................................39
9.1 TPS99001-Q1 Power Supply Architecture................39
9.2 TPS99001-Q1 Power Outputs.................................. 39
9.3 Power Supply Architecture........................................39
10 Layout...........................................................................40
10.1 Layout Guidelines................................................... 40
11 Device and Documentation Support..........................43
11.1 Device Support........................................................43
11.2 Receiving Notification of Documentation Updates..43
11.3 Support Resources................................................. 43
11.4 Trademarks............................................................. 43
11.5 Electrostatic Discharge Caution..............................43
11.6 Glossary..................................................................43
12 Mechanical, Packaging, and Orderable
SPI Interface................................................................21
6.13 Timing Requirements - ADC Interface.................... 22
6.14 Switching Characteristics........................................22
7 Detailed Description......................................................23
Information.................................................................... 44
4 Revision History
Changes from Revision * (June 2019) to Revision A (January 2021)
Page
First public release of data sheet........................................................................................................................1
Updated the numbering format for tables, figures, and cross-references throughout the document..................1
•
•
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5 Pin Configuration and Functions
RSVD
RSVD
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
DMD_VBIAS
DMD_VOFFSET
VSS_DRVR
RSVD
AVSS
VIN_LDOA_3P3
VLDOA_3P3
VSSL_ADC
LS_SENSE_N
LS_SENSE_P
VSSL_ADC
ADC_IN1
ADC_IN2
VSSL_ADC
ADC_IN3
VSSL_ADC
ADC_IN4
VSSL_ADC
ADC_IN5
ADC_IN6
ADC_IN7
ADC_VREF
V3P3V
RSVD
RSVD
RSVD
RSVD
DRVR_PWR
DMUX1
DMUX0
RSVD
RSVD
TPS99001-Q1
RSVD
VDD_IO
VSS_IO
SPI2_CLK
SPI2_SS_Z
SPI2_DOUT
SPI2_DIN
SPI1_DIN
SPI1_DOUT
SPI1_SS_Z
SPI1_CLK
DVDD
V1P8V
V1P1V
PBKG
AVSS
Figure 5-1. PZP Package
100-Pin HTQFP
Top View
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Table 5-1. Pin Functions - Initialization, Clock, and Diagnostics
PIN
TYPE
DESCRIPTION
NO.
NAME
WD1
6
7
8
9
I
Watchdog interrupt channel 1
Watchdog interrupt channel 2
WD2
I
PARK_Z
RESET_Z
O
O
DMD mirror parking signal (active low)
Reset output to the DLPC230-Q1. TPS99001-Q1 controlled.
Interrupt output signal to DLPC230-Q1 (open drain). Recommended to pull up to the
DLPC230-Q1 3.3-V rail controlled by the TPS99001-Q1's ENB_3P3V signal.
10
INT_Z
O
11
16
17
40
41
57
61
PROJ_ON
I
Input signal to enable/disable the IC and DLP projector
PWM shadow latch control; indicates a start of sequence
Sequencer clock
SEQ_START
SEQ_CLK
DMUX0
I
I
O
O
O
O
Digital test point output
DMUX1
Digital test point output
AMUX1
Analog test mux output 1
AMUX0
Analog test mux output 0
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Table 5-2. Pin Functions - Power and Ground
PIN
TYPE
DESCRIPTION
NO.
NAME
VSS_IO
VDD_IO
DVSS
13, 35
GND
POWER
GND
Ground connection for digital IO interface
14, 36
3.3-V power input for IO rail supply
24
Digital core ground return
25, 60, 75, 99
PBKG
GND
Substrate tie and ESD ground return
3.3-V power input for digital core supply
6-V power input
26
42
48
49
50
DVDD
POWER
POWER
GND
DRVR_PWR
VSS_DRVR
Ground connection for driver power
DMD_VOFFSET
DMD_VBIAS
POWER
POWER
VOFFSET output rail. Connect a 1-μF ceramic capacitor to ground
VBIAS output rail. Connect a 0.47-μF ceramic capacitor to ground
VRESET output rail. Connect a 1-μF ceramic capacitor to ground. Connect to
DRST_HS_IND through external diode. Connect anode of diode to DMD_VRESET.
51
DMD_VRESET
POWER
53
DRST_PGND
VIN_DRST
VSS_DRST
AVDD
GND
POWER
GND
Power ground for DMD power supply. Connect to ground plane
6-V input for DMD power supply
55
56
Ground supply for DMD power supply
3.3-V power supply input for analog circuit
Unused. Leave open or unconnected.
Filter cap interface for 5-V LDO
59
POWER
POWER
POWER
POWER
GND
63
VLDOT_M8
VLDOT_5V
VIN_LDOT_5V
GND_LDO
64
65
6-V power input for 5-V LDO
66
Power ground return for LDO
67
VIN_LDOT_3P3V
VLDOT_3P3V
VSS_TIA2
POWER
POWER
GND
6-V power input for 3.3-V LDO
68
Filter cap interface for 3.3-V LDO
Ground
71
72
VSS_TIA1
GND
Ground
78, 100
AVSS
GND
Analog ground
79
VIN_LDOA_3P3
VLDOA_3P3
VSSL_ADC
ADC_VREF
POWER
POWER
GND
6-V power input for dedicated ADC interface 3.3-V LDO supply
Dedicated ADC interface 3.3-V LDO filter cap output
External ADC channel bondwire and lead frame isolation ground
ADC reference voltage output
80
81, 84, 87, 89, 91
95
POWER
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Table 5-3. Pin Functions - Power Supply Management
PIN
TYPE
DESCRIPTION
NO.
NAME
1
2
3
ENB_1P1V
ENB_1P8V
ENB_3P3V
O
O
O
External 1.1-V buck enable. 3.3-V output.
External 1.8-V buck enable. 3.3-V output.
External 3.3-V buck enable. 3.3-V output
Connection for the DMD power supply inductor (10 μH). Connect a 330-pF, 50-V
capacitor to ground. X7R recommended.
52
54
58
DRST_LS_IND
DRST_HS_IND
VMAIN
ANA
ANA
I
Connection for the DMD power supply inductor (10 μH)
Main intermediate voltage monitor input. Use external resistor divider to set voltage
input for brownout monitoring.
62
96
97
98
VIN_LDOT_M8
V3P3V
O
I
Unused. Leave open or unconnected.
External 3.3-V buck voltage monitor input
External 1.8-V buck voltage monitor input
External 1.1-V buck voltage monitor input
V1P8V
I
V1P1V
I
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Table 5-4. Pin Functions - Reserved Pins
PIN
TYPE
DESCRIPTION
NO.
12
NAME
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
O
Reserved. Leave unconnected.
Reserved. Leave unconnected.
Reserved. Connect to ground.
Reserved. Connect to ground.
Reserved. Connect to ground.
Reserved. Connect to ground.
Reserved. Connect to ground.
Reserved. Connect to ground.
Reserved. Connect to ground
Reserved. Leave unconnected.
Reserved. Leave unconnected.
Reserved. Leave unconnected.
Reserved. Leave unconnected.
Reserved. Leave unconnected.
Reserved. Leave unconnected.
Reserved. Leave unconnected.
Reserved. Leave unconnected.
Reserved. Leave unconnected.
Reserved. Leave unconnected.
Reserved. Leave unconnected.
Reserved. Connect to ground.
Reserved. Connect to ground.
15
O
18
I
19
I
20
I
21
I
22
I
I
23
37
I
38
O
O
O
O
O
O
O
O
I
39
43
44
45
46
47
69
70
73
I
74
O
ANA
ANA
76
77
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Table 5-5. Pin Functions - Serial Peripheral Interfaces
PIN
TYPE
DESCRIPTION
NO.
NAME
27
28
29
30
31
32
33
34
SPI1_CLK
I
I
SPI control interface (DLPC230-Q1 master, TPS99001-Q1 slave), clock input
SPI1_SS_Z
SPI1_DOUT
SPI1_DIN
SPI control interface (DLPC230-Q1 master, TPS99001-Q1 slave), chip select (active low)
SPI control interface (DLPC230-Q1 master, TPS99001-Q1 slave), transmit data output
SPI control interface (DLPC230-Q1 master, TPS99001-Q1 slave), receive data input
SPI diagnostic port (slave), receive data input. For read-only monitoring.
SPI diagnostic port (slave), transmit data output. For read-only monitoring.
SPI diagnostic port (slave), chip select (active low). For read-only monitoring.
SPI diagnostic port (slave), clock input. For read-only monitoring.
O
I
SPI2_DIN
I
SPI2_DOUT
SPI2_SS_Z
SPI2_CLK
O
I
I
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Table 5-6. Pin Functions - Analog to Digital Converter
PIN
TYPE
DESCRIPTION
NO.
NAME
4
ADC_MISO
ADC_MOSI
LS_SENSE_N
LS_SENSE_P
ADC_IN1
O
I
ADC 2-wire interface - data output. DLPC230-Q1 master, TPS99001-Q1 slave.
ADC 2-wire interface - data input. DLPC230-Q1 master, TPS99001-Q1 slave.
Low side current sense ADC negative input, see Table 7-1
Low side current sense ADC positive input, see Table 7-1
External ADC channel 1, see Table 7-1
5
82
83
85
86
88
90
92
93
94
I
I
I
ADC_IN2
I
External ADC channel 2, see Table 7-1
ADC_IN3
I
External ADC channel 3, see Table 7-1
ADC_IN4
I
External ADC channel 4, see Table 7-1
ADC_IN5
I
External ADC channel 5, see Table 7-1
ADC_IN6
I
External ADC channel 6, see Table 7-1
ADC_IN7
I
External ADC channel 7, see Table 7-1
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
–0.3
–0.3
–0.3
–0.1
MAX
4
UNIT
VDD_IO to VSS_IO
DVDD to DVSS
4
AVDD to DVSS
4
All "VSS" to other "VSS" (grounds)
0.1
All digital input signals to ground (WD1, WD2, ADC_MOSI,
PROJ_ON, SEQ_START, SEQ_CLK, SPI1_CLK, SPI1_DIN,
SPI1_SS, SPI2_DIN, SPI2_CLK, SPI2_SS, EXT_SMPL)
–0.3
3.6
DRVR_PWR to ground
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–40
7.5
7.5
5
VIN_LDO_5V
Input
V
V3P3V to ground
voltage
V1P8V to ground
5
V1P1V to ground
5
VIN_LDOA_3P3 to ground
VIN_LDOT_3P3 to ground
ADC_IN(7:1) to ground
DRST_LS_IND to DRST_PGND
VIN_DRST to ground
VMAIN
7.5
7.5
3.6
27
7.5
7.5
7.5
130
150
Outputs
INT_Z
V
Operating junction temperature, TJ
Storage temperature, Tstg
°C
°C
–65
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
6.2 ESD Ratings
VALUE
±2000
±500
UNIT
Human-body model (HBM), per AEC Q100-002(1)
Electrostatic
discharge
V(ESD)
All pins
Corner pins
V
Charged-device model (CDM), per AEC
Q100-011
±750
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
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6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
TEMPERATURE
TA
Operating ambient temperature(1)
Operating junction temperature
–40
–40
105
125
°C
°C
TJ
VOLTAGE
VDD_IO
DVDD
IO 3.3-V voltage supply
Digital 3.3-V supply
3
3
3.3
3.3
3.3
3.6
3.6
3.6
1.6
7
V
V
V
V
V
V
V
V
V
AVDD
Analog 3.3-V supply
3
ADC
ADC(7:1) inputs
0.1
5.5
5.5
5.5
5.5
3
VIN_DRST
VIN_LDOT_5V
DMD reset regulator input
Power supply input to 5-V LDO
6
6
6
6
6
7
VIN_LDOA_3P3V Power supply input to 3.3-V ADC LDO
VIN_LDOT_3P3V Power supply input to 3.3-V LDO
7
7
DRVR_PWR
Gate driver power supply
7
(1) –40°C to 105°C ambient, free air convection, AEC Q100 grade 2.
6.4 Thermal Information
TPS99001-Q1
THERMAL METRIC(1) (2)
PZP (HTQFP)
UNIT
100 PINS
6.9
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
8.3
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
0.1
ψJB
8.2
RθJC(bot)
0.4
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report (SPRA953).
(2) Operating ambient temperature is dependent on system thermal design. Operating junction temperature may not exceed its specified
range across ambient temperature conditions.
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6.5 Electrical Characteristics - Analog to Digital Converter
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
12-BIT ADC(1)
VINPUT
INL
Input range(2)
0.1
–4
1.6
4
V
LSB
LSB
bits
µs
Integral non-linearity
Differential non-linearity
Effective number Of bits
S/H sampling period
S/H delay before conversion starts
S/H holding period
Over valid input range VINPUT
DNL
–2.5
10
2.5
ENOB
tSAMPLE
tDELAY
12
0.4
0.4
5.2
12.8
2.8
µs
tSHOLD
tCONV
102.4
102.4
245
µs
Conversion period
µs
ADC reference voltage is doubled
to 1.6 V
VREF
Measurement reference
0.784
0.8
0.816
V
Offset
–20
2
20
2
LSB
VOFFS
Gain error
"ADC_IN(7:1) inputs
%FSR
(1) ADC specifications refer to ADC core behavior, presume ideal clocks and IC input power conditions, unless otherwise noted.
(2) Results in invalid ADC codes below 256.
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6.6 Electrical Characteristics - Voltage Regulators
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VOFFSET REGULATOR
VOUT
IOUT
Output voltage
Across load conditions
8.25
8.5
8.75
16.3
V
Output current(2)
0.1(4)
mA
Powergood threshold, VOUT
rising
VPGTHRESHR
VPGTHRESHF
86%
Powergood threshold, VOUT
falling
66%
1
COUT
Output capacitor(3)
µF
µs
TDISC
Discharge time
COUT = 1 µF
260
VBIAS REGULATOR
VOUT
IOUT
Output voltage
15.5
16
16.5
1.5
V
Output current(2)
0.1(4)
mA
Powergood threshold, VOUT
rising
VPGTHRESHR
VPGTHRESHF
86%
Powergood threshold, VOUT
falling
66%
0.47
COUT
TDISC
Output capacitor(3)
µF
µs
Discharge time
COUT = 0.47 µF
260
VRESET REGULATOR
VOUT
Output voltage
–10.5
–17.6
–10
–9.5
V
IOUT
Output current(1) (2)
Powergood threshold
Output capacitor(3)
Discharge time
–0.1(4)
mA
VPGTHRESHR
COUT
80%
1
µF
µs
TDISC
COUT = 1 µF
260
(1) VRESET current supplies both DMD and negative 8-V LDO.
(2) VOFFSET, VBIAS, and VRESET are designed to supply the DMD and negative 8-V LDO only, and should not be connected to
additional loads.
(3) The capacitance value of some ceramic capacitor types can diminish drastically depending on the applied DC voltage and
temperature. TI recommends X7R dielectric capacitors to minimize capacitance loss over voltage bias and temperatures. Using a
higher voltage rated part and/or a larger package size also helps minimize the capacitance reduction at the applied DC voltage. Refer
to the DLP5531Q1EVM for suggested components.
(4) Pull down resistors required to meet minimum current requirement.
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6.7 Electrical Characteristics - Temperature and Voltage Monitors
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
TEMPERATURE MONITOR
TEMPWARN
TEMPEMRG
Thermal warning threshold
Junction temperature
135
150
°C
°C
Thermal emergency threshold Junction temperature
1.1-V SUPPLY MONITOR
VTRIPN
Negative trip threshold
Negative going only
0.95
0.98
2%
1.01
V
Positive going threshold,
amount higher than negative trip
voltage
VTRIPHYST
Hysteresis
Size of glitch ignored (no reset)
with 2% overdrive
tGLITCH
Glitch suppression
20
1000
µs
V
1.8-V SUPPLY MONITOR
VTRIPN
Negative trip threshold
Negative going only
1.552
1.6
2%
1.648
Positive going threshold,
amount higher than negative trip
voltage
VTRIPHYST
Hysteresis
Size of glitch ignored (no reset)
with 2% overdrive
tGLITCH
Glitch suppression
20
1000
3.03
µs
V
3.3-V SUPPLY MONITOR
VTRIPN
Negative trip threshold
Negative going only
2.852
2.93
2%
Positive going threshold,
amount higher than negative trip
voltage
VTRIPHYST
Hysteresis
Size of glitch ignored (no reset)
with 2% overdrive
tGLITCH
Glitch suppression
20
1000
µs
VMAIN SYSTEM INPUT SUPPLY MONITOR
External resistor divider used to
translate VMAIN
VMAINTHRSH
tMAINGLITCH
VMAIN threshold
1.2125
20
1.25
1.2875
1000
V
VMAIN glitch suppression
At 2% overdrive
µs
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6.8 Electrical Characteristics - Current Consumption
PARAMETER
TEST CONDITIONS
MIN
TYP(1)
MAX(2)
UNIT
SUM OF 3.3-V SUPPLY PINS: DVDD, VDD_IO, AND AVDD
System off
System on
PROJ_ON low
1.5
3.5
2
4
mA
mA
Display ON state
SUM OF 6-V SUPPLY PINS: DRVR_PWR, VIN_DRST, VIN_LDOT_5V, VIN_LDOT_3P3V, AND VIN_LDOA_3P3V
System off
PROJ_ON low
1
2
mA
mA
System on(3)
Display ON state
98
119
(1) Typical measurements performed at 25°C and nominal voltage.
(2) Measurements taken at –40°C, 25°C, and 105°C. 3.3-V inputs measured at 3 V, 3.3 V, and 3.6 V. 6-V inputs measured at 5.5 V, 6 V,
and 7 V. The maximum current draw of all these conditions is shown.
(3) This number represents the current at the input to the TPS99001-Q1 when the DMD voltage rails output the maximum current as listed
in the respective sections of this data sheet. This number is the combination of the measured current when the DMD voltage regulator
is unloaded (35-mA typical, 56-mA max) and the estimated current draw on the 6-V supply when the DMD voltage regulator outputs
the maximum current (63 mA). The estimated current draw is calculated by the equation I6V = [(16 / 6) × IVBIAS + (8.5 / 6) × IVOFFSET
(–10 / 6) × IVRESET] / η where η = 0.9. In order to calculate the power dissipation of the TPS99001-Q1 in this condition, multiply the
current from the unloaded condition by the input voltage, and add the current from the DMD voltage regulator multiplied by the input
voltage multiplied by (1 – η).
+
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6.9 Power-Up Timing Requirements
TYP
UNIT
ten_dly
PROJ_ON to 1.1 V enable. This includes PROJ_ON tglitch Rising edge of PROJ_ON to rising edge of 1.1
time. V enable.
11
ms
(1) (2)
(1) (2)
(1) (2)
tmon1
Maximum time for 1.1 V rail to reach voltage threshold after Rising edge of ENB_1P1V to internal 1.1 V
10
10
10
10
ms
ms
ms
ms
enable has been asserted. This delay length will occur
even if 1.1 V meets threshold earlier.
monitor test.
tmon2
tmon3
tw1
Maximum time for 1.8 V rail to reach voltage threshold after Rising edge of ENB_1P8V to internal 1.8 V
enable has been asserted. This delay length will occur
even if 1.8 V meets threshold earlier.
monitor test.
Maximum time for 3.3 V rail to reach voltage threshold after Rising edge of ENB_3P3V to internal 3.3 V
enable has been asserted. This delay length will occur
even if 3.3 V meets threshold earlier.
monitor test.
RESETZ delay after voltage testing completion.
Completion of 3.3 V monitor test to RESETZ
rising edge.
(1) V1P1V, V1P8V, and V3P3V rails can be enabled prior to the TPS99001-Q1 assertion of their respective enable signal if required for
system power design. If necessary, ENB_1P1V may be connected to the 1.1 V, 1.8 V, and 3.3 V external supply enables.
(2) If any voltage threshold is not met within the specified time, the TPS99001-Q1 will not de-assert RESETZ. The power-up procedure
must be fully restarted in this situation.
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Figure 6-1. Power Up Timing
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6.10 Power-Down Timing Requirements
See (1)
MIN
MAX
UNIT
tvhold1
Host voltage hold time after VMAIN minimum
threshold reached.
VMAIN threshold to 6 V and 3.3 V
power loss.(2) (3)
900
μs
tmon4(max) + tpark(max) + tw2(max)
tvhold2
Host voltage hold time after PROJ_ON de-
asserted.
tmon5(max) + tpark(max) + tw2(max)
VMAIN threshold to 6 V and 3.3 V
power loss.(2) (3)
1.78
52
ms
tmon4
tmon5
tpark
VMAIN monitoring time.
PROJ_ON de-assertion reaction time.
DMD Park time.
Minimum voltage trip threshold to
PARKZ falling edge.
120
1
μs
ms
μs
μs
Falling edge of PROJ_ON to PARKZ
falling edge.
PARKZ falling edge to start
DMD_VOFFSET discharge.
280
260
tdischarge DMD voltage rail discharge time.
VOFFSET Cout= 1 μF
VRESET Cout= 1 μF
VBIAS Cout= 0.47 μF
(4)
tw2
DMD voltage disable to RESETZ de-assertion. Start of DMD voltage rail discharge to
RESETZ falling edge.
500
μs
(1) There are two methods for initiating the power down sequence:
a. VMAIN voltage decreases below its minimum threshold. This is typical if the TPS99001-Q1 is expected to initiate the power down
sequence when main power is removed from the system. Note that the 6 V and 3.3 V input rails must remain within operating
range for a specified period of time after the power-down sequence begins.
b. PROJ_ON low. This is allows a host controller to initiate power down through a digital input to the TPS99001-Q1.
(2) 6 V input rails include DRVR_PWR, VIN_DRST, VIN_LDOT_5V, VIN_LDOA_3P3V, VIN_LDOT3P3V.
(3) 3.3 V input rails include VDD_IO, DVDD, AVDD.
(4) The DMD specifies a maximum absolute voltage difference between VBIAS and VOFFSET. In order to remain below this maximum
voltage difference, VBIAS must discharge faster than VOFFSET. This is accomplished by using a smaller Cout capacitance for VBIAS
in order to allow it to discharge quicker than VOFFSET.
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Voltage Monitor
Threshold
VMAIN
6V In
tvhold1
Host
Control
3.3V In
PROJ ON
tmon4
PARKZ
DMD_VOFFSET
DMD_VBIAS
DMD_VRESET
RESETZ
tdischarge
tpark
tw2
ENB_1P1V
ENB_1P8V
ENB_3P3V
Figure 6-2. Power Down Timing - VMAIN Trigger
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Figure 6-3. Power Down Timing - PROJ_ON Trigger
6.11 Timing Requirements - Sequencer Clock
MIN
NOM
MAX
UNIT
ƒSEQ_CLK
tJPP
SEQ_CLK Frequency
30.00
MHz
SEQ_CLK Jitter (peak to peak)
–3%
–2%
25
3%
0%
ƒSS
SEQ_CLK allowable spread spectrum
SEQ_CLK Spread Spectrum Modulation Frequency
SEQ_CLK Spread Spectrum Modulation Frequency Steps
ƒSSMOD
ƒSSSTEPS
100
kHz
50
steps
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6.12 Timing Requirements - Host / Diagnostic Port SPI Interface
MIN
31
10
10
0
NOM
MAX
UNIT
ns
tSPICPER
tSPICHIGH
tSPICLOW
tSPIDOUT
tSSSETUP
tSSHOLD
SPI CLK Cycle Time
33
SPI CLK High Time
ns
SPI CLK Low Time
ns
CLK Falling to DOUT
15
ns
SPI SS_Z to CLK Rising Setup Time
SPI CLK Rising to SS_Z Hold Time
SPI DIN to CLK Rising Setup Time
SPI CLK Rising to DIN Hold Time
5
ns
5
ns
tDINSETUP
tDINHOLD
5
ns
5
ns
Figure 6-4. DLPC230-Q1 Diagnostic Interface Timing
Figure 6-5. Chip Select Setup and Hold Timing
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6.13 Timing Requirements - ADC Interface
MIN
5
NOM
MAX
UNIT
ns
tADCDINSETUP
tADCDINHOLD
tADCDOUT
ADC DIN to CLK Rising Setup Time
ADC CLK Rising to DIN Hold Time
CLK Rising to DOUT
5
ns
0
15
ns
6.14 Switching Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
INTERNAL CLOCK
ƒOSC Internal Oscillator Frequency
TEST CONDITIONS
MIN
TYP
MAX
UNIT
1.76
2
2.24
MHz
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7 Detailed Description
7.1 Overview
The TPS99001-Q1 is an integral component of the DLP5531-Q1 chipset, which also includes the DLPC230-Q1
DMD display controller. The TPS99001-Q1 provides a high-voltage, high-precision, three-rail regulator to cost-
effectively create DMD mirror control voltages (16 V, 8.5 V, –10 V). A complete system power monitor and DMD
mirror parking solution is included to increase system robustness and reduce cost. In addition, the TPS99001-Q1
includes numerous system monitoring and diagnostic features, such as configurable ADCs and watchdogs.
An integrated 12-bit ADC provides useful information about the operating condition of the system. Several
external ADC channels are included for general usage (LED temperature measurement, etc). One of the
external ADC channels includes a differential input amplifier and is dedicated to LED current measurement. The
DLPC230-Q1 and TPS99001-Q1 ADC control blocks support up to 63 samples per video frame, with precise
hardware alignment of samples to the DMD sequence timeline.
Two SPI buses are included. The first bus is intended for command and control, and the second is a read-only
bus for optional redundant system condition monitoring. The SPI ports include support for byte-level parity
checking.
Two windowed watchdog circuits are included to provide validation of DLPC230-Q1 microprocessor operation
and monitoring of DMD sequencer activity. The TPS99001-Q1 also includes on-die temperature threshold
monitoring and a monitor circuit to validate the external clock ratio (of the SEQ_CLK) against an internal
oscillator.
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7.2 Functional Block Diagram
7.3 Feature Description
7.3.1 Analog to Digital Converter
The TPS99001-Q1 includes a 12-bit analog to digital converter block with a 32:1 input mux and dual sample-
and-hold circuits. It also includes a custom high speed serial control interface which when used in tandem with
the DLPC230-Q1 provides up to 63 DMD sequence-aligned samples per frame, with hardware-based sample
timing and shadow-latched results. The hardware sample timing and shadow latch relieves the DLPC230-Q1
processor from ADC timing tasks, freeing up processor resources for other uses.
Figure 7-1 illustrates the structure of the ADC controller blocks .
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Figure 7-1. ADC Subsystem Block Diagram
The ADC block contains a dedicated channel reserved for differential low side LED current measurements. Two
sample-and-hold circuits are included to support paired LED current/voltage measurements. (Note: when
performing paired samples, they are sampled simultaneously, but converted sequentially, so the conversion time
doubles). An additional seven external ADC channels are supported. The remaining 24 multiplexer inputs enable
measurement of internal TPS99001-Q1 operating parameters.
The DLPC230-Q1 contains a custom ADC control block that supports up to 63 ADC samples per frame. The
samples are aligned with DMD sequencer activity, configurable through system configuration tools. This
alignment makes measurement of specific light pulses (LED current and voltage) within a sequence possible,
with precise repeatability from frame to frame. Up to 63 samples per frame are supported. The 63 sample buffer
includes a shadow latch that updates each frame. This latched output is held constant for a complete frame time,
allowing time for the DLPC230-Q1 to collect and process the information.
A reference voltage output is also included in the ADC block. This provides a low current voltage reference
which matches the reference used by the ADC for conversion. This external reference can be used to bias
thermistor voltage dividers, providing greater accuracy than would be possible using a mix of external and
internal references. (Note: Current supply is limited. Loads which exceed the specified current maximum rating
on ADC_VREF output may result in unpredictable ADC behavior). Regardless of whether the reference voltage
is used, a 0.1uF capacitor should be connected from this pin to ground.
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7.3.1.1 Analog to Digital Converter Input Table
Table 7-1. Analog to Digital Converter Input Table
INTERNAL OR
EXTERNAL
PARAMETER
Low side sense amp
TEST CONDITIONS(1)
MIN
22.56
TYP
MAX
UNIT
Channel 0, Gain
Channel 0, Gain
Channel 0, Gain
External
External
External
Gain set to 24x
Gain set to 12x
Gain set to 9x
24
12
9
25.44 V/V
Low side sense amp
Low side sense amp
11.28
8.46
12.72 V/V
9.54 V/V
ADC_IN1_PAD
(LED_ANODE)
Channel 1, Gain
External
0.980
1.000
1.020 V/V
Channel 2, Gain
Channel 3, Gain
Channel 4, Gain
ADC_IN2_PAD (VLED)
ADC_IN3_PAD
External
External
External
0.980
0.980
0.980
1.000
1.000
1.000
1.020 V/V
1.020 V/V
1.020 V/V
ADC_IN4_PAD
ADC_IN5_PAD
(R_LED_THERM)
Channel 5, Gain
Channel 6, Gain
Channel 7, Gain
External
External
External
0.980
0.980
0.980
1.000
1.000
1.000
1.020 V/V
1.020 V/V
1.020 V/V
ADC_IN6_PAD
(G_LED_THERM)
ADC_IN7_PAD
(B_LED_THERM)
Channel 8, Gain
Channel 9, Gain
Channel 10, Gain
Channel 10, Offset
Channel 11, Gain
Channel 12, Gain
Channel 13, Gain
Channel 14, Gain
Channel 15, Gain
Channel 17, Gain
Channel 18, Gain
Channel 19, Gain
Channel 20, Gain
Channel 28, Gain
Channel 29, Gain
VBIAS
VOFFSET
VRESET
Internal
Internal
Internal
Internal
Internal
Internal
Internal
Internal
Internal
Internal
Internal
Internal
Internal
Internal
Internal
0.0596
0.1112
0.0621
0.117
0.0646 V/V
0.1218 V/V
–0.1978
–0.190 –0.1822 V/V
–1.169
VRESET
–1.217 –1.1935
V
VMAIN
0.52546
0.31302
0.65706
0.40326
0.2209
0.49
0.559 0.59254 V/V
0.333 0.35298 V/V
0.699 0.74094 V/V
0.429 0.45474 V/V
DVDD
V1.1
V1.8
V3.3
0.235
0.5
0.2491 V/V
0.51 V/V
ext ADC VREF
Driver Power
Die Temp1
Die Temp2
Channel not used
Main Bandgap, 0.5 V
0.20398
0.490
0.217 0.23002 V/V
0.500
0.500
0.510 V/V
0.510 V/V
0.490
0.980
1.000
1.020 V/V
(1) Conversion formula is (X + Offset) * Gain. X is the input voltage. Offset is 0 V unless specified above.
7.3.2 Power Sequencing and Monitoring
The TPS99001-Q1 is specifically designed to perform correct power-up and power-down sequencing to ensure
long term reliable operation of the DMD. The high voltage DMD mirror supplies require special power
sequencing order, and restrictions on voltage differences between the power rails (VRESET, VBIAS, and
VOFFSET) throughout power up, power down, and normal operation. The TPS99001-Q1 handles these
requirements for the system designer.
7.3.2.1 Power Monitoring
Main asynchronous digital logic reset (DVDD_RSTZ) – Monitor of the main power of the 3.3 V power supply
input to the TPS99001-Q1. This monitor output is used as an asynchronous reset for all of the digital logic inside
TPS99001-Q1.
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Figure 7-2. Internal DVDD Monitor
The PROJ_ON pin is the main on/off switch for DLP subsystem. 1 is ON, 0 is OFF. Once DVDD_ARSTZ is
released, TPS99001-Q1 will begin sampling the PROJ_ON pin. If it is low, system stays in the OFF state. If it
goes high, TPS99001-Q1 begins to progress through the power-on process.
The TPS99001-Q1 includes a VMAIN brown out monitor function. A voltage monitor observes the voltage on the
VMAIN input pin, as shown in Figure 7-3. The Zener may be necessary for over voltage protection of the pin, in
case the voltage being monitored has the potential to go high, such as a battery input.
Either PROJ_ON or VMAIN may be used to turn the system on and off, and doing so will remove power to the
DLPC230-Q1. For fast control of turning the display on and off without removing power to the DLPC230-Q1,
change the operating mode of the DLPC230-Q1 embedded software between 'Standby' and 'Display'.
main power after
preregulator/filter
R1
VMAIN
pwrgood1
voltage
monitor
if necessary
R2
Figure 7-3. VMAIN Brown Out Monitor
This monitor is used to provide the DLP subsystem with an early warning that power to the unit is going away.
The system will park the DMD mirrors and proceed to a ready for power-off state if the VMAIN input voltage falls
below a fixed threshold. External resistors should be used to divide the input power rail. Once a VMAIN brown
out occurs, the main power rails to the TPS99001-Q1 must remain within their operating ranges until the
TPS99001-Q1 power-down is complete.
The main power rails to the chipset (6 V, 3.3 V, 1.8 V and 1.1 V) are monitored with real time power monitors as
well. Each of these monitors is logically 'OR'ed together to produce the pwrgood2 signal in Figure 7-4.
Figure 7-4. Real-Time Power Rail Monitors
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Additionally, all power within the TPS99001-Q1 can be monitored by the ADC function. DLPC230-Q1 software
configures the ADC block to collect all voltage information in the system each frame. Any gross out of
specification issues are captured and reported as system errors in the DLPC230-Q1 system status.
7.3.3 DMD Mirror Voltage Regulator
The DMD mirror voltage regulator generates three high voltage supply rails: DMD_VRESET, DMD_VBIAS and
DMD_VOFFSET. The DMD regulator uses a switching regulator where the inductor is time shared between all
three supplies. The inductor is charged up to a certain current level and then discharged into one of the three
supplies. In cases where a supply does not need additional charge, the time slot normally allocated to that
supply is skipped and the supplies requiring more charge receive all of the charging time.
For proper operation, specific bulk capacitance values are required for each supply rail. Refer to Section 6.7 for
recommended values for the capacitors. The regulator contains active power down/discharge circuits. To meet
timing requirements, total capacitance (actual capacitance, not the nominal) must not exceed these levels by
substantial amounts, as defined in Section 6.7. Power down timing should be verified in each specific system
design. Too low of a total capacitance will result in excessive ripple on the supply rails which may impact DMD
mirror dynamic behavior. Care should be taken to use capacitors which maintain the recommended minimum
capacitance over the expected operating device temperature range. Large size packages are required here that
do not lose so much capacitance at high voltages.
Although the average current drawn by the DMD on these supplies is small (10’s of mA worst case), the peak
currents can be several amps over 10’s of nano-seconds. To supply this peak current, use of small value, high
frequency decoupling capacitors should be included as close as practical to the DMD power input pins.
VSS_DRST
56
55
54
53
6 V
VIN_DRST
> = 10 µF
DRST_HS_IND
DRST_PGND
VRESET
1 µF
DRST_LS_IND
DMD_VRESET
DMD_VBIAS
Note: Include
high frequency
decoupling
52
51
50
49
capacitors
close to DMD
power pins.
DMD
High-Voltage
Regulator
VBIAS
DMD_VOFFSET
VOFFSET
0.47 µF
1 µF
Figure 7-5. DMD Voltage Regulator Circuit
7.3.4 Low Dropout Regulators
The TPS99001-Q1 includes three low drop out regulators, dedicated to specific internal functions:
•
•
•
A 5 V output regulator for internal analog circuits (VIN_LDOT_5V input, VLDOT_5V output)
A 3.3 V output regulator for internal analog (VIN_LDOT_3P3V input, VLDOT_3P3V output)
A 3.3 V output regulator dedicated to the ADC block (VIN_LDOA_3P3 input, VLDOA_3P3 output)
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The positive output LDO regulators are all designed to operate from the same nominal 6 V input as is needed by
the DMD mirror voltage regulator, VIN_DRST. However, care must be taken to isolate the sensitive analog circuit
power supply inputs from switching noise, through dedicated sub-planes and supply filtering techniques.
7.3.5 System Monitoring Features
7.3.5.1 Windowed Watchdog Circuits
The TPS99001-Q1 contains two windowed watchdog circuits that can be used to detect malfunctions within the
DLPC230-Q1.
Figure 7-6. Windowed Watchdog Function
The DLPC230-Q1 software uses both watchdog circuits. Watchdog #1 (WD1) monitors the internal
microprocessor of the DLPC230-Q1 through a wire connection to a dedicated GPIO line from DLPC230-Q1.
Watchdog #2 (WD2) is used to monitor the DLPC230-Q1 sequencer operation (through monitoring of the
SEQ_STRT pin, wired to WD2 input).
When this function is enabled, two registers control the timing of the opening and closing of a watchdog trigger
window. Process is initiated by a rising edge on the respective WDx pin. If another rising edge occurs before the
WD trigger window opens, a watchdog error is issued. If the end of the open window period is reached without
receiving a rising edge on WDx, an error is issued. The process restarts any time a WDx rising edge is received.
The two watchdogs are independent.
7.3.5.2 Die Temperature Monitors
The TPS99001-Q1 contains two on-chip die temperature monitors, for reduncy purposes, to monitor the internal
temperature of the TPS99001-Q1. Each monitor has an output that indicates whether the die temperature has
exceeded one of two thresholds. One monitors a warning threshold, and the other monitors an over-tempreature
error threshold. If the warning threshold is exceeded, a processor interrupt may be generated. If the over-
temperature error threshold is exceeded during operation, the TPS99001-Q1 will initiate an emergency
shutdown procedure and then wait for a toggle of the PROJ_ON pin to initiate a system restart while operating in
a low power state. The system will not proceed through the power on initialization steps unless the on die
temperature is below the warning threshold. The status of these temperature monitor output bits is available over
the SPI buses as long as DVDD and VDD_IO power supplies are up and stable.
7.3.5.3 External Clock Ratio Monitor
The TPS99001-Q1 operates from two primary clock sources: an internal low frequency oscillator (2 MHz, used
for system initialization and other maintenance purposes), and an external high speed (30 MHz) clock,
SEQ_CLK, used for most timing critical applications, such as the ADC. The TPS99001-Q1 includes a function
that reports the ratio of this internal vs. external clock. This ratio is available over the SPI bus. The DLPC230-Q1
can check this ratio and compare to expected value. If the ratio is incorrect, there is a possibility the DLPC230-
Q1 oscillator may have locked to an incorrect harmonic, or some other fault condition has occurred.
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7.3.6 Communication Ports
7.3.6.1 Serial Peripheral Interface (SPI)
The TPS99001-Q1 provides two four-wire SPI ports that support transfers up to 30 MHz clock rates. The primary
port (SPI1) supports register reads and writes, and serves as the primary set up and control interface for the
device. The DLPC230-Q1 is the master of SPI1 to control the TPS99001-Q1 during system operation. A
secondary read-only four wire SPI port (SPI2) is available to provide status information to an optional second
microcontroller in the system.
For both ports, the SPIx_SS_Z serves as the active low chip select for the SPI port. A SPI frame is initiated by
SPIx_SS_Z pin going low, and is completed when SPIx_SS_Z pin is driven high.
The secondary SPI port serves as a read-only system monitor port. All registers in the address space are read
accessible over this port. The protocol is effectively the same as the main port except for being read-only. Note
that data is clocked in on the rising edge of the SPI2_CLK.
When using this port, one must always transmit the full transaction packet. Failure to do so may result in
corruption of data.
SPI2_SS_Z
Header
Don‘t care 16 bit word
dummy
byte
address
SPI2_DIN
0
7
7
0
15
0
valid read cycle:
regdata(15:8)
regdata(7:0)
SPI2_DOUT
Figure 7-7. SPI Port 2 Protocol (Read Only)
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7.4 Device Functional Modes
The following diagram in Figure 7-8 illustrates the functional operating modes of the TPS99001-Q1.
Figure 7-8. Top Level System States
7.4.1 OFF
The asynchronous internal reset of the device places system in this state. All supplies (DMD supplies, 1.1 V, 1.8
V, 3.3 V) are asynchronously disabled and RESETZ output to DLPC230-Q1 is held low. Once the internal reset
is released, communication over SPI2 is supported.
Exit from OFF state progresses to the STANDBY state. To exit OFF state, the following must all be true:
•
•
•
VMAIN input monitor must show good status.
PROJ_ON (projector on) input pin must be high.
The die temperature warning must indicate the die temperature is below the warning threshold. Upon exit of
OFF state and before entry to STANDBY, the external 1.1 V, 1.8 V, and 3.3 V supplies are powered on in
sequence – first 1.1 V, then 1.8 V, then 3.3 V.
Internal monitors of 1.1 V, 1.8 V, and 3.3 V (and 6 V input on VIN_LDOT_5V) will hold off progression to
STANDBY until all 4 rails are in operational range. After power is good, RESETZ output signal is held low for a
specific period to ensure a proper reset cycle for the DLPC230-Q1, and then it is released to transition to
STANDBY.
7.4.2 STANDBY
Upon entry to STANDBY state, RESETZ is set high and DLPC230-Q1 begins its boot process.
Exit options from STANDBY state include:
•
A die over temp error sends system to SHUTDOWN state. An over temperature error in the STANDBY state
means something is wrong with the system.
•
•
•
PROJ_ON low sends to OFF state.
Software commanded power cycle. System proceeds to OFF state.
If either of the watchdog timers have been enabled by software and an error occurs, system proceeds to OFF
state.
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•
•
If power unexpectedly goes bad, system proceeds to OFF state.
DLPC230-Q1 software begins to enable DMD voltages. Sends to POWERING_DMD state. This is the first
step in DMD voltage enabling process.
During the STANDBY phase, the DLPC230-Q1 software performs DMD and DLPC230-Q1 sequencer
configuration steps. The software is in charge of DMD voltage enable timing, interleaving necessary DMD
configuration register writes, and DLPC230-Q1 ASIC block configuration steps. After the DLPC230-Q1 software
begins enabling DMD voltages, the TPS99001-Q1 proceeds to POWERING_DMD state.
7.4.3 POWERING_DMD
Once the DLPC230-Q1 software begins enabling DMD voltages when in STANDBY, the system enters
POWERING_DMD state. In this state, the DLPC230-Q1 software performs all steps needed to properly
configure and power up the DMD safely.
Exiting from POWERING_DMD state, the DLPC230-Q1 software confirms that DMD is powered up. This sends
the TPS99001-Q1 to DISPLAY_RDY state. This is the last step in DMD voltage enabling process.
If a PROJ_ON low is received during power on, the TPS99001-Q1 will still complete the power on sequence.
7.4.4 DISPLAY_RDY
In the display ready state, the DLPC230-Q1 may enable illumination at any time.
Once the DLPC230-Q1 software enables illumination, the TPS99001-Q1 enters the DISPLAY state.
Exit conditions:
•
A DMD park event has occurred including power not good, PROJ_ON low, die over temp error, software park
initiated, or software power cycle initiated. These events send the TPS99001-Q1 to PARKING state.
7.4.5 PARKING
DMD parking is taking place. PARKZ output signal (to DLPC230-Q1) is asserted low in this state. Timers count
down time then the control for the DMD voltage regulators is disabled. Once the final hardware delay elapses,
the next state is STANDBY.
7.4.6 SHUTDOWN
The shutdown state is entered only when a die over temperature condition is experienced. All switchable on chip
activity is halted. The only exit conditions from this state are PROJ_ON low (0) or true power off. This state is
readable via the 2nd diagnostic SPI port. All power supplies are disabled.
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7.5 Register Maps
7.5.1 System Status Registers
ADDRESS
NAME
BITS
DESCRIPTION
Chip Revision ID, R-only, Reset Value 0000
Unused
[15:8] Unused
0x00
Major
Minor
[7:4]
[3:0]
Major revision
Minor revision
Status Set, R/W, Reset Value 0000
PG Fault Status
[15]
[13]
[12]
Asserted when any bin in user register 38h is set
Power good timer for VOFS, VRST, or VBIAS expired
VXPG Init
Main SPI parity error
Parity error on a SPI1 port transaction occurred (command or write data) on previous
command
ADC block error
Checksum error 3
Checksum error 2
Checksum error 1
WD2
[11]
[10]
[9]
"OR" of all errors in ADC block. Refer to x0D to determine specific error.
Checksum error in LED section
Checksum error in light sensor conditioning section
Checksum error in ADC sub-system section
Watchdog #2 error
[8]
[7]
0x01
WD1
[6]
Watchdog #1 error
Top level state change
[5]
Indicates top level state machine has changed state. Can be used to indicate that the
TPS99001-Q1 has exited DISPLAY state unexpectedly due to a random fault
VXPG Fault
[3]
[2]
Set 1 by hardware if power good fault occurs for VOFS, VRST, or VBIAS
DIE Over temp warning
Thermal conditions on chip have reached the warning level. If temperature continues to
rise, system will reach die over temp error temperature and emergency actions will be
taken by TPS99001-Q1
DIE Over temp error
PROJ_ON_LOW
[1]
[0]
Thermal conditions on chip have reached the emergency/error. Emergency actions will
be taken by TPS99001-Q1 to protect the system. This error bit is non-maskable for
PARKZ output
Projector ON input pin is low (produces a 1 on this status bit).
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ADDRESS
NAME
BITS
DESCRIPTION
General Status 1, R-only, Reset Value 0000
Clock ratio monitor
[15:12] Mid-scale reading (1000 ± 1) indicate approximately 30-MHz external signal has been
applied
Open
[11:8]
[7:5]
Reserved
Last Reset (2:0)
Root cause of last reset cycle, last pass through the OFF state.
“000” – true power on cycle, internal reset set/release
“001” – PROJ_ON went low
“010” – watchdog timer 1 error
“011” – watchdog timer 2 error
“100” – die over temperature error
“101” – SW power cycle command
all others unused
Top State (4:0)
[4:0]
Top level state machine current state
0x00 = SHUTDOWN
0x01 = Internal initialization
0x02 = OFF
0x05
0x03 = Internal initialization
0x04 = Initializing 1P1V
0x05 = Initializing 1P8V
0x06 = Initializing 3P3V
0x07 = De-assert RESETZ
0x08 = STANDBY
0x09 = VOFFSET enabled
0x0A = VBIAS enabled
0x0B = VRESET enabled
0x0C = DISPLAY READY
0x0D = DISPLAY ON
0x0E = Parking initialized
0x0F = VBIAS and VRESET disabled
0x10 = VOFFSET disabled
0x11 = DMD voltage discharge
7.5.2 ADC Control
ADDRESS
NAME
BITS
DESCRIPTION
ADC Block Status SET, Read, Reset Value 0000
Unused
[15:8] Reserved
AD3 Command Stop-bit
[7]
Indicates that a stop bit was missing
Error
ADC Timeline Error
[6]
Indicates that a new command was received while previous command
was still in progress
Command error
Parity error detected
Ch2 underflow
[5]
[4]
[3]
An error was detected on a serial bus command
A parity error in bit stream was detected
0x0D
ADC conversion results presented in channel two register experienced
an underflow
Ch2 saturated
Ch1 underflow
Ch1 saturated
[2]
[1]
[0]
ADC conversion results presented in channel two register are
saturated
ADC conversion results presented in channel one register experienced
an underflow
ADC conversion results presented in channel one register are
saturated
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7.5.3 General Fault Status
ADDRESS
NAME
BITS
DESCRIPTION
General Fault Status, R-only, Reset Value 0000, Value of 1 indicates a Fault
VBIAS Powergood Fault
VRST Powergood Fault
VOFS Powergood Fault
Powergood 1 Fault
[15]
[14]
[13]
[12]
VBIAS is below the minimum specified voltage
VRESET is below the minimum specified voltage
VOFFSET is below the minimum specified voltage
VMAIN or AVDD rail is below the minimum specified voltage (Logical
OR).
Powergood 2 Fault
[10]
[9]
At least one of 1.1 V, 1.8 V, 3.3 V, and 6 V supplies is below the
minimum specified voltage (Logical OR).
ADC 3V LDO
Powergood Fault
ADC 3V LDO is below the minimum specified voltage
ADC 3V LDO is above the maximum specified voltage
3V LDO is below the minimum specified voltage
3V LDO is above the maximum specified voltage
0x38
ADC 3V LDO Over
Voltage Fault
[8]
3V LDO Powergood
Fault
[7]
3V LDO Over Voltage
Fault
[6]
LDO Over Voltage Fault
V3P3 Powergood Fault
V1P8 Powergood Fault
V1P1 Powergood Fault
[5]
[2]
[1]
[0]
LDO is above the maximum specified voltage
3.3 V is below the minimum specified voltage
1.8 V is below the minimum specified voltage
1.1 V is below the minimum specified voltage
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8 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
8.1 Application Information
The DLP5531-Q1 chipset is designed to support projection-based automotive applications such as high
resolution headlights.
The DLP5531-Q1 chipset consists of three components—the DLP5531-Q1 (DMD), the DLPC230-Q1, and the
TPS99001-Q1. The DMD is a light modulator consisting of tiny mirrors that are used to form and project images.
The DLPC230-Q1 is a controller for the DMD; it formats incoming video and controls the timing of the DMD
illumination sources and the DMD in order to display the incoming video. The TPS99001-Q1 is a management
IC for the entire chipset. In conjunction, the DLPC230-Q1 and the TPS99001-Q1 can also be used for system-
level monitoring, diagnostics, and failure detection features.
8.2 Typical Applications
Pulldown resistors are required on the pins in the below table to avoid a floating input during the power-up and
power-down conditions.
Table 8-1. Pulldown Resistor Requirements
PIN
5
NAME
TYP
10 kΩ
10 kΩ
10 kΩ
10 kΩ
10 kΩ
10 kΩ
10 kΩ
10 kΩ
56 kΩ
110 kΩ
68 kΩ
ADC_MOSI
WD1
6
16
17
27
30
31
34
49
50
51
SEQ_START
SEQ_CLK
SPI1_CLK
SPI1_DIN
SPI2_DIN
SPI2_CLK
DMD_VOFFSET(1)
DMD_VBIAS(1)
DMD_VRESET(1)
(1) Resistor pull downs are required to create a minimum load for DMD_VOFFSET, DMD_VBIAS, and DMD_VRESET. Each of these
pulldowns should provide a load from 0.1mA to 1mA. If the -8 V LDO is used, then the pull down for DMD_VRESET may be
eliminated.
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8.2.1 Headlight
Figure 8-1. Headlight System Block Diagram
8.2.1.1 Design Requirements
The DLPC230-Q1 is a controller for the DMD and the light sources in headlight applications. It receives input
video from the host and synchronizes DMD and light source timing in order to achieve the desired video. The
DLPC230-Q1 formats input video data that is displayed on the DMD. It synchronizes these video segments with
light source timing in order to create video with grayscale shading.
The DLPC230-Q1 receives inputs from a host processor in the vehicle. The host provides commands and input
video data. R/W commands can be sent using either the I2C bus or SPI bus. The bus that is not being used for
R/W commands can be used as a read-only bus for diagnostic purposes. Input video can be sent over an
OpenLDI bus or a parallel 24-bit bus. The 24-bit bus can be limited to only 8-bits of data for single light source
systems such as headlights. The SPI flash memory provides the embedded software for the DLPC230-Q1’s
ARM core, any calibration data, and default settings. The TPS99001-Q1 provides diagnostic and monitoring
information to the DLPC230-Q1 using an SPI bus and several other control signals such as PARKZ, INTZ, and
RESETZ to manage power-up and power-down sequencing. The TMP411 uses an I2C interface to provide the
DMD array temperature to the DLPC230-Q1.
The outputs of the DLPC230-Q1 are configuration and monitoring commands to the TPS99001-Q1, timing
controls to the LED or laser driver, control signals to the DMD, and monitoring and diagnostics information to the
host processor. The DLPC230-Q1 communicates with the TPS99001-Q1 over an SPI bus. It uses this to
configure the TPS99001-Q1 and to read monitoring and diagnostics information from the TPS99001-Q1. The
DLPC230-Q1 sends drive enable signals to the LED or laser driver, and synchronizes this with the DMD mirror
timing. The control signals to the DMD are sent using a sub-LVDS interface.
The TPS99001-Q1 is a highly integrated mixed-signal IC that controls DMD power and provides monitoring and
diagnostics information for the headlight system. The power sequencing and monitoring blocks of the
TPS99001-Q1 properly power up the DMD and provide accurate DMD voltage rails, and then monitor the
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system’s power rails during operation. The integration of these functions into one IC significantly reduces design
time and complexity. The TPS99001-Q1 also has several general-purpose ADCs that designers can use for
system level monitoring.
The TPS99001-Q1 receives inputs from the DLPC230-Q1, the power rails it monitors, the host processor, and
potentially several other ADC ports. The DLPC230-Q1 sends configuration and control commands to the
TPS99001-Q1 over an SPI bus and several other control signals. The TPS99001-Q1 includes watchdogs to
monitor the DLPC230-Q1 and ensure that it is operating as expected. The power rails are monitored by the
TPS99001-Q1 in order to detect power failures or glitches and request a proper power down of the DMD in case
of an error. The host processor can read diagnostics information from the TPS99001-Q1 using a dedicated SPI
bus. Additionally the host can request the image to be turned on or off using a PROJ_ON signal. Lastly, the
TPS99001-Q1 has several general-purpose ADCs that can be used to implement system level monitoring
functions.
The outputs of the TPS99001-Q1 are diagnostic information and error alerts to the DLPC230-Q1, and control
signals to the LED or laser driver. The TPS99001-Q1 can output diagnostic information to the host and the
DLPC230-Q1 over two SPI busses. In case of critical system errors, such as power loss, it outputs signals to the
DLPC230-Q1 that trigger power down or reset sequences. It also has output signals that can be used to
implement various LED or laser driver topologies.
The DMD is a micro-electro-mechanical system (MEMS) device that receives electrical signals as an input (video
data), and produces a mechanical output (mirror position). The electrical interface to the DMD is a sub-LVDS
interface with the DLPC230-Q1. The mechanical output is the state of more than 1.3 million mirrors in the DMD
array that can be tilted ±12°. In a projection system the mirrors are used as pixels in order to display an image.
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9 Power Supply Recommendations
The TPS99001-Q1 requires two power inputs and also provides several power outputs, as well as controlling
additional external power supplies. The power supply architecture is explained in Section 9.3.
9.1 TPS99001-Q1 Power Supply Architecture
•
•
6.5 V
3.3 V (LDO recommended)
9.2 TPS99001-Q1 Power Outputs
•
DMD Required Voltages:
– DMD_VOFFSET
– DMD_VBIAS
– DMD_VRESET
•
Internally used LDOs. These are not designed to be used externally, but are listed here as they require
external bypass capacitors:
– 5 V
– 3.3 V
– 3.3 V ADC
9.3 Power Supply Architecture
TI recommends the following power supply architecture:
Figure 9-1. Headlight Power Supply Architecture
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10 Layout
10.1 Layout Guidelines
The TPS99001-Q1 is both a power and precision analog IC. As such, care must be taken to the layout of certain
signals and circuits within the system. Along with general layout best practices, pay attention to the following
areas of detail, which are discussed in this document.
•
•
•
•
•
•
Power/high current signals
Sensitive analog signals
High speed digital signals
High power current loops
Kelvin sensing connections
Ground separation
10.1.1 Power/High Current Signals
The TPS99001-Q1 switches a relatively high amount of current via the switching regulator which generates the
voltages used by the DMD.
The DMD regulator consists of the following pins of the TPS99001-Q1:
Table 10-1. TPS99001-Q1 DMD Regulator Pins
PIN
49
50
51
52
53
54
55
56
NAME
PEAK BOARD CURRENT
800 mA
DMD_VOFFSET
DMD_VBIAS
DMD_VRESET
DRST_LS_IND
DRST_PGND
DRST_HS_IND
VIN_DRST
800 mA
800 mA
800 mA
800 mA
800 mA
800 mA
VSS_DRST
800 mA
The value of 800 mA for these pins relates to the peak current through the inductor due to the nature of the
switching regulator architecture. The DC current for these paths will be closer to the load current drawn by the
DMD.
In addition to these high current signals that are driven by the TPS99001-Q1, the LED driver electronics will
likely have other circuits which handle the high currents required by the LEDs. These currents may be as high as
6 A and therefore will also require special consideration by the layout engineer. As a guide for the PCB trace
width requirements, the reader is referred to TI’s Application Note (SLUA366). The PCB trace widths used in TI’s
design were:
Table 10-2. PCB Trace Widths
SIGNAL GROUP
PCB TRACE WIDTH
DMD Regulator
10 mils
10.1.2 Sensitive Analog Signals
The following signals are analog inputs to TPS99001-Q1. Most of these analog inputs are DC levels and are
somewhat insensitive to noise, but others are part of the real-time color control algorithm of the TPS99001-Q1
and therefore must be kept immune from noise injection from other signals. The list of analog input pins is as
follows:
Table 10-3. TPS99001-Q1 Analog Input Pins
PIN
NAME
SIGNAL TYPE
82
LS_SENSE_N
Real-time
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Table 10-3. TPS99001-Q1 Analog Input Pins (continued)
PIN
83
85
86
88
90
92
93
94
96
97
98
NAME
LS_SENSE_P
ADC_IN1
ADC_IN2
ADC_IN3
ADC_IN4
ADC_IN5
ADC_IN6
ADC_IN7
V3P3V
SIGNAL TYPE
Real-time
Real-time
DC
DC
DC
DC
DC
DC
DC
V1P8V
DC
V1P1V
DC
10.1.3 High Speed Digital Signals
The TPS99001-Q1 has three serial interfaces that are used to transmit data into and out of the device. All these
of these interfaces have a maximum clock speed of 30 MHz. In order to help prevent against high levels of EMI
emissions, these signals should be laid out with impedance matched, low inductance traces. In particular, the
three clocks for these interfaces should be low inductance, and if a cable or a connector is used, the clock signal
should be adjacent to the ground signal return.
Table 10-4. SPI1 Interface from DLPC230-Q1 to TPS99001-Q1
PIN
27
28
29
30
NAME
FUNCTION
Clock (30 MHz)
Slave Select
Data
SPI1_CLK
SPI1_SS_Z
SPI1_DOUT
SPI1_DIN
Data
Table 10-5. SPI2 Interface from Customer MCU to TPS99001-Q1
PIN
31
32
33
34
NAME
FUNCTION
SPI2_DIN
SPI2_DOUT
SPI2_SS_Z
SPI2_CLK
Data
Data
Slave Select
Clock (Up to 30 MHz)
Table 10-6. ADC3 Interface from DLPC230-Q1 to TPS99001-Q1
PIN
4
NAME
FUNCTION
ADC_MISO
ADC_MOSI
Data
5
Data
17
SEQ_CLK
Clock (30 MHz)
To avoid crosstalk, a PCB trace spacing requirement is suggested, such as the “3 W rule” which specifies that if
the trace width is 5 mils, then traces should be spaced out at least 15 mils from center to center. On TI’s PCB
design, the typical trace spacing was 20 mils.
10.1.4 Kelvin Sensing Connections
There are many places in the system design where the current through a signal path is measured by use of a
sense resistor in series with the signal path. In these cases, the resistor should be connected by use of a
“Kelvin” connection, or a “Force-Sense” connection. This means that two connections are made to the resistor
that carry the high level of current, and two connections are made separately to measure the voltage across the
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resistor. This prevents the sense lines from being affected by the extra resistance of the copper traces, and
makes the measurement more accurate. An example of the “Force-Sense” connection is shown in Figure 10-1.
Figure 10-1. Kelvin Sensing Layout
The TPS99001-Q1 uses a sense resistor to measure the current delivered to the LEDs. These differential sense
lines are the inputs to the part LS_SENSE_P and LS_SENSE_N. It is important to notice that although
LS_SENSE_N may be electrically connected to ground by the netlist, this signal must be routed as a separate
trace to prevent it from being affected by changes in the ground plane.
10.1.5 Ground Separation
Separated ground planes are good for isolating noise from different parts of the circuit to other. However, when
designing with separate ground planes, one must be careful of how the signals are routed to avoid large
inductive loops. If separate ground planes are used, TI recommends the following ground connections to the
TPS99001-Q1. In addition, the grounds should be connected electrically by a via or 0 Ω resistor. If a unified
ground plane is used, the following can be used as a guideline for which groups of signals should be routed
apart from other signals.
Table 10-7. TPS99001-Q1 Ground Separation
PIN
NAME
GROUND
Digital
13, 35
VSS_IO
24
DVSS
Digital
25, 60, 75, 99
PBKG
Analog
Power
Power
Power
Analog
Analog
Analog
Analog
Analog
48
VSS_DRVR
DRST_PGND
VSS_DRST
GND_LDO
VSS_TIA
AVSS
53
56
66
71, 72
78, 100
81, 84, 87, 89, 91
Thermal Pad
VSSL_ADC
DAP
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
11.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
11.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
11.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
DLP® is a registered trademark of Texas Instruments.
All trademarks are the property of their respective owners.
11.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
11.6 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
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12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2021 Texas Instruments Incorporated
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Product Folder Links: TPS99001-Q1
PACKAGE OPTION ADDENDUM
www.ti.com
21-Jan-2021
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPS9901TPZPQ1
TPS9901TPZPRQ1
ACTIVE
ACTIVE
HTQFP
HTQFP
PZP
PZP
100
100
90
RoHS & Green
NIPDAU
Level-3-260C-168 HR
Level-3-260C-168 HR
-40 to 105
-40 to 105
TPS9901TPZP
TPS9901TPZP
1000 RoHS & Green
NIPDAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
21-Jan-2021
Addendum-Page 2
GENERIC PACKAGE VIEW
PZP 100
14 x 14, 0.5 mm pitch
PowerPAD TM TQFP - 1.2 mm max height
PLASTIC QUAD FLATPACK
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224739/A
www.ti.com
PACKAGE OUTLINE
PZP0100K
PowerPADTM TQFP - 1.2 mm max height
SCALE 1.000
PLASTIC QUAD FLATPACK
PIN 1 ID
14.2
13.8
B
A
100
76
1
75
14.2
13.8
16.2
15.8
TYP
25
51
50
26
0.27
0.17
100X
96X 0.5
4X 12
0.08
C A B
1.2 MAX
SEE DETAIL A
C
SEATING PLANE
0.08 C
0.09-0.20
TYP
50
26
25
51
0
MIN
4X (0.26)
NOTE 4
0.25
GAGE PLANE
(1)
12X
(0.2)
NOTE 4
6.00
4.68
0.75
0.45
0.15
0.05
0 -7
DETAIL A
DETAIL
SCALE: 12
A
EXPOSED
THERMAL PAD
TYPICAL
12X (0.4)
NOTE 4
75
1
76
100
6.00
4.68
4218999/A 12/2018
PowerPAD is a trademark of Texas Instruments.
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Reference JEDEC registration MS-026, variation ACD.
4. Strap features may not be present,
www.ti.com
EXAMPLE BOARD LAYOUT
PZP0100K
PowerPADTM TQFP - 1.2 mm max height
PLASTIC QUAD FLATPACK
(
12) NOTE 8
(6)
SYMM
SOLDER MASK
DEFINED PAD
100
76
100X (1.5)
1
75
100X (0.3)
96X (0.5)
(6)
SYMM
(15.4)
(1.35)
TYP
SOLDER MASK
OPENING
25
51
(
0.2) TYP
VIA
METAL COVERED
BY SOLDER MASK
26
50
(1.35) TYP
SEE DETAILS
(15.4)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:5X
0.05 MIN
ALL AROUND
0.05 MAX
ALL AROUND
SOLDER MASK
METAL
EXPOSED
METAL
EXPOSED
METAL
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4218999/A 12/2018
NOTES: (continued)
5. Publication IPC-7351 may have alternate designs.
6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
7. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
numbers SLMA002 (www.ti.com/lit/slma002) and SLMA004 (www.ti.com/lit/slma004).
8. Size of metal pad may vary due to creepage requirement.
www.ti.com
EXAMPLE STENCIL DESIGN
PZP0100K
PowerPADTM TQFP - 1.2 mm max height
PLASTIC QUAD FLATPACK
(6)
BASED ON
0.125 THICK STENCIL
SEE TABLE FOR
SYMM
DIFFERENT OPENINGS
FOR OTHER STENCIL
THICKNESSES
76
100
100X (1.5)
100X (0.3)
1
75
96X (0.5)
SYMM
(15.4)
(6)
BASED ON
0.125 THICK
STENCIL
51
25
26
50
METAL COVERED
BY SOLDER MASK
(15.4)
SOLDER PASTE EXAMPLE
EXPOSED PAD
100% PRINTED SOLDER COVERAGE BY AREA
SCALE:5X
STENCIL
THICKNESS
SOLDER STENCIL
OPENING
0.1
6.71 X 6.71
6 X 6 (SHOWN)
5.48 X 5.48
0.125
0.150
0.175
5.07 X 5.07
4218999/A 12/2018
NOTES: (continued)
9. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
10. Board assembly site may have different recommendations for stencil design.
www.ti.com
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TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
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IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
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standards, and any other safety, security, regulatory or other requirements.
These resources are subject to change without notice. TI grants you permission to use these resources only for development of an
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TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2023, Texas Instruments Incorporated
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