TPSF12C3DYYR [TI]
适用于三相系统的共模有源 EMI 滤波器 | DYY | 14 | -40 to 150;
| 型号： | TPSF12C3DYYR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 适用于三相系统的共模有源 EMI 滤波器 | DYY | 14 | -40 to 150 |
| 文件： | 总31页 (文件大小：3100K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPSF12C3
ZHCSQ99A –MARCH 2023 –REVISED APRIL 2023
TPSF12C3 用于在三相交流电源系统中降低共模噪声的独立有源EMI 滤波器
1 特性
3 说明
• 功能安全型
TPSF12C3 是一款有源滤波器 IC，旨在降低三相交流
电源系统中的共模(CM) 电磁干扰(EMI)。
– 可提供用于功能安全系统设计的文档
• 电压检测、电流注入有源EMI 滤波器
配置了电压检测和电流注入(VSCI) 的有源 EMI 滤波器
(AEF) 使用电容倍增器电路来模拟传统无源滤波器设计
中的 Y 电容器。该器件使用一组检测电容器来检测每
条电源线上的高频噪声，并使用注入电容器将降噪电流
注入电源线。有效的有源电容由电路增益和注入电容设
置。AEF 检测和注入阻抗使用相对较低的电容值，组
件尺寸较小。该器件包括集成滤波、补偿和保护电路，
以及使能输入。
– 针对CISPR 11 和CISPR 32 B 级传导EMI 要
求进行了优化
– 在适用的EMI 频率范围（150kHz 至3MHz）内
实现共模发射低阻抗
– 扼流圈尺寸、重量和成本减少了50% 以上
– 峰值注入电流为±80mA（典型值）
– 具有113MHz 单位带宽增益积的放大器
• 8 V 至16 V 的宽电源电压范围
• 结温范围为–40°C 至150°C
• 三相交流电源系统的简单外部配置
– 集成检测滤波器和求和网络
– 线路频率下漏电流低
– 简化的补偿网络
• 固有保护特性，可实现稳健设计
TPSF12C3 在 EMI 测量所需频率范围内提供了极低的
CM 噪声阻抗路径。在指定频率范围（例如 150kHz 至
3MHz）的下限降低高达 30dB 的 CM 噪声，可显著降
低CM 滤波器实施方案的尺寸、重量和成本。
封装信息
封装(1)
封装尺寸（标称值）
器件型号
– 可承受6kV 浪涌(IEC 61000-4-5)，更大限度减
少了外部元件数量
DYY（SOT-23-THIN，
14）
TPSF12C3
4.20mm × 2.00mm
– 用于远程开/关控制的使能引脚
– 具有迟滞功能的VDD 电压UVLO 保护
– 具有迟滞功能的热关断保护
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
• 4.2mm × 2mm SOT-23，14 引脚(DYY) 封装
2 应用
• 电网基础设施–电动汽车充电站
• HVAC 电机控制、航天和国防
• 焊机、逆变器和其他工业系统
• 通信电源交流/直流整流器
L1
L2
AC/DC
3-phase
regulator
AC source
L3
N
Chassis
PE
CINJ
CSEN1–CSEN4
COMP1
SENSE1
COMP2
INJ
EN
SENSE2
SENSE3
SENSE4
REFGND
VDD
12 V
IGND
TPSF12C3
Chassis (PE)
简化原理图
EMI 降噪结果
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SNVSCB8
TPSF12C3
ZHCSQ99A –MARCH 2023 –REVISED APRIL 2023
www.ti.com.cn
Table of Contents
8.3 Feature Description.....................................................9
8.4 Device Functional Modes..........................................12
9 Applications and Implementation................................13
9.1 Application Information............................................. 13
9.2 Typical Applications.................................................. 13
9.3 Power Supply Recommendations.............................21
9.4 Layout....................................................................... 21
10 Device and Documentation Support..........................24
10.1 Device Support....................................................... 24
10.2 Documentation Support.......................................... 25
10.3 接收文档更新通知................................................... 25
10.4 支持资源..................................................................25
10.5 Trademarks.............................................................25
10.6 静电放电警告.......................................................... 25
10.7 术语表..................................................................... 25
11 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Device Comparison Table...............................................3
6 Pin Configuration and Functions...................................3
7 Specifications.................................................................. 4
7.1 Absolute Maximum Ratings........................................ 4
7.2 ESD Ratings............................................................... 4
7.3 Recommended Operating Conditions.........................4
7.4 Thermal Information....................................................5
7.5 Electrical Characteristics.............................................5
7.6 System Characteristics............................................... 7
7.7 Typical Characteristics................................................8
8 Detailed Description........................................................9
8.1 Overview.....................................................................9
8.2 Functional Block Diagram...........................................9
Information.................................................................... 25
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
Changes from Revision * (March 2023) to Revision A (April 2023)
Page
• 将状态从“预告信息”更改为“量产数据”....................................................................................................... 1
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English Data Sheet: SNVSCB8
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5 Device Comparison Table
JUNCTION TEMPERATURE
DEVICE
ORDERABLE PART NUMBER
PHASES
GRADE
RANGE
TPSF12C3
TPSF12C1
TPSF12C3DYYR
TPSF12C1DYYR
3
1
3
1
Commerical
Commercial
Automotive
Automotive
–40°C to 150°C
–40°C to 150°C
–40°C to 150°C
–40°C to 150°C
TPSF12C3-Q1
TPSF12C1-Q1
TPSF12C3QDYYRQ1
TPSF12C1QDYYRQ1
6 Pin Configuration and Functions
NC
VDD
1
2
3
4
5
6
7
14
IGND
13
12
11
10
9
INJ
NC
NC
SENSE1
SENSE2
SENSE3
SENSE4
COMP2
COMP1
REFGND
EN
8
Not to scale
图6-1. 14-Pin SOT-23-THIN DYY Package (Top View)
表6-1. Pin Functions
PIN
TYPE(1)
DESCRIPTION
NO.
NAME
NC
1, 3, 12
No internal connection. Tie to the GND plane on the PCB.
Power supply for IC. Bypass to IGND with a 1-µF X7R ceramic capacitor.
Sense input (power line 1, 2, 3, or neutral)
Sense input (power line 1, 2, 3, or neutral)
Sense input (power line 1, 2, 3, or neutral)
Sense input (power line 1, 2, 3, or neutral)
Enable signal to activate noise cancellation
Reference ground (Kelvin connected to IGND)
Connection 1 for external compensation circuit
Connection 2 for external compensation circuit
Injection signal output
–
P
I
2
4
VDD
SENSE1
SENSE2
SENSE3
SENSE4
EN
5
I
6
I
7
I
8
I
9
REFGND
COMP1
COMP2
INJ
G
I
10
11
13
14
I
O
G
IGND
Injection ground
(1) P = Power, G = Ground, I = Input, O = Output
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7 Specifications
7.1 Absolute Maximum Ratings
Over the recommended operating junction temperature range of –40°C to 150°C (unless otherwise noted)(1)
MIN
–0.3
–5.5
–0.3
–0.3
–0.3
–0.3
–0.3
MAX
UNIT
V
Pin voltage
Pin voltage
Pin voltage
Pin voltage
Pin voltage
Pin voltage
Pin voltage
Sink current
VDD to IGND and REFGND
SENSE1, SENSE2, SENSE3, SENSE4 to REFGND
COMP1 to IGND and REFGND
COMP2 to IGND and REFGND
INJ to IGND
18
5.5
V
5.5
V
15
V
VVDD
18
V
EN to IGND and REFGND
IGND to REFGND
V
0.3
V
INJ
150
150
150
150
mA
mA
°C
°C
Source current INJ
TJ
Operating junction temperature
Storage temperature
–40
–55
Tstg
(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If
used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully
functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.
7.2 ESD Ratings
VALUE
±2000
±500
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
Charged-device model (CDM), per ANSI/ESDA/JEDEC JS-002 (2)
V(ESD)
Electrostatic discharge
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
Over the recommended operating junction temperature range of –40°C to 150°C (unless otherwise noted)
MIN
NOM
MAX
16
UNIT
V
VVDD
VINJ
VSENSE
VEN
VDD voltage range
Output voltage range
Sense voltage range
Pin voltage
8
12
2.5
V
V
VDD –2
5
V
–5
0
16
V
IINJ
Output current range
Operating ambient temperature
Source and sink magnitude
80
mA
°C
TA
105
–40
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7.4 Thermal Information
DYY (SOT-23-THIN)
UNIT
THERMAL METRIC(1)
14 PINS
RθJA
RθJC(top)
RθJB
ψJT
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
94
43
30
1.3
28
°C/W
°C/W
°C/W
°C/W
°C/W
Junction-to-top characterization parameter
Junction-to-board characterization parameter
ψJB
(1) For more information about traditional and new thermal metrics, see Semiconductor and IC Package Thermal Metrics application
report.
7.5 Electrical Characteristics
Limits apply over the junction temperature (TJ) range of –40°C to 150°C, unless otherwise stated. Minimum and maximum
limits are specified through test, design or statistical correlation. Typical values represent the most likely parametric norm at
TJ = 25°C, and are provided for reference purposes only. Unless otherwise stated, the following conditions apply: VVDD = 12
V(1)
.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
SUPPLY
SENSE1, SENSE2, SENSE3, and
SENSE4 grounded, VEN = 5 V, 8 V ≤
6.25
11
13.2
25.5
mA
V
VDD ≤16 V
IQ
VDD quiescent current
SENSE1, SENSE2, SENSE3, and
SENSE4 grounded, VEN = 5 V, VVDD
12 V, TJ = 25°C
=
13.2
55
15.5
ISD
VDD shutdown supply current
VEN = 0 V
µA
SUPPLY VOLTAGE UVLO
VVDD-UV-R
VVDD-UV-F
VVDD-UV-HYS
ENABLE
VEN-H
UVLO rising threshold
VVDD rising
VVDD falling
7.35
6.4
7.7
6.7
7.95
7.0
V
V
V
UVLO falling threshold
UVLO hysteresis
0.97
EN voltage high
2.2
V
V
VEN-L
EN voltage low
0.8
REN
EN pin pull-up resistance to VDD
EN input leakage current
VEN = 0 V
850
840
kΩ
nA
IEN-LKG
VEN = 12 V
INPUT FILTER NETWORK
CSEN = 2 µF(2), 60 Hz
CSEN = 2 µF(2), 50 kHz
CSEN = 2 µF(2), 500 kHz(3)
CSEN = 2 µF(2), 1 MHz(3)
–44
–4
–2
–1
Gain from shorted power lines through
single sense cap, CSEN, to COMP1 vs.
REFGND
ACM
dB
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7.5 Electrical Characteristics (continued)
Limits apply over the junction temperature (TJ) range of –40°C to 150°C, unless otherwise stated. Minimum and maximum
limits are specified through test, design or statistical correlation. Typical values represent the most likely parametric norm at
TJ = 25°C, and are provided for reference purposes only. Unless otherwise stated, the following conditions apply: VVDD = 12
V(1)
.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
SENSE1 shorted to SENSE2,
SENSE3 shorted to SENSE4,
CSEN1 = CSEN3 = 1 µF(2), 60 Hz
–71
SENSE1 shorted to SENSE2,
SENSE3 shorted to SENSE4,
CSEN1 = CSEN3 = 1 µF(2), 1 kHz
–59
–42
–43
–35
SENSE1 shorted to SENSE2,
SENSE3 shorted to SENSE4,
CSEN1 = CSEN3 = 1 µF(2), 500 kHz(3)
Gain from differential signal applied to
SENSE lines to COMP1 vs. REFGND
ADM
dB
SENSE1 shorted to SENSE2,
SENSE3 shorted to SENSE4,
CSEN1 = CSEN3 = 1 µF(2), 1 MHz(3)
SENSE1 shorted to SENSE2,
SENSE3 shorted to SENSE4,
CSEN1 = CSEN3 = 1 µF(2), 10 MHz(3)
AMPLIFIER
ADC
DC gain
52
58
113
1
69
dB
MHz
MHz
V
fBW
Unity gain bandwidth(3)
40 dB gain frequency
COMP1 offset voltage
fBW40
VOFST
2
Maximum output voltage for linear
operation(3)
VVDD
–
2
VINJ-MAX
VINJ-MIN
COMP2 to INJ gain > 36 dB
COMP2 to INJ gain > 36 dB
V
V
Minimum output voltage for linear
operation(3)
2.5
80
mA
mA
VINJ = VVDD –2 V
IINJ-MAX-OP
INJ current at linearity limits(3)
VINJ = VIGND + 2.5 V
–80
PSRR
10 pF in parallel with the series
combination of 10 nF and 2 kΩ
between COMP1 and COMP2, 10 kHz
PSRR10
0
6
dB
ms
10 pF in parallel with the series
combination of 10 nF and 2 kΩ
between COMP1 and COMP2, 100
kHz
PSRR100
STARTUP
Time from VDD = EN applied until
output valid
tW
Startup delay(3)
43
tSU
tSD
EN high to valid output
42
ms
µs
EN low to stop output signal
0.32
THERMAL SHUTDOWN
TJ-SHD
Thermal shutdown threshold(3)
TJ-HYS
Thermal shutdown hysteresis(3)
Temperature rising
175
20
°C
°C
(1) MIN and MAX limits are 100% production tested at 25ºC unless otherwise specified. Limits over the operating temperature range
verified through correlation using Statistical Quality Control (SQC) methods. Limits are used to calculate Average Outgoing Quality
Level (AOQL).
(2) Capacitance chosen for effective test only. Do not use this capacitance in applications.
(3) Parameter specified by design, statistical analysis and production testing of correlated parameters.
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7.6 System Characteristics
The following specifications apply only to the typical applications circuit, with nominal component values. Specifications in the
typical (TYP) column apply to TJ = 25°C and VVDD = 12 V only. Specifications in the minimum (MIN) and maximum (MAX)
columns apply to the case of typical components over the temperature range of TJ = –40°C to 150°C. These specifications
are not ensured by production testing.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY
ISUPPLY
Input supply current with INJ loaded
15
mA
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7.7 Typical Characteristics
VVDD = VEN = 12 V, unless otherwise specified.
80
60
40
20
0
30
25
20
15
10
5
VVDD = 8 V
VVDD = 12 V
VVDD = 16 V
0
-50
-25
0
25
50
75
100
125
150
-50
-25
0
25
50
75
100
125
150
Junction Temperature (°C)
Junction Temperature (°C)
VEN = 0 V
图7-2. Quiescent Supply Current vs. Temperature
图7-1. Shutdown Supply Current vs. Temperature
10
2
8
6
4
2
1.5
1
0.5
Rising
Falling
Rising
Falling
0
-50
0
-50
-25
0
25
50
75
100
125
150
-25
0
25
50
75
100
125 150
Junction Temperature (°C)
Junction Temperature (°C)
图7-4. EN Threshold vs. Temperature
图7-3. VDD UVLO Thresholds vs. Temperature
0
0
-20
-40
-60
-80
-20
-40
-60
-80
0.01
0.1
1
10
100
1000
10000
1
10
100
1000
10000
Frequency (kHz)
Frequency (kHz)
图7-5. Input Filter Response –Common Mode
图7-6. Input Filter Response –Differential Mode
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8 Detailed Description
8.1 Overview
The TPSF12C3 is an active electromagnetic interference (EMI) filter that is designed to reduce common-mode
(CM) conducted emissions in off-line power converter systems. Using a VSCI architecture, the device senses the
high-frequency noise on each power line using a set of Y-rated capacitors, CSEN1-4, then injects noise-canceling
currents back into the power lines using a Y-rated capacitor, CINJ, along with a damping circuit that ensures
stability. The device includes integrated filtering, compensation and protection circuitry.
The TPSF12C3 provides a low-impedance shunt path for CM noise in the frequency range of interest for EMI
measurement. This feature can achieve approximately 15 to 30 dB of CM attenuation over the applicable
frequency range (for example, 100 kHz to 3 MHz) helping to reduce the size of CM chokes, typically the largest
components in the filter.
The TPSF12C3 operates over a supply voltage range of 8 V to 16 V and can withstand 18 V. The device
features include:
• Internal circuitry that simplifies compensation and design
• Built-in supply voltage UVLO to ensure proper operation
• Built-in thermal shutdown protection
• An EN input that allows power saving when the system is idling
The active EMI filter circuit significantly reduces EMI filter cost, size, and weight, while helping to meet CISPR 11
and CISPR 32 Class B limits for conducted emissions. Leveraging a pin arrangement designed for simple layout
that requires relatively few external components, the TPSF12C3 is specified for maximum ambient and junction
temperatures of 105°C and 150°C, respectively.
8.2 Functional Block Diagram
Inject stage
Neutral
INJ
VDD
REF
EN
REFGND
IGND
GND
GND
GND
8.3 Feature Description
8.3.1 Active EMI Filtering
A compact and efficient design of the input EMI filter is one of the main challenges in high-density switching
regulator design and is critical to achieving the full benefits of electrification in industrial, enterprise, aerospace
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and other highly constrained system environments. For AC-input applications in general, CM chokes and Y-
capacitors provide CM filtering, whereas the leakage inductance of the CM chokes and the X-capacitors provide
DM filtering. However, CM filters for such applications may have limited Y-capacitance due to touch-current
safety requirements and thus require large-sized CM chokes to achieve the requisite attenuation – ultimately
resulting in filter designs with bulky, heavy and expensive passive components. Fortunately, the deployment of
active filter circuits enable more compact filter solutions for next-generation power conversion systems.
8.3.1.1 Schematics
图 8-1 and 图 8-2 show schematics for conventional two-stage passive EMI filters with and without neutral,
respectively, in kilowatt-scale, grid-connected applications. L, N and PE refer to the respective live, neutral and
protective earth connections. Multistage filters as shown provide high roll-off and are widely used in high-power
AC line applications where CM noise is often more challenging to mitigate than DM noise. The low-order
switching harmonics usually dictate the size of the reactive filter components based on the required corner
frequency (or multiple corner frequencies in multistage designs).
Also included in 图 8-1 and 图 8-2 are the corresponding active filter designs. The active circuit replaces the
bank of Y-capacitors positioned between the CM chokes with a three-phase AEF circuit using the TPSF12C3 to
provide a lower impedance shunt path for CM currents. The sense pins of the TPSF12C3 interface with the
power lines using a set of Y-rated sense capacitors, typically 680 pF, and feed into an internal high-pass filter
and signal combiner. The IC rejects both line-frequency (50-Hz or 60-Hz) AC voltage as well as DM
disturbances, while amplifying high-frequency CM disturbances and maintaining closed-loop stability using an
external tunable damping circuit.
LCM1
LCM2
Passive filter circuit
L1
CX1
CX2
CX3
CX4
CX5
CX6
CX7
CX8
CX9
CY5 CY6 CY7 CY8
L2
3-phase
AC/DC
regulator
3-phase
AC supply
L3
N
Chassis
PE
CY1 CY2 CY3 CY4
4-5 times
lower
4-5 times
lower
inductance
inductance
LCM1-AEF
LCM2-AEF
Active filter circuit
L1
L2
CX1
CX2
CX3
CX4
CX5
CX6
CINJ
CX7
CX8
3-phase
AC/DC
regulator
3-phase
AC supply
L3
CX9
N
Chassis
PE
CSEN3
CSEN1
CG1
RG
CY1 CY2 CY3 CY4
CSEN4
CSEN2
CG2
CD3
CD1
RD3
COMP1
SENSE1
COMP2
INJ
RD1A
DINJ
RD1
SENSE2
TPSF12C3
= 3-phase source
EN
VDD
CD2
RD2
SENSE3
= 3-phase AC/DC
12 V
CVDD
SENSE4
REFGND
= Three-phase AEF IC
= Sense, inject capacitors
IGND
图8-1. Circuit Schematic of a Three-Phase, Four-Wire Passive Filter and Corresponding Active Filter
Solution for CM Attenuation
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Passive filter circuit
LCM1
LCM2
L1
CX1
CX2
CX3
CX4
CX5
CX6
CX7
3-phase
AC/DC
regulator
3-phase
AC supply
L2
CX8
L3
CX9
PE
Chassis
CY1 CY2 CY3
CY4 CY5 CY6
4-5 times
lower
inductance
4-5 times
lower
inductance
LCM1-AEF
LCM2-AEF
Active filter circuit
L1
CX1
CX2
CX3
CX4
CX5
CX6
CINJ
CX7
CX8
CX9
3-phase
AC/DC
regulator
3-phase
AC supply
L2
L3
Chassis
PE
CSEN3
CSEN1
CG1
RG
CY1 CY2 CY3
CSEN2
CG2
CD3
CD1
RD3
COMP1
SENSE1
COMP2
INJ
RD1A
DINJ
RD1
SENSE2
TPSF12C3
= 3-phase source
= 3-phase AC/DC
EN
VDD
CD2
RD2
SENSE3
12 V
CVDD
SENSE4
REFGND
= Three-phase AEF IC
IGND
= Sense, inject capacitors
图8-2. Circuit Schematic of a Three-Phase, Three-Wire Passive Filter and Corresponding Active Filter
Solution for CM Attenuation
The X-capacitors placed between the two CM chokes effectively provide a low-impedance path between the
power lines from a CM standpoint, typically up to low-MHz frequencies. This allows current injection onto one
power line, typically neutral, using only one inject capacitor. If the three-phase filter is a three-wire system
without neutral as shown in 图 8-2, the SENSE4 pin of the TPSF12C3 ties to ground and the inject capacitor
couples through a star-point connection of the X-capacitors.
8.3.2 Capacitive Amplification
An AEF circuit for CM noise mitigation fundamentally either amplifies the apparent inductance of a CM choke or
the apparent capacitance of a Y-capacitor over the frequency range of interest. A VSCI AEF circuit configured for
CM attenuation uses an amplifier stage as a capacitive multiplier of the inject capacitor, CINJ. This higher value
of the active capacitance supports lower values for the CM chokes to achieve a target attenuation. More
specifically, the amplified Y-capacitance enables a reduction of each CM choke inductance by up to 80% (while
keeping the filter corner frequencies effectively unchanged), resulting in lower size, weight, and cost of the CM
chokes.
Capacitive multiplication of the inject capacitance occurs over a relevant frequency range for low- and mid-
frequency emissions, while not impacting the value at low frequency applicable for touch current measurement.
The total capacitance of the sense and inject capacitors (highlighted in yellow in 图 8-1 and 图 8-2) is kept less
than or equal to that of the replaced Y-capacitors in the equivalent passive filter, which results in the total line-
frequency leakage current remaining effectively unchanged or reduced.
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8.3.3 Integrated Line Rejection Filter
The TPSF12C3 has a built-in input line filter. The high-pass filter stage attenuates the large line-frequency (50
Hz or 60 Hz) components of the power-line voltages, both line-to-line and line-to-earth, thus maximizing the
useful voltage range of the low-voltage output at INJ.
The circuit also sums the signals in a CM combiner, rejecting the DM components of the voltages and extracting
a signal that represents the CM noise signature without line-frequency components. Combined with the action of
the high-pass filter, the net result is that the COMP1 pin voltage represents the sensed high-frequency CM noise
that the device attempts to cancel. Because the entire filter is integrated in the device, matching is better than
what can be achieved using discrete components.
8.3.4 Compensation
The TPSF12C3 contains partial internal compensation that, when combined with two capacitors and a resistor
between COMP1 and COMP2, forms a lead-lag network. This internal network allows fewer external
components to be used.
8.3.5 Remote Enable
The TPSF12C3 has an enable input, EN, that allows the device to be shut down, drastically reducing power
consumption during intervals when EMI mitigation is not required. The typical quiescent current consumption is
13.2 mA and 55 μA when the device is enabled and disabled, respectively. Because many designs may not use
this feature, a 850-kΩ pullup resistor connects internally between VDD and EN, allowing the EN pin to be left
open.
In addition, INJ is pulled low when the device is disabled to reduce the effective resistance in series with CINJ
.
8.3.6 Supply Voltage UVLO Protection
To ensure that the TPSF12C3 operates safely while VDD is powered on and off as well as during brownout
conditions, this device has a built-in UVLO protection to provide predictable behavior while VDD is below its
operating voltage. UVLO releases when the VDD voltage exceeds 7.7 V (typical), allowing normal operation.
UVLO engages if the VDD voltage falls below approximately 6.7 V (typical). There is approximately 1 V of UVLO
hysteresis.
8.3.7 Thermal Shutdown Protection
The TPSF12C3 provides built-in overtemperature protection that shuts down the device if the junction
temperature exceeds approximately 175°C. After the junction temperature decreases by approximately 20°C,
the device restarts. This process is repeated until the ambient temperature or power dissipation is reduced. The
device has a relatively low thermal time constant and can cycle into and out of thermal shutdown at a high rate
during a sustained overtemperature condition.
8.4 Device Functional Modes
8.4.1 Shutdown Mode
The EN pin provides ON and OFF control for the TPSF12C3. When the EN voltage is below approximately 0.8
V, the device is in shutdown mode. Most internal circuitry is shutdown. The quiescent current in shutdown mode
drops to 55 µA (typical). The TPSF12C3 also employs VDD internal undervoltage protection. If the VDD voltage
is below its UVLO threshold, the device remains off. The INJ output pulls to ground while in shutdown mode.
8.4.2 Active Mode
The TPSF12C3 is in active mode when VVDD is above its UVLO threshold, EN is high, and there is no
overtemperature fault. The simplest way to enable operation is to connect EN to VDD, which allows startup when
the applied supply voltage exceeds the UVLO threshold voltage. In this mode, the device amplifies signals on
COMP2 and outputs the amplified signal on the INJ pin.
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9 Applications and Implementation
备注
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
9.1 Application Information
The TPSF12C3 common-mode AEF IC helps to improve the CM EMI signature of three-phase AC power
systems. The device provides a very low impedance path for CM noise in the frequency range of interest for EMI
measurement and helps to meet prescribed limits for EMI standards, such as:
• CISPR 11, EN 55011 –Industrial, Scientific and Medical (ISM) applications
• CISPR 25, EN 55025 –Automotive applications
• CISPR 32, EN 55032 –Multimedia applications
To expedite and streamline the process of designing of a TPSF12C3-based solution, a comprehensive
TPSF12C3 quickstart calculator is available by download to assist the system designer with component selection
for a given application.
9.2 Typical Applications
For the circuit schematic, bill of materials, PCB layout files, and test results of a TPSF12C3-powered
implementation, see the TPSF12C3 EVM.
9.2.1 Design 1 –AEF Circuit for Grid Infrastructure Applications
图 9-1 shows a schematic diagram of a 10-kW high-density AC/DC regulator with conventional two-stage
passive EMI filter. The CM chokes and Y-capacitors provide CM filtering, whereas the leakage inductance of the
CM chokes and the X-capacitors provide DM filtering. Similar to TI reference designs TIDA-01606, the circuit
uses a three-phase power-factor correction (PFC) stage with SiC power MOSFETs.
The PFC stage runs at a fixed switching frequency of 100 kHz. Even though the use of GaN or SiC power
switches enables a high power density, the conventional passive EMI filter typically occupies over 20% of the
total solution size.
LCM1
LCM2
L1
L2
CX1
CX2
CX3
CX4
CX5
CX6
CX7
CX8
CX9
CY5 CY6 CY7 CY8
3-phase
AC/DC
regulator
3-phase
AC supply
L3
N
Chassis
PE
CY1 CY2 CY3 CY4
图9-1. Circuit Schematic of a Three-phase AC/DC Regulator With a Conventional Two-Stage Passive EMI
Filter
The AC/DC stage increases the CM EMI signature based on the high dv/dt of the SiC power switches as well as
the various switch-node parasitic capacitances to chassis ground.
This application example replaces the four Y-capacitors, designated as CY1, CY2, CY3 and CY4 in 图 9-1, with a
three-phase AEF circuit using the TPSF12C3. See 图 9-2. The AEF circuit provides effective capacitive
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multiplication of the inject capacitor, which reduces the inductance values to maintain the target LC corner
frequencies and thus the size, weight, and cost of the CM chokes, now designated as LCM1-AEF and LCM2-AEF
.
The total capacitance of the sense and inject capacitors is kept less than or equal to that of the replaced Y-
capacitors, which results in the total line-frequency leakage current remaining effectively unchanged or reduced.
LCM1-AEF
LCM2-AEF
AC mains
L1
CX1
CX4
CX7
L2
3-phase
AC/DC
regulator
3-phase
CX8
CX2
CX5
AC supply
L3
CX3
CX6
CX9
N
Chassis
PE
CY1–CY4
CG1
CG2
RG
CSEN3
CSEN1
CINJ
CSEN4
CSEN2
U1
CD3
CD1
RD3
COMP1
SENSE1
COMP2
RD1A
INJ
EN
RD1
DINJ
SENSE2
SENSE3
SENSE4
REFGND
= 3-phase source
= 3-phase AC/DC
= 3-phase AEF IC
TPSF12C3
From MCU
CD2
RD2
Chassis-referred
power supply
VDD
CVDD
IGND
= Sense, inject capacitors
Chassis (PE)
图9-2. Circuit Schematic of a Three-phase Regulator With AEF Circuit Connected
9.2.1.1 Design Requirements
表 9-1 shows the intended operating parameters for this application example. Also included is the total Y-rated
filter capacitance that is allowed in order to meet the applicable touch current fault specification.
表9-1. Design Parameters
DESIGN PARAMETER
VALUE
230 V L-N or 400 V L-L (RMS)
47 Hz to 63 Hz
600 V to 1 kV
18 A
AC input voltage
AC input line frequency
DC output voltage range
DC output current (max)
Rated output power
10 kW
AC/DC stage switching frequency
Total Y-rated filter capacitance (maximum)
100 kHz
10 nF
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9.2.1.2 Detailed Design Procedure
表 9-2 gives the selected component values, which are the same as those used in the TPSF12C3 EVM. This
design uses a TVS diode placed at the low-voltage side of the inject capacitor for clamping during input surge
conditions.
表9-2. AEF Circuit Components for Application Circuit 1
REFERENCE
DESIGNATOR
QTY
SPECIFICATION
MANUFACTURER(1)
PART NUMBER
CSEN1, CSEN2
CSEN3, CSEN4
,
4
Capacitor, ceramic, 680 pF, 300 VAC, Y2
MuRata
DE2B3SA681KN3AX02F
DE2E3SA472MA3BX02F
(2)
(2)
CINJ
1
1
1
1
1
1
1
1
1
1
1
1
1
Capacitor, ceramic, 4.7 nF, 300 VAC, Y2
Capacitor, ceramic, 4.7 nF, 50 V, 0603
Capacitor, ceramic, 22 nF, 50 V, 0603
Capacitor, ceramic, 4.7 nF, 50 V, 0603
Capacitor, ceramic, 10 nF, 50 V, 0603
Capacitor, ceramic, 10 pF, 50 V, 0603
Capacitor, ceramic, 1 µF, 25 V, X7R, 0603
TVS diode, bidirectional, 24 V, SOD-323
Resistor, 1 kΩ, 0.1 W, 0603
MuRata
Various
Various
Various
Various
Various
Various
Eaton
(2)
CD1
–
(2)
CD2
–
CD3
CG1
CG2
CVDD
DINJ
RD1
RD1A
RD2
RD3
RG
–
–
–
–
STS321240B301
Various
Various
Various
Various
Various
–
–
–
–
–
Resistor, 50 Ω, 0.1 W, 0603
Resistor, 200 Ω, 0.1 W, 0603
Resistor, 698 Ω, 0.1 W, 0603
Resistor, 1.5 kΩ, 0.1 W, 0603
TPSF12C3 common-mode AEF IC for three-phase AC
power systems
U1
1
Texas Instruments
TPSF12C3DYYR
(1) See the Third-Party Products Disclaimer.
(2) Check the effective capacitance value based on the applied voltage and operating temperature.
More generally, the TPSF12C3 AEF IC is designed to operate with a wide range of passive filter components
and system parameters.
9.2.1.2.1 Sense Capacitors
The sense pins of the TPSF12C3 feed into a high-pass filter and signal combiner within the IC, which rejects the
line-frequency and DM components of the power line voltages, extracting the high-frequency CM component.
The sense pins externally interface to the power lines using Y-rated capacitors, designated as CSEN1, CSEN2
,
CSEN3 and CSEN4 in Figure 9-2. Choose Y2-rated sense capacitors of 680 pF, 300 VAC in this application to
establish voltages at the SENSE pins of less than 1-V peak-to-peak when operating at maximum line voltage.
9.2.1.2.2 Inject Capacitor
The INJ node interfaces to a power line using a Y-rated capacitor, designated as CINJ in Figure 9-2. Choose a
Y2-rated inject capacitor of 4.7 nF, 300 VAC in this design to accommodate an AC voltage swing at INJ with at
least a 2.5-V margin of headroom from the positive and negative supply rails. The INJ pin biases at half the VDD
supply voltage. Assuming a 12-V supply rail and allowing 2.5 V of upper and lower headroom, this implies that a
swing of ±3.5 V is available around the DC operating midpoint.
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备注
Many commercially available Y-rated capacitors yield an effective capacitance that derates
significantly with operating temperature. The effective capacitance value can be much lower than the
nameplate capacitance, particularly when operating near the boundaries of the rated operating
temperature range. Select the dielectric of the sense and inject capacitors to meet the required
temperature range. Depending on the implementation, lower than expected sense and inject
capacitances can affect the stability performance.
9.2.1.2.3 Compensation Network
The CM noise signal derived from the internal sensing filter and summation network of the TPSF12C3 is
internally inverted and amplified by a gain stage. The components between the COMP1 and COMP2 pins of the
IC, designated as as RG, CG1 and CG2 in Figure 9-2, set the gain characteristic.
More specifically, resistor RG establishes a high midband AEF gain at frequencies where EMI filtering is
required. Capacitor CG1 increases the impedance of that branch at low frequencies, which sets a lower AEF
amplifer gain to further reject line-frequency components appearing at the INJ output. Capacitor CG2 preserves
gain at high frequencies, which extends the AEF bandwidth.
Choose a value for RG between 1 kΩand 2 kΩ. A resistance of 1.5 kΩis a common choice and selected in this
example to set a midband gain of 50 dB. Choose capacitances for CG1 and CG2 of 10 nF and 10 pF, respectively,
which establishes a gain rolloff below approximately 10 kHz for line- and low-frequency attenuation.
9.2.1.2.4 Injection Network
The components connected between the INJ pin and inject capacitor establish a damped injection network.
Damping is specifically required to manage resonance between the CM choke inductance and inject
capacitance, which manifests in the AEF loop gain as a pair of complex zeros.
图 9-3 highlights three specific RC branches: RD1, RD1A and CD1 form one branch from the INJ pin; RD2 and CD2
in series connect to GND; RD3 and CD3 in parallel connect to the inject capacitor.
LCM1-AEF
LCM2-AEF
L1
L2
3-phase
AC/DC
regulator
3-phase
AC source
L3
N
Chassis
PE
CX1–CX3
CX4–CX6
CX7–CX9
CY1–CY4
CG1
RG
CSEN1–CSEN4
CINJ
CG2
ZD3
CD3
U1
ZD1
RD1A
RD3
COMP1
SENSE1
COMP2
CD1
INJ
RD1
DINJ
SENSE2
SENSE3
SENSE4
REFGND
ZD2
CD2
RD2
= ZD1 branch
EN
VDD
= ZD2 branch
= ZD3 branch
12 V
CVDD
IGND
TPSF12C3
Chassis (PE)
图9-3. Injection Network
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Based on the injection mechanism, the AEF circuit presents a low shunt impedance to CM noise. Given the
three damping impedance branches highlighted in 图9-3, 方程式1 approximates the AEF impedance as:
(1)
where the term GAEF is the gain from the power lines to the INJ node (see the TPSF12C3 quickstart calculator
for related detail).
方程式 1 shows that the impedance ZINJ appears in series with ZD3 and a parallel combination of ZD1 and ZD2.
Furthermore, the gain GAEF is reduced by the voltage divider ratio between ZD2 and ZD1. These effects combine
to increase the effective impedance of the AEF and hence reduce its attenuation performance, thus illustrating a
trade-off between performance and stability.
So while an injection network is needed for stability, it also adds impedance in series with the inject capacitor,
thus compromising EMI mitigation. As shown below, the user can minimize the impact on performance with
careful and appropriate design.
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Increasing
frequency
Low-frequency
equivalent circuit
Mid-frequency
equivalent circuit
CSEN1–CSEN4
CSEN1–CSEN4
CINJ
CINJ
CG1
RG
RD3
RD3
COMP1
COMP2
COMP1
SENSE1
COMP2
CD1
SENSE1
SENSE2
SENSE3
SENSE4
REFGND
INJ
INJ
RD1
SENSE2
SENSE3
SENSE4
REFGND
EN
EN
VDD
CD2
CD2
VDD
12 V
12 V
IGND
IGND
TPSF12C3
TPSF12C3
RC filter (RD1, CD2) provides compensation
at low frequency for stability
The impedance of CD1 shunts that of RD1 as
frequency increases. Lower impedance in series
with CINJ helps AEF performance. CD2 > CD1
RD3 in series with inject capacitor CINJ
provides damping at low frequency
Increasing
frequency
Increasing
frequency
Highest-frequency
equivalent circuit
High-frequency
equivalent circuit
CSEN1–CSEN4
CSEN1–CSEN4
CINJ
CINJ
RG
CG2
CD3
CD3
CD1
COMP1
COMP2
COMP1
SENSE1
COMP2
RD1A
SENSE1
SENSE2
SENSE3
SENSE4
REFGND
INJ
INJ
VINJD
SENSE2
SENSE3
SENSE4
REFGND
EN
VDD
EN
VDD
12 V
RD2
12 V
RD2
IGND
IGND
TPSF12C3
TPSF12C3
At high frequencies, the impedance of RD1A
exceeds that of CD1. RD1A provides damping and
improves the phase margin of the AEF loop
At higher frequency, the impedance of RD2 exceeds
that of CD2, resulting in RD2 and CD1 forming a high-
pass filter, which maximizes VINJD
As frequency increases, the impedance of CD3 shunts that
of RD3, which helps attenuation performance. CD3ꢀꢁ CINJ
图9-4. Dominant Components of the Injection Network vs Frequency
Illustrated in 图 9-4, at low frequencies in the range of 5 kHz to 50 kHz, components RD1 and CD2 provide
compensation and RD3 damps the effects of LC resonance. At higher frequencies (above 10 kHz), the dominant
component impedance of each branch transitions to enable better attenuation performance:
• RD1 transitions to CD1
• CD2 transitions to RD2
• RD3 transitions to CD3
Finally, CD1 transitions to RD1A if needed for phase margin of the AEF loop at high frequencies, typically above
100 kHz. When viewed in a clockwise direction, 图 9-4 shows these transitions in sequence as frequency
increases.
Below are basic guidelines to select the component values for the injection network:
1. The undamped loop gain characteristic is likely to be unstable within the range of 5 kHz to 50 kHz, which, as
mentioned previously, relates to an LC resonance between CM choke inductance and inject capacitance.
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Observe from circuit simulation –or by using the TPSF12C3 quickstart calculator –the frequency,
fLFstability, at which the phase crosses –180° with positive gain, indicating negative gain margin.
2. Choose a corner frequency with RD1 and CD2 equal to one fifth of the instability frequency:
(2)
Assigning RD1 = 1 kΩand assuming instablity at 35 kHz, use 方程式3 to find a value for the capacitance of
CD2:
(3)
3. Select CD1 < CD2, where a typical choice is CD1 = CD2/5 = 4.7 nF.
4. Choose the resistance of RD2 such that the RD2, CD2 corner frequency is equal to that of RD1, CD1:
(4)
5. Select the resistance of RD3 to damp the resonance around the instability frequency, fLFstability
.
• A typical choice for RD3 is 500 Ωto 1 kΩ.
• Assign CD3 equal to CINJ or a suitable value such that the RD3, CD3 corner frequency is less than
switching frequency.
• A lower resistance for RD3 results in more damping but at the penalty of reduced high-frequency
attenuation (or forces a higher value for CD3 to maintain the applicable corner frequency below the
switching frequency).
6. Select a resistance for RD1A of 50 Ωto improve the phase margin of the AEF loop (if needed).
9.2.1.2.5 Surge Protection
EMI filter designs, both passive and active, typically use MOVs connected from the power lines to chassis
ground to clamp surge voltage transients. While the sense pins of the TPSF12C3 have internal clamp protection,
the higher value of inject capacitance produces larger currents during surge events and thus requires external
protection. Place a bidirectional TVS diode on the low-voltage side of the inject capacitor with standoff voltage of
24 V. Using the SOD-323 packaged device given in 表 9-2, clamping occurs at 40 V and 50 V with surge
currents of 1 A and 8 A, respectively.
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9.2.1.3 Application Curves
Unless otherwise indicated, VVDD = VEN = 12 V.
–29dB
AEF disabled
AEF enabled
备注
A high DM noise signature may mask improvement in CM noise performance related to AEF. A
reduction of CM choke inductance may also reduce leakage inductance, which could impact DM noise
attenuation. Install higher X-capacitance or a discrete DM filter inductor to manage DM attenuation as
needed. Also, use a DM-CM noise splitter to isolate the CM component of the measured total noise.
图9-5. CISPR 32 Class B EMI Mitigation Result with AEF On and Off (EN Tied High and Low)
VLINE 500 V/DIV
VINJ-C 20 V/DIV
VLINE 500 V/DIV
VINJ-C 20 V/DIV
INJ TVS diode clamps
Negative undershoot
eventually decays
SENSE internal
protection clamps
INJ TVS diode clamps
SENSE internal
VSENSE1 10 V/DIV
ISENSE1 2 A/DIV
VSENSE1 10 V/DIV
ISENSE1 2 A/DIV
protection clamps
200 µs/DIV
1 µs/DIV
(a)
(b)
图9-6. IEC 61000-4-5 Positive Surge, 5-kV Single Strike –1 µs/div (a), 200 µs/div (b)
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Positive overshoot
eventually decays
VLINE 500 V/DIV
VINJ-C 20 V/DIV
VLINE 500 V/DIV
VINJ-C 20 V/DIV
INJ TVS diode clamps
INJ TVS diode clamps
VSENSE1 10 V/DIV
ISENSE1 2 A/DIV
VSENSE1 10 V/DIV
ISENSE1 2 A/DIV
SENSE internal
SENSE internal
protection clamps
protection clamps
200 ꢀs/DIV
1 ꢀs/DIV
(a)
(b)
图9-7. IEC 61000-4-5 Negative Surge, 5-kV Single Strike –1 µs/div (a), 200 µs/div (b)
VLINE 500 V/DIV
VSENSE1 10 V/DIV
VLINE 500 V/DIV
VSENSE1 10 V/DIV
ISENSE1 2 A/DIV
IINJ 10 A/DIV
ISENSE1 2 A/DIV
IINJ 10 A/DIV
10 s/DIV
10 s/DIV
(a)
(b)
图9-8. IEC 61000-4-5 Surge, 5-kV Repetitive Strike at 10-Second Intervals –Positive (a), Negative (b)
备注
The surge test circuit used MOVs (Littelfuse V20E300P) connected from line and neutral filter inputs
to chassis ground. See 图9-11.
9.3 Power Supply Recommendations
The TPSF12C3 AEF IC operates over a wide supply voltage range of 8 V to 16 V (typically 12 V) and is
referenced to chassis ground of the system. The characteristics of this VDD bias supply must be compatible with
the Absolute Maximum Ratings and Recommended Operating Conditions in this data sheet. In addition, the VDD
supply must be capable of delivering the required supply current to the loaded AEF circuit.
The supply rail can already be present in the system or can be derived using a low-cost solution with an auxiliary
winding from an isolated flyback regulator. Connect a ceramic capacitor of at least 1 µF close to the VDD and
IGND pins of the TPSF12C3. Ensure that the ripple voltage at VDD is less than 20 mV peak-to-peak to avoid
low-frequency noise amplification.
9.4 Layout
Proper PCB design and layout is important in active EMI circuits (where high regulator voltage and current slew
rates exist) to achieve reliable device operation and design robustness. Furthermore, the EMI performance of
the design depends to a large extent on PCB layout.
9.4.1 Layout Guidelines
The following list summarizes the essential guidelines for PCB layout and component placement to optimze AEF
performance. 图 9-9 and 图 9-10 show a recommended layout for the TPSF12C3 circuit specifically with
optimized placement and routing of the IC and small-signal components. 图 9-11 shows an example of a three-
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phase, four-wire filter board design with CM chokes, X-capacitors, Y-capacitors, protection components
(varistors and X-capacitor discharge resistors), and AEF circuit.
• Position the sense and inject capacitors between the CM chokes near the X-capacitor that couples the
injected signal to the other power lines. Avoid placement close to the CM choke windings that may result in
parasitic coupling to the sense and inject capacitors.
• Maintain adequate clearance spacing between high-voltage and low-voltage traces. As an example, 图9-11
has 150 mils (3.8 mm) copper-to-copper spacing from power lines (lives and neutral) to chassis ground.
• Route the sense lines S1, S2, S3 and S4 away from the INJ line. Avoid coupling between the sense and
inject traces.
• Use a solid ground connection between the TPSF12C3 and the filter board. Minimize parasitic inductance
from the AEF circuit return to the chassis ground connections on the board.
• Place a ceramic capacitor close to VDD and IGND. Minimize the loop area to the VDD and IGND pins.
• Place the compensation network copnponents close to the COMP1 and COMP2 pins. Reduce noise
sensitivity of the feedback compensation network path by placing components RG, CG1 and CG2 close to the
COMP pins. COMP2 is the inverting input to the AEF anplifier and represents a high-impedance node
sensitive to noise.
• Provide enough PCB area for proper heatsinking. Use sufficient copper area to acheive a low thermal
impedance. Provide adequate heatsinking for the TPSF12C3 to keep the junction temperature below 150°C.
A top-side ground plane is an important heat-dissipating area. Use several heat-sinking vias to connect
REFGND (pin 9) and IGND (pin 14) to ground copper on other layers.
9.4.2 Layout Example
图9-9. Typical Layout
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Legend
Top layer copper
Layer-2 GND plane
Top solder
Route sense traces S1, S2,
S3 and S4 away from the
INJ trace
Keep the VDD capacitor
close to the VDD pin
Place the compensation
network close to the
COMP1 and COMP2 pins
Keep the damping network
close to the INJ pin
INJ pin probe point
图9-10. Typical Top-Layer Design
Legend
Top layer copper
Bottom layer copper
Top solder
图9-11. Typical Three-Phase Filter Board Design With AEF
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10 Device and Documentation Support
10.1 Device Support
10.1.1 第三方产品免责声明
TI 发布的与第三方产品或服务有关的信息，不能构成与此类产品或服务或保修的适用性有关的认可，不能构成此
类产品或服务单独或与任何TI 产品或服务一起的表示或认可。
10.1.2 Development Support
All AEF devices from the family shown in 表 10-1 are rated for a maximum junction temperature of 150°C and
are functional safety-capable. See the Texas Instruments power-supply filter ICs landing page for more detail.
表10-1. Common-mode AEF IC Family
JUNCTION TEMPERATURE
DEVICE
ORDERABLE PART NUMBER
PHASES
GRADE
RANGE
TPSF12C3
TPSF12C1
TPSF12C3DYYR
TPSF12C1DYYR
3
1
3
1
Commercial
Commercial
Automotive
Automotive
–40°C to 150°C
–40°C to 150°C
–40°C to 150°C
–40°C to 150°C
TPSF12C3-Q1
TPSF12C1-Q1
TPSF12C3QDYYRQ1
TPSF12C1QDYYRQ1
For development support see the following:
• TPSF12C3 quickstart calculator
• TPSF12C3 EVM Altium layout source files
• TPSF12C3 PSPICE for TI and SIMPLIS simulation models
• TPSF12C3 EVM user's guide
• For TI's reference design library, visit TI Reference Design library
• To design a low-EMI power supply, review TI's comprehensive EMI Training Series
• TI Reference Designs:
– 3-kW, 180-W/in3 single-phase totem-pole bridgeless PFC reference design with 16-A max input
– 1-kW reference design with CCM totem pole PFC and current-mode LLC realized by C2000™ and GaN
– 7.4-kW on-board charger reference design with CCM totem pole PFC and CLLLC DC/DC using C2000™
MCU
– GaN-based, 6.6-kW, bidirectional, onboard charger reference design
– 10-kW, bidirectional three-phase three-level (T-type) inverter and PFC reference design
• Technical Articles:
– Texas Instruments, How a stand-alone active EMI filter IC shrinks common-mode filter size
– Texas Instruments, How device-level features and package options can help minimize EMI in automotive
designs
– Texas Instruments, How to use slew rate for EMI control
• White Papers:
– Texas Instruments, How Active EMI Filter ICs Mitigate Common-Mode Emissions and Save PCB Space in
Single- and Three-Phase Systems
– Texas Instruments, An Overview of Conducted EMI Specifications for Power Supplies
– Texas Instruments, An Overview of Radiated EMI Specifications for Power Supplies
• Video:
– Texas Instruments, Single- and three-phase active EMI filter ICs mitigate common-mode EMI, save space
and reduce cost
• To view a related device of this product, see the TPSF12C1 single-phase active EMI filter for common-mode
noise mitigation or refer to the Texas Instruments power-supply filter ICs landing page
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10.2 Documentation Support
10.2.1 Related Documentation
For related documentation, see the following:
• Texas Instruments, TI pioneers the industry's first stand-alone active EMI filter ICs, supporting high-density
power supply designs press release
• Texas Instruments, An Engineer's Guide To EMI In DC/DC Regulators e-book
• Texas Instruments, Reduce Buck Converter EMI and Voltage Stress by Minimizing Inductive Parasitics ADJ
article
• Texas Instruments, Designing High Performance, Low-EMI, Automotive Power Supplies application report
• Texas Instruments, EMI Filter Components And Their Nonidealities For Automotive DC/DC Regulators
technical brief
10.3 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
10.4 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
10.5 Trademarks
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
10.6 静电放电警告
静电放电(ESD) 会损坏这个集成电路。德州仪器(TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理
和安装程序，可能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级，大至整个器件故障。精密的集成电路可能更容易受到损坏，这是因为非常细微的参
数更改都可能会导致器件与其发布的规格不相符。
10.7 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
11 Mechanical, Packaging, and Orderable Information
The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this datasheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPSF12C3DYYR
ACTIVE SOT-23-THIN
DYY
14
3000 RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 150
TPSF12C3
Samples
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TPSF12C3 :
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
14-Jul-2023
Automotive : TPSF12C3-Q1
•
NOTE: Qualified Version Definitions:
Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
•
Addendum-Page 2
PACKAGE OUTLINE
SOT-23-THIN - 1.1 mm max height
PLASTIC SMALL OUTLINE
DYY0014A
C
3.36
3.16
SEATING PLANE
PIN 1 INDEX
AREA
A
0.1 C
12X 0.5
14
1
4.3
4.1
NOTE 3
2X
3
7
8
0.31
0.11
14X
0.1
C A
B
1.1 MAX
2.1
1.9
B
0.2
0.08
TYP
SEE DETAIL A
0.25
GAUGE PLANE
0°- 8°
0.1
0.0
0.63
0.33
DETAIL A
TYP
4224643/B 07/2021
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed
0.15 per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.50 per side.
5. Reference JEDEC Registration MO-345, Variation AB
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EXAMPLE BOARD LAYOUT
SOT-23-THIN - 1.1 mm max height
PLASTIC SMALL OUTLINE
DYY0014A
SYMM
14X (1.05)
1
14
14X (0.3)
SYMM
12X (0.5)
8
7
(R0.05) TYP
(3)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 20X
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
METAL
NON- SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4224643/B 07/2021
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
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EXAMPLE STENCIL DESIGN
SOT-23-THIN - 1.1 mm max height
PLASTIC SMALL OUTLINE
DYY0014A
SYMM
14X (1.05)
1
14
14X (0.3)
SYMM
12X (0.5)
8
7
(R0.05) TYP
(3)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 20X
4224643/B 07/2021
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
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