TPSI3052SQDWZRQ1 [TI]
具有集成式 15V 栅极电源的汽车类增强型隔离式开关驱动器 | DWZ | 8 | -40 to 125;
| 型号： | TPSI3052SQDWZRQ1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有集成式 15V 栅极电源的汽车类增强型隔离式开关驱动器 | DWZ | 8 | -40 to 125 开关 栅 驱动 驱动器 栅极 |
| 文件： | 总45页 (文件大小：3490K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPSI3052-Q1
ZHCSMH9A –APRIL 2022 –REVISED FEBRUARY 2023
TPSI3052-Q1 具有集成15-V 栅极电源的汽车类增强型隔离式开关驱动器
TPSI3052-Q1 根据所需的输入引脚数量，支持两种工
1 特性
作模式。在双线模式（通常用于驱动机械继电器）中，
控制开关仅需两个引脚，并支持6.5V 至48V 的宽工作
电压范围。在三线模式中，由外部提供 3V 至 5.5V 的
初级侧电源， 并通过独立的使能引脚控制开关。
TPSI3052S-Q1 具有可实现开关控制的一次性启用功
能，且仅在三线模式下可用。此功能对于驱动 SCR 非
常有用，通常只需要一个电流脉冲即可触发。
• 无需隔离式次级电源
• 驱动外部功率晶体管或SCR
• 5-kVRMS reinforced isolation
• 具有1.5/3A 峰值拉电流和灌电流的15-V 栅极驱动
• 适用于外部辅助电路的最高50 mW 电源
• 支持交流或直流开关
• 支持双线或三线模式
• 七电平功率传输，电阻可选
• 功能安全型
次级侧可为驱动多种电源开关提供 15 V 的浮动稳压电
源轨，无需次级偏置电源。具体用途包括为直流应用驱
动单个电源开关，或为交流应用驱动两个背靠背电源开
关，以及各种类型的 SCR。TPSI3052-Q1 集成式隔离
保护功能非常稳健，与传统机械继电器和光耦合器相
比，其可靠性更高、功耗更低，且温度范围更宽。
– 可提供用于功能安全系统设计的文档
• 符合面向汽车应用的AEC Q-100 标准：
– 温度等级1：–40 至+125°C，TA
• 安全相关认证
– 计划：符合DIN EN IEC 60747-17 (VDE
0884-17) 标准的7071VPK 增强型隔离
– 计划：符合UL 1577 标准且长达1 分钟的
5kVRMS 隔离
使用从 PXFR 引脚到 VSSP 的外部电阻器在七个功率
等级设置中选择一个，以调节 TPSI3052-Q1 的功率传
输。此操作可根据应用需求权衡功率损耗与次级侧功
耗。
器件信息
封装(1)
2 应用
封装尺寸（标称值）
7.50mm × 5.85mm
7.50mm × 5.85mm
器件型号
TPSI3052-Q1
• 固态继电器(SSR)
• 电池管理系统
• 车载充电器
SOIC 8 引脚(DWZ)
SOIC 8 引脚(DWZ)
TPSI3052S-Q1 (2)
• 混合动力、电动和动力总成系统
• 楼宇自动化
• 工厂自动化和控制
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
(2) 产品预发布。
DC Link Pre-charge
3 说明
+
TPSI3052-Q1 是一款完全集成的隔离式开关驱动器，
与外部电源开关结合使用时，可构成完整的隔离式固态
继电器 (SSR)。当标称栅极驱动电压为 15 V、峰值拉
电流和灌电流为 1.5/3.0A 时，可以选择多种外部电源
开关来满足各种应用需求。TPSI3052-Q1 可通过初级
侧电源自行产生次级偏置电源，因此无需隔离式次级电
源偏置。而且，TPSI3052-Q1 可以有选择性地向外部
配套电路供电，以满足不同的应用需求。
DC Link
Cap
-
3–5.5 V
EN
VDRV
VDDH
Micro
PWR
SIGNAL
PXFR
VDDP
3–5.5 V
VDDM
VSSS
VSSP
TPSI3052-Q1 简化版原理图
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLVSFY5
TPSI3052-Q1
ZHCSMH9A –APRIL 2022 –REVISED FEBRUARY 2023
www.ti.com.cn
Table of Contents
8 Detailed Description......................................................17
8.1 Overview...................................................................17
8.2 Functional Block Diagram.........................................17
8.3 Feature Description...................................................17
8.4 Device Functional Modes..........................................24
9 Application and Implementation..................................25
9.1 Application Information............................................. 25
9.2 Typical Application.................................................... 25
9.3 Power Supply Recommendations.............................33
9.4 Layout....................................................................... 33
10 Device and Documentation Support..........................37
10.1 Related Links.......................................................... 37
10.2 接收文档更新通知................................................... 37
10.3 支持资源..................................................................37
10.4 Trademarks.............................................................37
10.5 静电放电警告.......................................................... 37
10.6 术语表..................................................................... 37
11 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 绝对最大额定值...........................................................4
6.2 ESD Ratings............................................................... 4
6.3 Recommended Operating Conditions.........................4
6.4 热性能信息..................................................................5
6.5 Power Ratings.............................................................5
6.6 Insulation Specifications............................................. 5
6.7 Safety-Related Certifications...................................... 6
6.8 Safety Limiting Values.................................................6
6.9 Electrical Characteristics.............................................7
6.10 开关特性..................................................................10
6.11 Insulation Characteristic Curves............................. 12
6.12 Typical Characteristics............................................13
7 Parameter Measurement Information..........................15
Information.................................................................... 37
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
Changes from Revision * (April 2022) to Revision A (December 2022)
Page
• 将器件状态从预告信息更改为量产数据.............................................................................................................1
Copyright © 2023 Texas Instruments Incorporated
2
Submit Document Feedback
Product Folder Links: TPSI3052-Q1
TPSI3052-Q1
ZHCSMH9A –APRIL 2022 –REVISED FEBRUARY 2023
www.ti.com.cn
5 Pin Configuration and Functions
EN
VDRV
1
2
3
8
7
6
PXFR
VDDP
VSSP
VDDH
VDDM
VSSS
4
5
图5-1. TPSI3052-Q1, TPSI3052S-Q1 8-Pin SOIC Top View
表5-1. Pin Functions
PIN
I/O
TYPE(1)
DESCRIPTION
NO.
NAME
1
EN
I
Active high driver enable
—
Power transfer can be adjusted by selecting one of seven power level settings
using an external resistor from the PXFR pin to VSSP. In three-wire mode, a
given resistor setting sets the duty cycle of the power converter (see 表8-1) and
hence the amount of power transferred. In two-wire mode, a given resistor
setting adjusts the current limit of the EN pin (see 表8-2) and hence the amount
of power transferred.
2
PXFR
I
—
3
4
5
6
7
8
VDDP
VSSP
VSSS
VDDM
VDDH
VDRV
P
GND
GND
P
Power supply for primary side
Ground supply for primary side
Ground supply for secondary side
Generated mid supply
—
—
—
—
—
O
P
Generated high supply
Active high driver output
—
(1) P = power, GND = ground, NC = no connect
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
3
Product Folder Links: TPSI3052-Q1
TPSI3052-Q1
ZHCSMH9A –APRIL 2022 –REVISED FEBRUARY 2023
www.ti.com.cn
6 Specifications
6.1 绝对最大额定值
在自然通风条件下的工作温度范围内测得（除非另有说明）(1)
参数(1)
最小值
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
-40
最大值
6
单位
V
初级侧电流(2)
初级侧电流(2)
初级侧电流(2)
次级侧电流(3)
次级侧电流(3)
次级侧电流(3)
次级侧电流(3)
结温，TJ
VDDP
EN
60
V
PXFR
60
V
VDRV
18
V
VDDH
18
V
VDDM
VDDH-VDDM
结温，TJ
6
V
12
V
150
150
°C
°C
-65
贮存温度，Tstg
(1) 超出绝对最大额定值运行可能会对器件造成永久损坏。绝对最大额定值并不表示器件在这些条件下或在建议运行条件以外的任何其他条
件下能够正常运行。如果超出建议运行条件但在绝对最大额定值范围内使用，器件可能不会完全正常运行，这可能影响器件的可靠性、
功能和性能并缩短器件寿命。
(2) 所有电压值均以VSSP 为基准。
(3) 所有电压值均以VSSS 为基准。
6.2 ESD Ratings
VALUE
UNIT
Human body model (HBM), per AEC Q100-002(1)
HBM ESD classification level 2
±2000
V(ESD)
Electrostatic discharge
V
Charged device model (CDM), per AEC
Q100-011
CDM ESD classification level C4B
Corner pins (1, 4, 5, and 8)
Other pins
±750
±500
(1) AEC Q100-002 indicates that HBM stressing must be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
3.0
NOM
MAX
5.5
48.0
5.5
5.5
330
20
UNIT
V
VDDP
EN
Primary side supply voltage in three-wire mode(1)
Enable in two-wire mode(1)
0
V
Enable in three-wire mode(1)
0
V
PXFR
CVDDP
Power transfer control(1)
0
V
Decoupling capacitance on VDDP and VSSP, two-wire mode(3)
Decoupling capacitance on VDDP and VSSP, three-wire mode(3)
Decoupling capacitance across VDDH and VDDM(3)
Decoupling capacitances across VDDM and VSSS(3)
Ambient operating temperature
220
0.22
0.004
0.012
–40
–40
65
nF
µF
µF
µF
°C
°C
V/ms
(2)
CDIV1
CDIV2
TA
15
(2)
40
125
150
TJ
Operating junction temperature
EN rise and fall rates, two-wire mode.
|ΔVEN/Δt|
(1) All voltage values are with respect to VSSP.
(2) CDIV1 and CDIV2 should be of same type and tolerance. CDIV2 capacitance value should be at least three times the capacitance value of
CDIV1 i.e. CDIV2 ≥3 x CDIV1
(3) All capacitance values are absolute. Derating should be applied where necessary.
.
Copyright © 2023 Texas Instruments Incorporated
4
Submit Document Feedback
Product Folder Links: TPSI3052-Q1
TPSI3052-Q1
ZHCSMH9A –APRIL 2022 –REVISED FEBRUARY 2023
www.ti.com.cn
6.4 热性能信息
器件
热指标(1) (2)
DWZ(SOIC)
单位
8 引脚
RϴJA
89.3
40.3
45.2
10.3
44.4
°C/W
°C/W
°C/W
°C/W
°C/W
结至环境热阻
RϴJC(top)
RΘJB
ψJT
结至外壳（顶部）热阻
结至电路板热阻
结至顶部特征参数
结至电路板特征参数
ΨJB
(1) 仅估算。
(2) 有关新旧热指标的更多信息，请参阅半导体和IC 封装热指标应用报告。
6.5 Power Ratings
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VVDDP = 5 V,
RPXFR = 20 kΩ, three-wire mode,
CVDRV = 100 pF,
CDIV1 = 33 nF, CDIV2 = 100 nF
fEN = 1-kHz square wave, VEN = 5 V peak
to peak.
Maximum power dissipation, VDDP.
250
mW
mW
PD
RPXFR = 20 kΩ, two-wire mode,
CVDRV = 100 pF,
CDIV1 = 33 nF, CDIV2 = 100 nF
fEN = 1-kHz square wave, VEN = 48 V
peak to peak.k.
Maximum power dissipation, EN.
350
6.6 Insulation Specifications
SPECIFIC
ATION
PARAMETER
TEST CONDITIONS
UNIT
CREEPAGE AND TRACKING
CLR
CPG
External clearance(1)
Shortest terminal-to-terminal distance through air
mm
mm
≥8.5
Shortest terminal-to-terminal distance across the
package surface
External Creepage(1)
≥8.5
DTI
CTI
Distance through the insulation
Comparative tracking index
Material Group
Minimum internal gap (internal clearance)
DIN EN 60112 (VDE 0303-11); IEC 60112
According to IEC 60664-1
µm
V
≥120
≥600
I
I-IV
Rated mains voltage ≤600 VRMS
Rated mains voltage ≤1000 VRMS
Overvoltage category per IEC 60664-1
I-III
DIN EN IEC 60747-17 (VDE 0884-17)
VIORM Maximum repetitive peak isolation voltage
AC voltage (bipolar)
1414
1000
1414
7070
VPK
VRMS
VDC
AC voltage (sine wave)
DC voltage
VIOWM
Maximum isolation working voltage
Maximum transient isolation voltage
VTEST = VIOTM; t = 60 s (qualification test)
VPK
VIOTM
VTEST = 1.2 × VIOTM; t = 1 s (100% production
test)
8484
9230
12000
VPK
VPK
VPK
Tested in air;
1.2/50-µs waveform per IEC 62638-1
VIMP
Maximum impulse voltage(2)
Tested in oil (qualification test);
1.2/50-µs waveform per IEC 62638-1
VIOSM
Maximum surge isolation voltage(3)
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
5
Product Folder Links: TPSI3052-Q1
TPSI3052-Q1
ZHCSMH9A –APRIL 2022 –REVISED FEBRUARY 2023
www.ti.com.cn
6.6 Insulation Specifications (continued)
SPECIFIC
ATION
PARAMETER
TEST CONDITIONS
UNIT
Method a: After input-output safety test subgroup
2/3,
Vini = VIOTM, tini = 60 s;
≤5
Vpd(m) = 1.2 × VIORM, tm = 10 s.
Method a: After environmental tests subgroup 1,
Vini = VIOTM, tini = 60 s;
Vpd(m) = 1.6 × VIORM, tm = 10 s.
qpd
Apparent charge(4)
pC
≤5
≤5
Method b1: At routine test (100% production test)
and preconditioning (type test), Vini = VIOTM, tini
=
1 s;
Vpd(m) = 1.875 × VIORM, tm = 1 s.
CIO
RIO
Barrier capacitance, input to output(5)
Insulation resistance, input to output(5)
3
pF
VIO = 0.4 × sin (2πft), f = 1 MHz
VIO = 500 V, TA = 25°C
> 1012
> 1011
> 109
2
VIO = 500 V, 100°C ≤TA ≤125°C
VIO = 500 V at TS = 150°C
Ω
Pollution degree
Climatic category
40/125/21
UL 1577
(1) Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application.
Care should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the
isolator on the printed-circuit board do not reduce this distance. Creepage and clearance on a printed-circuit board become equal in
certain cases. Techniques such as inserting grooves, ribs, or both on a printed-circuit board are used to help increase these
specifications.
(2) Testing is carried out in air to determine the intrinsic surge immunity of the package.
(3) Testing is carried out in oil to determine the intrinsic surge immunity of the isolation barrier.
(4) Apparent charge is electrical discharge caused by a partial discharge (pd).
(5) All pins on each side of the barrier tied together creating a two-pin device.
6.7 Safety-Related Certifications
VDE
UL
Plan to certify according to DIN EN IEC 60747-17 (VDE 0884-17)
Reinforced insulation; Maximum transient isolation voltage, 7070
Plan to certify under UL 1577 Component Recognition Program
VPK; Maximum repetitive peak isolation voltage, 1414 VPK; Maximum Single protection, 5000 VRMS
surge isolation voltage, 12000 VPK
Certificate planned
Certificate planned
6.8 Safety Limiting Values
PARAMETER(1) (2)
TEST CONDITIONS
MIN
TYP
MAX
UNIT
RθJA = 89.3°C/W, VVDDP = 5.5 V,
TJ = 150°C, TA = 25°C,
three-wire mode.
254
RθJA = 89.3°C/W, VEN = 24 V,
IS
Safety input, output, or supply current
TJ = 150°C, TA = 25°C,
two-wire mode.
58
mA
RθJA = 89.3°C/W, VEN = 48 V,
TJ = 150°C, TA = 25°C,
two-wire mode.
29
R
θJA = 89.3°C/W,
PS
Safety input, output, or total power
1.4
W
TJ = 150°C, TA = 25°C.
Copyright © 2023 Texas Instruments Incorporated
6
Submit Document Feedback
Product Folder Links: TPSI3052-Q1
TPSI3052-Q1
ZHCSMH9A –APRIL 2022 –REVISED FEBRUARY 2023
www.ti.com.cn
6.8 Safety Limiting Values (continued)
PARAMETER(1) (2)
TEST CONDITIONS
MIN
TYP
MAX
UNIT
TS
Maximum safety temperature
150
°C
(1) Safety limiting intends to minimize potential damage to the isolation barrier upon failure of input or output circuitry. A failure of the I/O
can allow low resistance to ground or the supply and, without current limiting, dissipate sufficient power to overheat the die and
damage the isolation barrier, potentially leading to secondary system failures.
(2) The safety-limiting constraint is the maximum junction temperature specified in the data sheet. The power dissipation and junction-to-
air thermal impedance of the device installed in the application hardware determines the junction temperature. The assumed junction-
to-air thermal resistance in the Thermal Information table is that of a device installed on a high-K test board for leaded surface-mount
packages. The power is the recommended maximum input voltage times the current. The junction temperature is then the ambient
temperature plus the power times the junction-to-air thermal resistance.
6.9 Electrical Characteristics
over operating free-air temperature range (unless otherwise noted). Typicals at TA = 25℃. CVDDP = 220 nF (two-wire mode),
CVDDP = 1 µF (three-wire mode) , CDIV1 = 5.1 nF, CDIV2 = 15 nF, CVDRV = 100 pF, RPXFR = 7.32 kΩ ±1%
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
COMMON
VDDP under-voltage threshold
rising
VVDDP_UV_R
VDDP rising
2.50
2.35
2.70
2.55
75
2.90
2.75
V
V
VDDP under-voltage threshold
falling
VVDDP_UV_F
VVDDP_UV_HYS
VVDDH_UV_R
VDDP falling
VDDP under-voltage threshold
hysteresis
mV
V
VDDH under-voltage threshold
rising
VDDH rising.
VDDH falling.
12.5
9.9
13
13.4
10.9
VDDH under-voltage threshold
falling.
VVDDH_UV_F
10.4
V
VDDH under-voltage threshold
hysteresis.
VVDDH_UV_HYS
VVDDM_UV_R
VVDDM_UV_F
VVDDM_UV_HYS
IQ_VDDH
2.5
3.3
3
V
V
VDDM under-voltage threshold
rising
VDDM rising.
VDDM falling.
2.8
2.6
3.7
3.5
VDDM under-voltage threshold
falling
V
VDDM under-voltage threshold
hysteresis.
0.3
45
1.7
2.5
1.5
3
V
Internal quiescent current of VDDH
supply.
µA
Force VVDDH = 15 V,
sink IVDRV = 50 mA.
Driver on resistance in low state.
Driver on resistance in high state.
Ω
Ω
A
A
RDSON_VDRV
Force VVDDH = 15 V,
source IVDRV = 50 mA.
VDRV peak output current during
rise
VVDDH in steady state, transition EN
low to high, measure peak current.
IVDRV_PEAK
VDRV peak output current during
fall
VVDDH in steady state, transition EN
high to low, measure peak current.
TSD
Temperature shutdown
173
32
℃
℃
TSDH
Temperature shutdown hysteresis
CMTI
Common-mode transient immunity |VCM| = 1000 V
100 V/ns
TWO-WIRE MODE
Minimum voltage on EN to be
detected as a valid logic high.
VIH_EN
VIL_EN
6.5
V
Maximum voltage on EN to be
detected as a valid logic low.
2.0
V
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
7
Product Folder Links: TPSI3052-Q1
TPSI3052-Q1
ZHCSMH9A –APRIL 2022 –REVISED FEBRUARY 2023
www.ti.com.cn
6.9 Electrical Characteristics (continued)
over operating free-air temperature range (unless otherwise noted). Typicals at TA = 25℃. CVDDP = 220 nF (two-wire mode),
CVDDP = 1 µF (three-wire mode) , CDIV1 = 5.1 nF, CDIV2 = 15 nF, CVDRV = 100 pF, RPXFR = 7.32 kΩ ±1%
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
IEN_START
Enable current at startup
27
mA
EN = 0 V →6.5 V
EN = 6.5 V,
RPXFR = 7.32 kΩ,
1.9
6.8
mA
RPXFR ≥100 kΩor RPXFR ≤1 kΩ,
VVDDH in steady state.
IEN
Enable current steady state
EN = 6.5 V,
RPXFR = 20 kΩ,
VVDDH in steady state.
mA
V
EN = 6.5 V,
VVDDH in steady state,
measure average VDDP voltage.
VVDDP_AVG
VDDP average voltage.
VDDH output voltage
4.5
15
15
EN = 6.5 V,
VVDDH in steady state.
VVDDH
13.9
13.9
16.2
16.2
V
V
EN = 6.5 V,
VVDDH in steady state,
no DC loading.
VVDRV_H
VDRV output voltage driven high
EN = 6.5 V →0 V,
VVDDH in steady state,
sink 10 mA load.
VVDRV_L
VDRV output voltage driven low
0.1
5.5
V
V
EN = 6.5 V, steady state.
RPXFR = 7.32 kΩ,
Average VDDM voltage when
sourcing external current.
RPXFR ≥100 kΩor RPXFR ≤1 kΩ,
4.6
4.6
CDIV1 = 75 nF, CDIV2 = 220 nF,
source 0.20 mA from VDDM,
measure VDDM voltage.
VVDDM_IAUX
EN = 6.5 V, steady state.
RPXFR = 20 kΩ,
CDIV1 = 75 nF, CDIV2 = 220 nF,
source 1.2 mA from VDDM,
measure VDDM voltage.
Average VDDM voltage when
sourcing external current.
5.5
V
THREE-WIRE MODE
Minimum voltage on EN to be
detected as a valid logic high.
VIH(min) = 0.7 x VVDDP
VVDDP = 3 V
2.1
V
V
VIH_EN
VVDDP = 5.5 V
3.85
VVDDP = 3 V
0.9
V
V
Maximum voltage on EN to be
detected as a valid logic low.
VIL_EN
VVDDP = 5.5 V
1.65
Copyright © 2023 Texas Instruments Incorporated
8
Submit Document Feedback
Product Folder Links: TPSI3052-Q1
TPSI3052-Q1
ZHCSMH9A –APRIL 2022 –REVISED FEBRUARY 2023
www.ti.com.cn
6.9 Electrical Characteristics (continued)
over operating free-air temperature range (unless otherwise noted). Typicals at TA = 25℃. CVDDP = 220 nF (two-wire mode),
CVDDP = 1 µF (three-wire mode) , CDIV1 = 5.1 nF, CDIV2 = 15 nF, CVDRV = 100 pF, RPXFR = 7.32 kΩ ±1%
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
EN = 3.3 V,
VVDDP = 3.3 V,
RPXFR = 7.32 kΩ,
3.1
R
PXFR ≥100 kΩor RPXFR ≤1 kΩ,
CVDDP = 10 µF,
VVDDH in steady state,
measure IVDDP
.
mA
EN = 3.3 V,
VVDDP = 3.3 V,
RPXFR = 20 kΩ,
CVDDP = 10 µF,
VVDDH in steady state,
26
4.8
37
measure IVDDP
.
VDDP average current in steady
state
IVDDP
EN = 5 V,
VVDDP = 5 V,
RPXFR = 7.32 kΩ,
PXFR ≥100 kΩor RPXFR ≤1 kΩ,
mA
mA
R
CVDDP = 10 µF,
VVDDH in steady state,
measure IVDDP
.
EN = 5 V,
VVDDP = 5 V,
RPXFR = 20 kΩ,
CVDDP = 10 µF,
VVDDH in steady state,
measure IVDDP
.
VVDDP = 3.3 V, EN = 0.0 V, steady
state.
RPXFR = 7.32 kΩ,
Average VDDM voltage when
sourcing external current.
CDIV1 = 75 nF,
VVDDM_IAUX
VVDDM_IAUX
VVDDM_IAUX
VVDDM_IAUX
4.6
4.6
4.6
4.6
5.5
5.5
5.5
5.5
V
V
V
V
CDIV2 = 220 nF,
Source 0.35 mA from VDDM
measure VVDDM
.
VVDDP = 5.0 V, EN = 0.0 V, steady
state.
RPXFR = 7.32 kΩ,
CDIV1 = 75 nF,
CDIV2 = 220 nF,
Source 0.50 mA from VDDM
Average VDDM voltage when
sourcing external current.
measure VVDDM
.
VVDDP = 3.3 V, EN = 0.0 V, steady
state.
RPXFR = 20 kΩ
CDIV1 = 75 nF,
CDIV2 = 220 nF,
Source 3.0 mA from VDDM
Average VDDM voltage when
sourcing external current.
measure VVDDM
.
VVDDP = 5.0 V, EN = 0.0 V, steady
state.
RPXFR = 20 kΩ
CDIV1 = 75 nF
Average VDDM voltage when
sourcing external current.
CDIV2 = 220 nF
Source 5.0 mA from VDDM
measure VVDDM
.
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
9
Product Folder Links: TPSI3052-Q1
TPSI3052-Q1
ZHCSMH9A –APRIL 2022 –REVISED FEBRUARY 2023
www.ti.com.cn
6.9 Electrical Characteristics (continued)
over operating free-air temperature range (unless otherwise noted). Typicals at TA = 25℃. CVDDP = 220 nF (two-wire mode),
CVDDP = 1 µF (three-wire mode) , CDIV1 = 5.1 nF, CDIV2 = 15 nF, CVDRV = 100 pF, RPXFR = 7.32 kΩ ±1%
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
VVDDP = 3.0 V,
VVDDH
VDDH output voltage
EN = 3.0 V,
VVDDH in steady state.
13.9
15
16.2
16.2
V
V
VVDDP = 3.0 V,
EN = 3.0 V,
VVDDH in steady state,
no DC loading.
VVDRV_H
VDRV output voltage driven high
VDRV output voltage driven low
13.9
15
VVDDP = 3.0 V,
EN = 0 V,
VVDDH in steady state,
VDRV sinking 10 mA.
VVDRV_L
0.1
V
6.10 开关特性
在自然通风条件下的工作温度范围内测得（除非另有说明）。TA = 25℃时的典型值。CVDDP = 220nF（双线模式），CVDDP
1µF（三线模式），CDIV1 = 5.1nF，CDIV2 = 15nF，CVDRV= 100pF，RPXFR = 7.32kΩ±1%
=
参数
测试条件
最小值 典型值 最大值 单位
两线模式
tLO_EN
5
µs
µs
EN 的低电平时间。
EN = 0V →6.5V，
VVDDH = 7.5V。
在50% 电平从EN 上升到VDDH 的
传播延迟时间。
tLH_VDDH
tLH_VDRV
tHL_VDRV
tR_VDRV
tF_VDRV
165
185
2.4
6
EN = 0V →6.5V，
VVDRV = 13.5V。
在90% 电平从EN 上升到VDRV 的
传播延迟时间。
µs
µs
ns
ns
从EN 下降到VDRV（电平为
10%）的传播延迟时间。
EN = 6.5V →0V，
VVDRV = 1.5V。
3
从EN 上升到VDRV（电平从15% EN = 0V →6.5V，
升至85%）的VDRV 上升时间。
VVDRV = 2.25V 至12.75V。
从EN 下降到VDRV（电平从85% EN = 6.5V →0V，
降至15%）的VDRV 下降时间。
5
VVDRV = 12.75V 至2.25V。
三线模式
tLO_EN
5
5
µs
µs
EN 的低电平时间。
EN 的高电平时间。
VVDDP = 3.3V，VVDDH = 稳态。
VVDDP = 3.3V，VVDDH = 稳态。
tHI_EN
VDRV 在一次性使能模式下的高电平
时间。仅限
TPSI3052S-Q1。
一次性使能仅在三线模式下可用。
tHI_VDRV
2.5
85
3
µs
µs
µs
VVDDP = 3.3V，稳态。
EN = 0V，1V/µs 时
从VDDP 上升到VDDH（处于50% VVDDP = 0V →3.3V，
电平）的传播延迟时间。
tLH_VDDH
VVDDH = 7.5V。
CDIV1 = 3.3nF，CDIV2 = 220nF。
VVDDP = 3.3V，
VVDDH 稳态，
在90% 电平从EN 上升到VDRV 的
传播延迟时间
tLH_VDRV
4.5
3
EN = 0V →3.3V，
VVDRV = 13.5V。
VVDDP = 3.3V，
VVDDH 稳态，
从EN 下降到VDRV（电平为
10%）的传播延迟时间
tHL_VDRV
2.5
µs
µs
EN = 3.3V →0V，
VVDRV = 1.5V。
EN = 3.3V，-1V/µs 时
VVDDP = 3.3V →0V，
VVDRV = 1.5V。
从VDDP 下降到VDRV（电平为
10%）的传播延迟时间。由于主电源
断电导致的超时机制。
tHL_VDRV_PD
300
Copyright © 2023 Texas Instruments Incorporated
10
Submit Document Feedback
Product Folder Links: TPSI3052-Q1
TPSI3052-Q1
ZHCSMH9A –APRIL 2022 –REVISED FEBRUARY 2023
www.ti.com.cn
6.10 开关特性(continued)
在自然通风条件下的工作温度范围内测得（除非另有说明）。TA = 25℃时的典型值。CVDDP = 220nF（双线模式），CVDDP
1µF（三线模式），CDIV1 = 5.1nF，CDIV2 = 15nF，CVDRV= 100pF，RPXFR = 7.32kΩ±1%
=
参数
测试条件
VVDDP = 3.3V，
VDDH 稳态，
EN = 0V →3.3V，
VVDRV = 2.25V 至12.75V。
最小值 典型值 最大值 单位
V
从EN 上升到VDRV（电平从15%
升至85%）的VDRV 上升时间
tR_VDRV
6
5
ns
ns
VVDDP = 3.3V，
VVDDH 稳态，
从EN 下降到VDRV（电平从85%
降至15%）的VDRV 下降时间
tF_VDRV
EN = 3.3V →0V，
VVDRV = 12.75V 至2.25V。
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
11
Product Folder Links: TPSI3052-Q1
TPSI3052-Q1
ZHCSMH9A –APRIL 2022 –REVISED FEBRUARY 2023
www.ti.com.cn
6.11 Insulation Characteristic Curves
300
280
260
240
220
200
180
160
140
120
100
80
80
60
40
20
0
VEN = 24 V
VEN = 48 V
60
40
20
0
0
25
50
75
100
125
150
0
25
50
75
100
125
150
TA (C)
TA (C)
图6-1. Thermal Derating Curve for Limiting Current 图6-2. Thermal Derating Curve for Limiting Current
per VDE and IEC, Three-Wire Mode
per VDE and IEC, Two-Wire Mode
1500
1400
1300
1200
1100
1000
900
800
700
600
500
400
300
200
100
0
0
25
50
75
100
125
150
TA (C)
图6-3. Thermal Derating Curve for Limiting Power per VDE and IEC
Copyright © 2023 Texas Instruments Incorporated
12
Submit Document Feedback
Product Folder Links: TPSI3052-Q1
TPSI3052-Q1
ZHCSMH9A –APRIL 2022 –REVISED FEBRUARY 2023
www.ti.com.cn
6.12 Typical Characteristics
18
17
16
15
14
13
12
11
10
9
17
16
15
14
13
12
11
10
9
8
8
7
7
6
6
5
5
4
4
3
3
VEN
VEN
2
2
VVDDM
VVDDH
VVDRV
VVDDM
VVDDH
VVDRV
1
1
0
0
-1
-1
0
5
10
15
20
25
30
35
40
45
50
0
5
10
15
20
25
30
35
40
45
50
Time (s)
Time (s)
Three-wire mode
CDIV1 = 5.1 nF
CDIV2 =15 nF
VDDP = 5.0 V
CVDRV = 100 pF
CVDDP = 1 μF
Three-wire mode
VDDP = 5.0 V
CVDRV = 100 pF
CVDDP = 1 μF
RPXFR = 7.32 kΩ
TA = 25°C
RPXFR = 7.32 kΩ
TA = 25°C
CDIV1 = 5.1 nF
CDIV2 =15 nF
IAUX = 0 mA
IAUX = 0 mA
图6-4. tLH_VDRV, Three-Wire Mode
图6-5. tHL_VDRV, Three-Wire Mode
4.8
4.6
4.4
4.2
4
5
4.9
4.8
4.7
4.6
4.5
4.4
4.3
4.2
4.1
4
TA = 25C
TA = 125C
TA = 25C
TA = 125C
3.8
3.6
3.4
3.2
3
0
10
20
30
40
50
60
70
80
90
100
0
10
20
30
40
50
60
70
80
90
100
CVDRV (nF)
CVDRV (nF)
Three-wire mode
VDDP = 3.3 V
Three-wire mode
VDDP = 3.3 V
RPXFR = 7.32 kΩ
RPXFR = 7.32 kΩ
CDIV1 = 2.2 μF
CDIV2 = 2.2 μF
CDIV1 = 2.2 μF
CDIV2 = 2.2 μF
图6-6. tLH_VDRV versus CVDRV
图6-7. tHL_VDRV versus CVDRV
16
15
14
13
12
11
10
9
16
15
14
13
12
11
10
9
VEN
VEN
VVDDM
VVDDH
VVDRV
VVDDM
VVDDH
VVDRV
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
0
0
-1
-1
-0.3
0
0.3
0.6
0.9
1.2
1.5
1.8
2.1
2.4
2.7
-100 -50
0
50 100 150 200 250 300 350 400 450 500 550 600
Time (ms)
Time (ms)
Two-wire mode
EN = 12 V
Two-wire mode
EN = 12 V
RPXFR = 7.32 kΩ
TA = 25°C
RPXFR = 7.32 kΩ
TA = 25°C
CDIV1 = 33 nF
CDIV2 =100 nF
CVDRV = 100 pF
CVDDP = 220 nF
CDIV1 = 33 nF
CDIV2 =100 nF
CVDRV = 100 pF
CVDDP = 220 nF
IAUX = 0 mA
IAUX = 0 mA
图6-8. tLH_VDRV, Two-Wire Mode
图6-9. tHL_VDRV, Two-Wire Mode
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
13
Product Folder Links: TPSI3052-Q1
TPSI3052-Q1
ZHCSMH9A –APRIL 2022 –REVISED FEBRUARY 2023
www.ti.com.cn
6.12 Typical Characteristics (continued)
14
25
22.5
20
RPXFR = 7.32 k
RPXFR = 7.32 k
RPXFR = 9.09 k
RPXFR = 11 k
RPXFR = 12.7 k
RPXFR = 14.7 k
RPXFR = 16.5 k
RPXFR = 20 k
13
RPXFR = 9.09 k
RPXFR = 11 k
RPXFR = 12.7 k
RPXFR = 14.7 k
RPXFR = 16.5 k
RPXFR = 20 k
12
11
10
9
17.5
15
8
7
12.5
10
6
5
7.5
5
4
3
2
2.5
0
1
0
0
50
100
150
200
250
300
350
400
450
500
0
50
100
150
200
250
300
350
400
450
500
CDIV1 (nF), (CDIV2 = 3 x CDIV1
)
CDIV1 (nF), (CDIV2 = 3 x CDIV1)
tSTART represents the time from VDDP rising to VDDM and
VDDH fully discharged rails reaching > 95% of their final levels.
tSTART represents the time from VDDP rising to VDDM and
VDDH fully discharged rails reaching > 95% of their final levels.
Three-wire mode
IAUX = 0 mA
VDDP = 5.0 V
TA = 25°C
Three-wire mode
IAUX = 0 mA
VDDP = 3.3 V
TA = 25°C
图6-10. tSTART versus CDIV1, CDIV2
图6-11. tSTART versus CDIV1, CDIV2
100
90
80
70
60
50
40
30
20
10
0
RPXFR = 7.32 k
RPXFR = 9.09 k
RPXFR = 11 k
RPXFR = 12.7 k
RPXFR = 14.7 k
RPXFR = 16.5 k
RPXFR = 20 k
0.01
0.03
0.05
0.07
0.09
0.11
0.13
0.15
0.17
0.19
1/QLOAD (nC)-1
Three-wire mode
IAUX = 0 mA
VDDP = 5.0 V
TA = 25°C
Three-wire mode
IAUX = 0 mA
VDDP = 5.0 V
TA = 25°C
图6-13. Max. fEN versus QLOAD = 100 nC to 1000 nC
图6-12. Max. fEN versus QLOAD = 10 nC to 100 nC
6
5.75
5.5
5.25
5
6
VVDDP = 3.3 V
VVDDP = 5 V
VVDDP = 3.3 V
VVDDP = 5 V
5.75
5.5
5.25
5
4.75
4.5
4.25
4
4.75
4.5
4.25
4
3.75
3.5
3.25
3
3.75
3.5
3.25
3
2.75
2.5
2.25
2
2.75
2.5
2.25
2
1.75
1.5
1.75
1.5
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
6
6.5
7
IAUX (mA)
IAUX (mA)
Three-wire mode
CDIV1 = 150 nF
TA = 25°C
Three-wire mode
CDIV1 = 150 nF
TA = 25°C
RPXFR = 20 kΩ
RPXFR = 11 kΩ
CDIV2 = 470 nF
CDIV2 = 470 nF
CVDDP = 1 μF
CVDDP = 1 μF
图6-14. VVDDM versus IAUX
图6-15. VVDDM versus IAUX
Copyright © 2023 Texas Instruments Incorporated
14
Submit Document Feedback
Product Folder Links: TPSI3052-Q1
TPSI3052-Q1
ZHCSMH9A –APRIL 2022 –REVISED FEBRUARY 2023
www.ti.com.cn
7 Parameter Measurement Information
50%
50%
EN
tLH_VDDH
50%
VDDH
tLH_VDRV
90%
85%
85%
tF_VDRV
15%
10%
15%
VDRV
tR_VDRV
tHL_VDRV
图7-1. Two-Wire Mode Timing, Standard Enable (TPSI3052-Q1 Only)
50%
50%
tLH_VDDH
VDDP
50%
VDDH
EN
tHI_EN
tLO_EN
50%
50%
50%
tHL_VDRV_PD
tLH_VDRV
90%
tF_VDRV
85%
85%
15%
10%
15%
tR_VDRV
10%
VDRV
tHL_VDRV
图7-2. Three-Wire Mode Timing, Standard Enable (TPSI3052-Q1 Only)
50%
50%
VDDP
tLH_VDDH
50%
VDDH
EN
tHI_EN
tLO_EN
50%
50%
tLH_VDRV
50%
tHL_VDRV_PD
tF_VDRV
90%
85%
50%
15%
85%
50%
15%
10%
VDRV
tR_VDRV
tHI_VDRV
图7-3. Three-Wire Mode Timing, One-Shot Enable (TPSI3052S-Q1 Only)
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
15
Product Folder Links: TPSI3052-Q1
TPSI3052-Q1
ZHCSMH9A –APRIL 2022 –REVISED FEBRUARY 2023
www.ti.com.cn
Pass/Fail criteria: Output
must remain stable.
EN
PXFR
VDRV
VDDH
+
VDDP
CDIV1
CVDRV
CVDDP
RPXFR
VSSP
VDDM
VSSS
VVDRV
Modulator
CDIV2
-
GNDO
GNDI
+ VCM
-
图7-4. Common-Mode Transient Immunity Test Circuit
Copyright © 2023 Texas Instruments Incorporated
16
Submit Document Feedback
Product Folder Links: TPSI3052-Q1
TPSI3052-Q1
ZHCSMH9A –APRIL 2022 –REVISED FEBRUARY 2023
www.ti.com.cn
8 Detailed Description
8.1 Overview
The TPSI3052-Q1 is a fully integrated, reinforced isolated power switch driver, which when combined with an
external power switch, forms a complete isolated Solid State Relay (SSR). With a nominal gate drive voltage of
15 V and 1.5/3.0-A peak source and sink current, a large variety of external power switches can be chosen to
meet a wide range of applications. The TPSI3052-Q1 generates its own secondary supply from the power
received from its primary side, so no isolated secondary bias supply is required.
The Functional Block Diagram shows the primary side that includes a transmitter that drives an alternating
current into the primary winding of an integrated transformer at a rate determined by the setting of the PXFR pin
and the logic state of the EN pin. The transmitter operates at high frequency to optimally drive the transformer to
its peak efficiency. In addition, the transmitter uses spread spectrum techniques to greatly improve EMI
performance, allowing many applications to achieve CISPR 25 - Class 5. During transmission, data information
transfers to the secondary side alongside with the power. On the secondary side, the voltage induced on the
secondary winding of the transformer is rectified, and the shunt regulator regulates the output voltage level of
VDDH. Lastly, the demodulator decodes the received data information and drives VDRV high or low based on
the logic state of the EN pin.
8.2 Functional Block Diagram
EN
VDRV
PXFR
VDDP
VDDH
VDDM
Modulator
VSSP
VSSS
8.3 Feature Description
8.3.1 Transmission of the Enable State
The TPSI3052-Q1 and TPSI3052S-Q1 use a modulation scheme to transmit the switch enable state information
across the isolation barrier. The transmitter modulates the EN signal with an internally generated, high frequency
carrier (89-MHz typical), and differentially drives the primary winding of the isolation transformer. The receiver on
the secondary side demodulates the received signal and asserts VDRV high or low based on the data received.
8.3.2 Power Transmission
The TPSI3052-Q1 and TPSI3052S-Q1 do not use an isolated supply for their power. The secondary side power
is obtained by the transferring of the primary side input power across the isolation transformer. The modulation
scheme uses spread spectrum of the high frequency carrier (89-MHz typical) to improve EMI performance
assisting applications in meeting the CISPR 25 Class 5 standards.
8.3.3 Gate Driver
The TPSI3052-Q1 and TPSI3052S-Q1 have an integrated gate driver that provides a nominal 15-V gate voltage
with 1.5/3.0-A peak source and sink current sufficient for driving many power transistors or Silicon-Controlled
Rectifiers (SCR). When driving external power transistors, TI recommends bypass capacitors (CDIV2 = 3 * CDIV1
)
from VDDH to VDDM and VDDM to VSSS of 20 times the equivalent gate capacitance.
The gate driver also includes an active clamp keep off circuit. This feature helps to keep the driver output, VDRV,
low should power be lost on the secondary supply rails e.g. power loss on the VDDP supply prevents power
transfer. Should power be lost, the active clamp keep off circuit will attempt to clamp the voltage of VDRV to
under 2 V relative to VSSS.
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
17
Product Folder Links: TPSI3052-Q1
TPSI3052-Q1
ZHCSMH9A –APRIL 2022 –REVISED FEBRUARY 2023
www.ti.com.cn
8.3.4 Modes Overview
The TPSI3052-Q1 and TPSI3052S-Q1 have two modes of operation: two-wire mode and three-wire mode.
In two-wire mode, the power on the primary side is provided directly by the EN pin. Setting EN high causes
power transfer to the secondary side. As power transfers, the secondary rails, VDDM and VDDH, begin to rise.
After sufficient power is available on the secondary side, VDRV is asserted high. Setting EN low causes VDRV
to assert low and halts power transfer to the secondary side.
In three-wire mode, the power on the primary side is provided by a dedicated, low output impedance supply
connected to VDDP. In this case, power transfer is independent from the enable state. If VDDP power is present,
power is transferred from the primary side to the secondary side regardless of the EN state. In steady state
conditions, when sufficient power is available on the secondary side, setting EN high causes VDRV to assert
high. Setting EN low causes VDRV to assert low.
In standard enable, available only on the TPSI3052-Q1, VDRV follows the state of the EN pin and is used in
most load switch applications. In one-shot enable mode, available only on the TPSI3052S-Q1 in three-wire
mode, when a rising transition occurs on EN, VDRV is asserted high momentarily and then automatically
asserted low, forming a one-shot pulse on VDRV. This event is useful for driving SCR devices that require only
one burst of power to trigger. To re-trigger VDRV, EN must first transition low, followed by another rising
transition.
8.3.5 Three-Wire Mode
Three-wire mode is used for applications that require higher levels of power transfer or the shortest propagation
delay TPSI3052-Q1 can offer. VDDP is supplied independently from the EN pin by a low output impedance
external supply that can deliver the required power. In this mode, power from the primary side to the secondary
side always occurs regardless of the state of the EN pin. Setting the EN pin logic high or low asserts or de-
asserts VDRV, thereby enabling or disabling the external switch, respectively. 图 8-1 shows the basic setup
required for three-wire mode operation which requires EN, VDDP, and VSSP signals. EN can be driven up to 5.5
V which is normally driven from the circuitry residing on the same rail as VDDP. In this example, the TPSI3052-
Q1 is being used to drive back-to-back MOSFETs in a common-source configuration. CVDDP provides the
required decoupling capacitance for the VDDP supply rail of the device. CDIV1 and CDIV2 provide the required
decoupling capacitances of the VDDH and VDDM supply rails that provide the peak current to drive the external
MOSFETs.
图 8-2 and 图 8-3 show the basic operation from start-up to steady-state conditions. 图 8-2 shows operation
using standard enable of the TPSI3052-Q1. After power up, the TPSI3052-Q1 begins to transfer power from
VDDP to the secondary side for a fixed time period (25-μs typical) at a duty cycle rate determined by RPXFR
,
which begins to charge up the VDDH (and VDDM) secondary side rails. Power transfer continues as long as
VDDP is present. The time required to fully charge VDDH depends on several factors including the values of
VDDP, CDIV1, CDIV2, RPXFR, and the overall power transfer efficiency. When the application drives the EN pin to a
logic high, the TPSI3052-Q1 signals information from the primary side to the secondary side to assert VDRV and
drive it high. Similarly, setting EN pin to a logic low causes VDRV to be driven low. 图 8-3 shows operation using
one-shot enable of the TPSI3052S-Q1. The start-up behavior is identical. In one-shot enable, when the
application drives the EN pin to a logic high, VDRV is asserted high (tHI_VDRV), then is automatically asserted low
by the TPSI3052S-Q1. To assert VDRV high again, the EN pin must transition low first, followed by a transition
high.
Copyright © 2023 Texas Instruments Incorporated
18
Submit Document Feedback
Product Folder Links: TPSI3052-Q1
TPSI3052-Q1
ZHCSMH9A –APRIL 2022 –REVISED FEBRUARY 2023
www.ti.com.cn
3–5.5 V
Micro
EN
VDRV
PWR
RPXFR
SIGNAL
PXFR
VDDP
VDDH
VDDM
VSSS
CDIV1
3–5.5 V
CVDDP
CDIV2
VSSP
图8-1. Three-Wire Mode Simplified Schematic
VDDP
VVDDH
VDDH
EN
VVDRV_H
VDRV
图8-2. Three-Wire Mode with TPSI3052-Q1 (Standard Enable)
VDDP
VVDDH
VDDH
EN
VVDRV_H
VDRV
图8-3. Three-Wire Mode with TPSI3052S-Q1 (One-shot Enable)
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
19
Product Folder Links: TPSI3052-Q1
TPSI3052-Q1
ZHCSMH9A –APRIL 2022 –REVISED FEBRUARY 2023
www.ti.com.cn
To reduce average power, the TPSI3052-Q1 transfers power from the primary side to the secondary side in a
burst fashion. The period of the burst is fixed while the burst on time is programmable by selecting one of seven
appropriate resistor values, RPXFR, from the PXFR to VSSP pins, thereby changing the duty cycle of the power
converter. This action provides flexibility in the application, allowing tradeoffs in power consumed versus power
delivered. Higher power converter settings increase the burst on time which, in turn, increases average power
consumed from the VDDP supply and increases the amount of power transferred to the secondary side VDDH
and VDDM supplies. Similarly, lower power converter settings decrease the burst on time which, in turn,
decreases average power consumed from the VDDP supply and decreases the amount of power transferred to
the secondary side.
表8-1 summarizes the three-wire mode power transfer selection.
表8-1. Three-Wire Mode Power Transfer Selection
Power Converter Duty Cycle
(Three-Wire Mode, Nominal)
(1) (2)
RPXFR
Description
13.3%
26.7%
40.0%
53.3%
66.7%
80.0%
93.3%
7.32 kΩ
9.09 kΩ
11 kΩ
The device supports seven, fixed power transfer settings, by selection of a
corresponding RPXFR value . Selecting a given power transfer setting adjusts the
duty cycle of the power converter and hence the amount of power transferred.
Higher power transfer settings leads to an increased duty cycle of the power
converter leading to increased power transfer and consumption. During power
up, the power transfer setting is determined and remains fixed at that setting until
VDDP power cycles.
12.7 kΩ
14.7 kΩ
16.5 kΩ
20 kΩ
(1) Standard resistor (EIA E96), 1% tolerance, nominal value.
(2) PXFR ≥100 kΩor RPXFR ≤1 kΩsets the duty cycle of the power converter to 13.3%.
R
8.3.6 Two-Wire Mode
图 8-4 shows the basic setup required for two-wire mode operation, which requires the EN signal and VSSP
ground signal. EN can be driven up to 48 V. No current limiting resistor is required on EN because the
TPSI3052-Q1 limits the input current based on the values set by the RPXFR resistor (see 表8-2). In this example,
the TPSI3052-Q1 is being used to drive back-to-back MOSFETs in a common-source configuration. CVDDP
provides the required decoupling capacitance for the VDDP supply rail of the device. CDIV1 and CDIV2 provide the
required decoupling capacitance of the VDDH and VDDM supply rails that provide the peak current to drive the
external MOSFETs.
图8-5 shows the typical operation in two-wire mode configured for standard enable. The application drives EN to
a logic high and the TPSI3052-Q1 begins its power-up sequence. During power up, the current provided by the
EN pin, IEN, begins to charge up the external capacitance, CVDDP, and the voltage on VDDP begins to rise until it
reaches VVDDP_H. After VDDP reaches its peak, VVDDP_H, the TPSI3052-Q1 transfers stored energy on CVDDP to
the secondary side for a fixed time (3.3-μs typical) which begins to charge up the VDDH (and VDDM)
secondary side rails thereby discharging the voltage on VDDP. In steady state, this results in an average voltage
on VDDP, VVDDP_AVG. This cycle repeats until the VDDH (and VDDM) secondary side rails are fully charged. The
time required to fully charge VDDH depends on several factors including the values of CVDDP, CDIV1, CDIV2
,
RPXFR, and the overall power transfer efficiency. After VDDH is fully charged, VDRV is asserted high and
remains high while the EN pin remains at a logic high. When the application drives the EN pin to a logic low, the
charge on VDDP begins to discharge. Prior to VDDP reaching its UVLO falling threshold, TPSI3052-Q1 signals
information from the primary side to the secondary side to de-assert VDRV and drive it low. Because power is no
longer being transferred, all rails begin to fully discharge.
Copyright © 2023 Texas Instruments Incorporated
20
Submit Document Feedback
Product Folder Links: TPSI3052-Q1
TPSI3052-Q1
ZHCSMH9A –APRIL 2022 –REVISED FEBRUARY 2023
www.ti.com.cn
6.5–48 V
RPXFR
EN
VDRV
PWR
SIGNAL
PXFR
VDDP
VDDH
VDDM
VSSS
CDIV1
CVDDP
CDIV2
VSSP
图8-4. Two-Wire Mode Simplified Schematic
VVDDP_H
90%
tLH_VDDP_H
VDDP
VVDDH
VVDDH_UV_R
VDDH
50%
EN
VVDRV_H
VDRV
图8-5. Two-Wire Mode with Standard Enable (TPSI3052-Q1 Only)
In two-wire mode, power is supplied directly by the EN pin. When EN is asserted high, the TPSI3052-Q1
transfers power to the secondary side for a fixed time (3.3-μs nominal) while the time period varies. The period
varies due to the hysteretic control of the power transfer that ensures the average current supplied through the
EN pin is maintained. The amount of average current, and hence the amount of power transferred, is
programmable by selecting one of seven appropriate resistor values, RPXFR, from the PXFR to VSSP pins.
Higher settings of RPXFR increase IEN which increases the average power consumed from the EN pin and
increases the amount of power transferred to the secondary side VDDH supply. Similarly, lower settings of RPXFR
decrease IEN, which decreases the average power consumed from the EN pin and decreases the amount of
power transferred to the secondary side.
表8-2 summarizes the two-wire mode power selection.
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
21
Product Folder Links: TPSI3052-Q1
TPSI3052-Q1
ZHCSMH9A –APRIL 2022 –REVISED FEBRUARY 2023
www.ti.com.cn
表8-2. Two-Wire Mode Power Selection
(1) (2)
RPXFR
7.32 kΩ
IEN (Two-Wire Mode, Nominal)
Description
1.9 mA
2.8 mA
3.7 mA
4.5 mA
5.2 mA
6.0 mA
6.7 mA
9.09 kΩ
11 kΩ
The device supports seven, fixed EN input current limit options selected by the
corresponding RPXFR specified value. Higher current limit selections lead to
increased power transfer and consumption. During power up, the EN input current
limit is determined and remains fixed at that setting until VDDP power cycles.
12.7 kΩ
14.7 kΩ
16.5 kΩ
20 kΩ
(1) Standard resistor (EIA E96), 1% tolerance, nominal value.
(2) PXFR ≥100 kΩor RPXFR ≤1 kΩsets the IEN to 1.9 mA.
R
8.3.7 VDDP, VDDH, and VDDM Undervoltage Lockout (UVLO)
TPSI3052-Q1 and TPSI3052S-Q1 implement an internal UVLO protection feature for both input and output
power supplies, VDDP, VDDH, and VDDM. When VDDP is lower than the UVLO threshold voltage, power
ceases to be transferred to the VDDM and VDDH rails. Over time the VDDH and VDDM rails will begin to
discharge. If enough charge is available on VDDP, the device will attempt to signal VDRV to assert low. If not
enough charge is available on VDDP, a timeout mechanism will ensure VDRV asserts low after the timeout has
been reached. When either VDDH or VDDM are lower than their respective UVLO thresholds, VDRV will be
asserted low regardless of the EN state. The UVLO protection blocks feature hysteresis, which helps to improve
the noise immunity of the power supply. During turn-on and turn-off, the driver sources and sinks a peak
transient current, which can result in voltage drop of the VDDH, VDDM power supplies. The internal UVLO
protection block ignores the associated noise during these normal switching transients.
8.3.8 Power Supply and EN Sequencing
During power up, the device will automatically determine if two-wire or three-wire mode is to be entered. Once
two-wire or three-wire mode is determined, the mode is maintained until another power cycle is performed.
Therefore, it is important to understand different scenarios that may affect the device operation.
In two-wire mode, the device is supplied power from a single external voltage source via EN, which charges the
CVDDP capacitance on VDDP. The voltage supply is required to meet the power supply needs at the selected
PXFR setting, as well as, meet the recommended minimum ramp time, |ΔVEN/Δt|. To ensure two-wire mode is
entered properly, VEN must reach VIH_EN prior to VVDDP reaching VVDDP_UV_R. This is summarized in 图 8-6.
Similarly, it is recommend that VEN meet the minimum recommended ramp down time to VIL_EN. Too slow a ramp
down time may cause insufficient power to be transferred while slowly transitioning between VIH_EN and VIL_EN
leading to intermittent de-assertions and assertions of VDRV. This may continue until the power transfer reduces
sufficiently to maintain VDRV low.
Copyright © 2023 Texas Instruments Incorporated
22
Submit Document Feedback
Product Folder Links: TPSI3052-Q1
TPSI3052-Q1
ZHCSMH9A –APRIL 2022 –REVISED FEBRUARY 2023
www.ti.com.cn
VIH_EN
VEN
VIL_EN
VEN
t
VVDDP_UV_R
Two-wire mode
VVDDP
图8-6. Two-wire Mode Entry
In most three-wire mode applications, EN and VDDP are supplied by the same voltage rail and source. It is
recommended that VEN remain below VIL_EN until VVDDP reaches VVDDP_UV_R. It is also possible in some
applications to connect EN directly to the VDDP supply. These two scenarios are shown in 图8-7.
VVDDP_UV_R
VVDDP
VEN = VVDDP
VIL_EN
VEN
图8-7. Three-wire Mode Power Sequences
In three-wire mode applications with separate voltage sources supplying EN and VDDP, it is recommended that
VEN remain below VIL_EN until VVDDP reaches VVDDP_UV_R. If VEN reaches VIH_EN prior to VVDDP reaching
VVDDP_UV_R, current from the supply that sources EN will attempt to power VDDP. Depending on the other
supply's impedance residing on VDDP and the amount of power available from the EN pin, VVDDP may begin to
rise and eventually exceed VVDDP_UV_R. At that point, the device will begin to transfer power to the secondary
and start charging the VDDM and VDDH rails. If VDDP remains above VVDDP_UV_R, the device will continue to
transfer power to the secondary eventually charging the VDDM and VDDH rails and VDRV may assert high.
8.3.9 Thermal Shutdown
The device contains an integrated temperature sensor to monitor its local temperature. When the sensor
reaches its threshold, it automatically ceases power transfer from the primary side to the secondary side. In
addition, if power is still present on VDDP, the driver is automatically asserted low. The power transfer is disabled
until the local temperature reduces enough to re-engage.
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
23
Product Folder Links: TPSI3052-Q1
TPSI3052-Q1
ZHCSMH9A –APRIL 2022 –REVISED FEBRUARY 2023
www.ti.com.cn
8.4 Device Functional Modes
表8-3 summarizes the functional modes for the TPSI3052-Q1 and TPSI3052S-Q1.
表8-3. TPSI3052-Q1, TPSI3052S-Q1 Device Functional Modes
VDDP(6)
VDDH
EN(6)
VDRV
COMMENTS
L
L
TPSI3052-Q1 normal operation:
VDRV output state assumes logic state of EN logic
state.
H
L
H
L
TPSI3052S-Q1 (7)normal operation (three-wire
mode only):
Powered up(2)
Powered up(4)
rising edge of EN causes VDRV to be singly pulsed
high. EN must be asserted low first to assert
another pulse.
L →H
L →H →L
Disabled operation:
VDRV output disabled, keep off circuitry applied.
Powered down(3)
Powered up(2)
Powered down(5)
Powered down(5)
X(1)
X(1)
L
L
Disabled operation:
VDRV output disabled, keep off circuitry applied.
Disabled operation:
when VDDP is powered down, output driver is
disabled automatically after timeout, keep off
circuitry applied.
Powered down(3)
Powered up(4)
X(1)
L
(1) X: do not care.
(2)
(3) VVDDP < VDDP undervoltage lockout falling threshold, VVDDP_UV_F
(4) VDDH ≥VDDH undervoltage lockout rising threshold, VVDDH_UV_R
(5) VVDDH < VDDH undervoltage lockout falling threshold, VVDDH_UV_F
VVDDP ≥VDDP undervoltage lockout rising threshold, VVDDP_UV_R.
.
V
.
.
(6) Refer to Power Supply and EN Sequencing for additional information.
(7) Product preview.
Copyright © 2023 Texas Instruments Incorporated
24
Submit Document Feedback
Product Folder Links: TPSI3052-Q1
TPSI3052-Q1
ZHCSMH9A –APRIL 2022 –REVISED FEBRUARY 2023
www.ti.com.cn
9 Application and Implementation
备注
以下应用部分中的信息不属于TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客 户应负责确定
器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。
9.1 Application Information
The TPSI3052-Q1 is a fully integrated, isolated switch driver with integrated bias, which when combined with an
external power switch, forms a complete isolated solid state relay solution. With a nominal gate drive voltage of
15 V with 1.5/3.0-A peak source and sink current, a large variety of external power switches such as MOSFETs,
IGBTs, or SCRs can be chosen to meet a wide range of applications. The TPSI3052-Q1 generates its own
secondary bias supply from the power received from its primary side, so no isolated secondary supply bias is
required.
The TPSI3052-Q1 supports two modes of operation based on the number of input pins required. In two-wire
mode, typically found in driving mechanical relays, controlling the switch requires only two pins and supports a
wide voltage range of operation of 6.5 V to 48 V. In three-wire mode, the primary supply of 3 V to 5.5 V is
supplied externally, and the switch is controlled through a separate enable. Available in three-wire mode only,
the TPSI3052S-Q1 features a one-shot enable for the switch control. This feature is useful for driving SCRs that
typically require only one pulse of current to trigger.
The secondary side provides a regulated, floating supply rail of 15 V for driving a large variety of power switches
with no need for a secondary bias supply. The TPSI3052-Q1 can support driving single power switch, dual back-
to-back, parallel power switches for a variety of AC or DC applications. The TPSI3052-Q1 integrated isolation
protection is extremely robust with much higher reliability, lower power consumption, and increased temperature
ranges than those found using traditional mechanical relays and optocouplers.
The power dissipation of the TPSI3052-Q1 can be adjusted by an external resistor from the PXFR pin to VSSP.
This feature allows for tradeoffs in power dissipation versus power provided on the secondary depending on the
needs of the application.
9.2 Typical Application
The circuits in 图9-1 and 图9-2 show a typical application for driving silicon based MOSFETs in three-wire mode
and two-wire mode, respectively.
VP
RGSRC
RGSNK
EN
VDRV
VSSP
PWR
RPXFR
SIGNAL
PXFR
VDDP
VDDH
VDDM
VSSS
CDIV1
CVDDP
+
–
CDIV2
VP
VSSP
图9-1. TPSI3052-Q1 Three-Wire Mode Driving MOSFETs
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
25
Product Folder Links: TPSI3052-Q1
TPSI3052-Q1
ZHCSMH9A –APRIL 2022 –REVISED FEBRUARY 2023
www.ti.com.cn
RGSRC
RGSNK
6.5–48 V
EN
VDRV
PWR
RPXFR
SIGNAL
PXFR
VDDP
VDDH
VDDM
VSSS
CDIV1
CVDDP
CDIV2
VSSP
图9-2. TPSI3052-Q1 Two-Wire Mode Driving MOSFETs
9.2.1 Design Requirements
表9-1 lists the design requirements of the TPSI3052-Q1 gate driver.
表9-1. TPSI3052-Q1 Design Requirements
DESIGN PARAMETERS
Total gate capacitance
FET turn-on time
100 nC
1 µs
Propagation delay
< 4 µs
Switching frequency
Supply voltage (VDDP)
10 kHz
5 V ± 5%
9.2.2 Detailed Design Procedure
9.2.2.1 Two-Wire or Three-Wire Mode Selection
The first design decision is to determine if two-wire or three-wire mode can be used in the application. For this
design, note that the overall propagation delay is less than 4 µs and only three-wire mode is able to meet this
requirement. In this case, two-wire mode is not applicable. Two-wire mode, due to its limited power transfer, is
typically limited to very low frequency applications of less than a few kHz or when enable times are not critical.
9.2.2.2 Standard Enable, One-Shot Enable
Next, based on the application a decision must be if standard enable or one-shot enable mode is required. In
this design, assume that after the switch is enabled, it is desired that the switch remain enabled until
commanded to be disabled. Therefore, standard enable mode is assumed. In most applications that involve
driving FETs, standard enable is appropriate. If driving SCRs or TRIACS, one-shot mode can be beneficial.
9.2.2.3 CDIV1, CDIV2 Capacitance
The CDIV1 and CDIV2 capacitances required depends on the amount of drop that can be tolerated on the VDDH
rail during switching of the external load. The charge stored on the CDIV1 and CDIV2 capacitances is used to
provide the current to the load during switching. During switching, charge sharing occurs and the voltage on
VDDH drops. At a minimum, TI recommends that the total capacitance formed by the series combination of
CDIV1 and CDIV2 be sized to be at least 30 times the total gate capacitance to be switched. This sizing results in
an approximate 0.5-V drop of the VDDH supply rail that is used to supply power to the VDRV signal. 方程式 1
and 方程式2 can be to used to calculate the amount of capacitance required for a specified voltage drop.
CDIV1 and CDIV2 must be of the same type and tolerance.
Q
n + 1
n
LOAD
∆ V
C
=
×
, n ≥ 3.0
(1)
(2)
DIV1
DIV2
C
= n × C
, n ≥ 3.0
DIV1
where
Copyright © 2023 Texas Instruments Incorporated
26
Submit Document Feedback
Product Folder Links: TPSI3052-Q1
TPSI3052-Q1
ZHCSMH9A –APRIL 2022 –REVISED FEBRUARY 2023
www.ti.com.cn
• n is a real number greater than or equal to 3.0.
• CDIV1 is the external capacitance from VDDH to VDDM.
• CDIV2 is the external capacitance from VDDM to VSSS.
• QLOAD is the total charge of the load from VDRV to VSSS.
• ΔV is the voltage drop on VDDH when switching the load.
备注
CDIV1 and CDIV2 represent absolute capacitances and components selected must be adjusted for
tolerances and any derating necessary to achieve the required capacitances.
Larger values of ΔV can be used in the application, but excessive droop can cause the VDDH undervoltage
lockout falling threshold (VVDDH_UVLO_F) to be reached and cause VDRV to be asserted low. Note that as the
series combination of CDIV1 and CDIV2 capacitances increases relative to QLOAD, the VDDH supply voltage drop
decreases, but the initial charging of the VDDH supply voltage during power up increases.
For this design, assuming n = 3 and ΔV≅ 0.5 V, then
3 + 1
3
120 nC
0.5 V
C
=
×
= 320 nF
(3)
(4)
DIV1
C
= 3 × 320 nF = 960 nF
DIV2
For this design, CDIV1 = 330 nF and CDIV2 = 1 μF standard capacitor values were selected.
9.2.2.4 RPXFR Selection
The selection of RPXFR allows for a tradeoff between power consumed and power delivered, as described in the
Three-wire Mode section. For this design, one must choose an appropriate RPXFR selection that ensures enough
power is transferred to support the amount of load being driven at the specified switching frequency.
During switching of the load, QLOAD of charge on VDDH is transferred to the load and VDDH supply voltage
droops. After each switching cycle, this charge must be replenished before the next switching cycle occurs. This
action ensures that the charge residing on VDDH does not deplete over time due to subsequent switching cycles
of the load. The time it takes to recover this charge, tRECOVER, can be estimated as follows:
Q
1
LOAD
t
=
≅
(5)
RECOVER
I
f
OUT
MAX
where
• QLOAD is the load charge in Coulombs.
• IOUT is the average current available from VDDH supply in Amperes (A).
• fMAX is maximum switching frequency in Hertz (Hz).
For this design, QLOAD = 100 nC and fMAX = 10 kHz are known, so IOUT required can be estimated as
I
≅ 100 nC × 10 kHz = 1.0 mA
(6)
OUT
IOUT represents the minimum average current required to meet the design requirements. Using the TPSI3052-
Q1 calculator tool, one can easily find the RPXFR necessary by referring to the IOUT or fMAX columns directly. 表
9-2 shows the results from the tool, assuming VDDP = 4.75 V, to account for the supply tolerance specified in
the design requirements. The TPSI3052-Q1 Calculator tool can be found at 表10-1.
表9-2. Results from the TPSI3052-Q1 Calculator Tool, TA = 25°C, Three-Wire Mode
Power
Converter
Duty Cycle, %
fEN_MAX
kHz
,
IAUX_MAX
mA
,
IVDDP, mA
PIN, mW
POUT, mW
IOUT, mA
tSTART, µs
tRECOVER, µs
RPXFR, kΩ
7.32
9.09
13.3
21.1
5.3
8.3
25.0
39.6
5.9
10.0
0.35
0.62
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
27
Product Folder Links: TPSI3052-Q1
TPSI3052-Q1
ZHCSMH9A –APRIL 2022 –REVISED FEBRUARY 2023
www.ti.com.cn
表9-2. Results from the TPSI3052-Q1 Calculator Tool, TA = 25°C, Three-Wire Mode (continued)
Power
Converter
Duty Cycle, %
fEN_MAX
kHz
,
IAUX_MAX
mA
,
IVDDP, mA
PIN, mW
POUT, mW
IOUT, mA
tSTART, µs
tRECOVER, µs
RPXFR, kΩ
11
40.0
53.3
66.7
80.0
93.3
15.8
75.1
26.8
36.1
45.5
58.8
68.8
1.74
2076
56.3
17.8
23.9
30.2
39.0
45.6
2.3
4.1
12.7
14.7
16.5
20
21.1
26.4
31.6
36.9
100.1
125.2
150.2
175.2
2.35
2.98
3.86
4.52
1581
1287
1032
905
41.8
33.2
25.7
21.9
6.0
8.6
10.0
表9-3 summarizes the various output parameters of the calculator tool.
表9-3. TPSI3052-Q1 Calculator Tool Parameter Descriptions
Parameter
Description
External resistor setting that controls the amount of power transferred to the load by adjusting the duty
cycle. Higher RPXFR settings lead to increased power transfer and power consumption.
RPXFR
Nominal duty cycle of the power converter. Higher RPXFR settings leads to higher duty cycles of the power
converter and higher power transfer.
Power Converter Duty Cycle
IVDDP
PIN
POUT
IOUT
Average current consumed from the VDDP supply
Average power consumed from the VDDP supply
Average power delivered to the VDDH supply
Average current delivered to the VDDH supply
Start-up time from VDDP rising until VDDH supply rail is fully charged. This parameter assumes VDDH and
VDDM supply rails are fully discharged initially.
tSTART
tRECOVER
fMAX
Represents the time for the VDDH rail to recover after switching the load present on VDRV
Maximum switching frequency possible for a given RPXFR setting for the applied loading conditions
Maximum auxiliary current available at current user input settings. There is an inverse relationship between
IAUX_MAX
fMAX and IAUX_MAX
.
For this design example, RPXFR must be configured to the 9.09-kΩsetting or higher to transfer enough power to
support switching the specified load at the required 10-kHz frequency.
9.2.2.5 CVDDP Capacitance
For two-wire mode, the recommended capacitance CVDDP from VDDP to VSSP is 220 nF.
For this design, three-wire mode is required to meet the design requirements. For three-wire mode, increasing
the amount of capacitance, CVDDP, improves the ripple on the VDDP supply. For this design, 1 μF in parallel
with 100 nF is used.
9.2.2.6 Gate Driver Output Resistor
The optional external gate driver resistors, RGSRC and RGSNK, along with the diode are used to:
1. Limit ringing caused by parasitic inductances and capacitances
2. Limit ringing caused by high voltage switching dv/dt, high current switching di/dt, and body-diode reverse
recovery
3. Fine-tune gate drive strength for sourcing and sinking
4. Reduce electromagnetic interference (EMI)
The TPSI3052-Q1 has a pullup structure with a P-channel MOSFET with a peak source current of 1.5 A.
Therefore, the peak source current can be predicted with:
V
VDDH
I
≅ min 1.5 A,
(7)
O +
R
+ R
+ R
GFET_INT
DSON_VDRV
GSRC
where
Copyright © 2023 Texas Instruments Incorporated
28
Submit Document Feedback
Product Folder Links: TPSI3052-Q1
TPSI3052-Q1
ZHCSMH9A –APRIL 2022 –REVISED FEBRUARY 2023
www.ti.com.cn
• RGSRC: external turn-on resistance.
• RDSON_VDRV: TPSI3052-Q1 driver on resistance in high state. See Electrical Characteristics.
• VVDDH: VDDH voltage. Assumed 15.1 V in this example.
• RGFET_INT: external power transistor internal gate resistance, found in the power transistor data sheet.
Assume 0 Ωfor this example.
• IO+: peak source current. The minimum value between 1.5 A, the gate driver peak source current, and the
calculated value based on the gate drive loop resistance.
For this example, RDSON_VDRV = 2.5Ω, RGSRC = 10 Ω, and RGFET_INT = 0 Ωresults in:
15.1 V
2.5 Ω + 10 Ω + 0 Ω
I
≅ min 1.5 A,
= 1.21 A
(8)
O +
Similarly, the TPSI3052-Q1 has a pulldown structure with an N-channel MOSFET with a peak sink current of 3.0
A. Therefore, assuming RGFET_INT = 0 Ω, the peak sink current can be predicted with:
1
I
≅ min 3.0 A, V
× R
+ R
− R
× V ×
F
(9)
O −
VDDH
GSRC
GSNK
GSRC
R
× R
GSNK
+ R
DSON_VDRV
× R
GSRC
+ R
GSNK
GSRC
where
• RGSRC: external turn-on resistance.
• RGSNK: external turn-off resistance.
• RDSON_VDRV: TPSI3052-Q1 driver on resistance in low state. See Electrical Characteristics.
• VVDDH: VDDH voltage. Assumed 15.1 V in this example.
• VF: diode forward voltage drop. Assumed 0.7 V in this example.
• IO-: peak sink current. The minimum value between 3.0 A, the gate driver peak sink current, and the
calculated value based on the gate drive loop resistance.
For this example, assuming RDSON_VDRV = 1.7 Ω, RGSRC = 10 Ω, RGSNK = 5.0 Ω, and RGFET_INT = 0 Ω, results
in:
1
I
≅ min 3.0 A, 15.1 V × 10 Ω + 5 Ω − 10Ω × 0.7 V ×
= 2.91 A
(10)
O −
10 Ω × 5 Ω + 1.7 Ω × 10Ω + 5 Ω
Importantly, the estimated peak current is also influenced by PCB layout and load capacitance. Parasitic
inductance in the gate driver loop can slow down the peak gate drive current and introduce overshoot and
undershoot. Therefore, TI strongly recommends to minimize the gate driver loop.
9.2.2.7 Start-up Time and Recovery Time
As described in the CDIV1, CDIV2 Capacitance section, the start-up time of the fully discharged VDDH rail
depends on the amount of capacitance present on the VDDH supply. The rate at which this capacitance is
charged depends on the amount of power transferred from the primary side to the secondary side. The amount
of power transferred can be adjusted by choosing RPXFR. Increasing the resistor settings for RPXFR transfers
more power from the primary supply (VDDP) to the secondary supply (VDDH), thereby reducing the overall start-
up and recovery times.
9.2.2.8 Supplying Auxiliary Current, IAUX From VDDM
The TPSI3052-Q1 is capable of providing power from VDDM to support external auxiliary circuitry as shown in
图 9-3. In this case, the required transfer power must include the additional power consumed by the auxiliary
circuitry on the VDDM rail. The RPXFR value must be set to meet the overall power requirements.
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
29
Product Folder Links: TPSI3052-Q1
TPSI3052-Q1
ZHCSMH9A –APRIL 2022 –REVISED FEBRUARY 2023
www.ti.com.cn
VP
RGSRC
RGSNK
EN
VDRV
VSSP
PWR
RPXFR
SIGNAL
PXFR
VDDP
VDDH
VDDM
VSSS
CDIV1
IAUX
CVDDP
Auxiliary
Circuit
+
–
CDIV2
VP
VSSP
图9-3. Supplying Auxiliary Power From VDDM
As an example, assume that the auxiliary circuitry requires an average current of 4 mA. 表 9-4 summarizes the
results from the TPSI3052-Q1 calculator tool. The Calculator tool can be found at 表10-1.
表9-4. Results from the TPSI3052-Q1 Calculator Tool, TA = 25°C, Three-Wire Mode with IAUX = 4 mA
Power
Converter
Duty Cycle, %
fEN_MAX
kHz
,
IAUX_MAX
mA
,
IVDDP, mA
PIN, mW
POUT, mW
IOUT, mA
tSTART, µs
tRECOVER, µs
RPXFR, kΩ
7.32
13.3
21.1
40.0
53.3
66.7
80.0
93.3
5.3
25.0
5.9
0.35
N/A
N/A
N/A
N/A
N/A
N/A
N/A
4.1
9.09
11
8.3
15.8
21.1
26.4
31.6
36.9
39.6
75.1
10.0
26.8
36.1
45.5
58.8
68.8
0.62
1.74
2.35
2.98
3.86
4.52
N/A
N/A
N/A
N/A
N/A
12.7
14.7
16.5
20
100.1
125.2
150.2
175.2
3557
2285
1549
1262
96.0
60.1
39.3
31.2
10.4
16.6
25.5
32.1
6.0
8.6
10.0
Based on the results in 表9-4, several observations can be made:
• With RPXFR = 7.32 kΩ , RPXFR = 9.09 kΩ, and RPXFR = 11 kΩ, insufficient power is available to meet the
application power needs specified in the design requirements in 表9-1.
• With RPXFR = 12.7 kΩ and higher, sufficient power is transferred to meet the specified design requirements,
however, for this design, RPXFR = 14.7 kΩ was selected for additional margin.
• For a given RPXFR, because a significant amount of the transferred power is being provided to the auxiliary
circuitry, tSTART is longer, and fMAX reduced when compared to the results shown in 表9-2 with IAUX = 0 mA.
9.2.2.9 VDDM Ripple Voltage
Note that when supplying power from VDDM, that is when IAUX > 0 mA, additional voltage ripple is present on
the VDDM rail. For a given RPXFR setting, this ripple can be reduced by applying additional capacitance from
VDDM to VSSS or increasing the RPXFR setting for more power tranfser. For this design example, the ripple on
VDDM, VDDMripple, computed in the calculator tool is 35 mV.
Copyright © 2023 Texas Instruments Incorporated
30
Submit Document Feedback
Product Folder Links: TPSI3052-Q1
TPSI3052-Q1
ZHCSMH9A –APRIL 2022 –REVISED FEBRUARY 2023
www.ti.com.cn
9.2.3 Application Curves
Three-wire mode
CDIV1 = 330 nF
IAUX = 0 mA
VDDP = 5.0 V
Three-wire mode
CDIV1 = 330 nF
IAUX = 0 mA
VDDP = 5.0 V
RPXFR = 11 kΩ
RPXFR = 11 kΩ
CDIV2 = 1 μF
CDIV2 = 1 μF
CVDRV = 6.8 nF
TA = 25°C
CVDRV = 6.8 nF
TA = 25°C
图9-4. Power Up, VEN = VVDDP, Three-Wire Mode, TPSI3052-Q1
图9-5. tLH_VDRV, Three-Wire Mode, TPSI3052-Q1
Three-wire mode
CDIV1 = 330 nF
IAUX = 0 mA
VDDP = 5.0 V
Three-wire mode
CDIV1 = 330 nF
IAUX = 0 mA
VDDP = 5.0 V
RPXFR = 11 kΩ
RPXFR = 11 kΩ
CDIV2 = 1 μF
CDIV2 = 1 μF
CVDRV = 6.8 nF
TA = 25°C
CVDRV = 6.8 nF
TA = 25°C
图9-6. tHL_VDRV, Three-Wire Mode, TPSI3052-Q1
图9-7. Three-Wire Mode, fEN = 10 kHz, TPSI3052-Q1
Three-wire mode
CDIV1 = 330 nF
IAUX = 4 mA
VDDP = 5.0 V
Three-wire mode
CDIV1 = 330 nF
IAUX = 4 mA
VDDP = 5.0 V
RPXFR = 14.7 kΩ
RPXFR = 14.7 kΩ
CDIV2 = 1 μF
CDIV2 = 1 μF
CVDRV = 6.8 nF
TA = 25°C
CVDRV = 6.8 nF
TA = 25°C
图9-8. Power Up, VEN = VVDDP, Three-Wire Mode,
图9-9. tLH_VDRV, Three-Wire Mode, TPSI3052-Q1
TPSI3052-Q1
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
31
Product Folder Links: TPSI3052-Q1
TPSI3052-Q1
ZHCSMH9A –APRIL 2022 –REVISED FEBRUARY 2023
www.ti.com.cn
9.2.3 Application Curves (continued)
Three-wire mode
CDIV1 = 330 nF
IAUX = 4 mA
VDDP = 5.0 V
Three-wire mode
CDIV1 = 330 nF
IAUX = 4 mA
VDDP = 5.0 V
RPXFR = 14.7 kΩ
RPXFR = 14.7 kΩ
CDIV2 = 1 μF
CDIV2 = 1 μF
CVDRV = 6.8 nF
TA = 25°C
CVDRV = 6.8 nF
TA = 25°C
图9-10. tHL_VDRV, Three-Wire Mode, TPSI3052-Q1
图9-11. Three-Wire Mode, fEN = 10 kHz, TPSI3052-Q1
9.2.4 Insulation Lifetime
Insulation lifetime projection data is collected by using industry-standard Time Dependent Dielectric Breakdown
(TDDB) test method. In this test, all pins on each side of the barrier are tied together creating a two-terminal
device and high voltage applied between the two sides; See 图 9-12 for TDDB test setup. The insulation
breakdown data is collected at various high voltages switching at 60 Hz over temperature. For reinforced
insulation, VDE standard requires the use of TDDB projection line with failure rate of less than 1 part per million
(ppm). Even though the expected minimum insulation lifetime is 20 years at the specified working isolation
voltage, VDE reinforced certification requires additional safety margin of 20% for working voltage and 87.5% for
lifetime which translates into minimum required insulation lifetime of 37.5 years at a working voltage that's 20%
higher than the specified value.
图 9-13 shows the intrinsic capability of the isolation barrier to withstand high voltage stress over its lifetime.
Based on the TDDB data, the intrinsic capability of the insulation is 1000 VRMS with a lifetime of 1184 years.
图9-12. Test Setup for Insulation Lifetime Measurement
Copyright © 2023 Texas Instruments Incorporated
32
Submit Document Feedback
Product Folder Links: TPSI3052-Q1
TPSI3052-Q1
ZHCSMH9A –APRIL 2022 –REVISED FEBRUARY 2023
www.ti.com.cn
图9-13. Insulation Lifetime Projection Data
9.3 Power Supply Recommendations
In three-wire mode, to help ensure a reliable supply voltage, TI recommends that the CVDDP capacitance from
VDDP to VSSP consists of a 0.1-μF bypass capacitor for high frequency decoupling in parallel with a 1 μF for
low frequency decoupling.
In two-wire mode, TI recommends that the CVDDP capacitance placed from VDDP to VSSP consists of a 220-nF
capacitor connected close to the device between the VDDP and VSSP pins. The recommended absolute
capacitance must be 220 nF, so if derating is required, a higher component value can be needed.
Low-ESR and low-ESL capacitors must be connected close to the device between the VDDP and VSSP pins.
9.4 Layout
9.4.1 Layout Guidelines
Designers must pay close attention to PCB layout to achieve optimum performance for the TPSI3052-Q1. Some
key guidelines are:
• Component placement:
– Place the driver as close as possible to the power semiconductor to reduce the parasitic inductance of the
gate loop on the PCB traces.
– Connect low-ESR and low-ESL capacitors close to the device between the VDDH and VDDM pins and the
VDDM and VSSS pins to bypass noise and to support high peak currents when turning on the external
power transistor.
– Connect low-ESR and low-ESL capacitors close to the device between the VDDP and VSSP pins.
– Minimize parasitic capacitances on the RPXFR pin.
• Grounding considerations:
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
33
Product Folder Links: TPSI3052-Q1
TPSI3052-Q1
ZHCSMH9A –APRIL 2022 –REVISED FEBRUARY 2023
www.ti.com.cn
– Limit the high peak currents that charge and discharge the transistor gates to a minimal physical area.
This limitation decreases the loop inductance and minimizes noise on the gate terminals of the transistors.
Place the gate driver as close as possible to the transistors.
– Connect the driver VSSS to the Kelvin connection of MOSFET source or IGBT emitter. If the power device
does not have a split Kelvin source or emitter, connect the VSSS pin as close as possible to the source or
emitter terminal of the power device package to separate the gate loop from the high power switching
loop.
• High-voltage considerations:
– To ensure isolation performance between the primary and secondary side, avoid placing any PCB traces
or copper below the driver device. TI recommends a PCB cutout or groove to prevent contamination that
can compromise the isolation performance.
• Thermal considerations:
– Proper PCB layout can help dissipate heat from the device to the PCB and minimize junction-to-board
thermal impedance (θJB).
– If the system has multiple layers, TI also recommends connecting the VDDH and VSSS pins to internal
ground or power planes through multiple vias of adequate size. These vias must be located close to the IC
pins to maximize thermal conductivity. However, keep in mind that no traces or coppers from different high
voltage planes are overlapping.
9.4.2 Layout Example
图9-14 shows a PCB layout example with the signals and key components labeled.
图9-14. 3-D PCB View
图9-15 and 图9-16 show the top and bottom layer traces and copper.
Copyright © 2023 Texas Instruments Incorporated
34
Submit Document Feedback
Product Folder Links: TPSI3052-Q1
TPSI3052-Q1
ZHCSMH9A –APRIL 2022 –REVISED FEBRUARY 2023
www.ti.com.cn
图9-15. Top Layer
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
35
Product Folder Links: TPSI3052-Q1
TPSI3052-Q1
ZHCSMH9A –APRIL 2022 –REVISED FEBRUARY 2023
www.ti.com.cn
图9-16. Bottom Layer
Copyright © 2023 Texas Instruments Incorporated
36
Submit Document Feedback
Product Folder Links: TPSI3052-Q1
TPSI3052-Q1
ZHCSMH9A –APRIL 2022 –REVISED FEBRUARY 2023
www.ti.com.cn
10 Device and Documentation Support
10.1 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to order now.
表10-1. Related Links
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
PARTS
PRODUCT FOLDER
ORDER NOW
TPSI3052-Q1
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
TPSI3052S-Q1
10.2 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
10.3 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
10.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
10.5 静电放电警告
静电放电(ESD) 会损坏这个集成电路。德州仪器(TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理
和安装程序，可能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级，大至整个器件故障。精密的集成电路可能更容易受到损坏，这是因为非常细微的参
数更改都可能会导致器件与其发布的规格不相符。
10.6 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
11 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
37
Product Folder Links: TPSI3052-Q1
PACKAGE OPTION ADDENDUM
www.ti.com
12-Apr-2023
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPSI3052QDWZRQ1
TPSI3052SQDWZRQ1
ACTIVE
ACTIVE
SO-MOD
SO-MOD
DWZ
DWZ
8
8
1000 RoHS & Green
1000 RoHS & Green
NIPDAU
Level-3-260C-168 HR
Level-3-260C-168 HR
-40 to 125
-40 to 125
I3052Q1
I3052SQ1
Samples
Samples
NIPDAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
12-Apr-2023
OTHER QUALIFIED VERSIONS OF TPSI3052-Q1 :
Catalog : TPSI3052
•
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
•
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
17-Apr-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPSI3052QDWZRQ1 SO-MOD DWZ
TPSI3052SQDWZRQ1 SO-MOD DWZ
8
8
1000
1000
330.0
330.0
16.4
16.4
12.05 6.15
12.05 6.15
3.3
3.3
16.0
16.0
16.0
16.0
Q1
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
17-Apr-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TPSI3052QDWZRQ1
TPSI3052SQDWZRQ1
SO-MOD
SO-MOD
DWZ
DWZ
8
8
1000
1000
350.0
350.0
350.0
350.0
43.0
43.0
Pack Materials-Page 2
PACKAGE OUTLINE
DWZ0008A
SOIC - 2.8 mm max height
SMALL OUTLINE PACKAGE
C
SEATING PLANE
11.75
11.25
TYP
PIN 1 ID
AREA
0.1 C
6X 1.27
8
1
5.95
5.75
NOTE3
2X
3.81
4
5
0.51
0.31
8X
7.6
7.4
NOTE4
0.25
C A
A
B
2.8 MAX
0.33
0.13
TYP
SEE DETAIL A
(2.286)
0.25
GAGE PLANE
0.46
0.36
0 -8
1
0.5
DETAIL A
TYPICAL
2.1
(
)
1.9
4226306/A 09/2020
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Ref. JEDEC registration MS-013
www.ti.com
EXAMPLE BOARD LAYOUT
DWZ0008A
SOIC - 2.8 mm max height
SMALL OUTLINE PACKAGE
8X (1.8)
SEE DETAILS
SYMM
SYMM
8X (0.6)
6X (1.27)
(10.9)
LAND PATTERN EXAMPLE
9.1 mm NOMINAL CLEARANCE/CREEPAGE
SCALE: 6X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL
METAL
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4226306/A 09/2020
NOTES: (continued)
5. Publication IPC-7351 may have alternate designs.
6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DWZ0008A
SOIC - 2.8 mm max height
SMALL OUTLINE PACKAGE
SYMM
8X (1.8)
8X (0.6)
SYMM
6X (1.27)
(10.9)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 6X
4226306/A 09/2020
NOTES: (continued)
7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.
www.ti.com
重要声明和免责声明
TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，
不保证没有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担
保。
这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验
证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。
这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。
您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成
本、损失和债务，TI 对此概不负责。
TI 提供的产品受 TI 的销售条款或 ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI 提供这些资源并不会扩展或以其他方式更改
TI 针对 TI 产品发布的适用的担保或担保免责声明。
TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE
邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2023，德州仪器 (TI) 公司
相关型号：
©2020 ICPDF网 联系我们和版权申明