TPSM560R6HRDAR [TI]
采用 5mm x 5.5mm x 4mm QFN 封装的 4.2V 至 60V 输入、1V 至 16V 输出、0.6A 降压模块 | RDA | 15 | -40 to 125;
| 型号： | TPSM560R6HRDAR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 采用 5mm x 5.5mm x 4mm QFN 封装的 4.2V 至 60V 输入、1V 至 16V 输出、0.6A 降压模块 | RDA | 15 | -40 to 125 |
| 文件： | 总30页 (文件大小：2273K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPSM560R6H
ZHCSNI2 –SEPTEMBER 2021
TPSM560R6H 采用增强型HotRod™ QFN 封装的60V 输入、1V 至16V 输出、
600mA 电源模块
1 特性
3 说明
• 提供功能安全
TPSM560R6H 是一款高度集成的 600mA 电源模块，
在热增强型 QFN 封装内整合了一个带有功率
MOSFET 的 60V 输入直流/直流降压转换器、一个屏
蔽式电感器和多个无源器件。此 5.0mm × 5.5mm ×
4.0mm、15 引脚 QFN 封装采用增强型 HotRod QFN
技术来实现增强的热性能、小尺寸和低 EMI。封装引
脚外露，具有单个大型散热焊盘，方便布局布线和组
装。
– 可帮助进行功能安全系统设计的文档
• 5.0mm × 5.5mm × 4.0mm 增强型HotRod™ QFN
– 出色的热性能：在85°C 且无散热的情况下高达
9.6W 的输出功率
– 标准封装尺寸：单个大型散热焊盘和所有引脚均
分布在封装外围
• 专为可靠耐用的应用而设计
– 宽输入电压范围：4.2V 至60V
– 高达66V 的输入电压瞬态保护
– 工作结温范围：–40°C 至+125°C
• 固定1MHz 开关频率
TPSM560R6H 是一款紧凑、易用的电源模块，具有
1.0V 至 16V 的可调节宽输出电压范围。该总体解决方
案仅需四个外部元件，并且省去了设计流程中的环路补
偿和磁性器件选型过程。TPSM560R6H 具有全套功
能，包括电源正常状态指示、可编程UVLO、预偏置启
动、过流和温度保护，因此是为各种应用供电的出色器
件。空间受限型应用可从 5.0mm × 5.5mm 封装中受
益。
• FPWM 运行模式
• 针对超低EMI 要求进行了优化
– 集成屏蔽式电感器和高频旁路电容器
– 符合EN55011 EMI 标准
• 26µA 非开关静态电流
• 单调启动至预偏置输出
• 无环路补偿或自举组件
器件信息
封装(1)
封装尺寸（标称值）
器件型号
TPSM560R6H
QFN (15)
5.0mm × 5.5mm
• 具有迟滞功能的精密使能和输入UVLO
• 具有迟滞功能的热关断保护
• 使用TPSM560R6H 并借助WEBENCH® Power
Designer 创建定制设计
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
2 应用
• 现场发送器和传感器、PLC 模块
• 恒温器、视频监控、HVAC 系统
• 交流和伺服驱动器、旋转编码器
• 工业运输、资产跟踪
• 负输出应用
100
90
80
70
60
50
40
PGOOD
VIN
VIN
EN
VOUT
VOUT
CIN
TPSM560R6H
RFBT
COUT
V5V
FB
30
VOUT = 12 V
20
VIN = 24 V
PGND
AGND
VIN = 48 V
VIN = 60 V
10
0
RFBB
0
0.1
0.2
0.3
0.4
0.5
0.6
Output Current (A)
典型效率(VOUT = 12V)
典型电路原理图
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLVSG72
TPSM560R6H
ZHCSNI2 –SEPTEMBER 2021
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Table of Contents
7.4 Device Functional Modes..........................................14
8 Applications and Implementation................................16
8.1 Application Information............................................. 16
8.2 Typical Application.................................................... 16
9 Power Supply Recommendations................................18
10 Layout...........................................................................19
10.1 Layout Guidelines................................................... 19
10.2 Layout Example...................................................... 19
11 Device and Documentation Support..........................23
11.1 Device Support........................................................23
11.2 Documentation Support.......................................... 23
11.3 接收文档更新通知................................................... 23
11.4 支持资源..................................................................23
11.5 Trademarks............................................................. 23
11.6 Electrostatic Discharge Caution..............................24
11.7 术语表..................................................................... 24
12 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings ....................................... 4
6.2 ESD Ratings .............................................................. 4
6.3 Recommended Operating Conditions ........................5
6.4 Thermal Information ...................................................5
6.5 Electrical Characteristics ............................................6
6.6 Typical Characteristics (VIN = 12 V)............................7
6.7 Typical Characteristics (VIN = 24 V)............................8
6.8 Typical Characteristics (VIN = 48 V)............................9
6.9 Typical Characteristics (VIN = 60 V)..........................10
7 Detailed Description......................................................11
7.1 Overview................................................................... 11
7.2 Functional Block Diagram......................................... 11
7.3 Feature Description...................................................12
Information.................................................................... 24
4 Revision History
DATE
REVISION
NOTES
September 2021
*
Initial release
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5 Pin Configuration and Functions
VIN
VIN
1
14
NC
2
13
12
11
10
9
EN
NC
3
4
5
6
PGOOD
V5V
15
SW
PGND
AGND
FB
DNC
NC
7
VOUT
VOUT
8
图5-1. 15-Pin QFN RDA Package (Top View)
表5-1. Pin Functions
PIN
TYPE(1)
DESCRIPTION
NO.
NAME
Analog ground. Zero voltage reference for internal references and logic. All electrical parameters are
measured with respect to this pin. This pin must be connected to PGND at a single point. See 节10.2 for
a recommended layout.
10
AGND
G
Do not connect. Do not connect this pin to ground, to another pin, or to any other voltage. This pin is
connected to the internal bootstrap capacitor. This pin must be soldered to an isolated pad.
5
2
DNC
EN
—
Enable pin. This pin turns the converter on when pulled high and turns off the converter when pulled low.
This pin can be connected directly to VIN. Do not float. This pin can be used to set the input undervoltage
lockout with two resistors. See 节7.3.4.
I
Feedback input. Connect the mid-point of the feedback resistor divider to this pin. Connect the upper
resistor (RFBT) of the feedback divider to VOUT at the desired point of regulation. Connect the lower
resistor (RFBB) of the feedback divider to AGND.
9
FB
NC
I
Not connected. These pins are not connected to any circuitry within the module. Leaving these pins
unconnected to any other signal increases spacing near the high voltage pins (VIN, SW, EN, and DNC).
However, if the high voltage spacing is not needed in the application, connecting these pins to the PGND
plane can help enhance shielding and thermal performance.
3, 6, 13
—
Power ground. This is the return current path for the power stage of the device. Connect this pad to the
input supply return, load return, and capacitors associated with the VIN and VOUT pins. See 节10.2 for a
recommended layout.
15
12
PGND
G
O
Power-good pin. An open-drain output that asserts low if the feedback voltage is not within the specified
window thresholds. A 10-kΩto 100-kΩpullup resistor is required and can be tied to the V5V pin or other
DC voltage less than 18 V. If not used, this pin can be left open or connected to PGND.
PGOOD
4
SW
VIN
O
I
Switch node. Do not place any external component on this pin or connect this pin to any signal.
Input supply voltage. Connect the input supply to these pins. Connect input capacitors between these
pins and PGND in close proximity to the device.
1, 14
Output voltage. These pins are connected to the internal output inductor. Connect these pins to the
output load and connect external output capacitors between these pins and PGND.
7, 8
11
VOUT
V5V
O
O
Internal 5-V LDO output. Supplies internal control circuits. Do not connect to external loads. This pin can
be used as logic supply for the PGOOD pin.
(1) G = Ground, I = Input, O = Output
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6 Specifications
6.1 Absolute Maximum Ratings
Over the operating ambient temperature range(1)
PARAMETER
MIN
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
0
MAX
UNIT
VIN to PGND
66
VIN + 0.3
22
EN to AGND(2)
Input voltage
PGOOD to AGND(2)
FB to AGND
V
5.5
AGND to PGND
VOUT to PGND(2)
VCC to AGND
0.3
30
Output voltage
5.5
Operating IC junction
temperature, TJ
125
°C
°C
–40
–55
(3)
Storage temperature, Tstg
150
245
3
Peak reflow case temperature
Maximum number or reflows allowed
Mechanical vibration
Mechanical shock
Mil-STD-883H, Method 2007.3, 1 msec, 1/2 sine, mounted
Mil-STD-883H, Method 2002.5, 20 to 2000Hz
20
G
G
500
(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If
used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully
functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.
(2) The voltage on this pin must not exceed the voltage on the VIN pin by more than 0.3 V.
(3) The ambient temperature is the air temperature of the surrounding environment. The junction temperature is the temperature of the
internal power IC when the device is powered. Operating below the maximum ambient temperature, as shown in the safe operating
area (SOA) curves in the tTypical Applications sections, ensures that the maximum junction temperature of any component inside the
module is never exceeded.
6.2 ESD Ratings
VALUE
±1500
±1500
UNIT
Human-body model (HBM)(1)
V(ESD)
Electrostatic discharge
V
Charged-device model (CDM)(2)
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
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6.3 Recommended Operating Conditions
Over operating ambient temperature range (unless otherwise noted) (1)
MIN
4.2
1
MAX
60
UNIT
V
Input voltage, VIN
Output voltage, VOUT
Output current, IOUT
16 (3)
0.6
V
0
A
(2)
EN voltage, VEN
0
VIN
V
(2)
PGOOD pullup voltage, VPGOOD
0
18
V
Operating ambient temperature, TA
105
°C
–40
(1) Recommended operating conditions indicate conditions where the device is intended to be functional, but do not ensure specific
performance limits. For ensured specifications, see the Electrical Characteristics.
(2) The voltage on this pin must not exceed the voltage on the VIN pin by more than 0.3 V.
(3) The recommended maximum output voltage varies depending input voltage.
6.4 Thermal Information
TPSM560R6H
THERMAL METRIC(1)
RDA (QFN)
15 PINS
20.4
UNIT
Nat Conv
100 LFM
200 LFM
°C/W
°C/W
°C/W
°C/W
°C/W
°C
RθJA
Junction-to-ambient thermal resistance (2)
18.9
17.6
Junction-to-top characterization parameter (3)
Junction-to-board characterization parameter (4)
Thermal shutdown temperature
3.6
ψJT
ψJB
15.3
170
TSHDN
Recovery temperature
158
°C
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
(2) The junction-to-ambient thermal resistance, RθJA, applies to devices soldered directly to a 6.35-cm × 8.25-cm, four-layer PCB with 2-
oz. copper. Additional airflow and PCB copper area reduces RθJA. See 节10.2.1 for more information.
(3) The junction-to-top board characterization parameter, ψJT, estimates the junction temperature, TJ, of a device in a real system, using a
procedure described in JESD51-2A (section 6 and 7). TJ = ψJT × Pdis + TT; where Pdis is the power dissipated in the device and TT is
the temperature of the top of the device.
(4) The junction-to-board characterization parameter, ψJB, estimates the junction temperature, TJ, of a device in a real system, using a
procedure described in JESD51-2A (sections 6 and 7). TJ = ψJB × Pdis + TB; where Pdis is the power dissipated in the device and TB
is the temperature of the board 1 mm from the device.
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6.5 Electrical Characteristics
Limits apply over TA = –40°C to +105°C, VIN = 24 V, VOUT = 3.3 V, IOUT = 600 mA, (unless otherwise noted); minimum and
maximum limits are specified through production test or by design. Typical values represent the most likely parametric norm
and are provided for reference only.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
INPUT VOLTAGE (VIN
)
Input voltage range
VIN turn-on
Over IOUT range
4.2 (1)
60
V
V
VIN
VIN increasing, IOUT = 0 A, VEN = VIN
VIN decreasing, IOUT = 0 A, VEN = VIN
VEN = 0 V, IOUT = 0 A
3.8
3.3
5
VIN turn-off
V
ISHDN
Shutdown supply current
µA
INTERNAL LDO (V5V)
Internal LDO output voltage appearing
at the V5V pin
V5V
4.75
5
5.25
V
6 V ≤VIN ≤60 V
FEEDBACK
VFB
Load regulation
Line regulation
0.057
0.024
0.2
%
%
TA = +25°C, 0 A ≤IOUT ≤0.6 A
TA = +25°C, IOUT = 0 A, 6 V ≤VIN ≤60 V
FB = 1 V
VFB
IFB
Current into FB pin
nA
CURRENT
IOUT
Output current
TA = 25ºC
0
0.6
A
A
IOUT
Overcurrent threshold
VOUT = 3.3 V, TA = 25ºC
0.89
0.4
FB pin voltage required to trip short-
circuit Hiccup mode
VHC
tHC
V
Time between current-limit hiccup
burst
94
ms
ENABLE (EN PIN)
EN input level required to turn on the
internal LDO
VEN-VCC-H
VEN-VCC-L
VEN-H
Rising threshold
Falling threshold
Rising threshold
1.14
1.30
V
V
V
EN input level required to turn off the
internal LDO
0.3
EN input level required to start
switching
1.157
1.231
VEN-HYS
ILKG-EN
Hysteresis below VEN-H
Hysteresis below VEN-H; falling
VEN = 3.3 V
110
0.2
mV
nA
Enable input leakage current
POWER GOOD (PGOOD PIN)
VPG-LOW-UP
VPG-HIGH-DN
VPG-HIGH-UP
VPG-LOW-DN
RPG
VOUT rising (fault)
% of FB voltage
% of FB voltage
% of FB voltage
% of FB voltage
VEN = 0 V
107%
105%
95%
93%
35
VOUT falling (good)
VOUT rising (good)
VOUT falling (fault)
Power-good flag, RDSON
Ω
Minimum input voltage for proper
PGOOD function
VIN-PG
IPG = 50 µA, EN = 0 V
2
V
PERFORMANCE
Efficiency
VOUT = 3.3 V, IOUT = 0.75 A, TA = 25ºC
VOUT = 5.0 V, IOUT = 0.75 A, TA = 25ºC
81%
86%
η
Efficiency
η
SOFT START
tSS
Internal soft-start time
4.5
1(2)
ms
SWITCHING FREQUENCY
Switching frequency
IOUT = 0.75 A, TA = 25ºC
0.85
1.15
MHz
ƒSW
(1) The recommended minimum VIN is 4.2 V or (VOUT + 600 mV), whichever is greater.
(2) The typical switching frequency of this device changes based on operating conditions. See the Switching Frequency section for more
information.
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6.6 Typical Characteristics (VIN = 12 V)
TA = 25°C, unless otherwise noted.
100
90
80
70
60
50
40
30
20
10
0
0.6
0.5
0.4
0.3
0.2
0.1
0
VOUT
5.0 V
3.3 V
2.5 V
1.8 V
1.2 V
VOUT
5.0 V
3.3 V
2.5 V
1.8 V
1.2 V
0
0.1
0.2
0.3
0.4
0.5
0.6
0
0.1
0.2
0.3
0.4
0.5
0.6
Output Current (A)
Output Current (A)
图6-1. Efficiency
图6-2. Power Dissipation
115
105
95
8
7
6
5
4
3
2
1
0
VOUT
5.0 V
3.3 V
2.5 V
1.8 V
1.2 V
85
75
65
55
45
35
Airflow
Nat Conv
0
0.1
0.2
0.3
0.4
0.5
0.6
25
0
0.1
0.2
0.3
0.4
0.5
0.6
Output Current (A)
Output Current (A)
COUT = 4 × 47 µF, 25-V, ceramic
Device soldered to a 63.5-mm × 82.5-mm, 4-layer PCB
图6-3. Output Voltage Ripple
图6-4. Safe Operating Area (All VOUT
)
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6.7 Typical Characteristics (VIN = 24 V)
TA = 25°C, unless otherwise noted.
100
90
80
70
60
50
40
30
20
10
0
1.2
1
VOUT
15 V
12 V
9 V
5 V
3.3 V
2.5 V
1.8 V
0.8
0.6
0.4
0.2
0
VOUT
15 V
12 V
9 V
5 V
3.3 V
2.5 V
1.8 V
0
0.1
0.2
0.3
0.4
0.5
0.6
0
0.1
0.2
0.3
0.4
0.5
0.6
Output Current (A)
Output Current (A)
图6-5. Efficiency
图6-6. Power Dissipation
115
105
95
20
18
16
14
12
10
8
VOUT
15 V
12 V
9 V
5 V
85
3.3 V
2.5 V
1.8 V
75
65
6
55
4
45
2
35
Airflow
Nat Conv
0
0
0.1
0.2
0.3
0.4
0.5
0.6
25
0
0.1
0.2
0.3
0.4
0.5
0.6
Output Current (A)
Output Current (A)
COUT = 4 × 47-µF, 25-V, ceramic
Device soldered to a 63.5-mm × 82.5-mm, 4-layer PCB
图6-7. Output Voltage Ripple
图6-8. Safe Operating Area (All VOUT
)
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6.8 Typical Characteristics (VIN = 48 V)
TA = 25°C, unless otherwise noted.
100
90
80
70
60
50
40
30
20
10
0
2
1.8
1.6
1.4
1.2
1
VOUT
15 V
12 V
9 V
5 V
3.3 V
VOUT
15 V
12 V
9 V
5 V
0.8
0.6
3.3 V
0
0.1
0.2
0.3
0.4
0.5
0.6
0
0.1
0.2
0.3
0.4
0.5
0.6
Output Current (A)
Output Current (A)
图6-9. Efficiency
图6-10. Power Dissipation
115
105
95
18
16
14
12
10
8
VOUT
15 V
12 V
9 V
5 V
3.3 V
85
75
65
6
55
4
45
2
35
Airflow
Nat Conv
0
0
0.1
0.2
0.3
0.4
0.5
0.6
25
0
0.1
0.2
0.3
0.4
0.5
0.6
Output Current (A)
Output Current (A)
COUT = 2 × 47-µF, 25-V, ceramic
Device soldered to a 63.5-mm × 82.5-mm, 4-layer PCB
图6-11. Output Voltage Ripple
图6-12. Safe Operating Area (VOUT < 10 V)
115
115
105
95
85
75
65
55
45
35
25
105
95
85
75
65
55
45
Airflow
200 LFM
100 LFM
Nat Conv
Airflow
100 LFM
Nat Conv
35
25
0
0.1
0.2
0.3
0.4
0.5
0.6
0
0.1
0.2
0.3
0.4
0.5
0.6
Output Current (A)
Output Current (A)
Device soldered to a 63.5-mm × 82.5-mm, 4-layer PCB
Device soldered to a 63.5-mm × 82.5-mm, 4-layer PCB
图6-13. Safe Operating Area (VOUT = 12 V)
图6-14. Safe Operating Area (VOUT = 15 V)
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6.9 Typical Characteristics (VIN = 60 V)
TA = 25°C, unless otherwise noted.
100
90
80
70
60
50
40
30
20
10
0
2.5
2.2
1.9
1.6
1.3
1
VOUT
15 V
12 V
9 V
5 V
3.3 V
VOUT
15 V
12 V
9 V
5 V
3.3 V
0
0.1
0.2
0.3
0.4
0.5
0.6
0
0.1
0.2
0.3
0.4
0.5
0.6
Output Current (A)
Output Current (A)
图6-15. Efficiency
图6-16. Power Dissipation
115
105
95
18
16
14
12
10
8
VOUT
15 V
12 V
9 V
5 V
3.3 V
85
75
65
6
55
4
45
2
Airflow
100 LFM
Nat Conv
35
0
0
0.1
0.2
0.3
0.4
0.5
0.6
25
0
0.1
0.2
0.3
0.4
0.5
0.6
Output Current (A)
Output Current (A)
COUT = 2 × 47-µF, 25-V, ceramic
Device soldered to a 63.5-mm × 82.5-mm, 4-layer PCB
图6-17. Output Voltage Ripple
图6-18. Safe Operating Area (VOUT = 5.0 V)
115
115
105
95
85
75
65
55
45
35
25
105
95
85
75
65
55
45
35
25
Airflow
Airflow
400 LFM
200 LFM
100 LFM
Nat conv
400 LFM
200 LFM
100 LFM
Nat conv
0
0.1
0.2
0.3
0.4
0.5
0.6
0
0.1
0.2
0.3
0.4
0.5
0.6
Output Current (A)
Output Current (A)
Device soldered to a 63.5-mm × 82.5-mm, 4-layer PCB
Device soldered to a 63.5-mm × 82.5-mm, 4-layer PCB
图6-19. Safe Operating Area (VOUT = 12 V)
图6-20. Safe Operating Area (VOUT = 15 V)
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7 Detailed Description
7.1 Overview
The TPSM560R6H converter is an easy-to-use, synchronous buck, DC-DC power module that operates from a
4.2-V to 60-V supply voltage. The device is intended for step-down conversions from 5-V, 12-V, 24-V, and 48-V
unregulated, semi-regulated, or fully-regulated supply rails. With an integrated power controller, inductor, and
MOSFETs, the TPSM560R6H delivers up to 600-mA DC load current, with high efficiency and ultra-low input
quiescent current, in a very small solution size. Although designed for simple implementation, this device offers
flexibility to optimize its usage according to the target application. Control-loop compensation is not required,
reducing design time and external component count.
The TPSM560R6H incorporates several features for comprehensive system requirements, including the
following:
• Open-drain power-good circuit for power-rail sequencing and fault reporting
• Monotonic start-up into prebiased loads
• Precision enable with customizable hysteresis for programmable line undervoltage lockout (UVLO)
• Overcurrent and thermal shutdown with automatic recovery
These features enable a flexible and easy-to-use platform for a wide range of applications. The pin arrangement
is designed for simple PCB layout, requiring as few as four external components.
7.2 Functional Block Diagram
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7.3 Feature Description
7.3.1 Adjustable Output Voltage (FB)
The TPSM560R6H has an adjustable output voltage range from 1.0 V to 16 V. Setting the output voltage
requires two resistors, RFBT and RFBB (see 图 7-1). Connect RFBT between VOUT at the regulation point and the
FB pin. Connect RFBB between the FB pin and AGND (pin 10). The recommended value of RFBT is 10 kΩ. The
value for RFBB can be calculated using 方程式1.
1.0
RFBB
=
× RFBT
1.0
VOUT
(1)
VOUT
RFBT
10 kꢀ
FB
RFBB
AGND
图7-1. FB Resistor Divider
表7-1. Standard RFBB Values
RFBB (kΩ) (1)
RFBB (kΩ) (1)
4.32
VOUT (V)
1.0
VOUT (V)
3.3
open
49.9
20.0
12.4
10.0
6.65
4.99
1.2
5.0
2.49
1.5
7.5
1.54
1.8
10
1.10
2.0
12
0.909
0.715
0.665
2.5
15
3.0
16
(1) RFBT = 10 kΩ
Select an RFBT value of 10 kΩ for most applications. A larger RFBT value consumes less DC current, which is
mandatory if light-load efficiency is critical. However, RFBT larger than 1 MΩ is not recommended because the
feedback path becomes more susceptible to noise. High feedback resistance generally requires more careful
layout of the feedback path. It is important to keep the feedback trace as short as possible while keeping the
feedback trace away from the noisy area of the PCB. For more layout recommendations, see 节10.
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7.3.2 Minimum Input Capacitance
The TPSM560R6H requires a minimum input capacitance of 9.4 μF (2 × 4.7 μF) of ceramic type. High-quality,
ceramic-type X5R or X7R capacitors with sufficient voltage rating are required. Place the input capacitors, as
close as possible to both VIN pins of the device between VIN and PGND as shown in 节 10.1. Applications with
transient load requirements can benefit from adding additional bulk capacitance to the input as well.
7.3.3 Minimum Output Capacitance
The TPSM560R6H requires a minimum amount of ceramic output capacitance for stability, depending on the
output voltage setting. 图 7-2 shows the amount of required output capacitance, which is also the amount of
effective capacitance. The effects of DC bias and temperature variation must be considered when using ceramic
capacitance. For ceramic capacitors, the package size, voltage rating, and dielectric material contribute to the
differences between the standard rated value and the actual effective value of the capacitance. Additional output
capacitance above the minimum can be added to reduce output voltage ripple and to improve transient
response. When adding additional capacitance above the minimum, the capacitance can be ceramic type, low-
ESR polymer type, or a combination of the two.
275
250
225
200
175
150
125
100
75
50
25
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
Output Voltage (V)
图7-2. Minimum Required Output Capacitance
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7.3.4 Precision Enable (EN), Undervoltage Lockout (UVLO), and Hysteresis (HYS)
The EN pin provides precision ON and OFF control for the TPSM560R6H. Once the EN pin voltage exceeds the
threshold voltage, the device starts operation. The simplest way to enable the device is to connect EN directly to
VIN. This lets the device start up when VIN is within its valid operating range. An external logic signal can also be
used to drive the EN input to toggle the output on and off and for system sequencing or protection. This input
must not be allowed to float.
The TPSM560R6H implements internal undervoltage lockout (UVLO) circuitry on the VIN pin. The device is
disabled when the VIN pin voltage is below the internal VIN UVLO threshold. The internal VIN UVLO rising
threshold is 3.8 V (typical) with a typical hysteresis of 500 mV.
If an application requires a higher UVLO threshold, the EN input supports adjustable UVLO by connecting a
resistor divider from the VIN to EN pin. Applying a voltage greater than or equal to 1.14 V causes the device to
enter Standby mode, powering the internal LDO, but not producing an output voltage. Increasing the EN voltage
to 1.231 V (typical) fully enables the device, letting it enter Start-up mode and start the soft-start period. When
the EN input is brought below 1.121 V (110-mV hysteresis), the regulator stops running and enters Standby
mode. Further decrease in the EN voltage to below 0.3 V completely shuts down the device.
The TPSM560R6H uses a reference-based soft start that prevents output voltage overshoots and large inrush
currents as the regulator is starting up. The rise time of the output voltage is approximately 4 ms.
7.3.5 Power Good (PGOOD)
The TPSM560R6H provides a PGOOD signal to indicate when the output voltage is within regulation. Use the
PGOOD signal for output monitoring, fault protection, or start-up sequencing of downstream converters. PGOOD
is an open-drain output that requires a pullup resistor to a DC supply not greater than 18 V. V5V or VOUT can be
used as the pullup voltage source. The typical range of pullup resistance is 10 kΩ to 100 kΩ. If necessary, use a
resistor divider to decrease the voltage from a higher voltage pullup rail. If this function is not needed, the
PGOOD pin must be grounded.
When the output voltage exceeds 95% (rising) or decreases below 105% (falling) of the setpoint, the internal
PGOOD switch turns off and PGOOD can be pulled high by the external pullup. If the FB voltage falls below 93%
or rises above 107% of the setpoint, the internal PGOOD switch turns on, and PGOOD is pulled low to indicate
that the output voltage is out of regulation.
Note that during initial power up, a delay of approximately 4 ms (typical) is inserted from the time that EN is
asserted to the time that the power-good flag goes high. This delay only occurs during start-up and is not
encountered during normal operation of the power-good function.
7.3.6 Overcurrent Protection (OCP)
The TPSM560R6H is protected from overcurrent conditions using cycle-by-cycle current limiting for overload
conditions and Hiccup mode for short circuits. The current is compared every switching cycle to the current limit
threshold. During an overcurrent condition, the output voltage decreases.
7.3.7 Thermal Shutdown
Thermal shutdown is an integrated self-protection used to limit junction temperature and prevent damage related
to overheating. Thermal shutdown turns off the device when the junction temperature exceeds 170°C (typical) to
prevent further power dissipation and temperature rise. Junction temperature decreases after shutdown and the
TPSM560R6H restarts when the junction temperature falls to 158°C (typical).
7.4 Device Functional Modes
7.4.1 Active Mode
The TPSM560R6H is in Active mode when VIN is above the turn-on threshold and the EN pin voltage is above
the EN high threshold. Connect the EN pin to VIN to allow the device to start up when a valid input voltage is
applied. This allows self start-up of the TPSM560R6H when the input voltage is in the operation range of 4.2 V
to 60 V. Connecting a resistor divider between VIN, EN, and AGND adjusts the UVLO to delay the turn on until
VIN is closer to its regulated voltage.
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7.4.2 Standby Mode
Start-up and shutdown are controlled by the EN input. This input features precision thresholds, allowing the use
of an external voltage divider to provide an adjustable input UVLO. Applying a voltage greater than or equal to
1.14 V causes the device to enter Standby mode, powering the internal LDO, but not producing an output
voltage. Increasing the EN voltage to 1.231 V (typical) fully enables the device, letting it enter Start-up mode and
start the soft-start period. When the EN input is brought below 1.121 V (110-mV hysteresis), the regulator stops
running and enters Standby mode. Further decrease in the EN voltage to below 0.3 V completely shuts down the
device.
7.4.3 Shutdown Mode
The EN pin provides ON and OFF control for the TPSM560R6H. When VEN is below the EN low threshold, the
device is in Shutdown mode. Both the internal LDO and the switching regulator are off. The quiescent current in
Shutdown mode drops to 5 µA at VIN = 24 V.
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8 Applications and Implementation
备注
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
8.1 Application Information
The TPSM560R6H only requires a few external components to convert from a wide range of supply voltages to a
fixed output voltage. To expedite and streamline the process of designing of a TPSM560R6H, WEBENCH®
online software is available to generate complete designs, leveraging iterative design procedures and access to
comprehensive component databases. The following section describes the design procedure to configure the
TPSM560R6H power module.
As mentioned previously, the TPSM560R6H also integrates several optional features to meet system design
requirements, including precision enable, UVLO, and PGOOD indicator. The following application circuit shows
TPSM560R6H configuration options suitable for several application use cases. Refer to the TPSM560R6HEVM
User's Guide for more detail.
8.2 Typical Application
图8-1 shows the schematic diagram of a 24-V input, 5-V output, 600-mA converter.
V5V
TPSM560R6H
100 k
VIN = 24 V
PGOOD
VOUT
VIN
EN
VOUT = 5 V
4.7 µF
100 V
4.7 µF
100 V
10 k
47 µF
10 V
47 µF
10 V
FB
PGND
AGND
2.49 k
图8-1. TPSM560R6H Typical Schematic
8.2.1 Design Requirements
For this design example, use the parameters listed in 表 8-1 as the input parameters and follow the design
procedures in 节8.2.2.
表8-1. Design Example Parameters
DESIGN PARAMETER
VALUE
24 V typical
5 V
Input voltage VIN
Output voltage VOUT
Output current rating
600 mA
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8.2.2 Detailed Design Procedure
8.2.2.1 Custom Design With WEBENCH® Tools
Click here to create a custom design using the TPSM560R6H device with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
• Run electrical simulations to see important waveforms and circuit performance.
• Run thermal simulations to understand board thermal performance.
• Export customized schematic and layout into popular CAD formats.
• Print PDF reports for the design, and share the design with colleagues.
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
8.2.2.2 Output Voltage Setpoint
The output voltage of the TPSM560R6H device is externally adjustable using a resistor divider. The
recommended value of RFBT is 10 kΩ. The value for RFBB can be selected from 表 7-1 or calculated using 方程
式2:
1.0
RFBB
=
× RFBT
1.0
VOUT
(2)
For the desired output voltage of 5 V, the formula yields a value of 2.5 kΩ. Choose the closest available
standard value of 2.49 kΩfor RFBB
.
8.2.2.3 Input Capacitor Selection
The TPSM560R6H requires a minimum input capacitance of 2 × 4.7-µF ceramic type. High-quality ceramic type
X5R or X7R capacitors with sufficient voltage rating are recommended. The voltage rating of input capacitors
must be greater than the maximum input voltage.
For this design, 2 × 4.7-µF, 100-V ceramic capacitors are selected.
8.2.2.4 Output Capacitor Selection
The TPSM560R6H requires a minimum amount of output capacitance for proper operation. The minimum
amount of required output varies depending on the output voltage. See 图 7-2 for the required output
capacitance. Additional output capacitance can be added to reduce ripple voltage or for applications with
transient load requirements.
For this design example, 2 × 47-µF, 10-V, ceramic capacitors are used.
8.2.2.5 Power-Good Signal
Use a pullup resistor between the PGOOD pin and a valid voltage source for applications requiring a power-
good signal to indicate that the output voltage is present and in regulation.
For this design, a 100-kΩ resistor is placed between the PGOOD pin and the V5V pin (the internal 5-V LDO
output).
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8.2.3 Application Curves
VIN = 24 V
VOUT = 5 V
IOUT = 600 mA
VIN = 24 V
VOUT = 5 V
IOUT = 600 mA
图8-3. Enable Shutdown Waveforms
图8-2. Start-Up Waveforms
COUT = 2 × 47 µF
IOUT = 600 mA
COUT = 2 × 47 µF 400-mA load step
2.5 A/µs
图8-4. Output Ripple Waveform
图8-5. Transient Response Waveform
9 Power Supply Recommendations
The TPSM560R6H is designed to operate from an input voltage supply range between 4.2 V and 60 V. This
input supply must be able to provide the maximum input current and maintain a voltage above the set UVLO
voltage. Ensure that the resistance of the input supply rail is low enough that an input current transient does not
cause a high enough drop at the TPSM560R6H supply rail to cause a false UVLO fault triggering and system
reset. If the input supply is located more than a few inches from the TPSM560R6H, additional bulk capacitance
can be required in addition to the ceramic input capacitance. A 47-μF electrolytic capacitor is a typical choice for
this function because the capacitor ESR provides a level of damping against input filter resonances. A typical
ESR of 0.5 Ωprovides enough damping for most input circuit configurations.
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10 Layout
The performance of any switching power supply depends as much on the layout of the PCB as the component
selection. Use the following guidelines to design a PCB with the best power conversion performance, optimal
thermal performance, and minimal generation of unwanted EMI.
10.1 Layout Guidelines
To achieve optimal electrical and thermal performance, an optimized PCB layout is required. 图10-1 and 图10-2
show a typical PCB layout. Some considerations for an optimized layout are:
• Use large copper areas for power planes (VIN, VOUT, and PGND) to minimize conduction loss and thermal
stress.
• Connect all PGND pins together using copper plane.
• Connect the AGND pin to the PGND copper at a single point near the pin.
• Place ceramic input and output capacitors close to the device pins to minimize high frequency noise.
• Locate additional output capacitors between the ceramic capacitor and the load.
• Place RFBT and RFBB as close as possible to their respective pins.
• Use multiple vias to connect the power planes to internal layers.
10.2 Layout Example
图10-2. Typical Top-Layer
图10-1. Typical Layout
图10-4. Typical PGND-Layer
图10-3. Typical Mid-Layer
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10.2.1 Theta JA Versus PCB Area
The amount of PCB copper as well as airflow affects the thermal performance of the device. 图 10-5 shows the
effects of copper area and airflow on the junction-to-ambient thermal resistance (RθJA) of the TPSM560R6H.
The junction-to-ambient thermal resistance versus PCB area is plotted for a 4-layer PCB.
To determine the required copper area for an application:
1. Determine the maximum power dissipation of the device in the application by referencing the power
dissipation graphs in the Typical Characteristics.
2. Calculate the maximum θJA using 方程式3 and the maximum ambient temperature of the application.
(125˘C œ TA(max)
)
ꢀJA
=
(˘C/W)
PD(max)
(3)
3. Reference 图10-5 to determine the minimum required PCB area for the application conditions.
50
Nat Conv
100 LFM
200 LFM
45
40
35
30
25
20
15
0
5
10
15
20
25
30
35
40
45
50
55
PCB Area (cm²)
图10-5. θJA Versus PCB Area
10.2.2 Package Specifications
表10-1. Package Specifications Table
TPSM560R6H
VALUE
UNIT
Weight
429
mg
Flammability
Meets UL 94 V-O
MTBF Calculated Reliability
Per Bellcore TR-332, 50% stress, TA = 40°C, ground benign
87.7
MHrs
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10.2.3 EMI
The TPSM560R6H is compliant with EN55011 radiated emissions. 图 10-6 through 图 10-9 show typical
examples of radiated emission plots for the TPSM5601R5H (1.5-A version). Expect slightly better results for the
TPSM560R6H as it is rated for 600 mA. The graphs include the plots of the antenna in the horizontal and vertical
positions.
10.2.3.1 EMI Plots
EMI plots were measured using the standard TPSM5601R5HEVM.
图10-6. Radiated Emissions 24-V Input, 5-V Output, 1.5-A Load
图10-7. Radiated Emissions 24-V Input, 5-V Output, 1.5-A Load (Spread Spectrum)
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图10-8. Radiated Emissions 24-V Input, 12-V Output, 1.5-A Load
图10-9. Radiated Emissions 48-V Input, 12-V Output, 1.5-A Load
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11 Device and Documentation Support
11.1 Device Support
11.1.1 第三方产品免责声明
TI 发布的与第三方产品或服务有关的信息，不能构成与此类产品或服务或保修的适用性有关的认可，不能构成此
类产品或服务单独或与任何TI 产品或服务一起的表示或认可。
11.1.2 Development Support
For development support, see the following:
• For TI's reference design library, visit TI Designs.
• To view a related device of this product, see the TPSM5601R5Hx.
11.1.2.1 Custom Design With WEBENCH® Tools
Click here to create a custom design using the TPSM560R6H device with WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
• Run electrical simulations to see important waveforms and circuit performance.
• Run thermal simulations to understand board thermal performance.
• Export customized schematic and layout into popular CAD formats.
• Print PDF reports for the design, and share the design with colleagues.
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
11.2 Documentation Support
11.2.1 Related Documentation
For related documentation, see the following:
• Texas Instruments, TPSM560R6HEVM User's Guide
• Texas Instruments, Using the TPSM5601R5Hx in an Inverting Buck-Boost Topology Application Report
• Texas Instruments, Using New Thermal Metrics Application Report
• Texas Instruments, Semiconductor and IC Package Thermal Metrics Application Report
11.3 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
11.4 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
11.5 Trademarks
HotRod™ and TI E2E™ are trademarks of Texas Instruments.
WEBENCH® is a registered trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
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11.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
11.7 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this datasheet, refer to the left-hand navigation.
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重要声明和免责声明
TI 提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，不保证没
有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担保。
这些资源可供使用TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的TI 产品，(2) 设计、验
证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他安全、安保或其他要求。这些资源如有变更，恕不另行通知。TI 授权您仅可
将这些资源用于研发本资源所述的TI 产品的应用。严禁对这些资源进行其他复制或展示。您无权使用任何其他TI 知识产权或任何第三方知
识产权。您应全额赔偿因在这些资源的使用中对TI 及其代表造成的任何索赔、损害、成本、损失和债务，TI 对此概不负责。
TI 提供的产品受TI 的销售条款(https:www.ti.com/legal/termsofsale.html) 或ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI
提供这些资源并不会扩展或以其他方式更改TI 针对TI 产品发布的适用的担保或担保免责声明。重要声明
邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2021，德州仪器(TI) 公司
PACKAGE OPTION ADDENDUM
www.ti.com
27-Jan-2023
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPSM560R6HRDAR
ACTIVE
B3QFN
RDA
15
1000 RoHS & Green
NIPDAU
Level-3-245C-168 HR
-40 to 125
560R6H
Samples
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OUTLINE
RDA0015A
B3QFN - 4.1 mm max height
S
C
A
L
E
1
.
8
0
0
PLASTIC QUAD FLATPACK - NO LEAD
5.1
4.9
A
B
PIN 1 INDEX AREA
5.6
5.4
4.1 MAX
0.08 C
C
SEATING PLANE
2.5 0.05
PKG
0.45
0.25
0.1
2X
1.5 0.05
10X
C A B
1.3
1.1
3X
(0.16) TYP
0.05
C
7
8
2X 0.725
2.6 TYP
1.43
PKG
4.6 0.05
15
2.5 0.05
8X 0.65
2X 0.975
14
1
0.6
0.4
4X
0.6
0.4
10X
0.1
C A B
C
1.3
1.1
0.05
PIN 1 ID
4224086/C 03/2019
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
RDA0015A
B3QFN - 4.1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(2.5)
(1.5)
4X (1.4)
PKG
4X (0.5)
14
1
2X (0.975)
10X (0.7)
10X (0.35)
(4.6)
PKG
15
(1)
TYP
(2.5)
2X (1.43)
8X (0.65)
2X (0.725)
7
8
(R0.05) TYP
(1) TYP
(
0.2) VIA
TYP
2X (4)
(4.7)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 16X
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
EXPOSED
METAL
EXPOSED
METAL
SOLDER MASK
OPENING
METAL EDGE
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK DEFINED
S
C
A
L
E
3
0
.
0
0
0
SOLDER MASK DETAILS
4224086/C 03/2019
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
RDA0015A
B3QFN - 4.1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
PKG
4X (1.35)
4X (0.6)
4X (0.45)
14
1
4X
(1.15)
2X (0.975)
10X (0.65)
15
10X (0.3)
PKG
4X (0.475)
4X
(0.95)
4X
(0.65)
2X (1.43)
8X (0.65)
4X (1.675)
2X (0.725)
7
8
(R0.05) TYP
4X (0.425)
4X (0.625)
2X (4)
(4.7)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 15:
56% PRINTED SOLDER COVERAGE BY AREA
SCALE: 16X
4224086/C 03/2019
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
重要声明和免责声明
TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，
不保证没有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担
保。
这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验
证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。
这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。
您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成
本、损失和债务，TI 对此概不负责。
TI 提供的产品受 TI 的销售条款或 ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI 提供这些资源并不会扩展或以其他方式更改
TI 针对 TI 产品发布的适用的担保或担保免责声明。
TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE
邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2023，德州仪器 (TI) 公司
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