TPSM63608RDFR_技术文档

TPSM63608

ZHCSRQ3 –FEBRUARY 2023

TPSM63608 高密度、3V 至36V 输入、1V 至20V 输出、6A（峰值为8A）采用

增强型HotRod™ QFN 封装的同步降压直流/直流电源模块

1 特性

3 说明

• 提供功能安全

TPSM63608 源自同步降压模块系列，是一款高度集成

的 36V、6A 直流/直流解决方案，集成了多个功率

MOSFET、一个屏蔽式电感器和多个无源器件，并采

用增强型 HotRod^™QFN 封装。该模块的 VIN 和

VOUT 引脚位于封装的边角处，可优化输入和输出电

容器的放置。模块下方具有四个较大的散热焊盘，可在

制造过程中实现简单布局和轻松处理。

– 可提供用于功能安全系统设计的文档

• 多功能36V_IN、6A_OUT同步降压模块

– 集成MOSFET、电感器和控制器

– 可调节输出电压范围为1V 至20 V

– 6.5mm × 7.5mm × 4mm 超模压塑料封装

– 具有–40°C 至125°C 的结温范围

– 可在200 kHz 至2.2 MHz 范围内调节频率

– 负输出电压应用功能

TPSM63608 具有 1V 到 20 V 的输出电压，旨在快

速、轻松实现小尺寸 PCB 的低EMI 设计。总体解决方

案仅需四个外部元件，并且省去了设计流程中的磁性和

补偿元件选择过程。

• 在整个负载范围内具有超高效率

– 95%+ 峰值效率

– 具有用于提升效率的外部偏置选项

尽管针对空间受限型应用采用了简易的小尺寸设计，

TPSM63608 模块还提供了许多特性来实现稳健的性

能：具有迟滞功能的精密使能端可实现输入电压 UVLO

调节、电阻可编程开关节点压摆率和展频选项以改善

EMI。与集成式 VCC、自举和输入电容器一起使用，

可提高可靠性和密度。该模块可配置为在满负载电流范

围 (FPWM) 内保持恒定开关频率，也可配置为可变频

率 (PFM) 以提高轻负载效率。包含 PGOOD 指示器，

可实现时序控制、故障报告和输出电压监测功能。

– 外露焊盘可实现低热阻抗。EVM θ_JA

18.2°C/W。

– 关断时的静态电流为0.6 µA（典型值）

– 4A 负载下的典型压降为0.5V

=

• 超低的传导和辐射EMI 信号

– 具有双输入路径和集成电容器的低噪声封装可降

低开关振铃

– 电阻器可调开关节点压摆率

– 符合CISPR 11 和32 B 类发射要求

• 适用于可扩展电源

封装信息

封装⁽¹⁾

– 与TPSM63610（36V、8A）引脚兼容

• 固有保护特性，可实现稳健设计

封装尺寸（标称值）

器件型号

TPSM63608

RDF（B3QFN，

22）

6.50mm × 7.50mm

– 精密使能输入和漏极开路PGOOD 指示器（用

于时序、控制和V_INUVLO）

– 过流和热关断保护

(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附

录。

• 使用TPSM63608 并借助WEBENCH^®Power

空白

Designer 创建定制设计方案

2 应用

• 测试和测量以及航天和国防

• 工厂自动化和控制

• 降压和反相降压/升压电源

V_IN= 3 V...36 V

100

95

90

85

80

VIN1

CBOOT

VIN2

C_IN

RBOOT

PGND

TPSM63608

V_OUT= 5 V

VLDOIN

EN/SYNC

I_OUT= 6 A

VCC

VOUT1

VOUT2

R_PG

SPSP

R_FBT

C_OUT

PG

RT

FB

VIN = 12 V

VIN = 24 V

VIN = 36 V

75

70

R_FBB

R_RT

AGND

SYNC/

MODE

0

1

2

3

4

5

6

* V_OUTenters dropout

if V_IN< 5.8 V

Output Current (A)

典型效率（V_OUT= 5V, F_SW= 1MHz）

典型原理图

本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问

www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: SLVSH66

TPSM63608

ZHCSRQ3 –FEBRUARY 2023

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Table of Contents

8.3 Feature Description...................................................13

8.4 Device Functional Modes..........................................21

9 Applications and Implementation................................22

9.1 Application Information............................................. 22

9.2 Typical Applications.................................................. 22

9.3 Power Supply Recommendations.............................30

9.4 Layout....................................................................... 30

10 Device and Documentation Support..........................33

10.1 Device Support....................................................... 33

10.2 Documentation Support.......................................... 34

10.3 接收文档更新通知................................................... 34

10.4 支持资源..................................................................34

10.5 Trademarks.............................................................34

10.6 静电放电警告.......................................................... 34

10.7 术语表..................................................................... 34

11 Mechanical, Packaging, and Orderable

1 特性................................................................................... 1

2 应用................................................................................... 1

3 说明................................................................................... 1

4 Revision History.............................................................. 2

5 Device Comparison Table...............................................3

6 Pin Configuration and Functions...................................3

7 Specifications.................................................................. 5

7.1 Absolute Maximum Ratings........................................ 5

7.2 ESD Ratings............................................................... 5

7.3 Recommended Operating Conditions.........................5

7.4 Thermal Information....................................................6

7.5 Electrical Characteristics.............................................6

7.6 System Characteristics............................................... 9

7.7 Typical Characteristics..............................................10

8 Detailed Description......................................................12

8.1 Overview...................................................................12

8.2 Functional Block Diagram.........................................13

Information.................................................................... 34

4 Revision History

注：以前版本的页码可能与当前版本的页码不同

DATE

REVISION

NOTES

February 2023

*

Initial Release

2

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5 Device Comparison Table

PEAK OUTPUT

CURRENT

(TRANSIENT

CONDITIONS)

ORDERABLE PART

RATED OUTPUT

CURRENT

DEVICE

JUNCTION TEMPERATURE RANGE

NUMBER

TPSM63610

TPSM63610E

TPSM63608

TPSM63610RDFR

TPSM63610EXTRDFR

TPSM63608RDFR

8 A

6 A

10 A

8 A

–40°C to 125°C

–55°C to 125°C

–40°C to 125°C

6 Pin Configuration and Functions

VIN2

EN

1

18

VIN1

PGND

AGND

19

2

3

4

5

6

7

8

17

16

15

14

13

12

11

RBOOT

CBOOT

SW

NC

MODE

SPSP

PG

20

21

VLDOIN

VCC

AGND

FB

RT

AGND

22

VOUT1

9

10

VOUT2

图6-1. 22-Pin B3QFN RDF Package (Top View)

表6-1. Pin Functions

TYPE⁽¹⁾

DESCRIPTION

NO.

NAME

Input supply voltage. Connect the input supply to these pins. Connect input capacitors between these

pins and PGND in close proximity to the device.

1, 18

VIN1, VIN2

P

External bootstrap resistor connection. RBOOT is brought out to use in conjunction with CBOOT to

effectively lower the value of the internal series bootstrap resistance to adjust the switch-node slew rate,

if necessary. A resistance from 0 to 500 Ωcan be connected between RBOOT and CBOOT. A

resistance of 0 Ωhas the fastest slew rate and highest efficiency. A value of 100 Ωcreates a nice

balance between efficiency and EMI. Leaving open sets the slew rate to 20 ns and TI does not

recommend due to increased self heating.

2

RBOOT

I

Bootstrap pin for the internal high-side gate driver. A 100-nF bootstrap capacitor is internally connected

from this pin to SW within the module to provide the bootstrap voltage. CBOOT is brought out to use in

conjunction with RBOOT to effectively lower the value of the internal series bootstrap resistance to

adjust the switch-node slew rate, if necessary.

3

4

5

6

CBOOT

SW

O

P

Switch node. Do not place any external component on this pin or connect to any signal. The amount of

copper placed on this pin must be kept to a minimum to prevent issues with noise and EMI.

Input bias voltage. Input to the internal LDO that supplies the internal control circuits. Connect to an

output voltage point to improve efficiency. Connect an optional high-quality 0.1-μF to 1-μF capacitor

from this pin to ground for improved noise immunity. If the output voltage is above 12 V, connect this pin

to ground.

VLDOIN

VCC

Internal LDO output. Used as a supply to the internal control circuits. Do not connect to any external

loads. A 1-μF capacitor internally connects from VCC to AGND.

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表6-1. Pin Functions (continued)

TYPE⁽¹⁾

DESCRIPTION

NO.

NAME

Analog ground. Zero-voltage reference for internal references and logic. All electrical parameters are

measured with respect to this pin. These pins must be connected to PGND. See Layout Example for a

recommended layout.

7, 11, 21,

22

AGND

G

Feedback input. Connect the midpoint of the feedback resistor divider to this pin. Connect the upper

resistor (R_FBT) of the feedback divider to V_OUTat the desired point of regulation. Connect the lower

resistor (R_FBB) of the feedback divider to AGND. Do not leave open or connect to ground.

8

FB

I

P

I

VOUT1,

VOUT2

Output voltage. These pins are connected to the internal buck inductor. Connect these pins to the output

load and connect external output capacitors between these pins and PGND.

9, 10

12

Frequency setting pin used to set the switching frequency between 200 kHz and 2.2 MHz by placing an

external resistor from RT to AGND. Connect to VCC for 400 kHz. Connect to ground for 2.2 MHz. Do not

leave open.

RT

PG

Open-drain power-good monitor output that asserts low if the FB voltage is not within the specified

window thresholds. A 10-kΩto 100-kΩpullup resistor to a suitable voltage is required . If not used, PG

can be left open or connected to GND.

13

14

O

I

Connect to VCC or through a resistor to ground to enable spread spectrum. Connect to GND to disable

spread spectrum. If using spread spectrum, a VCC connection turns off the spread spectrum tone

correction while a resistor to ground (10-30 kΩ) adjusts the tone correction to lower the output voltage

ripple. Do not float this pin.

SPSP

This pin controls the mode of operation of the device. Modes include Auto mode (automatic PFM/PWM

operation), forced pulse width modulation (FPWM), and synchronized to an external clock. The clock

triggers on the rising edge of an applied external clock. Pull low to enable PFM operation, pull high to

enable FPWM, or connect to a clock to synchronize to an external frequency in FPWM mode. Do not

float this pin. When synchronized to an external clock, use the RT pin to set the internal frequency close

to the synchronized frequency to avoid disturbances if the external clock is turned on and off

SYNC/

MODE

15

I

16

17

NC

EN

No connection. Tie to GND or leave open.

—

Precision enable input to regulator. High = on, low = off. Can be connected to VIN. Precision enable

allows the pin to be used as an adjustable UVLO. Do not float

I

Power ground. This is the return current path for the power stage of the device. Connect these pads to

the input supply return, the load return, and the capacitors associated with the VIN and VOUT pins. See

Layout Example for a recommended layout.

19, 20

PGND

G

(1) P = Power, G = Ground, I = Input, O = Output

4

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7 Specifications

7.1 Absolute Maximum Ratings

Over the recommended operating junction temperature range⁽¹⁾

PARAMETER

MIN

–0.3

0

MAX

42

UNIT

V

Voltages

Current

Voltages

T_stg

Transient VIN to AGND, PGND⁽²⁾

Continuous VIN to AGND, PGND⁽²⁾

SW to AGND, PGND

36

V

V_IN+ 0.3

5.5

V

RBOOT, CBOOT to SW

V

Transient EN or SYNC/MODE to AGND, PGND⁽²⁾

Continuous EN or SYNC/MODE to AGND, PGND⁽²⁾

BIAS to AGND, PGND

42

V

36

V

16

V

FB to AGND, PGND: Adjustable Versions

RESET to AGND, PGND

5.5

V

20

V

RESET sink current⁽⁴⁾

0

10

mA

V

RT to AGND, PGND

-0.3

5.5

VCC to AGND, PGND

5.5

V

–0.3

–1

PGND to AGND⁽³⁾

2

V

Storage temperature

150

°C

–65

(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply

functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If

used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully

functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.

(2) A maximum of 42 V can be sustained at this pin for duration of ≤100 ms at a duty cycle of ≤0.01%. 36 V can be sustained for the

life of this device.

(3) This specification applies to voltage durations of 100 ns or less. The maximum D.C. voltage must not exceed +/- 0.3 V.

(4) Do not exceed pin voltage rating.

7.2 ESD Ratings

VALUE

UNIT

Human-body model (HBM), per ANSI/ESDA/

JEDEC JS-001⁽¹⁾

±2000

V

V_(ESD)

Electrostatic discharge

Charged-device model (CDM), per ANSI/ESDA/

JEDEC JS-002⁽²⁾

±750

V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

Over the recommended operating junction temperature range of –40°C to 125°C (unless otherwise noted) ⁽¹⁾

MIN

MAX

UNIT

V

Input voltage

Output voltage Output Adjustment Range for adjustable output versions ⁽²⁾

Input Voltage Range⁽¹⁾

3

36

20

1

V

Frequency

Frequency adjustment range

200

2200

kHz

Sync

Frequency

Synchronization frequency range

200

2200

kHz

Output current I_OUT

Temperature Operating junction temperature, T_J

0

6

A

125

°C

–40

(1) 3.7 V is required at VIN for start-up, an extended input voltage range down to 3.0 V is possible after start-up; See Minimum input

voltage for start-up conditions.

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(2) Under no conditions can the output voltage be allowed to fall below zero volts.

7.4 Thermal Information

TPSM636XX

THERMAL METRIC ⁽¹⁾

RDF

22 PINS

18

UNIT

R_θJA

Junction-to-ambient thermal resistance (TPSM63610EVM) ⁽³⁾

Junction-to-ambient thermal resistance (JESD 51-7) ⁽²⁾

Junction-to-case (top) thermal resistance

°C/W

R_θJA

25

R_θJC(top)

R_θJB

12.8

7.4

Junction-to-board thermal resistance

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

0.7

Ψ_JT

7.2

Ψ_JB

R_θJC(bot)

3.6

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

(2) The value of R_ΘJAgiven in this table is only valid for comparison with other packages and can not be used for design purposes. These

values were calculated in accordance with JESD 51-7, and simulated on a 4-layer JEDEC board. They do not represent the

performance obtained in an actual application. For example, the EVM R_ΘJA= 21.6 °C/W. For design information please see the

thermal design and layout section.

(3) Refer to the EVM User's Guide for board layout and additional information. For thermal design information please see the thermal

design and layout section.

7.5 Electrical Characteristics

Limits apply over the recommended operating junction temperature range of -40°C to +125°C, unless otherwise noted.

Minimum and Maximum limits are specified through test, design or statistical correlation. Typical values represent the most

likely parametric norm at T_J= 25°C, and are provided for reference purposes only. Unless otherwise stated the following

conditions apply: V_IN= 12. VIN1 shorted to VIN2 = V_IN. V_OUTis output set point.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

SUPPLY VOLTAGE (VIN PIN)

Needed to start up

3.7

3

V

V_IN

Minimum operating input voltage

Minimum voltage hysteresis

Once Operating

V_{IN_OP_H}

I_Q

I_SD

I_B

1

Non-switching input current; measured

at VIN pin ⁽³⁾

V_FB= +5%, V_BIAS= 5 V

V_EN= 0 V, V_IN= 12 V

0.5

10

7.5

26

µA

Shutdown quiescent current; measured

at VIN pin

0.57

18.5

V_FB= +5%, V_BIAS= 5 V, Auto Mode

Enabled

Current into BIAS pin (not switching)

ENABLE (EN PIN)

V_EN

Enable input-threshold voltage - rising

V_ENrising

1.0

0.1

0.4

1.263

0.35

1.365

0.5

V

V_{EN_HYST}

V_{EN_WAKE}

I_EN

Enable threshold hysteresis

Enable Wake-up threshold

Enable pin input current

V

V_IN= V_EN= 12 V

1.5

50

nA

INTERNAL LDO (VCC PIN)

V_BIAS= 0V

3.4

3.2

V_CC

Internal VCC voltage

V

V_BIAS= 3.3 V, 20 mA

V_INvoltage at which Internal VCC under

voltage lock-out is released

V_{CC_UVLO}

I_VCC= 0A

3.75

V

Internal VCC under voltage lock-out

hysteresis

V_{CC_UVLO_HYST}

Hysteresis below V_{CC_UVLO}

1.2

VOLTAGE REFERENCE (FB PIN)

6

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7.5 Electrical Characteristics (continued)

Limits apply over the recommended operating junction temperature range of -40°C to +125°C, unless otherwise noted.

Minimum and Maximum limits are specified through test, design or statistical correlation. Typical values represent the most

likely parametric norm at T_J= 25°C, and are provided for reference purposes only. Unless otherwise stated the following

conditions apply: V_IN= 12. VIN1 shorted to VIN2 = V_IN. V_OUTis output set point.

PARAMETER

TEST CONDITIONS

V_IN= 3.0 V to 36 V, FPWM Mode

Adjustable versions only, V_FB= 1 V

MIN

TYP

MAX UNIT

Initial reference voltage accuracy for

adjustable (1 V FB) versions

V_FB

I_FB

0.985

1

1.015

50

V

Input current from FB to AGND

nA

CURRENT LIMITS

I_{SC_6}

Short circuit high-side current Limit

8.4

7

11.5

8.2

14.2

9.1

A

I_{LS-LIMIT_6}

I_{PEAK-MIN_6}

I_{L-NEG_6}

Low-side current limit

6 A Variant, Duty cycle approaches 0%

Auto Mode, static measurement

Minimum Peak Inductor Current

Negative current limit

1.3

–4.9

–3.4

–2.3

Zero-cross current limit. Positive current

direction is out of SW pin.

I_L-ZC

70

mA

V

V_HICCUP

Hiccup threshold on FB pin

0.36

0.4

0.44

POWER GOOD (/RESET PIN)

V _RESET-OVRESET upper threshold - Rising

V _RESET-UV

% of FB voltage

109.5

93

112

95

114.5

97.5

%

RESET lower threshold - Falling

RESET UV threshold as percentage of

steady state output voltage with output

voltage and UV threshold, falling, read

at the same T_J, and V_IN.

V _{RESET_GUARD}

Falling

97

%

V _RESET-HYS-

RESET fallling threshold hysteresis

RESET rising threshold hysteresis

% of FB voltage

1.3

%

V

FALLING

V _RESET-HYS-

RISING

Minimum input voltage for proper

RESET function

Measured when V_RESET< 0.4 V with 10

kOhm pullup to external 5 V

V _{RESET_VALID}

1.2

0.4

46.0 µA pull up to RESET pin, V_IN= 1.0

V, V_EN= 0 V

RESET Low-level function output

voltage

1 mA pull up to RESET pin, V_IN= 12 V,

V_EN= 0 V

V_OL

V

2 mA pull up to RESET pin, V_IN= 12 V,

V_EN= 3.3 V

R_RESET

RESET ON resistance,

RESET edge deglitch delay

V_EN= 5 V, 1mA pull up current

V_EN= 0 V, 1mA pull up current

44

18

26

125

40

Ω

µs

R_RESET

t_{RESET_FILTER}

10

45

Time FB must be valid before RESET is

released.

t_{RESET_ACT}

RESET active time

1.2

2.1

3.75

ms

OSCILLATOR (RT and SYNC PINS)

f_OSCInternal oscillator frequency

f_OSC

RT = GND

RT = VCC

1.90

320

2.2

2.42

450

MHz

kHz

Internal oscillator frequency

400

Oscillator frequency measured using

maximum value of RT resistor to select

2.2 MHz

f_{FIXED_2.2MHz}

1.95

352

2.2

2.42

MHz

kHz

RT = 6.81 kΩ

Oscillator frequency measured using

minimum value of RT resistor to select

0.4 MHz

f_{FIXED_0.4MHz}

400

700

448

770

RT = 40.2 kΩ

RT = 22.6 kΩ

f_ADJ

Center Trim oscillator frequency

SYNC/MODE input voltage low

SYNC/MODE input voltage high

630

0.4

kHz

V

V_SYNCDL

V_SYNCDH

1.7

V

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7.5 Electrical Characteristics (continued)

Limits apply over the recommended operating junction temperature range of -40°C to +125°C, unless otherwise noted.

Minimum and Maximum limits are specified through test, design or statistical correlation. Typical values represent the most

likely parametric norm at T_J= 25°C, and are provided for reference purposes only. Unless otherwise stated the following

conditions apply: V_IN= 12. VIN1 shorted to VIN2 = V_IN. V_OUTis output set point.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

V_{SYNCD_HYST}

R_SYNC

SYNC/MODE input voltage hysteresis

0.185

1

V

Internal pulldown resistor to ensure

SYNC/MODE doesn't float

100

kΩ

High and Loww duration needed for

synchronizing clock to be recognized on

SYNC/MODE pin

t_{SYNC_EDGE}

100

7

ns

Time at one level needed to indicate

FPWM or Auto Mode

t_MSYNC

t_LOCK

20

µs

Time needed for clock to lock to a valid

synchronization signal

4.3

ms

RT = 39.2 kΩ

SPREAD SPECTRUM

Frequency increase of internal oscillator

from spread spectrum

1

4

7.5

-1

%

ΔFc+

ΔFc-

Frequency decrease of internal

oscillator from spread spectrum

-8

-4

HIGH SIDE DRIVE (CBOOT PIN)

Voltage on CBOOT pin compared to

SW which will turnoff high-side switch

V_{CBOOT_UVLO}

1.9

V

MOSFETS

R_DS-ON-HS

R_DS-ON-LS

High-side MOSFET on-resistance

Low-side MOSFET on-resistance

Load = 1 A, C_BOOT-SW= 3.2 V

21

13

39

25

mΩ

PWM LIMITS (SW PIN)

V_IN=18 V, V_SYNC/MODE= 5 V, I_OUT= 2A,

R_BOOT= 0 Ω

t_ON-MIN

Minimum HS switch on-time

62

81

ns

t_OFF-MIN

t_ON-MAX

Minimum HS switch off-time

Maximum switch on-time

V_IN= 5 V

70

103

11

ns

µs

HS timeout in dropout

While in frequency fold-back

fsw =1.85 MHz

6.9

98

8.9

D_MAX

Maximum switch duty cycle

%

87

START UP

V_IN= 12 V, C_VCC= 1 µF, time from EN

high to first SW pulse if output starts at

0 V

t_EN

Turn-on delay

0.82

1.2

2.7

ms

Time from first SW pulse to V_REFat

90%, of set point.

t_SS

t_W

1.6

2.2

40

ms

Short circuit wait time ("hiccup" time)

8

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7.6 System Characteristics

The following specifications apply only to the typical applications circuit, with nominal component values. Specifications in the

typical (TYP) column apply to T_J= 25°C only. These specifications are not ensured by production testing.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

SUPPLY

Input supply current when in V_IN= V_EN/SYNC= 24 V, V_OUT= V_VLDOIN= 3.3 V, V_MODE= 0 V, F_SW= 1 MHz,

I_IN

8

µA

regulation

I_OUT= 0 A

OUTPUT VOLTAGE

Load regulation

V_OUT= 3.3 V, V_IN= 24 V, I_OUT= 0.1 A to 4 A

4

1

mV

ΔV_OUT1

ΔV_OUT2

ΔV_OUT3

Line regulation

Load transient

V_OUT= 3.3 V, V_IN= 4 V to 36 V, I_OUT= 4 A

150

V_OUT= 5 V, V_IN= 24 V, I_OUT= 0 A to 4 A at 1 A/μs, C_OUT(derated)= 100 μF

EFFICIENCY

Efficiency

V_IN= 12 V, V_OUT= V_VLDOIN= 3.3 V, I_OUT= 4 A, F_SW= 1 MHz

V_IN= 24 V, V_OUT= V_VLDOIN= 3.3 V, I_OUT= 4 A, F_SW= 1 MHz

V_IN= 12 V, V_OUT= V_VLDOIN= 5 V, I_OUT= 4 A, F_SW= 1 MHz

V_IN= 24 V, V_OUT= V_VLDOIN= 5 V, I_OUT= 4 A, F_SW= 1 MHz

92.1

91

%

η

Efficiency

94.3

93

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7.7 Typical Characteristics

V_IN= 12 V, unless otherwise specified.

4

8

6

4

2

0

T_J= -40C

T_J= 25C

T_J= 125C

3

2

1

0

-50

-25

0

25

50

75

100

125

0

6

12

18

24

30

36

Junction Temperature (°C)

Input Voltage (V)

V_LDOIN= 3.3 V

V_MODE= 0 V

图7-2. Non-Switching Input Supply Current

图7-1. Shutdown Supply Current

图7-3. Feedback Voltage

图7-4. High-Side (Peak) and Low-Side (Valley) Current Limits

TPSM63608

35

1.4

1.2

1

30

25

20

15

10

5

0.8

0.6

0.4

V_ENRising

V_ENFalling

V_{EN_WAKE}Rising

V_{EN_WAKE}Falling

0.2

High-side MOSFET

Low-side MOSFET

0

-50

0

-50

-25

0

25

50

75

100

125

-25

0

25

50

75

100

125

Junction Temperature (°C)

图7-6. Enable Thresholds

图7-5. High-Side and Low-Side MOSFET R_DS(on)

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7.7 Typical Characteristics (continued)

V_IN= 12 V, unless otherwise specified.

115

110

105

100

95

70

60

50

40

30

20

10

0

90

OV Tripping

OV Recovery

UV Recovery

UV Tripping

85

80

-50

-25

0

25

50

75

100

125

200 400 600 800 1000 1200 1400 1600 1800 2000 2200

Frequency (kHz)

Junction Temperature (°C)

图7-7. Power-Good (PG) Thresholds

图7-8. Switching Frequency Set by RT Resistor

图7-9. EVM Thermal Performance

图7-10. EVM Thermal Performance

(V_IN= 12 V, V_OUT= 5 V, F_SW= 1 MHz)

(V_IN= 24 V, V_OUT= 5 V, F_SW= 1 MHz)

10

9

8

7

6

5

4

3

2

1

0

9

8

7

6

5

4

3

2

1

0

Airflow

250 LFM

Nat conv

Airflow

250 LFM

Nat conv

0

25

50

75

100

125

0

25

50

75

100

125

Ambient Temperature (°C)

图7-11. EVM Thermal Performance

图7-12. EVM Thermal Performance

(V_IN= 12 V, V_OUT= 3.3 V, F_SW= 700 kHz)

(V_IN= 24 V, V_OUT= 3.3 V, F_SW= 700 kHz)

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8 Detailed Description

8.1 Overview

The TPSM63608 is an easy-to-use, synchronous buck DC/DC power module designed for a wide variety of

applications where reliability, small solution size, and low EMI signature are of paramount importance. With

integrated power MOSFETs, a buck inductor, and PWM controller, the TPSM63608 operates over an input

voltage range of 3 V to 36 V with transients as high as 42 V. The module delivers up to 6-A (8-A peak) DC load

current with high conversion efficiency and ultra-low input quiescent current in a very small solution footprint.

Control loop compensation is not required, reducing design time and external component count.

With a programmable switching frequency from 200 kHz to 2.2 MHz using its RT pin or an external clock signal,

the TPSM63608 incorporates specific features to improve EMI performance in noise-sensitive applications:

• An optimized package and pinout design enables a shielded switch-node layout that mitigates radiated EMI

• Parallel input and output paths with symmetrical capacitor layouts minimize parasitic inductance, switch-

voltage ringing, and radiated field coupling

• Dual-random spread spectrum (DRSS) modulation reduces peak emissions

• Resistor-programmable switch-node slew rate

• Clock synchronization and FPWM mode enable constant switching frequency across the load current range

• Integrated power MOSFETs with enhanced gate drive control enable low-noise PWM switching

Together, these features significantly reduce EMI filtering requirements, while helping to meet CISPR 11 and

CISPR 32 Class B EMI limits for conducted and radiated emissions.

The TPSM63608 module also includes inherent protection features for robust system requirements:

• An open-drain PGOOD indicator for power-rail sequencing and fault reporting

• Precision enable input with hysteresis, providing

– Programmable line undervoltage lockout (UVLO)

– Remote ON and OFF capability

• Internally fixed output-voltage soft start with monotonic start-up into prebiased loads

• Hiccup-mode overcurrent protection with cycle-by-cycle peak and valley current limits

• Thermal shutdown with automatic recovery.

Leveraging a pin arrangement designed for simple layout that requires only a few external components, the

TPSM63608 is specified to maximum junction temperatures of 125°C. See typical performance curves to

estimate suitability in a given ambient environment.

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8.2 Functional Block Diagram

SPSP

SYNC/

MODE

R_SP

VLDOIN

Optional

external bias

(from VOUT)

RT

LDO bias

subregulator

VIN

Oscillator

VCC

R_RT

UVLO

SYNC

detect

V_IN= 3 V to 36 V

OTP

VIN1, VIN2

R_ENT

Shutdown

logic

Precision

enable for

V_INUVLO

EN

PG

Enable

logic

RBOOT

CBOOT

R_ENB

OCP

PGOOD

indicator

PGOOD

logic

C_IN

SW

Power

stage

and

control

logic

2.2 µH

V_OUT= 1 V to 20 V

R_FBT

VOUT1, VOUT2

FB

To VOUT

sense point

UVLO

OTP

OCP

EN

Soft start

+

C_OUT

R_FBB

Comp

VREF

PGND

AGND

8.3 Feature Description

8.3.1 Input Voltage Range (VIN1, VIN2)

With a steady-state input voltage range from 3 V to 36 V, the TPSM63608 module is intended for step-down

conversions from typical 12-V, 24-V, and 28-V input supply rails. The schematic circuit in 图 8-1 shows all the

necessary components to implement a TPSM63608-based buck regulator using a single input supply.

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V_IN= 3V to 36 V

VIN1

VIN2

C_IN1

10

C_IN2

10

F

PGND

EN

PGND

R_ENT

Precision enable

for V_INUVLO

PGOOD

indicator

TPSM63608

PG

R_ENB

Optional

external bias

R_PG

VLDOIN

V_OUT= 1-20 V

100 k

VOUT1

VOUT2

VCC

SYNC/

MODE

C_OUT

C_FF

R_FBT

CBOOT

RBOOT

FB

Optional

Synchronization

(200kHz-2.2MHz)

SPSP

RT

R_MODE

R_SS

R_RT

R_FBB

AGND

Adjustable

Switching

Frequency

图8-1. TPSM63608 Schematic Diagram with Input Voltage Operating Range of 3 V to 36 V

The minimum input voltage required for start-up is 3.7 V. Take extra care to make sure that the voltage at the

VIN pins of the module (VIN1 and VIN2) does not exceed the absolute maximum voltage rating of 42 V during

line or load transient events. Voltage ringing at the VIN pins that exceeds the 节7.1 can damage the IC.

8.3.2 Adjustable Output Voltage (FB)

The TPSM63608 has an adjustable output voltage range from 1 V up to a maximum of 20 V or slightly less than

V_IN, whichever is lower. Setting the output voltage requires two feedback resistors, designated as R_FBTand R_FBB

in 图8-1. The reference voltage at the FB pin is set at 1 V with a feedback system accuracy over the full junction

temperature range of ±1%. The junction temperature range for the device is –40°C to 125°C.

Calculate the value for R_FBBusing 方程式1 below based on a recommended value for R_FBTof 100 kΩ.

R

V

kΩ

FBT

R

kΩ =

(1)

FBB

OUT

1

− 1

表 8-1 lists the standard resistor values for several output voltages and the recommended switching frequency

range to maintain reasonable peak-to-peak inductor ripple current. This table also includes the minimum

required output capacitance for each output voltage setting to maintain stability. The capacitances as listed

represent effective values for ceramic capacitors derated for DC bias voltage and temperature. Furthermore,

place a feedforward capacitor, C_FF, in parallel with R_FBTto increase the phase margin when the output

capacitance is close to the minimum recommended value.

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表8-1. Standard R_FBTValues, Recommended F_SWRange and Minimum C_OUT

SUGGESTED

F_SWRANGE

(kHz)

SUGGESTED

F_SWRANGE

(MHz)

R_FBB

(kΩ) ⁽¹⁾

R_FBB

(kΩ) ⁽¹⁾

V_OUT

(V)

C_OUT(min)(µF)

(EFFECTIVE)

C_FF

(pF)

V_OUT

(V)

C_OUT(min)(µF)

(EFFECTIVE)

C_FF

(pF)

BOM⁽²⁾

4 × 100

μF (6.3

V)

4 × 47

μF (16

V)

1

Open

125

43.4

25

200 to 750

300 to 900

400 to 1100

500 to 1400

350

300

100

75

9

12.5

9.09

7.14

5.26

0.75 to 1.5

1 to 1.7

66

—

100

47

—

4 × 100

μF (6.3

V)

3 × 22

μF (25

V)

1.8

3.3

5

12

15

20

30

20

15

4 × 47

μF (10

V)

3 × 22

μF (25

V)

1 to 1.9

3 × 47

μF (10

V)

3 × 22

μF (25

V)

22

1.2 to 2.2

(1) R_FBT= 100 kΩ.

(2) Refer to 表8-3 for the output capacitor list.

Note that higher feedback resistances consume less DC current. However, an upper R_FBTresistor value higher

than 1 MΩ renders the feedback path more susceptible to noise. Higher feedback resistances generally require

more careful layout of the feedback path. Make sure to locate the feedback resistors close to the FB and AGND

pins, keeping the feedback trace as short as possible (and away from noisy areas of the PCB). See 节 9.4.2

guidelines for more detail.

8.3.3 Input Capacitors

Input capacitors are necessary to limit the input ripple voltage to the module due to switching-frequency AC

currents. TI recommends using ceramic capacitors to provide low impedance and high RMS current rating over a

wide temperature range. 方程式 2 gives the input capacitor RMS current. The highest input capacitor RMS

current occurs at D = 0.5, at which point the RMS current rating of the capacitors must be greater than half the

output current.

2

∆ i

2

L

I

=

D ×

I

× 1 − D +

(2)

CIN, rms

OUT

12

where

• D = V_OUT/ V_INis the module duty cycle.

Ideally, the DC and AC components of input current to the buck stage are provided by the input voltage source

and the input capacitors, respectively. Neglecting inductor ripple current, the input capacitors source current of

amplitude (I_OUT– I_IN) during the D interval and sink I_INduring the 1 – D interval. Thus, the input capacitors

conduct a square-wave current of peak-to-peak amplitude equal to the output current. The resultant capacitive

component of AC ripple voltage is a triangular waveform. Together with the ESR-related ripple component, 方程

式3 gives the peak-to-peak ripple voltage amplitude:

I

× D × 1 − D

× C

OUT

∆ V

=

+ I

× R

ESR

(3)

IN

OUT

F

SW

IN

方程式4 gives the input capacitance required for a particular load current:

I

× D × 1 − D

OUT

C

≥

(4)

IN

F

×

∆ V − I

× R

ESR

SW

IN OUT

where

• ΔV_INis the input voltage ripple specification.

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The TPSM63608 requires a minimum of two 10-µF ceramic input capacitors, preferably with X7R or X7S

dielectric and in 1206 or 1210 footprint. Additional capacitance can be required for applications to meet

conducted EMI specifications, such as CISPR 11 or CISPR 32.

表 8-2 includes a preferred list of capacitors by vendor. To minimize the parasitic inductance in the switching

loops, position the ceramic input capacitors in a symmetrical layout close to the VIN1 and VIN2 pins and connect

the capacitor return terminals to the PGND pins using a copper ground plane under the module.

表8-2. Recommended Ceramic Input Capacitors

VENDOR⁽¹⁾

TDK

DIELECTRIC

X7R

PART NUMBER

CASE SIZE

CAPACITANCE (µF)⁽²⁾

RATED VOLTAGE (V)

C3216X7R1H106K160AC

GCM32EC71H106KA03K

12105C106MAT2A

1206

10

50

Murata

AVX

X7S

1210

X7R

1210

Murata

X7R

GRM32ER71H106KA12L

1210

(1) Consult capacitor suppliers regarding availability, material composition, RoHS and lead-free status, and manufacturing process

requirements for any capacitors identified in this table. See the Third-Party Products Disclaimer.

(2) Nameplate capacitance values (the effective values are lower based on the applied DC voltage and temperature).

As discussed in Power Supply Recommendations, an electrolytic bulk capacitance (68 µF to 100 µF) provides

low-frequency filtering and parallel damping to mitigate the effects of input parasitic inductance resonating with

the low-ESR, high-Q ceramic input capacitors.

8.3.4 Output Capacitors

表 8-1 lists the TPSM63608 minimum amount of required output capacitance. The effects of DC bias and

temperature variation must be considered when using ceramic capacitance. For ceramic capacitors in particular,

the package size, voltage rating, and dielectric material contribute to differences between the standard rated

value and the actual effective value of the capacitance.

When including additional capacitance above C_OUT(min), the capacitance can be ceramic type, low-ESR polymer

type, or a combination of the two. See 表8-3 for a preferred list of output capacitors by vendor.

表8-3. Recommended Ceramic Output Capacitors

VENDOR⁽¹⁾

Murata

DIELECTRIC

X7R

PART NUMBER

CASE SIZE CAPACITANCE (µF)⁽²⁾

VOLTAGE (V)

GRM31CZ71C226ME15L

C3225X7R1C226M250AC

GRM32ER71C226KEA8K

C3216X6S1E226M160AC

12103C226KAT4A

1206

1210

1206

1210

1206

1210

22

16

25

10

16

4

TDK

X7R

Murata

TDK

X7R

22

X6S

22

AVX

X7R

22

Murata

AVX

X7R

GRM32ER71E226ME15L

1210ZC476MAT2A

22

X7R

47

Murata

TDK

X7R

GRM32ER71A476ME15L

GRM32EC81C476ME15L

C3216X6S0G107M160AC

GRM31CD80J107MEA8L

GRM32EC70J107ME15L

47

X6S

47

X6S

100

Murata

X6T

6.3

X7S

(1) Consult capacitor suppliers regarding availability, material composition, RoHS and lead-free status, and manufacturing process

requirements for any capacitors identified in the table. See the Third-Party Products Disclaimer.

(2) Nameplate capacitance values (the effective values are lower based on the applied DC voltage and temperature).

8.3.5 Switching Frequency (RT)

Connect a resistor, designated as R_RTin 图 8-1, between RT and AGND to set the switching frequency within

the range of 200 kHz to 2.2 MHz. Refer to 方程式5 to calculate R_RTfor a desired frequency.

16.4

R

kΩ =

− 0.633

(5)

RT

F

MHz

SW

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Refer to 表 8-1 or use the simplified expression in 方程式 5 to find a switching frequency that sets an inductor

ripple current of 15% to 35% of the 6-A module current rating at nominal input voltage: Refer to 节 8.3.7 if clock

synchronization is required.

8.3.6 Precision Enable and Input Voltage UVLO (EN)

The EN pin provides precision ON and OFF control for the TPSM63608. After the EN pin voltage exceeds the

rising threshold and V_INis above its minimum turn-on threshold, the device starts operation. The simplest way to

enable the TPSM63608 is to connect EN directly to VIN. This action allows the TPSM63608 to start up when V_IN

is within its valid operating range. However, many applications benefit from the use of an enable divider network

as shown in 图 8-1, which establishes a precision input undervoltage lockout (UVLO). This can be used for

sequencing, to prevent re-triggering the device when used with long input cables, or to reduce the occurrence of

deep discharge of a battery power source. An external logic signal can also be used to drive the enable input to

toggle the output on and off and for system sequencing or protection.

Calculate R_ENBusing 方程式6:

V

EN_RISE

V − V

R

kΩ = R

kΩ ×

(6)

ENB

ENT

V

IN on

EN_RISE

where

• A typical value for R_ENTis 100 kΩ.

• V_{EN_RISE}is enable rising threshold voltage of 1.263 V (typical).

• V_IN(on)is the desired start-up input voltage.

8.3.7 Frequency Synchronization (SYNC/MODE)

Synchronize the internal oscillator of the TPSM63608 with a positive clock edge to SYNC/MODE, as shown in 图

8-1. The synchronization frequency range is 200 kHz to 2.2 MHz.

TI recommends to tie a resistor from SYNC/MODE to either VCC or ground to keep the pin from floating if the

sync signal is lost or off at start-up. A value in the 100-kΩ range. After a valid synchronization signal is applied

for 2048 cycles, the clock frequency changes to that of the applied signal.

Referring to 图 8-2, the voltage edge at the SYNC/MODE pin must exceed the SYNC amplitude threshold,

V_SYNCDH, of 1.8 V to trip the internal synchronization pulse detector. In addition, the minimum SYNC/MODE

rising and falling pulse durations must be longer than the SYNC signal hold time, t_{SYNC_EDGE}, of 100 ns.

V_EN/SYNC

t_{SYNC_EDGE}

V_{EN_SYNC}

t

0

t_{SYNC_EDGE}

图8-2. Typical SYNC Waveform

8.3.8 Spread Spectrum

Spread spectrum is configurable using the SPSP pin. Spread spectrum eliminates peak emissions at specific

frequencies by spreading these peaks across a wider range of frequencies than a part with fixed-frequency

operation. The TPSM63608 implements a modulation pattern designed to reduce low frequency-conducted

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emissions from the first few harmonics of the switching frequency. The pattern can also help reduce the higher

harmonics that are more difficult to filter, which can fall in the FM band. These harmonics often couple to the

environment through electric fields around the switch node and inductor. The TPSM63608 uses a ±4% (typical)

spread of frequencies which can spread energy smoothly across the FM and TV bands. The device implements

Dual Random Spread Spectrum (DRSS). DRSS is a combination of a triangular frequency spreading pattern and

pseudorandom frequency hopping. The combination allows the spread spectrum to be very effective at

spreading the energy at the following:

• Fundamental switching harmonic with slow triangular pattern

• High frequency harmonics with additional psuedorandom jumps at the switching frequency

The advantage of DRSS is its equivalent harmonic attenuation in the upper frequencies with a smaller

fundamental frequency deviation. This reduces the amount of input current and output voltage ripple that is

introduced at the modulating frequency. Additionally, the TPSM63608 also allows further reduction of the output

voltage ripple caused by the spread spectrum modulating pattern. With the SPSP pin grounded, the spread

spectrum is disabled. With the SPSP pin tied to VCC, the spread spectrum is on. With the SPSP pin tied through

a resistor to ground, the spread spectrum is on. Also, a modulating tone correction is applied to the switcher to

reduce the output voltage ripple caused by the frequency modulation. The resistor is usually around 20 kΩ, and

can be more precisely calculated using 方程式7. Where I_RATED= 6 A for TPSM63608, L = 2.2µH.

V

IN

14.17 ×

V

OUT

R

kΩ =

(7)

SPSP

V

− V

IN

RATED

OUT

× L × F

+ 1.22

I

SW

图8-3. Output Ripple Without Ripple Cancellation Showing V_SW(Top), F_SW(Middle), V_OUT(Bottom)

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图8-4. Output Ripple with Ripple Cancellation Showing V_SW(Top), F_SW(Middle), V_OUT(Bottom)

The spread spectrum is only available while the clock of the TPSM63608 are free running at their natural

frequency. Any of the following conditions overrides spread spectrum, turning it off:

• The clock is slowed due to operation at low input voltage. This is operation in dropout.

• The clock is slowed under light load in auto mode. This is normally not seen above 750-mA load. Note that if

the device is operating in FPWM mode, spread spectrum is active, even if there is no load.

• The clock is slowed due to high input-to-output voltage ratio. This mode of operation is expected if on-time

reaches minimum on time.

8.3.9 Power-Good Monitor (PG)

The TPSM63608 provides a power-good status signal to indicate when the output voltage is within a regulation

window of 94% to 112%. The PG voltage goes low when the feedback (FB) voltage is outside of the specified

PGOOD thresholds (see 图 7-7). This action can occur during current limit and thermal shutdown, as well as

when disabled and during start-up.

PG is an open-drain output, requiring an external pullup resistor to a DC supply, such as VCC or V_OUT. To limit

current supplied by VCC, the recommended range of pullup resistance is 20 kΩ to 100 kΩ. A 26-µs deglitch filter

prevents false flag operation for short excursions of the output voltage, such as during line and load transients.

When EN is pulled low, PG is forced low and remains remains valid as long as the input voltage is above 1 V

(typical). Use the PG signal for start-up sequencing of downstream regulators, as shown in 图 8-5, or for fault

protection and output monitoring.

V_IN(on)= 13.9 V

V_IN(off)= 10 V

V_OUT2= 3.3 V

V_OUT1= 5 V

R_UV1

1 M

R_FB3

PG 13

R_PG

R_FB1

23.2 k

1 V

R_FB4

17

100 k

17

EN

40.2 k

R_UV2

FB

8

FB

8

1 V

100 k

R_FB2

10 k

Regulator #1

Regulator #2

Start-up based on

input voltage UVLO

Sequential start-up

based on PG

图8-5. TPSM63608 Sequencing Implementation Using PG and EN

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8.3.10 Adjustable Switch-Node Slew Rate (RBOOT, CBOOT)

Adjust the switch-node slew rate of the TPSM63608 to slow the switch-node voltage rise time and improve EMI

performance at high frequencies. However, slowing the rise time decreases efficiency. Care must be taken to

balance the improved EMI versus the decreased efficiency.

Place a resistor from RBOOT and CBOOT to allow adjustment of the internal resistance to balance EMI and

efficiency performance. If improved EMI is not required, connect RBOOT to CBOOT to short the internal resistor,

thus resulting in highest efficiency. If lower EMI is required, connect a resistor from 100 Ω – 500 Ω to. Floating

the R_BOOTpin results in 20-ns rise time and TI does not recommend due to increased power loss for higher load

currents.

8.3.11 Bias Supply Regulator (VCC, VLDOIN)

VCC is the output of the internal LDO subregulator used to supply the control circuits of the TPSM63608. The

nominal VCC voltage is 3.3 V. The VLDOIN pin is the input to the internal LDO. Connect this input to V_OUTto

provide the lowest possible input supply current. If the VLDOIN voltage is less than 3.1 V, VIN1 and VIN2 directly

power the internal LDO.

To prevent unsafe operation, VCC has UVLO protection that prevents switching if the internal voltage is too low.

See V_{CC_UVLO}and V_{CC_UVLO_HYS}in the 节7.5.

VCC must not be used to power external circuitry. Do not load VCC or short it to ground. VLDOIN is an optional

input to the internal LDO. Connect an optional high quality 0.1-µF to 1-µF capacitor from VLDOIN to AGND for

improved noise immunity.

The LDO provides the VCC voltage from one of two inputs: V_INor VLDOIN. When VLDOIN is tied to ground or

below 3.1 V, the LDO derives power from V_IN. The LDO input becomes VLDOIN when VLDOIN is tied to a

voltage above 3.1 V. The VLDOIN voltage must not exceed both V_INand 12 V.

方程式8 specifies the LDO power loss reduction as:

P_LDO-LOSS= I_LDO× (V_IN-LDO–V_VCC

)

(8)

The VLDOIN input provides an option to supply the LDO with a lower voltage than V_IN, thus minimizing the LDO

input voltage relative to VCC and reducing power loss. For example, if the LDO current is 10 mA at 1 MHz with

V_IN= 24 V and V_OUT= 5 V, the LDO power loss with VLDOIN tied to ground is 10 mA × (24 V – 3.3 V) = 207

mW, while the loss with VLDOIN tied to V_OUTis equal to 10 mA × (5 V – 3.3 V) = 17 mW – a reduction of 190

mW.

图8-6 and 图8-7 show typical efficiency plots with and without VLDOIN connected to VOUT.

100

95

90

85

80

75

V_VLDOIN= V_OUT

V_VLDOIN= GND

70

0

1

2

3

4

5

6

Output Current (A)

V_IN= 24 V

V_OUT= 5 V

F_SW= 1 MHz

V_IN= 36 V

V_OUT= 5 V

F_SW= 1 MHz

图8-6. Efficiency Increase with External Bias

图8-7. Efficiency Increase with External Bias

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8.3.12 Overcurrent Protection (OCP)

The TPSM63608 is protected from overcurrent conditions using cycle-by-cycle current limiting of the peak

inductor current. The current is compared every switching cycle to the current limit threshold. During an

overcurrent condition, the output voltage decreases.

The TPSM63608 employs hiccup overcurrent protection if there is an extreme overload. In hiccup mode, the

TPSM63608 module is shut down and kept off for 40 ms (typical) before a restart is attempted. If an overcurrent

or short-circuit fault condition still exists, hiccup repeats until the fault condition is removed. Hiccup mode

reduces power dissipation under severe overcurrent conditions, thus preventing overheating and potential

damage to the device. After the fault is removed, the module automatically recovers and returns to normal

operation.

8.3.13 Thermal Shutdown

Thermal shutdown is an integrated self-protection used to limit junction temperature and prevent damage related

to overheating. Thermal shutdown turns off the device when the junction temperature exceeds 168°C (typical) to

prevent further power dissipation and temperature rise. Junction temperature decreases after shutdown, and the

TPSM63608 attempts to restart when the junction temperature falls to 159°C (typical).

8.4 Device Functional Modes

8.4.1 Shutdown Mode

The EN pin provides ON and OFF control for the TPSM63608. When V_ENis below approximately 0.4 V, the

device is in shutdown mode. Both the internal LDO and the switching regulator are off. The quiescent current in

shutdown mode drops to 0.6 µA (typical). The TPSM63608 also employs internal undervoltage protection. If the

input voltage is below its UV threshold, the regulator remains off.

8.4.2 Standby Mode

The internal LDO for the VCC bias supply has a lower enable threshold than the regulator itself. When V_ENis

above 1.1 V (maximum) and below the precision enable threshold of 1.263 V (typical), the internal LDO is on and

regulating. The precision enable circuitry is turned on after the internal V_CCis above its UVLO threshold. The

switching action and voltage regulation are not enabled until V_ENrises above the precision enable threshold.

8.4.3 Active Mode

The TPSM63608 is in active mode when V_VCCand V_ENare above their relevant thresholds and no fault

conditions are present. The simplest way to enable operation is to connect EN to V_IN, which allows self start-up

when the applied input voltage exceeds the minimum start-up voltage.

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9 Applications and Implementation

备注

Information in the following applications sections is not part of the TI component specification, and TI

does not warrant its accuracy or completeness. TI’s customers are responsible for determining

suitability of components for their purposes, as well as validating and testing their design

implementation to confirm system functionality.

9.1 Application Information

The TPSM63608 synchronous buck module requires only a few external components to convert from a wide

range of supply voltages to an output voltage at an output current up to 6 A. To expedite and streamline the

process of designing a TPSM63608-based regulator, a comprehensive TPSM63608 quickstart calculator tool is

available by download to assist the system designer with component selection for a given application.

9.2 Typical Applications

For the circuit schematic, bill of materials, PCB layout files, and test results of a TPSM63608-powered

implementation, see the TPSM63610EVM 10-A reference design .

9.2.1 Design 1 –High-Efficiency 6-A (8-A peak) Synchronous Buck Regulator for Industrial Applications

The following figure shows the schematic diagram of a 5-V, 6-A buck regulator with a switching frequency of 1

MHz. In this example, the target half-load and full-load efficiencies are 94% and 92%, respectively, based on a

nominal input voltage of 24 V that ranges from 9 V to 36 V. A resistor R_RTof 15.8 kΩ sets the free-running

switching frequency at 1 MHz. An optional SYNC input signal allows adjustment of the switching frequency from

500 kHz to 1.4 MHz for this specific application.

V_IN= 9 V to 36 V

VIN1

VIN2

C_IN1

10

C_IN2

10

V_IN(on)= 6 V

V_IN(off)= 4.3 V

F

PGND

EN

PGND

R_ENT

187 k

Precision enable

for V_INUVLO

PGOOD

indicator

TPSM63608

PG

R_ENB

Optional

external bias

V_OUT= 5 V

I_OUT= 6 A

R_PG

49.9 k

VLDOIN

100 k

VOUT1

VOUT2

VCC

C_OUT

SYNC/

MODE

C_FF

22 pF

R_FBT

CBOOT

RBOOT

FB

3 ꢀ 47

F

100 k

Optional

Synchronization

SPSP

RT

R_MODE

R_SS

R_RT

R_FBB

AGND

24.9 k

15.8 k

Fsw =1MHz

图9-1. Circuit Schematic

9.2.1.1 Design Requirements

表 9-1 shows the intended input, output, and performance parameters for this application example. Note that if

the input voltage decreases below approximately 5.5 V, the regulator operates in dropout with the output voltage

below its 5-V setpoint.

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表9-1. Design Parameters

DESIGN PARAMETER

Input voltage range

VALUE

9 V to 36 V

6 V, 4.3 V

5 V

Input voltage UVLO turn on, off

Output voltage

Maximum output current

Switching frequency

6 A

1 MHz

±1%

Output voltage regulation

Module shutdown current

< 1 µA

表 9-2 gives the selected buck module power-stage components with availability from multiple vendors. This

design uses an all-ceramic output capacitor implementation.

表9-2. List of Materials for Application Circuit 1

REFERENCE

DESIGNATOR

QTY

SPECIFICATION

MANUFACTURER⁽¹⁾

PART NUMBER

Taiyo Yuden

TDK

UMJ325KB7106KMHT

CNA6P1X7R1H106K

GCM32EC71H106KA03

CGA6P3X7S1H106M

GRM32ER70J476ME20K

12106C476MAT2A

10 µF, 50 V, X7R, 1210, ceramic

C_IN1, C_IN2

2

Murata

10 µF, 50 V, X7S, 1210, ceramic

47 µF, 6.3 V, X7R, 1210, ceramic

47 µF, 10 V, X7R, 1210, ceramic

TDK

Murata

AVX

C_OUT1

,

3

1

Murata

GRM32ER71A476ME15L

1210ZC476MAT2A

C_OUT2,C_OUT3

AVX

100 µF, 6.3 V, X7S, 1210, ceramic

Murata

GRM32EC70J107ME15L

TPSM63608RDLR

U₁

TPSM63608 36-V, 6-A synchronous buck module

Texas Instruments

(1) See the Third-Party Products Disclaimer.

More generally, the TPSM63608 module is designed to operate with a wide range of external components and

system parameters. However, the integrated loop compensation is optimized for a certain range of output

capacitance.

9.2.1.2 Detailed Design Procedure

9.2.1.2.1 Custom Design With WEBENCH® Tools

Click here to create a custom design using the TPSM63608 module with WEBENCH® Power Designer.

1. Start by entering the input voltage (V_IN), output voltage (V_OUT), and output current (I_OUT) requirements.

2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.

3. Compare the generated design with other possible solutions from Texas Instruments.

The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time

pricing and component availability.

In most cases, these actions are available:

• Run electrical simulations to see important waveforms and circuit performance.

• Run thermal simulations to understand board thermal performance.

• Export customized schematic and layout into popular CAD formats.

• Print PDF reports for the design, and share the design with colleagues.

Get more information about WEBENCH tools at www.ti.com/WEBENCH.

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9.2.1.2.2 Output Voltage Setpoint

The output voltage of a TPSM63608 module is externally adjustable using a resistor divider. A recommended

value for R_FBTof 100 kΩ for improved noise immunity compared to 1 MΩ and reduced current consumption

compared to lower resistance values. Calculate R_FBBusing the following equation:

R

V

× V

FBT

OUT

REF

R

=

(9)

FBB

− V

Choose the closest standard value of 24.9 kΩfor R_FBB

.

9.2.1.2.3 Switching Frequency Selection

Connect a 15.8-kΩ resistor from RT to AGND to set a switching frequency of 1 MHz, which is designed for an

output of 5 V as it establishes an inductor peak-to-peak ripple current in the range of 20% to 40% of the 6-A

rated output current at a nominal input voltage of 24 V.

9.2.1.2.4 Input Capacitor Selection

The TPSM63608 requires a minimum input capacitance of 2 × 10-µF ceramic, preferably with X7R dielectric.

The voltage rating of input capacitors must be greater than the maximum input voltage. For this design, select

two 10-µF, X7R, 50-V, 1210 case size, ceramic capacitors connected from VIN1 and VIN2 to PGND as close as

possible to the module. See 图9-17 for recommneded layout placement.

9.2.1.2.5 Output Capacitor Selection

From 表 8-1, the TPSM63608 requires a minimum of 25 µF of effective output capacitance for proper operation

at an output voltage of 5 V at 2.2 MHz. Use high-quality ceramic type capacitors with sufficient voltage and

temperature rating. If needed, connect additional output capacitance to reduce ripple voltage or for applications

with specific load transient requirements.

For this design example, use three 47-µF, 6.3-V or 10-V, X7R, 1210, ceramic capacitors connected close to the

module from the VOUT1 and VOUT2 pins to PGND. The total effective capacitance at 5 V is approximately

78 µF and 57 µF at 25°C and –40°C, respectively.

9.2.1.2.6 Other Connections

Short RBOOT to CBOOT and connect VLDOIN to the 5-V output for best efficiency. To increase phase margin

when using an output capacitance close to the minimum in 表 8-1, a feedforward capacitor, designated as C_FF

can be placed across the upper feedback resistor. Place the zero created by C_FFand R_FBThigher than one fifth

the switching so that it boosts phase but does not significantly increase the crossover frequency. Because this

C_FFcapacitor can conduct noise from the output of the circuit directly to the FB node of the IC, a 4.99-kΩ

resistor, R_FF, must be placed in series with C_FF. If the ESR zero of the output capacitor is below 200 kHz, do not

use CFF.

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9.2.1.3 Application Curves

Unless otherwise indicated, V_IN= 24 V, V_OUT= 5 V, I_OUT= , and F_SW= 1 MHz.

100

95

90

85

80

75

70

100

95

90

85

80

75

70

VIN = 12 V

VIN = 24 V

VIN = 36 V

VIN = 12 V

VIN = 24 V

VIN = 36 V

0

1

2

3

4

5

6

0

1

2

3

4

5

6

Output Current (A)

V_OUT= 5 V

FPWM mode

F_SW= 1 MHz

V_OUT= 5 V

Auto mode

F_SW= 1 MHz

图9-2. Efficiency for V_OUT= 5 V

图9-3. Efficiency for V_OUT= 5 V

5.05

5.025

5

5.05

5.025

5

4.975

4.95

4.975

4.95

VIN = 12 V

VIN = 24 V

VIN = 36 V

VIN = 12 V

VIN = 24 V

VIN = 36 V

0

1

2

3

4

5

6

0

1

2

3

4

5

6

Output Current (A)

V_OUT= 5 V

FPWM mode

F_SW= 1 MHz

V_OUT= 5 V

Auto mode

F_SW= 1 MHz

图9-4. Load Regulation for V_OUT= 5 V

图9-5. Load Regulation for V_OUT= 5 V

CH 4 ( IOUT )

CH 3 ( VOUT )

CH 1 ( VIN )

CH 2 ( VOUT )

CH 3 ( PG )

V_OUT= 5 V

T_R= T_F= 4 µs

FPWM mode

V_IN= 24 V

F_SW= 1 MHz

Slew rate = 1 A/µs

V_IN= 24 V

I_OUT= 6 A

F_SW= 1 MHz

图9-7. Load Transient, 0 A to 4 A, 1 A/µs

图9-6. Start-up

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75

60

45

30

15

0

CH 1 ( VIN )

CH 2 ( VOUT )

CH 3 ( PG )

CISPR 11/32 Class B QP detector

CISPR 11/32 Class B AVG detector

Evaluation Board

CH 4 ( IOUT )

-15

0.1

0.2 0.3 0.5 0.7

1

2

3

4 5 6 78 10

20 30

Frequency (MHz)

Default EVM

V_OUT= 5 V

F_SW= 1 MHz

V_OUT= 5 V

F_SW= 1 MHz

图9-9. CISPR 11/32 Class B Conducted Emissions:

V_IN= 24 V, SPSP ON TPSM63610EVM

图9-8. Start-up into Short Circuit

50

45

40

35

30

25

20

15

10

CISPR11 Class B Limit

Evaluation Board (Horizontal)

Evaluation Board (Vertical)

0

5

0

100 200 300 400 500 600 700 800 900 1000

Frequency (MHz)

Additional 2 x

V_OUT= 5 V

F_SW= 1 MHz

Default EVM

V_OUT= 5 V

F_SW= 1 MHz

10pF C_INwith EMI

filter removed

图9-10. CISPR 11/32 Class B Conducted

Emissions: V_IN= 24 V, SPSP OFF TPSM63610EVM

图9-11. CISPR 11 Class B Radiated Emissions: V_IN

= 24 V, SPSP ON TPSM63610EVM

50

45

40

35

30

25

20

15

10

5

CISPR11 Class B Limit

Evaluation Board (Horizontal)

Evaluation Board (Vertical)

0

100 200 300 400 500 600 700 800 900 1000

Frequency (MHz)

Additional 2 x 10pF C_INwith EMI filter

removed

V_OUT= 5 V

F_SW= 1 MHz

图9-12. CISPR 11 Class B Radiated Emissions: V_IN= 24 V, SPSP OFF TPSM63610EVM

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9.2.2 Design 2 –Inverting Buck-Boost Regulator with Negative Output Voltage

图 9-13 shows the schematic diagram of an inverting buck-boost (IBB) regulator with an output of –12 V and a

switching frequency of 1 MHz with a nominal input voltage of 12 V that ranges from 9 V to 24 V.

VIN+

U₁

C_IN3

10

VIN1

VIN2

V_IN= 9 V to 24 V

VIN–

V_IN(on)= 8.9 V

F

C_IN1

10

C_IN2

10

F

PGND

R_ENT

604 k

–VOUT

TPSM63608

Optional

external bias

Precision

enable for

V_INUVLO

EN

VLDOIN

VOUT+

VOUT1

VOUT2

VCC

R_ENB

100 k

SYNC/

MODE

V_OUT= –12 V

I_OUT(max)= –3.8 A

C_OUT

CBOOT

RBOOT

FB

R_FBT

SPSP

3 ꢀ 22

F

110 k

–VOUT

PG

RT

VOUT–

–VOUT

R_RT

15.8 k

R_FBB

10 k

AGND

–VOUT

图9-13. Circuit Schematic

9.2.2.1 Design Requirements

表 9-3 shows the intended input, output, and performance parameters for this application example. With an IBB

topology, the module sees a total current of I_IN+ |–I_OUT|, which is highest at minimum input voltage.

表9-3. Design Parameters

DESIGN PARAMETER

Input voltage range

Input voltage UVLO turn on

Output voltage

VALUE

9 V to 24 V

8.9 V

–12 V

–3.8 A

1 MHz

Full-load current

Switching frequency

Output voltage regulation

±1%

表 9-4 gives the selected buck module power-stage components with availability from multiple vendors. This

design uses an all-ceramic output capacitor implementation.

表9-4. List of Materials for Application Circuit 2

REF DES

QTY

SPECIFICATION

10 µF, 50 V, X7R, 1210, ceramic

22 µF, 16 V, X7R, 1206, ceramic

22 µF, 25 V, X7R, 1210, ceramic

MANUFACTURER⁽¹⁾

PART NUMBER

C1210C106K5RACTU

CNA6P1X7R1H106K

GRM31CZ71C226ME15L

GRM32ER71E226ME15L

12103C226KAT4A

Kemet

C_IN1, C_IN2, C_IN3

3

TDK

Murata

C_OUT1, C_OUT2

,

3

1

C_OUT3

AVX

47 µF, 16 V, X6S, 1210, ceramic

Murata

GRM32EC81C476ME15L

TPSM63608RDLR

U₁

TPSM63608 36-V, 6-A synchronous buck module

Texas Instruments

(1) See the Third-Party Products Disclaimer.

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9.2.2.2 Detailed Design Procedure

9.2.2.2.1 Output Voltage Setpoint

For an output voltage of –12 V, choose upper and lower feedback resistance of 110 kΩ and 10 kΩ,

respectively, using Adjustable Output Voltage Equation.

9.2.2.2.2 IBB Maximum Output Current

The achievable output current with an IBB topology using the TPSM63608 is I_OUT(max)= I_LDC(max)× (1 – D),

where I_LDC(max)= 6 A is the rated current of the module and D = |V_OUT| / (V_IN+ |V_OUT|) is the IBB duty cycle. 图

9-14 provides the maximum output current capability as a function of input voltage for output voltage setpoints of

–3.3 V, –5 V and –12 V.

9.2.2.2.3 Switching Frequency Selection

Connect a 15.8-kΩ resistor from RT to AGND to set a switching frequency of 1 MHz, which is designed for an

output of –12 V.

9.2.2.2.4 Input Capacitor Selection

Use two 10-µF, 50-V, X7R-dielectric ceramic capacitors in 1210 case size connected symmetrically from the

VIN1 and VIN2 pins to PGND as close as possible to the module. More specifically, these capacitors appear

from the drain of the internal high-side MOSFET to the source of the low-side MOSFET, effectively connecting

from the positive input voltage to the negative output voltage terminals.

The sum of the input and output voltages, V_IN+ |–V_OUT|, is the effective applied voltage across the capacitors.

The total effective capacitance at 25°C and input voltages of 12 V and 24 V (corresponding to applied voltages

of 24 V and 36 V) is approximately 12 µF and 8 µF, respectively. Check the capacitance versus voltage derating

curve in the capacitor data sheet.

Use an additional 10-µF, 50-V capacitor directly across the input. This capacitor is designated as C_IN3and

connects across the VIN+ and VIN–terminals as shown in 图9-13.

9.2.2.2.5 Output Capacitor Selection

For this IBB design example, use three 22-µF, 25-V, X7R-dielectric ceramic capacitors in 1210 case size

connected symmetrically close to the module from the VOUT pins (Pin 9 and Pin 10) to PGND. The total

effective capacitance is approximately 25 µF with DC bias of 12 V.

9.2.2.2.6 Other Considerations

Short RBOOT to CBOOT and connect VLDOIN to the power stage GND terminal, which corresponds to VOUT

pins (Pin 9 and Pin 10) of the module, for best efficiency.

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9.2.2.3 Application Curves

Unless otherwise indicated, V_IN= 12 V, V_OUT= –12 V, and F_SW= 1 MHz.

6

5

4

3

2

1

0

95

90

85

80

75

70

65

VOUT = -3.3 V

VOUT = -5 V

VOUT = -12 V

VIN = 12 V

VIN = 24 V

0

0.5

1

1.5

2

2.5

3

3.5

0

3

6

9

12 15 18 21 24 27 30 33

Input Voltage (V)

Output Current (A)

图9-15. Efficiency for V_OUT= –12 V, FPWM Mode

图9-14. IBB Maximum Output Current

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9.3 Power Supply Recommendations

The TPSM63608 buck module is designed to operate over a wide input voltage range of 3 V to 36 V. The

characteristics of the input supply must be compatible with the Absolute Maximum Ratings and Recommended

Operating Conditions in this data sheet. In addition, the input supply must be capable of delivering the required

input current to the loaded regulator circuit. Estimate the average input current with 方程式10.

V

× I

OUT OUT

I

=

(10)

IN

V

× η

IN

where

• ηis the efficiency.

If the module is connected to an input supply through long wires or PCB traces with a large impedance, take

special care to achieve stable performance. The parasitic inductance and resistance of the input cables can

have an adverse affect on module operation. More specifically, the parasitic inductance in combination with the

low-ESR ceramic input capacitors form an underdamped resonant circuit, possibly resulting in instability or

voltage transients each time the input supply is cycled ON and OFF. The parasitic resistance causes the input

voltage to dip during a load transient. If the module is operating close to the minimum input voltage, this dip can

cause false UVLO triggering and a system reset.

The best way to solve such issues is to reduce the distance from the input supply to the module and use an

electrolytic input capacitor in parallel with the ceramics. The moderate ESR of the electrolytic capacitor helps

damp the input resonant circuit and reduce any overshoot or undershoot at the input. A capacitance in the range

of 47 μF to 100 μF is usually sufficient to provide input parallel damping and helps hold the input voltage

steady during large load transients. A typical ESR of 0.1 Ω to 0.4 Ω provides enough damping for most input

circuit configurations.

9.4 Layout

Proper PCB design and layout is important in high-current, fast-switching module circuits (with high internal

voltage and current slew rates) to achieve reliable device operation and design robustness. Furthermore, the

EMI performance of the module depends to a large extent on PCB layout.

9.4.1 Layout Guidelines

The following list summarizes the essential guidelines for PCB layout and component placement to optimze

DC/DC module performance, including thermals and EMI signature. 图 9-16 and 图 9-17 show a recommended

PCB layout for the TPSM63608 with optimized placement and routing of the power-stage and small-signal

components.

• Place input capacitors as close as possible to the VIN pins. Note the dual and symmetrical arrangement of

the input capacitors based on the VIN1 and VIN2 pins located on each side of the module package. The high-

frequency currents are split in two and effectively flow in opposing directions such that the related magnetic

fields contributions cancel each other, leading to improved EMI performance.

– Use low-ESR 1206 or 1210 ceramic capacitors with X7R or X7S dielectric. The module has integrated

dual 0402 input capacitors for high-frequency bypass.

– Ground return paths for the input capacitors must consist of localized top-side planes that connect to the

PGND pads under the module.

– Even though the VIN pins are connected internally, use a wide polygon plane on a lower PCB layer to

connect these pins together and to the input supply.

• Place output capacitors as close as possible to the VOUT pins. A similar dual and symmetrical arrangement

of the output capacitors enables magnetic field cancellation and EMI mitigation.

– Ground return paths for the output capacitors must consist of localized top-side planes that connect to the

PGND pads under the module.

– Even though the VOUT pins are connected internally, use a wide polygon plane on a lower PCB layer to

connect these pins together and to the load, thus reducing conduction loss and thermal stress.

30

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• Keep the FB trace as short as possible by placing the feedback resistors close to the FB pin. Reduce noise

sensitivity of the output voltage feedback path by placing the resistor divider close to the FB pin, rather than

close to the load. FB is the input to the voltage-loop error anplifier and represents a high-impedance node

sensitive to noise. Route a trace from the upper feedback resistor to the required point of output voltage

regulation.

• Use a solid ground plane on the PCB layer directly below the top layer with the module. This plane acts as a

noise shield by minimizing the magnetic fields associated with the currents in the switching loops. Connect

AGND pins 6 and 11 directly to PGND pin 19 under the module.

• Provide enough PCB area for proper heatsinking. Use sufficient copper area to acheive a low thermal

impedance commensurate with the maximum load current and ambient temperature conditions. Provide

adequate heatsinking for the TPSM63608 to keep the junction temperature below 150°C. For operation at full

rated load, the top-side ground plane is an important heat-dissipating area. Use an array of heat-sinking vias

to connect the exposed pads (PGND) of the package to the PCB ground plane. If the PCB has multiple

copper layers, connect these thermal vias to inner-layer ground planes. Make the top and bottom PCB layers

preferably with two-ounce copper thickness (and no less than one ounce).

9.4.1.1 Thermal Design and Layout

For a DC/DC module to be useful over a particular temperature range, the package must allow for the efficient

removal of the heat produced while keeping the junction temperature within rated limits. The TPSM63608

module is available in a small 6.5-mm × 7.55-mm 22-pin QFN (RDL) package to cover a range of application

requirements. The Thermal Information table summarizes the thermal metrics of this package with related detail

provided by the Semiconductor and IC Package Thermal Metrics application report.

The 22-pin QFN package offers a means of removing heat through the exposed thermal pads at the base of the

package. This allows a significant improvement in heatsinking, and it becomes imperative that the PCB is

designed with thermal lands, thermal vias, and one or more ground planes to complete the heat removal

subsystem. The exposed pads of the TPSM63608 are soldered to the ground-connected copper lands on the

PCB directly underneath the device package, reducing the thermal resistance to a very low value.

Preferably, use a four-layer board with 2-oz copper thickness for all layers to provide low impedance, proper

shielding and lower thermal resistance. Numerous vias with a 0.3-mm diameter connected from the thermal

lands to the internal and solder-side ground planes are vital to promote heat transfer. In a multi-layer PCB stack-

up, a solid ground plane is typically placed on the PCB layer below the power-stage components. Not only does

this provide a plane for the power-stage currents to flow, but it also represents a thermally conductive path away

from the heat-generating device.

9.4.2 Layout Example

Cin1

Rrt

Cout1

U1

Rfbb

Cboot

Rfbt

Cin2

Cout2

Rboot

Cvcc

图9-16. Typical Layout

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Legend

Top layer copper

Layer-2 GND plane

Top solder

SPSP

RT

AGND

MODE

VIN

EN

VOUT

Input

Capacitor

Output

Capacitor

Position the input

capacitors very close

to the VIN pins

Place an array of

PGND vias close to the

IC for heat spreading

PGND

Output

Capacitor

Input

Capacitor

FB

AGND

VIN

SW

Place the feedback

components close to the FB pin

Place thermal vias at the

VOUT pins for heat spreading

图9-17. Typical Top Layer Design

32

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10 Device and Documentation Support

10.1 Device Support

10.1.1 第三方产品免责声明

TI 发布的与第三方产品或服务有关的信息，不能构成与此类产品或服务或保修的适用性有关的认可，不能构成此

类产品或服务单独或与任何TI 产品或服务一起的表示或认可。

10.1.2 Development Support

With an input operating voltage from 3 V to 36 V and rated output current up to 10 A, the TPSM63608 family of

synchronous buck power modules provides flexibility, scalability and optimized solution size for a range of

applications. These modules enable DC/DC solutions with high density, low EMI and increased flexibility.

Available EMI mitigation features include dual-random spread spectrum (DRSS), RBOOT-configured switch-

node slew rate control, and integrated input bypass capacitors.

表10-1. Synchronous Buck DC/DC Power Module Family

DC/DC MODULE

RATED I_OUTPACKAGE

DIMENSIONS

FEATURES

EMI MITIGATION

TPSM63610

8 A

RT adjustable F_SW,

6.5 mm × 7.5 mm × 4 external

DRSS, RBOOT, integrated

input, VCC and BOOT

capacitors

B3QFN (22)

6 A

mm

synchronization,MODE

adjustable (PFM/FPWM)

TPSM63608

For development support see the following:

• For TI's reference design library, visit the TI Reference Design library.

• For TI's WEBENCH Design Environment, visit the WEBENCH^®Design Center.

• To design a low-EMI power supply, review TI's comprehensive EMI Training Series.

• To design an inverting buck-boost (IBB) regulator, visit DC/DC inverting buck-boost modules.

• TI Reference Designs:

– Multiple Output Power Solution For Kintex 7 Application

– Arria V Power Reference Design

– Altera Cyclone V SoC Power Supply Reference Design

– Space-optimized DC/DC Inverting Power Module Reference Design With Minimal BOM Count

– 3- To 11.5-V_IN, –5-V_OUT, 1.5-A Inverting Power Module Reference Design For Small, Low-noise Systems

• Technical Articles:

– Powering Medical Imaging Applications With DC/DC Buck Converters

– How To Create A Programmable Output Inverting Buck-boost Regulator

• To view a related device of this product, see the LM61495 36-V, 10-A synchronous buck converter.

10.1.2.1 Custom Design With WEBENCH® Tools

Click here to create a custom design using the TPSM63608 module with WEBENCH® Power Designer.

1. Start by entering the input voltage (V_IN), output voltage (V_OUT), and output current (I_OUT) requirements.

2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.

3. Compare the generated design with other possible solutions from Texas Instruments.

The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time

pricing and component availability.

In most cases, these actions are available:

• Run electrical simulations to see important waveforms and circuit performance.

• Run thermal simulations to understand board thermal performance.

• Export customized schematic and layout into popular CAD formats.

• Print PDF reports for the design, and share the design with colleagues.

Get more information about WEBENCH tools at www.ti.com/WEBENCH.

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10.2 Documentation Support

10.2.1 Related Documentation

For related documentation, see the following:

• Texas Instruments, Quick Reference Guide to TI Buck Switching DC/DC Application Notes Compilation of

Application Notes

• Texas Instruments, Innovative DC/DC Power Modules selection guide

• Texas Instruments, Enabling Small, Cool and Quiet Power Modules with Enhanced HotRod™ QFN Package

Technology white paper

• Texas Instruments, Benefits and Trade-offs of Various Power-Module Package Options white paper

• Texas Instruments, Simplify Low EMI Design with Power Modules white paper

• Texas Instruments, Power Modules for Lab Instrumentation white paper

• Texas Instruments, An Engineer's Guide To EMI In DC/DC Regulators e-book

• Texas Instruments, Soldering Considerations for Power Modules application report

• Texas Instruments, Practical Thermal Design With DC/DC Power Modules application report

• Texas Instruments, Using New Thermal Metrics application report

• Texas Instruments, AN-2020 Thermal Design By Insight, Not Hindsight application report

• Texas Instruments, Using the TPSM53602/3/4 for Negative Output Inverting Buck-Boost Applications

application report

10.3 接收文档更新通知

要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新进行注册，即可每周接收产品信息更

改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。

10.4 支持资源

TI E2E^™支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解

答或提出自己的问题可获得所需的快速设计帮助。

链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅

TI 的《使用条款》。

10.5 Trademarks

HotRod^™and TI E2E^™are trademarks of Texas Instruments.

WEBENCH^®is a registered trademark of Texas Instruments.

所有商标均为其各自所有者的财产。

10.6 静电放电警告

静电放电(ESD) 会损坏这个集成电路。德州仪器(TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理

和安装程序，可能会损坏集成电路。

ESD 的损坏小至导致微小的性能降级，大至整个器件故障。精密的集成电路可能更容易受到损坏，这是因为非常细微的参

数更改都可能会导致器件与其发布的规格不相符。

10.7 术语表

TI 术语表

本术语表列出并解释了术语、首字母缩略词和定义。

11 Mechanical, Packaging, and Orderable Information

The following pages include mechanical packaging and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this datasheet, refer to the left-hand navigation.

34

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PACKAGE OUTLINE

B3QFN - 4.05 mm max height

PLASTIC QUAD FLAT PACK- NO LEAD

RDF0022A

6.6

6.4

B

A

7.6

7.4

PIN 1 INDEX AREA

4.05

3.95

C

SEATING PLANE

0.08

C

(0.4)

(0.6)

4X

3.4

3.2

1.3

1.1

4X

(0.13) TYP

0.95

0.85

4X

22X (0.15)

0.1

C

A

B

0.05

C

9

10

22

21

1.1

0.9

4X

0.1

C

A

B

2X 6.5

2X 0.75

20

19

2X 2.25

0.3

0.2

14X

1

0.1

C

A

B

18

0.05

C

20X 0.65

1.1

PIN 1 ID

22X (0.125)

14X

0.9

4226290/A 09/2020

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.

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EXAMPLE BOARD LAYOUT

B3QFN - 4.05 mm max height

PLASTIC QUAD FLAT PACK- NO LEAD

RDF0022A

(5.7)

(0.05) MIN

ALL AROUND

TYP

4X (3.3)

(R 0.05) TYP

1

18

14X (0.25)

19

20

21

22

4X (1)

0.000 PKG ℄

2X (6.5)

2X (0.75)

14X (1.2)

2X (2.25)

4X (0.9)

9

10

20X (0.65)

4X (1.075)

(Ø0.2) TYP

4X (1.4)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE: 12X

SOLDER MASK

OPENING

0.05 MIN

ALL AROUND

0.05 MAX

ALL AROUND

METAL

EXPOSED METAL

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

EXPOSED METAL

SOLDER MASK

DEFINED

NON- SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

4226290/A 09/2020

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

number SLUA271 (www.ti.com/lit/slua271).

5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown

on this view. It is recommended that vias under paste be filled, plugged or tented.

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EXAMPLE STENCIL DESIGN

B3QFN - 4.05 mm max height

PLASTIC QUAD FLAT PACK- NO LEAD

RDF0022A

(5.7)

12X (0.95)

(R 0.05) TYP

1

18

14X (0.25)

19

12X (0.95)

20

21

0.000 PKG ℄

2X (6.5)

3X (0.75)

14X (1.2)

22

3X (2.25)

4X (0.9)

9

10

20X (0.65)

4X (1.075)

4X (1.4)

SOLDER PASTE EXAMPLE

BASED ON 0.1 mm THICK STENCIL

SOLDER COVERAGE:

PIN 19 TO 22 : 82%

SCALE: 12X

4226290/A 09/2020

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

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重要声明和免责声明

TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，

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您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成

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TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE

邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	TPSM63608RDFR
厂家：	TEXAS INSTRUMENTS
描述：	采用 7.5mm x 6.5mm HotRod™ QFN 封装的高密度 36V 输入、1V 至 20V 输出、6A 电源模块 \| RDF \| 22 \| -40 to 125 电源电路
文件：	总39页 (文件大小：2294K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

TPSM63608RDFR [TI]

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