TRF2432IRTQR [TI]
Dual-Band IQ/IF TRANSCEIVER WITH DUAL VCO SYNTHESIZERS; 双频IQ / IF收发器，双VCO合成器
| 型号： | TRF2432IRTQR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | Dual-Band IQ/IF TRANSCEIVER WITH DUAL VCO SYNTHESIZERS |
| 文件： | 总24页 (文件大小：551K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TRF2432
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SLWS177B–APRIL 2005–REVISED NOVEMBER 2006
Dual-Band IQ/IF TRANSCEIVER WITH DUAL VCO SYNTHESIZERS
FEATURES
Anti-Aliasing Filters Integrated
•
•
•
•
Highly Integrated 802.16 d/e Radio IQ/IF
Transceiver PLL ASIC
•
Differential LO and IF Interface for Enhanced
Spurious Immunity
Fully Integrated IF and RF VCOs and
Synthesizers
•
•
Lead Free Package
RF LO Frequency Range:
Super Heterodyne Architecture for Superior
Performance
–
2651 – 3150 MHz
•
Phase Noise 0.5 Degrees RMS Typical over
Channel BW
Internal PLL Reference Oscillator with Clock
Output for Base-Band ASICs
•
•
•
Reference Frequency: 40 or 44 MHz
Single 3.3-V Power Supply
•
•
Internal AGC and Power Control Function
IQ DC Offset Calibration Function and
IF = 374 MHz (Both Bands)
TBD PACKAGE
(TOP VIEW)
1
42
41
40
39
38
37
36
35
34
33
32
31
30
29
RFPD
PAPDA
PAPDB
ABSEL
V+RFLO
GND
GND
2
RXQP
RXQN
RXIP
3
4
5
RXIN
6
GND
7
LON
V+IFLO
STATUS
PE
8
LOP
9
GND
10
11
12
13
14
V+CP
TR
RSVD2
RFLOBP
RFLOTUN
RFLOCP
PAEN
RSVD1
IFLOBP
IFLOTUN
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2005–2006, Texas Instruments Incorporated
TRF2432
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SLWS177B–APRIL 2005–REVISED NOVEMBER 2006
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
DESCRIPTION
The TRF2432 is a fully integrated IQ transceiver specifically for use in 802.16 d/e applications. The TRF2432 is
designed to perform the IQ conversion at 374MHz IF as well as provide an RFLO and control logic to a TI RFFE
(Radio Frequency Front End). The TRF2432 uses a common IF frequency for both bands, which eliminates the
need for an additional IF filter in dual band applications. The TRF2432 has an internal IQ DC offset calibration
function for the receive IQ interface. Combined with a TI integrated RFFE, the TRF2432 completes the TI WLAN
two-chip radio.
The TRF2432 incorporates all of the system blocks from the modem to the RFFE except for the IF filtering and
the reference crystal. The ASIC uniquely incorporates an internal PLL reference oscillator where only a crystal is
needed, and also provides a clock output for base-band/MAC ASICs. TRF2432 includes two synthesizers with
VCOs, IQ modulator, IQ demodulator, anti aliasing filters, IF amplifiers, receive AGC circuit, transmit power
control and serial interface.
Functional Block Diagram
RX
RXAGC
AGC
CALEN
LPF
RXI
2
DC Offset
LPF
Calibration
RXQ
2
o
90
STATUS
XTALI
T/R
IF
Synth
T/R
IF
2
2
XTALO
CLKOUT
REFDIV
RF
Synth
2
LO
/2
PE
PAEN
RFPD
PWR
CTRL
PAPDA
PAPDB
SERIAL
TR
Serial
Dec.
3
A/B
Control
ABSEL
o
90
TXGC
TXQ
TX
GC
5
2
TXI
2
2
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SLWS177B–APRIL 2005–REVISED NOVEMBER 2006
DEVICE INFORMATION
Table 1. TERMINAL FUNCTIONS
TERMINAL
NO.
I/O
TYPE
DESCRIPTION
NAME
RFPD
1
O
O
O
O
I
Analog
Analog
Analog
Analog
Power
Analog
RF Dif.
RF Dif.
Analog
Power
-
RFFE sleep output
PAPDA
PAPDB
ABSEL
V+RFLO
GND
2
PA band A select to RFFE
PA band B select to RFFE
A or B band select to RFFE
+3.3V Power Supply. RF VCO bias
3
4
5
6
I
Connect to ground per suggested layout for normal operation
Positive going LO output
LON
7
O
O
I
LOP
8
Negative going LO output
GND
9
Connect to ground per suggested layout for normal operation
+3.3V Power Supply. Synthesizer Charge Pumps bias
Reserved. Leave open
V+CP
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
I
RSVD2
RFLOBP
RFLOTUN
RFLOCP
RSVD3
XTALO
V+D
-
O
I
Analog
Analog
Analog
-
Bypass Capacitor for LO1 (RF)
VCO Synthesizer 1 (RF) Tuning port
Synthesizer 1 (RF) Charge pump output
Reserved. Leave open
O
-
I/O
I
Analog
Power
Digital
Analog
Digital
Power
Digital
Digital
Digital
Negative crystal connection
+3.3V Power Supply. Digital Bias
CLKON
XTALBYP
CLKOP
V+CLK
CLK
O
O
O
I
Negative going reference clock output (40,44,20 or 22MHz)
Bypass Capacitor for crystal oscillator
Positive going reference clock output (40,44,20 or 22MHz)
+3.3V Power Supply. Reference Clock Bias
Clock line of 3-wire serial bus
I
DATA
I
Data line of 3-wire serial bus
EN
I
Load enable line of 3-wire serial bus
A transition high in RX active mode initiates DC offset calibration. Low disables
calibration circuit. Internal pull down
CALEN
25
I
Digital
XTALI
26
27
28
29
30
31
I/O
Analog
Analog
Digital
Analog
Analog
-
Positive crystal connection. Also input for external XO reference
Connect to ground per suggested layout for normal operation
Sets reference clock divider. Set HIGH to activate divide by 2. Internal pull down.
VCO Synthesizer 2 (IF) Tune port. CP2 Connected internally
Bypass Capacitor for LO2 (IF)
GND
I
I
REFDIV
IFLOTUN
IFLOBP
RSVD1
I
O
-
Reserved. Leave open.
PA enable. HIGH enables RFFE PA. Enables PAPDA or PAPDB. Internal pull
down.
PAEN
32
I
Digital
TR
33
34
35
36
37
38
39
40
41
42
43
I
I
Digital
Digital
Digital
Power
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Transmit or Receive control line. TX=HIGH, RX=LOW. Internal pull down.
Power enable. HIGH is enabled. Not defined internally.
RF, IF and REF synthesizer lock detect and calibration status.
+3.3V Power Supply. IF VCO bias
PE
STATUS
V+IFLO
GND
O
I
I
Connect to ground per suggested layout for normal operation
Receiver in-phase negative going output.
RXIN
RXIP
RXQN
RXQP
GND
O
O
O
O
I
Receiver in-phase positive going output.
Receiver quadrature negative going output.
Receiver quadrature positive going output.
Connect to ground per suggested layout for normal operation
Transmitter quadrature negative going output.
TXQN
I
3
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SLWS177B–APRIL 2005–REVISED NOVEMBER 2006
DEVICE INFORMATION (continued)
Table 1. TERMINAL FUNCTIONS (continued)
TERMINAL
NO.
I/O
TYPE
DESCRIPTION
NAME
TXQP
44
45
46
47
48
49
50
51
52
53
54
55
56
I
Analog
Analog
Analog
Analog
Digital
Digital
Digital
Digital
Digital
Analog
RF Dif.
RF Dif.
Power
Transmitter quadrature positive going output.
Transmitter in-phase negative going output.
TXIN
I
TXIP
I
Transmitter in-phase positive going output.
RXCMADJ
TXGC[4]
TXGC[3]
TXGC[2]
TXGC[1]
TXGC[0]
RXAGC
IFN
I
Connect resistor to ground to adjust common mode output voltage
I
TX Gain Control bit 4 (MSB). Logic LOW induces 16dB Atten. Internal pull down.
TX Gain Control bit 3. Logic LOW induces 8dB Atten. Internal pull down.
TX Gain Control bit 2. Logic LOW induces 4dB Atten. Internal pull down.
TX Gain Control bit 1. Logic LOW induces 2dB Atten. Internal pull down.
TX Gain Control bit 0 (LSB). logic LOW induces 1dB Atten. Internal pull down.
Receiver automatic gain control pin.
I
I
I
I
I
I/O
I/O
I
IF positive going input or output.
IFP
IF negative going input or output.
V+TR
+3.3V Power Supply. TX and RX IF amplifier bias.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)
UNIT
0 to 5.5 V
DC supply voltage, VCC
DC supply current, ICC
600 mA
RF input power
Any port and any mode
+10 dBm
Digital input voltage, VID
Analog input voltage, VIA
Junction temperature, TJC
Thermal resistance junction-to-case, θJC
Operating temperature, TA
Storage temperature, Tstg
Lead temperature
-0.3 V to VCC+0.3 V
0 to 3.6 V
125°C
25°C/W
-20°C to +85°C
-40°C to +105°C
+220°C
40 sec maximum
DC CHARACTERISTICS
PARAMETER
TEST CONDITIONS
MIN
TYP
3.3
100
90
MAX
3.6
125
110
85
UNIT
V
VCC
Supply votlage
Specification compliant
2.7
Transmit Mode Supply Current
Receive Mode Supply Current
Idle Mode Supply Current
Standby Mode Supply Current
Sleep Mode Supply Current
DC current, V+RFLO
TR = High, Active mode
TR = Low, Active mode
mA
mA
mA
mA
µA
70
10
15
10
VCC = 3.3 V, 0 < V+RFLO <
V+TR + 0.6V
Standby
Idle
0
0
Tx
11
11
Rx
4
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SLWS177B–APRIL 2005–REVISED NOVEMBER 2006
DC CHARACTERISTICS (continued)
PARAMETER
TEST CONDITIONS
MIN
TYP
0
MAX
UNIT
DC current, V+CP
V+TR - 0.6V < V+CP < V+TR +
0.6V
Standby
Idle
0.6
0.6
0.6
8.5
50/30
50/30
50/30
4
Tx
Rx
DC current, V+D
V+TR - 0.6V < V+D < V+TR +
0.6V
Standby
Idle
Tx
Rx
DC current, V+CLK
DC current, V+IFLO
DC current, V+TR
V+TR - 0.6V < V+CLK < V+TR + Standby
0.6V
Idle
4
Tx
Rx
4
4
0 < V+IFLO < V+TR + 0.6V
Standby
Idle
0
0
Tx
8.5
8.5
0.35
0.35
33/21
20
Rx
3.6 V max
Standby
Idle
Tx
Rx
RECEIVER CHARACTERISTICS
TA = 25°C and VCC = 3.3 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
MHz
dB
fIF
IF input frequency
374
71
Voltage gain
Gain control < 0.3 V
62
55
Analog Gain Control Range
Gain Control Sensitivity
Gain Control Linearity
Gain settling time
VAGC from .3 to 2.2V
Monotonic.
dB
-40
±3
-50
dB/V
From linear
Full range to within 0.5dB final gain
setting
0.25
µs
Output P-1dB
-7
dBm
Vppd
dB
Output 3rd order intercept point
Noise figure
4.8
7
From Full Gain to 40dB gain. Not to
increase more than 1dB per 1dB of
gain change thereafter.
IQ differential impedance
Output load impedance
Output swing
I, Q outputs (0-11MHz)
Single ended
100
1000
1.4
Ω
kΩ||pF
mVpd
dB
2||10
Input return loss
Measured into 200-Ω differential
9
Output common mode voltage
Adjustable by one resistor to
0.6
V
ground. Vcom = 0.56 + 0.48 × RADJ
RADJ is kΩ
,
I/Q gain mismatch
0 to 11 MHz band
0.1
0.9
0.5
3
dB
°
I/Q phase imbalance
I/Q differential DC offset
0 to 11 MHz band
After calibration. Min Gain
Before calibration
10
50
mV
mV
µs
DC offset calibration time
With 40 MHz reference. See
calibration instructions
32
5
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SLWS177B–APRIL 2005–REVISED NOVEMBER 2006
RECEIVER CHARACTERISTICS (continued)
TA = 25°C and VCC = 3.3 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
25
1
MAX
UNIT
dB
LPF attenuation
25 MHz
20
10.55 MHz
dB
TRANMITTER CHARACTERISTICS
TR = High, 2dB base band filter loss in RX band, MIN, TYP, and MAX rating are at 25°C and VCC = 3.3 V (unless otherwise
noted)
PARAMETER
Differential input impedance
Common-mode input voltage
Input voltage
TEST CONDITIONS
I, Q inputs. (0 – 11MHz)
Effected by V+. TRF2432
I, Q inputs, differential.
MIN
10
TYP
MAX
UNIT
kΩ
ZID
VIC
VI
1.1
2.1
V
0.3
374
5
Vpd
MHz
dB
fIF
IF input frequency
Voltage gain
TX Gain Control Word} = {11111}(1)
,
3
200-Ω differential output
Gain control range
Gain step size
31
1
dB
dB
Per bit
Sideband suppression
IFLO leakage
0 to 11 MHz band
25
2
30
-40
dB
Max. gain settings. TX IQ DC offset
< 1 mV
-35
dBm
Output 1dB compression
Output noise
Maximum gain setting
4
dBm
Maximum Gain. Decreasing 1dB per
dB attenuation until 15 dB
-137
-131 dBm/Hz
16 to 31dB down from max gain.
-145
-144 dBm/Hz
(1) Gain is referenced to the amplitude of either the I or Q signal, when they are in quadrature. i.e. For I = 0.5 × sin (wmt) and Q = 0.5 ×cos
(wmt) input in differential volts. The output at a gain of 0dB would ideally be a single tone at 0.5V differential across the 200-Ω outputs.
COMMON ELECTRICAL CHARACTERISTICS
MIN, TYP, and MAX ratings are at 25°C and VCC = 3.3 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
IF IO differential impedance
200
Ω
SYNTHESIZER CHARACTERISTICS
RF SYNTHESIZER CHARACTERISTICS
PARAMETER
Frequency range
Tuning step
TEST CONDITIONS
MIN
TYP
MAX
UNIT
MHz
kHz
µs
2536
3150
250
60
Settling time
±10kHz of final frequency. From
Standby to Idle measured from
enable
Phase noise (VCO)
4.5 MHz offset
-130
-143
0.6
dBc/Hz
dBc/Hz
°rms
20 MHz offset
Integrated phase error
Spurious suppression
10 kHz to 10 MHz
0.25 < ∆f < 3 MHz offset
> 3 MHz offset
-45-7∆f
-70
dBc
dBc
Power output
Into 100 Ω differential. With
-2
0
dBm
matching
6
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SLWS177B–APRIL 2005–REVISED NOVEMBER 2006
INTEGER MODE IF SYNTHESIZER CHARACTERISTICS
fREF = 44 MHz
PARAMETER
Frequency
TEST CONDITIONS
With 44 MHz crystal
MIN
TYP
374
60
MAX
UNIT
MHz
µs
Settling time
±10kHz of final frequency. From
Standby to Idle measured from
enable
Integrated phase error
Spurious suppression
10 kHz to 10 MHz
> 3 MHz offset
0.2
-70
°rms
dBc
FRACTIONAL MODE IF SYNTHESIZER CHARACTERISTICS
fREF = 40 MHz
PARAMETER
Frequency
TEST CONDITIONS
With 44 MHz crystal
MIN
TYP
374
60
MAX
UNIT
MHz
µs
Settling time
±10kHz of final frequency. From
Standby to Idle measured from
enable
Integrated phase error
Spurious suppression
10 kHz to 10 MHz
0.25 < ∆f < 3 MHz offset
> 3 MHz offset
0.1
-45-7∆f
-70
°rms
dBc
dBc
PLL REFERENCE/CLOCK OUTPUT CHARACTERISTICS
The TRF2432 synthesizers operate from a single 40 or 44 MHz reference. The TRF2432 can generate its own
PLL reference using an internal oscillator or it may also be driven from an external reference. The TRF2432
provides a user selectable, buffered clock output for base-band ASICs.
PLL REFERENCE OSCILLATOR SPECIFICATIONS
PARAMETER
Reference frequency
Start-up time
TEST CONDITIONS
MIN
TYP
40 or 44
0.5
MAX
UNIT
MHz
ms
fREF
From power on. Depends on Crystal
characteristics
Degradation to Crystal Reference
Accuracy
From crystal series resonance.
0.25
PPM
Jitter
5
1
10
2
ps
Vpp
External XO drive
Equivalent input load
Square-wave, must be AC Coupled
Single ended
0.8
500||10
Ω||pF
RECOMMENDED CRYSTAL SPECIFICATIONS
PARAMETER
Frequency
TEST CONDITIONS
MIN
TYP
MAX
UNIT
f
Series resonant, fundamental or 3rd
overtone
40 or 44
MHz
ESR
C
Effective series resistance
Shunt capacitance
100
20
Ω
pF
Maximum power handling
Frequency accuracy
50
µW
PPM
Over Temperature and Process
20
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CLOCK OUTPUT CHARACTERISTICS
PARAMETER
TEST CONDITIONS
REFDIV = 1
MIN
TYP
fREF/2
fREF
1
MAX
UNIT
MHz
MHz
Vppd
fCLK
Clock output frequency
REFDIV = 0
Differential
Output voltage swing
Duty cycle
0.4
DC
tr
50%
Rise time
3
3
8
ns
ns
pF
tf
Fall time
CL
Capacitance load
Per side
DIGITAL INTERFACE CHARACTERISTICS
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
0.5
UNIT
VIH
VIL
High-level input voltage
Low-level input voltage
High-level output voltage
Low-level output voltage
1.7
V
V
V
V
VOH
VOL
100-µA load current
-100-µA load current
2
0.2
SERIAL INTERFACE TIMING REQUIREMENTS
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Power Enable to Serial port on
From Sleep mode to standby mode.
PE High transition.
0.5
µs
Enable clock
Time to activate the serial port to
receive clocked and data.
10
ns
Hold time, data to clock
Setup time, data to clock
Clock low duration
10
10
10
10
10
10
ns
ns
ns
ns
ns
ns
Clock high duration
Setup time, clock to enable
Enable time
Should be held high when not
programming
CH
CLK
...
...
CD
CL
DC
DATA
D15
D14
D13
D0
CE
EH
EN
EN
PE
...
...
ON
Figure 1. Serial Interface Timing Diagram
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SERIAL REGISTERS
Data is written to the registers per the following format:
Table 2. Serial Interface Data Format
REGISTERS
ADDRESS
(MSB) 1st BIT IN
LAST BIT IN (LSB)
#
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
1
GCX TX_H REF_ FN_IF
X
A/B
PS1
PS0
1
1
0
1
1
0
1
0
P
S
2
CP
S_INV REF_ GC4
M
GC3
GC2
GC1
GC0
1
1
0
1
1
1
1
1
3
4
5
6
7
P
X
MR6
FI6
MR5
FI5
MR4
FI4
MR3
FI3
MR2
FI2
MR1
FI1
MR0
FI0
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
0
0
0
1
0
0
0
1
0
1
0
1
1
0
X
MI6
DI3
MI5
DI2
MI4
DI1
MI3
DI0
MI2
SI2
MI1
SI1
MI0
SI0
DI4
XO_L FR6
P
FR5
FR4
FR3
FR2
FR1
FR0
8
DR4
DR3
DR2
DR1
DR0
SR2
SR1
SR0
1
1
0
1
1
1
1
0
Table 3. Serial Register Definitions
NAME
Power mode
SYMBOL
# OF
BITS
DEFAULTS(1)
DESCRIPTION
PS
2
0
Determines mode of operation: Standby, Idle, or Active.
(see Table 17)
Band A or B select
TX gain control
A/B
GC
1
5
0
Selects TX and RX band. 1 = A band and 0 = B Band
[x,x,x,x,x]
Controls gain setting of TX if CGX=0 (see below). {11111}
is max gain and {00000} is minimum gain.
Spectral inversion
S_INV
1
1
Sets both the TX I/Q modulator and RX I/Q demodulator
for spectral inversion. S_INV = 1 for spectral inversion.
S_INV = 0 for no inversion.
Crystal pre-scalar
RF PLL frequency
P
DR
SR
FR
MR
DI
1
5
3
7
7
5
3
7
7
1
1
Sets the crystal or reference pre-scalar divider.
[0,1,0,1,0] = 10 Registers used to program the RF synthesizer operation
frequency.
[0,0,0] = 0
[0,1,1,0,0,0,0]=48
[1,0,0,1,1,1,1]=79
IF PLL frequency
X
X
X
X
1
Registers used to program the IF synthesizer operation
frequency. These registers are only effective, when the IF
synthesizer is in fractional-N mode (i.e. FN_IF=1)
SI
FI
MI
TX gain control MUX
GCX
GCX=0 switches the Tx gain control to the serial port.
GCX=1 switches the Tx gain control to the parallel input
pins.
Fractional N IF synthesizer
FN_IF
1
0
FN_IF =1 enables the fractional N IF synthesizer FN = 0
sets the IF synthesizer to a fixed frequency
REF_S
REF_M
REF_S
REF_M
CP
1
1
1
0
0
0
Always set REF_S = 0
Always set REF_M = 0
Charge Pump Current
Setting
CP = 1 puts charge pump for reference and fixed
synthesizers into continuous current mode. CP = 0 puts
synthesizers into current saving mode.
XO low power mode
XO_LP
1
1
XO_LP =1 puts crystal oscillator in low power mode.
XO_LP = 0 puts the crystal oscillator full-power mode for
better noise performance, and start-up time.
(1) Default values are the initial values after power up or after PE goes HIGH. “x” indicates undefined.
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Table 3. Serial Register Definitions (continued)
NAME
SYMBOL
# OF
BITS
DEFAULTS(1)
DESCRIPTION
Fractional N IF synthesizer
FN_IF
1
0
FN_IF =1 enables the fractional N IF synthesizer when in
idle or active mode. FN = 0 sets the IF synthesizer to a
fixed frequency (374 MHz with 44 MHz crystal) for low
power consumption.
TX output buffer high power
TX_HP
1
0
TX_HP = 1 puts IF amplifier in high linearity mode. TX_HP
= 0 puts the IF amplifier into normal linearity mode to save
current. This does not change linearity of the RFFE.
MODES OF OPERATION
Power Modes
Active Mode
−Tx or RX on depending on
TR setting
−VCOs on
−PA on if PAEN=HIGH and
TR=HIGH
− Can calibrate Rx DC I&Q offset
if TR=LOW
Serial CMD
Serial CMD
Standby Mode
− Crystal oscilator on
− REFOUT buffer on at
crystal frequency only.
− All registers active
− SERIAL port is active.
Idle Mode
Serial CMD
Standby Mode +
− RF/IF VCOs on
PE=
PE=
Sleep Mode
Power Off
Vcc=0V
Power On
& PE=LOW
Figure 2. Power Modes
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MODES OF OPERATION (continued)
Table 4. Power Mode Desriptions
MODE
PS1
1
PS0
RFFE
TX
RX
IF PLL
RF
PLL
CLK
OUT
XO
SERIA
L
COMMENTS
TR_SEL controls
Transmit/Receive mode
Register settings retained
Register settings retained
Active
Idle
1
X
X
X
X
X
X
X
X
X
0
1
0
X
X
X
X
X
X
X
Standb
y
Sleep
Settings not required
Input/Output Modes
The TRF2432 is designed to control power and band status for a TI RFFE. The TRF2432 is designed to drive
external P-MOSFETs to power up and down the appropriate sections of the RFFE. Table 4 lists the various
modes of the TRF2432 and the input parameters required to enter each mode. The corresponding outputs to the
RFFE are also described. Figure 4 illustrates the power control interface and recommended P-MOSFET circuit.
Table 5. Inputs/Outputs and Operational States
OPERATION
STATE
INPUT PARAMETERS
OUTPUT DRIVERS
INTERNAL FUNCTIONS
PINS
PAEN
REGISTERS
PS0
PE
TR
CALEN
PS1
A/B
PAPDA PAPDB
RFPD
ABSEL
TX
RX
SYNTH CRYST SERIAL
ESIZER
S
AL
OSC.
AND
DRIVE
R
BUS
Sleep mode
Standby mode
Idle mode
Low
High
High
High
X
X
X
X
X
X
X
X
X
X
X
X
0
1
X
0
1
1
X
X
X
X
High
High
High
High
High
High
High
High
High
High
High
Low
Low
Low
Low
Off
Off
Off
Off
Off
Off
Off
Off
Off
On
On
On
Off
On
On
On
X
Enabled
Active mode (PA
disabled)
Low
=(A/B) Enabled Enabled Enabled
Active mode (RX
A band)
High
High
High
High
High
Low
High
Low
High
Low
Low
High
Low
High
Low
X
X
X
X
1
1
1
1
1
1
1
1
1
1
1
1
0
0
X
High
Low
High
High
High
High
High
High
Low
High
Low
Low
High
High
Low
Off
On
Off
On
Off
On
Off
On
Off
On
Enabled
Enabled
Enabled
Enabled
Enabled
On
On
On
On
On
On
On
On
On
On
Active mode (TX
A band)
Active mode (RX
B band)
Low
Active mode (TX
B band)
Low
Low
Active mode
(RX-Cal.)
Rising
Edge
High(1)
=(A/B)
(1) Held in open state until calibration is complete or disabled (CAL_EN = High -> Low).
SYNTHESIZER PROGRAMMING
The RF synthesizer frequency is programmed with four bytes: DR, SR, FR and MR and the crystal pre-scalar: P.
See digital interface characteristics for programming instructions). The RF PLL locking frequency is calculated
as follows:
fRCF
(P ) 1)
FR
(MR ) 1)
ƪ8 (DR ) 3) * SR *
ƫ
fRFLO
+
(1)
fREF is the crystal reference frequency. On power-up the default register values (P=1, DR=10, SR=0, FR=48 and
MR=79) with a 40-MHz crystal will attempt to lock the RFLO to 2068 MHz. The valid register ranges are listed
below.
Table 6. Valid RF Register Ranges
REGISTER
MIN
7
MAX
31
DR
SR
0
7
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Table 6. Valid RF Register Ranges (continued)
REGISTER
FR
MIN
0
MAX
MR
MR
32
127
The IF frequency synthesizer defaults to integer mode (FN_IF =0) to operate from a 44 MHz reference and is
preset for 374 MHz IF. When using a 40 MHz reference, the synthesizer must be set to fractional mode (FN_IF
=1) and programmed. The synthesizer is programmed with four bytes DI, SI, FI and MI. The register
programming values for the IF synthesizer when using a 40 MHz reference are listed in Table 21.
Table 7. IF Register Values for 40-MHz Reference
REGISTER
VALUE
DI
SI
FI
16
2
32
79
MI
RFFE POWER CONTROL INTERFACE
The TRF2432 will control the RFFE power for all radio operational modes through three external P-MOSFETs.
The suggested circuit is illustrated in Figure 4.
+3.3V
IQ
XCVR
RFFE
Figure 3.
IQ DC Calibration
The TRF2432 receiver has an IQ DC offset calibration function. This operation can be performed in receiver
active mode only. The calibration process is entered by a rising edge on CALEN, which remains high as long as
the calibration is required. The calibration procedure is as follows:
1. Set to RX active mode
2. Wait for RF and IF Synthesizers to lock: STATUS=HIGH
3. Set Rx AGC to min gain
4. Set CALEN=HIGH to enter calibration mode:
a. IQ Transceiver turns off RFFE
b. Internal calibration process runs
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c. The Status bit is low during calibration procedure and returns high once the calibration is complete
5. Hold CALEN HIGH to maintain calibration
6. Return to RX active Mode
Notes on Calibration:
1. Calibration is retained as long as CALEN=HIGH and the RF2432 is not put into Sleep Mode.
2. To Reset calibration, set CALEN=LOW.
3. If CALEN is held LOW then calibration circuit is completely disabled, and does not contribute to any DC
offset.
IQ DC Calibration Timing
Table 8. Calibration Timing Requirements
PARAMETER
Calibration reset
Status low
TEST CONDITIONS
MIN
TYP
MAX
UNIT
µs
4
1
µs
Calibration time
1 tick = 44/fREF (e.g., fREF = 44 MHz,
tick = 1 µs)
68
tick
tCAL
STATUS
CALEN
tSL
t RS
Figure 4. Calibration Timing
TYPICAL CHARACTERISTICS
80
70
60
50
40
30
20
10
+25 C
+85 C
0 C
−30 C
0
0
0.5
1
1.5
2
2.5
Rx Gain vs. Temperature
VAGC(V)
Figure 5. RX Gain Control vs Temperature
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TYPICAL CHARACTERISTICS (continued)
50
45
40
35
30
V+=3.6V
V+=3.0V
V+=2.7V
500
1000
1500
2000
2500
Common Mode Voltage(mV)
Note: Output set for 1000 mVpp total swing.
Input −40 dBm/tone.
Rx Output IM vs. Common Mode Voltage
Figure 6. RX Intermod Level vs Common-Mode Votlage
55
50
45
40
35
30
25
500mVpp
1000mVpp
1500mVpp
500
1000
1500
2000
Rx Common Mode Voltage(mV)
Rx IM vs. Output Voltage Swing (V+=3.0V)
Figure 7. RX Intermod. Level vs Output Voltage Swing
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TYPICAL CHARACTERISTICS (continued)
3.0
2.0
1.0
0.0
3.6V
3.3V
3.0V
2.7V
−1.0
−2.0
−3.0
0.8
1
1.2
1.4
1.6
1.8
2
2.2
2.4
2.6
2.8
3
Vcm (V)
Tx OP1dB vs Vcm and V+
Figure 8. TX OP1dB vs Common-Mode Input Votlage
RF SYNTHESIZER PERFORMANCE
Figure 9. RFLO Phase Noise
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RF SYNTHESIZER PERFORMANCE (continued)
3400
3300
3200
3100
3000
2900
2800
2700
2600
2500
2400
2300
2200
+85 C
+25 C
0 C
−30 C
0.60
0.80
1.00
1.20
1.40
1.60
1.80
2.00
2.20
2.40
2.60
2.80
3.00
Vtune(V)
RC2432 RFLO Tuning vs Temperature
Figure 10. RF VCO Tuning Curves vs Voltages
3100
3000
2900
2800
2700
2600
2500
2400
2300
2200
2100
3.6V
3.3V
3.0V
2.7V
0.60
0.80
1.00
1.20
1.40
1.60
1.80
2.00
2.20
Vtune(V)
RC2432 RFLO Tuning vs V+
Figure 11. RF VCO Tuning Curves vs Temperature
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RF SYNTHESIZER PERFORMANCE (continued)
900
800
700
600
500
400
300
3.6V
3.3V
3.0V
2.7V
0.60
0.80
1.00
1.20
1.40
1.60
1.80
2.00
2.20
RC2432 RFLO Tuning Sensitivity vs V+
Vtune(V)
Figure 12. RF VCO Tuning Sensitivity vs VCC
1000
900
800
700
600
500
400
300
200
+85 C
+25 C
0 C
−30 C
0.60
0.80
1.00
1.20
1.40
1.60
1.80
2.00
2.20
2.40
2.60
2.80
3.00
RC2432 RFLO Tuning Sensitivity vs Temperature
Vtune(V)
Figure 13. RFLO Tuning Sensitivity vs Temperture
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IF SYNTHESIZER PERFORMANCE
Figure 14. IF Synthesizer Phase Noise
450
400
350
300
250
+85 C
+25 C
0 C
−30 C
0.60
0.80
1.00
1.20
1.40
1.60
1.80
2.00
2.20
2.40
2.60
2.80
3.00
IFLO Tuning vs Temperature
Vtune(V)
Figure 15. IFLO Tuning Curves vs Temperature
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IF SYNTHESIZER PERFORMANCE (continued)
120
110
100
90
+85 C
+25 C
0 C
−30 C
80
70
60
50
40
0.60
0.80
1.00
1.20
1.40
1.60
1.80
2.00
2.20
2.40
2.60
2.80
3.00
Vtune(V)
IFLO Tuning Sensitivity vs Temperature
Figure 16. IFLO Tuning Sensitivity vs Temperature
Figure 17. Reference Clock Differential Output
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APPLICATION INFORMATION
Figure 18. Package Dimensions
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APPLICATION INFORMATION (continued)
W2
P
W1
D1
D2
Feed Direction
Tape and Reel specifications defined per EIA−481−1A and EIA−481−2A.
Parts
per Reel
3500
Pitch P
(mm)
12
Tape Width
W1 (mm)
16
Reel Size
D (Inches)
13
Reel Width
W2 (mm)
Hub Dia.
D2 (mm)
Package Description
8mm x 8mm LPCC56 Pin
22.2
102
Figure 19. Tape and Reel Specifications
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PACKAGE OPTION ADDENDUM
www.ti.com
5-Feb-2007
PACKAGING INFORMATION
Orderable Device
TRF2432IRTQR
TRF2432IRTQRG3
TRF2432IRTQT
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
QFN
RTQ
56
56
56
56
2500 Green (RoHS &
no Sb/Br)
CU SN
CU SN
CU SN
CU SN
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
QFN
QFN
QFN
RTQ
RTQ
RTQ
2500 Green (RoHS &
no Sb/Br)
250 Green (RoHS &
no Sb/Br)
TRF2432IRTQTG3
250 Green (RoHS &
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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