TRF3750 [TI]
HIGH-PERFORMANCE INTEGER-N PLL FREQUENCY SYNTHESIZER; 高性能整数N分频PLL频率合成器
| 型号： | TRF3750 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | HIGH-PERFORMANCE INTEGER-N PLL FREQUENCY SYNTHESIZER |
| 文件： | 总32页 (文件大小：558K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TRF3750
www.ti.com
SLWS146A − MARCH 2004 − REVISED NOVEMBER 2004
HIGH-PERFORMANCE INTEGER-N PLL FREQUENCY SYNTHESIZER
and a 13-bit B counter. The R divider allows the user to
FEATURES
select the frequency of choice for the phase-frequency
detector (PFD) circuit, and with the use of the counters
implement an N divider of value N = A + P x B. With an
extended charge-pump supply (VCP) of up to 8 V, a wide
variety of external VCOs can be used to complete the
phase-locked loop. Ultra-low phase noise and reference
spur performance make the TRF3750 ideal for generating
the local oscillator in the most demanding wireless
applications.
D
D
D
D
Single Device Covers Frequencies Up to
2.4 GHz
Dual Supply Range: 3 V − 3.6 V and
4.5 V − 5.5 V
Separate Charge Pump Supply (V ) Up
CP
to 8 V
Simple 3-Wire Serial Interface Allows for Fully
Programmable:
− A, B, and R Counters
− Dual Modulus Prescaler [8/9, 16/17, 32/33,
and 64/65]
− Charge Pump Current
PW PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
RSET
CPOUT
CPGND
AGND
RFIN
RFIN
AVDD
REFIN
VCP
DVDD
MUXOUT
LE
DATA
CLOCK
CE
D
D
D
Lock Detect Output (Digital and Analog)
Versatile Hardware and Software Power Down
Packaged in a 16-Pin TSSOP Thin Quad
FlatPack and a 20-Pin 4 x 4 mm QFN Package
DGND
APPLICATIONS
D
Wireless Infrastructure
− GSM, IS136, EDGE/UWC−136
− IS95, UMTS, CDMA2000
RGP PACKAGE
(TOP VIEW)
D
D
D
D
Portable Wireless Communications
Wireless LAN
Wireless Transceivers
20 19 18 17 16
1
2
3
CPGND
MUXOUT
15
Communication Test Equipment
14
13
AGND
AGND
RFIN
LE
DESCRIPTION
DATA
CLOCK
CE
4
5
12
11
The TRF3750 frequency synthesizer is ideal for designing
the local os cillator portion of wireless transceivers by
providing complete programmability and ultra-low phase
noise. The device features a user-selectable dual-
modulus prescaler, a 14-bit reference (R) divider, a 6-bit A,
RFIN
6
7
8
9
10
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Products
conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters.
Copyright 2004, Texas Instruments Incorporated
TRF3750
www.ti.com
SLWS146A − MARCH 2004 − REVISED NOVEMBER 2004
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate
precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
FUNCTIONAL BLOCK DIAGRAM FOR TSSOP PACKAGE
DVDD
AVDD
VCP
15
7
16
Bias
PFD
1
2
RSET
14-Bit R
Counter
8
Charge
Pump
REFIN
CPOUT
14
11
12
13
CLOCK
DATA
LE
Current
Setting 1
Current
Setting 2
24-Bit Data
Shift Register
R Counter
Latch
22
Power
Down
Function
Latch
10
CE
22
N Counter
Latch
22
Lock
Detect
Initialization
Latch
22
19
N Divider
6
13
6-Bit
A Counter
13-Bit
B Counter
6
5
RFIN
RFIN
Prescaler
P/P+1
LD
LD
MUX
14
MUXOUT
DVDD
4
9
3
CPGND
AGND
DGND
2
TRF3750
www.ti.com
SLWS146A − MARCH 2004 − REVISED NOVEMBER 2004
ORDERING INFORMATION
SPECIFIED
PACKAGE
PACKAGE /
LEADS
PACKAGE
DESIGNATOR
ORDERING
NUMBER
TRANSPORT
MEDIA
TEMPERATURE
PRODUCT
QUANTITY
MARKING
RANGE
TRF3750IPW
TRF3750IPWR
TRF3750IRGP
TRF3750IRGPR
TSSOP-16
TSSOP-16
QFN-20
PW
PW
–40°C to 85°C
–40°C to 85°C
–40°C to 85°C
–40°C to 85°C
TRF3750
TRF3750
TRF3750
TRF3750
TRF3750IPW
TRF3750IPWR
TRF3750IRGP
TRF3750IRGPR
Tube
Reel
Tube
Reel
90
2000
91
RGP
RGP
QFN-20
1000
PIN ASSIGNMENTS
TERMINAL
(1)
TYPE
DESCRIPTION
The user needs to place an external resistor (R ) from this pin to ground to control the
NAME
QFN
NO.
TSSOP
NO.
R
19
1
O
SET
SET
maximum charge pump current. This node’s output voltage is typically around 1 V and the
relationship between I max and R is:
CPOUT
SET
23.5
RSET
I
+
CPOUTmax
A 4.7-kΩ resistor placed at this pin to ground would hence provide a maximum charge pump
output current of approximately 5 mA.
CPOUT
20
2
O
Charge pump output. This node provides the charge pump current that ultimately controls the
external VCO.
CPGND
AGND
RFIN
1
23
4
3
4
5
I
I
I
Charge pump ground
Analog ground
Complementary input to the prescaler. For single-ended applications, bypass with a small
capacitor to ground (typically 100 pF).
RFIN
5
6
7
I
I
Input to the prescaler. To complete the PLL, this signal must come from the output of the
external VCO.
AVDD
6, 7
Analog power supply. There are two possible supply ranges: 3 V − 3.6 V and 4.5 V − 5.5 V.
This value should be the same as the DVDD. Appropriate decoupling is necessary for optimal
performance.
REFIN
8
8
I
Reference frequency input. This externally provided reference gets divided by the selectable R
divider, and is used to synthesize the desired output frequency. Typically this input is an
ac-coupled sinusoid; however, a TTL or CMOS signal can also be used.
DGND
CE
9, 10
11
9
I
I
Digital ground
10
Chip enable. Setting this pin low puts the device into power down; setting it high activates the
charge pump if the software controlled power down is also disabled.
CLOCK
DATA
12
13
14
15
11
12
13
14
I
I
Serial clock input. This is the input that is used to clock the serial data into the 24-bit shift
register of the device. The data is read at the rising edge of this clock.
Serial data input. This is the data stream that contains the data to be loaded into the shift
register. The data is loaded MSB first.
LE
I
Load enable. When this asynchronous signal is asserted high, the data existing in the shift
register get loaded onto the selected latch.
MUXOUT
O
This user-selectable output can be controlled to provide the digital or analog lock detect
signals, the divide by N RF signal or the divide by R reference. The output can also be
3-stated.
DVDD
VCP
16, 17
18
15
16
I
I
Digital power supply. There are two possible supply ranges: 3 V − 3.6 V and 4.5 V − 5.5 V. This
value should be the same as the AVDD. Appropriate decoupling is necessary for optimal
performance.
Charge pump supply. This supply must be at least 1 V greater than the AVDD and DVDD and
can be as high as 8 V, accommodating a large range of possible VCOs.
(1)
The thermal pad on the bottom of the QFN package may be tied to ground, but is not required to meet specified performance.
3
TRF3750
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SLWS146A − MARCH 2004 − REVISED NOVEMBER 2004
ABSOLUTE MAXIMUM RATINGS
(1)
over operating free-air temperature range unless otherwise noted
UNIT
AVDD
−0.3 V to 6.5 V
−0.3 V to 0.3 V
(2)
AVDD to DVDD
VCP to AGND
Supply voltage range
−0.3 V to 9 V
Digital I/O voltage to DGND (DGND = 0 V)
−0.3 V to 6.5 V
Reference signal input
RF prescaler input
REFIN to DGND
−0.3 V to DVDD + 0.3 V
−0.3 V to 6.5 V
RFIN, RFIN to AGND
Continuous power dissipation
Storage temperature, T
See Dissipation Rating Table
−65°C to 150°C
260°C
Stg
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds
(1)
(2)
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values are with respect to network ground terminal.
DISSIPATION RATING TABLE
(1)
DERATING FACTOR
T = 85°C
POWER RATING
A
PACKAGE
T ≤ 25°C
A
ABOVE T = 25°C
A
16-pin TSSOP
20-pin QFN
2780 mW
2780 mW
22.2 mW/_C
29 mW/_C
1440 mW
1440 mW
(1)
This is the inverse of the junction-to-ambient thermal resistance when board mounted and with no airflow.
RECOMMENDED OPERATING CONDITIONS
MIN NOM
MAX
3.6
5.5
8
UNIT
V
AVDD = DVDD, 3.3 V range
3
4.5
3.3
5
AVDD = DVDD, 5 V range
VCP
V
Supply voltage
(AVDD, DVDD) + 1
0.8 x DVDD
V
High−level input voltage, V
V
IH
LE, DATA, CLK, CE
MUXOUT
Low−level input voltage, V
0.2 x DVDD
V
IL
High−level output voltage, V
DVDD − 0.4
−40
V
OH
OL
Low−level output voltage, V
0.4
85
V
Operating free-air temperature, T
°C
A
4
TRF3750
www.ti.com
SLWS146A − MARCH 2004 − REVISED NOVEMBER 2004
ELECTRICAL CHARACTERISTICS
Conditions: (AVDD = DVDD = 3.3 V or 5 V, AVDD + 1≤ VCP ≤ 8 V, R
otherwise stated)
= 4.7 kΩ, T = −40°C to 85°C, REFIN = 10 MHz at +5 dBm) (unless
SET
A
PARAMETER
TEST CONDITIONS
MIN
TYP
10
MAX
UNIT
AVDD = 3.3 V
AVDD = 5 V
DVDD = 3.3 V
DVDD = 5 V
VCP = 7 V
I
Supply current
Supply current
mA
AVDD
13
3
I
I
mA
DVDD
3.5
7.5
Supply current
mA
MHz
dBm
MHz
MHz
dBm
pF
VCP
RFIN input frequency (RF input)
RFIN input power level
2400
+5
−15
(1)
RF prescaler output frequency
REFIN input frequency (reference input)
REFIN input power level sensitivity
REFIN input capacitance
200
350
(1)
4
−10
5
(1)
PFD maximum frequency
60
MHz
mA
I
I
max Charge pump max source current
min Charge pump max sink current
5
CPOUT
−5
mA
CPOUT
Measured at the output of the
external loop filter, in locked
condition
(2)
VTUNE
Output tuning voltage
1
VCP−1.1
V
(1)
(2)
Assured by design.
VTUNE range shown is for optimal spurious performance; the device can function beyond these limits.
5
TRF3750
www.ti.com
SLWS146A − MARCH 2004 − REVISED NOVEMBER 2004
ELECTRICAL CHARACTERISTICS
Conditions (unless otherwise stated): AVDD = DVDD = 3.3 V or 5 V, VCP = 7 V; R
= 4.7 kΩ, T = 27°C, REFIN = 10 MHz at 6.5 dBm
A
SET
Referenced to 50 Ω, I max = 5 mA, Power Down: Normal Operation; Timer Counter Control: Not used; MUXOUT Control: 3-state; Fast
CPOUT
Lock Mode: Disabled, PFD Polarity: Positive, Anti-backlash Pulse width: 1.5 ns, Resync/Delay: Normal (Delay=0, Resync=0), Counter
Operation: Normal, Charge Pump Output: Normal, Lock Detect Precision: 5 cycles
PARAMETER
Phase noise 110 MHz)
TEST CONDITIONS
MIN
TYP MAX
UNIT
PFD = 200 kHz, Loop Loop BW = 20 kHz,
N =550, Phase noise measured at 1-kHz offset
spurs measured at PFD, 2 x PFD
−106
dBc/Hz
Reference spurs 110 MHz
−110
−99
dBc
dBc/Hz
dBc
PFD = 200 kHz, Loop Loop BW = 20 kHz,
N =1500, Phase noise measured at 1-kHz
offset spurs measured at PFD, 2 x PFD
Phase noise 300 MHz
Reference spurs 300 MHz
−110
−94
PFD = 200 kHz, Loop Loop BW = 20 kHz,
N = 2700, Phase noise measured at 1-kHz
offset spurs measured at PFD, 2 x PFD
Phase noise 540 MHz
dBc/Hz
dBc
Reference spurs 540 MHz
−90
PFD = 200 kHz, Loop Loop BW = 20 kHz,
N = 4180, Phase noise measured at 1-kHz
offset spurs measured at PFD, 2 x PFD
Phase noise 836 MHz
−91
dBc/Hz
dBc
Reference spurs 836 MHz
−100
−91
PFD = 200 kHz, Loop Loop BW = 20 kHz,
N = 4500, Phase noise measured at 1−kHz
offset spurs measured at PFD, 2 x PFD
Phase noise 900 MHz
dBc/Hz
Phase noise 900 MHz, over temperature and supply
Reference spurs 900 MHz
−90
PFD = 200 kHz, Loop Loop BW = 20 kHz,
N = 4500, Phase noise measured at 1-kHz
offset spurs measured at PFD, 2 x PFD
−100
−100
dBc
dBc
Reference spurs 900 MHz, over temperature and supply
PFD = 200 kHz, Loop Loop BW = 20 kHz,
N = 8750
Phase noise measured at 1-kHz offset spurs
Phase noise 1750 MHz
−84
−96
dBc/Hz
dBc
Reference spurs 1750 MHz
measured at PFD, 2 x PFD
PFD = 200 kHz, Loop Loop BW = 20 kHz,
N = 9800, Phase noise measured at 1-kHz
offset spurs measured at PFD, 2 x PFD
Phase noise 1960 MHz
−84
−82
−90
−90
−83
−90
dBc/Hz
Phase noise 1960 MHz, over temperature and supply
Reference spurs 1960 MHz
PFD = 200 kHz, Loop Loop BW = 20 kHz,
N = 9800, Phase noise measured at 1-kHz
offset spurs measured at PFD, 2 x PFD
dBc
dBc
Reference spurs 1960 MHz, over temperature and supply
Phase noise 2200 MHz
PFD = 200 kHz, Loop Loop BW = 20 kHz,
N = 11000, Phase noise measured at 1-kHz
offset spurs measured at PFD, 2 x PFD
dBc/Hz
dBc
Reference spurs 2200 MHz
6
TRF3750
www.ti.com
SLWS146A − MARCH 2004 − REVISED NOVEMBER 2004
PRODUCT TIMING CHARACTERISTICS
AVDD = DVDD = 3.3 V 10% or 5 V 10% , T = −40°C to 85°C (unless otherwise stated)
A
PARAMETER
(1)
TEST CONDITIONS
MIN
50
TYP
MAX
UNIT
ns
t
t
t
t
t
Clock period
(CLK)
su1
h
(2)
Data setup time
10
ns
(2)
Data hold time
LE pulse width
10
ns
(2)
(2)
20
ns
w
LE setup time
10
ns
su2
(1)
Production tested.
Assured by design.
(2)
t
(CLK)
CLOCK
t
su1
t
h
DATA
LE
DB20 (MSB)
DB19
DB2
DB1
DB0 (LSB)
t
w
t
su2
Figure 1. Serial Programming Timing Diagram
7
TRF3750
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SLWS146A − MARCH 2004 − REVISED NOVEMBER 2004
TYPICAL CHARACTERISTICS
(Conditions are based on Electrical Characteristics table on page 6, unless otherwise noted)
OUTPUT POWER
vs
FREQUENCY
PHASE NOISE
vs
FREQUENCY
0
−10
−20
−30
−40
−50
−60
−70
−80
−90
−100
−110
−120
−40
−50
AV
=
DV = 3.3 V
RMS = 0.14°
PFD = 200 kHz
Loop BW = 20 kHz
DD
DD
Reference Level = −7.4 dBm
I
= 5 mA
CP
Res. Bandwidth = 100 Hz
Video Bandwidth = 100 Hz
Average = 30
PFD = 200 kHz
Loop Loop BW = 20 kHz
−60
−70
−80
−90
−100
−110
−120
−130
−140
−110 dBc
−500−400−300−200−100
0
100 200 300 400 500
100
1k
10k
100k
1M
f − Frequency Offset from 110 MHz Carrier − kHz
f − Frequency Offset from 110 MHz Carrier − Hz
Figure 2. Reference Spurs
(RFOUT = 110 MHz)
Figure 3. Integrated Phase Noise
(RFOUT = 110 MHz)
OUTPUT POWER
vs
FREQUENCY
PHASE NOISE
vs
FREQUENCY
0
−10
−20
−30
−40
−50
−60
−70
−80
−90
−100
−110
−120
−40
−50
AV
I
= DV = 3.3 V
DD
= 5 mA
RMS = 0.18°
PFD = 200 kHz
Loop BW = 20 kHz
DD
Reference Level = −5.5 dBm
CP
Res. Bandwidth = 300 Hz
Video Bandwidth = 300 Hz
Average = 20
PFD = 200 kHz
Loop BW = 20 kHz
−60
−70
−80
−90
−100
−110
−120
−130
−140
−108 dBc
−500−400−300−200−100
0
100 200 300 400 500
100
1k
10k
100k
1M
f − Frequency Offset from 300 MHz Carrier − kHz
f − Frequency Offset from 300 MHz Carrier − Hz
Figure 4. Reference Spurs
(RFOUT = 300 MHz)
Figure 5. Integrated Phase Noise
(RFOUT = 300 MHz)
8
TRF3750
www.ti.com
SLWS146A − MARCH 2004 − REVISED NOVEMBER 2004
TYPICAL CHARACTERISTICS
OUTPUT POWER
vs
FREQUENCY
PHASE NOISE
vs
FREQUENCY
0
−40
−50
AV
= DV = 3.3 V
DD
= 5 mA
DD
Reference Level = −5.7 dBm
RMS = 0.36°
PFD = 200 kHz
Loop BW = 20 kHz
I
−10
−20
CP
Res. Bandwidth = 1 kHz
Video Bandwidth = 1 kHz
Average = 30
PFD = 200 kHz
Loop BW = 20 kHz
−60
−30
−70
−40
−80
−50
−60
−90
−70
−100
−110
−120
−130
−140
−91.5 dBc
−80
−90
−100
−110
−120
−500−400−300−200−100
0
100 200 300 400 500
100
1k
10k
100k
1M
f − Frequency Offset from 540 MHz Carrier − kHz
f − Frequency Offset from 540 MHz Carrier − Hz
Figure 6. Reference Spurs
(RFOUT = 540 MHz)
Figure 7. Integrated Phase Noise
(RFOUT = 540 MHz)
OUTPUT POWER
vs
FREQUENCY
PHASE NOISE
vs
FREQUENCY
0
−10
−20
−30
−40
−50
−60
−70
−80
−90
−100
−110
−120
−40
−50
RMS = 0.39°
PFD = 200 kHz
Loop BW = 20 kHz
AV
= AV
= 5 mA
= 3.3 V
DD
DD
Reference Level = −5.7 dBm
I
CP
Res. Bandwidth = 1 kHz
Video Bandwidth = 1 kHz
Average = 30
PFD = 200 kHz
Loop BW = 20 kHz
−60
−70
−80
−90
−100
−110
−120
−130
−140
−100 dBc
−500−400−300−200−100
0
100 200 300 400 500
100
1k
10k
100k
1M
f − Frequency Offset from 836 MHz Carrier − kHz
f − Frequency Offset from 836 MHz Carrier − Hz
Figure 8. Reference Spurs
(RFOUT = 836 MHz)
Figure 9. Integrated Phase Noise
(RFOUT = 836 MHz)
9
TRF3750
www.ti.com
SLWS146A − MARCH 2004 − REVISED NOVEMBER 2004
TYPICAL CHARACTERISTICS
OUTPUT POWER
vs
FREQUENCY
OUTPUT POWER
vs
FREQUENCY
0
−10
−20
−30
−40
−50
−60
−70
−80
−90
−100
−110
−120
0
−10
−20
−30
−40
−50
−60
−70
−80
−90
−100
AV
I
= DV = 3.3 V
= 5 mA
AV
I
= DV = 3.3 V
DD DD
DD
DD
Reference Level = −5.5 dBm
Reference Level = −5.4 dBm
= 5 mA
CP
CP
Res. Bandwidth = 1 kHz
Video Bandwidth = 1 kHz
Average = 30
PFD = 200 kHz
Loop BW = 20 kHz
Res. Bandwidth = 1 Hz
Video Bandwidth = 1 Hz
Average = 30
PFD = 200 kHz
Loop BW = 20 kHz
−100 dBc
−93 dBc/Hz
−500−400−300−200−100
0
100 200 300 400 500
−2.5 −2.0 −1.5 −1.0 −0.5 0.0 0.5 1.0 1.5 2.0 2.5
f − Frequency Offset from 900 MHz Carrier − kHz
f − Frequency Offset from 900 MHz Carrier − kHz
Figure 10. Reference Spurs
(RFOUT = 900 MHz)
Figure 11. Phase Noise
(RFOUT = 900 MHz)
PHASE NOISE
vs
FREQUENCY
OUTPUT POWER
vs
FREQUENCY
−40
−50
0
−10
−20
−30
−40
−50
−60
−70
−80
−90
−100
−110
−120
RMS = 0.40°
PFD = 200 kHz
Loop BW = 20 kHz
AV
I
= DV = 3.3 V
DD
= 5 mA
DD
Reference Level = −5.3 dBm
CP
Res. Bandwidth = 1 kHz
Video Bandwidth = 1 kHz
Average = 25
PFD = 200 kHz
Loop BW = 20 kHz
−60
−70
−80
−90
−100
−110
−120
−130
−140
−96 dBc
−500−400−300−200−100
0
100 200 300 400 500
100
1k
10k
100k
1M
f − Frequency Offset from 900 MHz Carrier − Hz
f − Frequency Offset from 1750 MHz Carrier − kHz
Figure 12. Integrated Phase Noise
(RFOUT = 900 MHz)
Figure 13. Reference Spurs
(RFOUT = 1750 MHz)
10
TRF3750
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SLWS146A − MARCH 2004 − REVISED NOVEMBER 2004
TYPICAL CHARACTERISTICS
PHASE NOISE
vs
FREQUENCY
OUTPUT POWER
vs
FREQUENCY
−40
0
−10
−20
−30
−40
−50
−60
−70
−80
−90
−100
−110
−120
RMS = 0.95°
PFD = 200 kHz
Loop BW = 20 kHz
AV
I
= DV = 3.3 V
DD
= 5 mA
DD
Reference Level = −6.9 dBm
−50
−60
CP
Res. Bandwidth = 1 kHz
Video Bandwidth = 1 kHz
Average = 30
PFD = 200 kHz
Loop BW = 20 kHz
−70
−80
−90
−100
−110
−120
−130
−140
−92 dBc
100
1k
10k
100k
1M
−500−400−300−200−100
0
100 200 300 400 500
f − Frequency Offset from 1750 MHz Carrier − Hz
f − Frequency Offset from 1960 MHz Carrier − kHz
Figure 14. Phase Noise
(RFOUT = 1750 MHz)
Figure 15. Reference Spurs
(RFOUT = 1960 MHz)
OUTPUT POWER
vs
FREQUENCY
PHASE NOISE
vs
FREQUENCY
0
−10
−20
−30
−40
−50
−60
−70
−80
−90
−100
−40
−50
AV
I
= DV = 3.3 V
DD
= 5 mA
RMS = 0.98°
PFD = 200 kHz
Loop BW = 20 kHz
DD
Reference Level = −6.7 dBm
CP
Res. Bandwidth = 1 Hz
Video Bandwidth = 1 Hz
Average = 30
PFD = 200 kHz
Loop BW = 20 kHz
−60
−70
−80
−90
−100
−110
−120
−130
−140
−84 dBc/Hz
−2.5 −2.0 −1.5 −1.0 −0.5 0.0 0.5 1.0 1.5 2.0 2.5
100
1k
10k
100k
1M
f − Frequency Offset from 1960 MHz Carrier − kHz
f − Frequency Offset from 1960 MHz Carrier − Hz
Figure 16. Phase Noise
(RFOUT = 1960 MHz)
Figure 17. Integrated Phase Noise
(RFOUT = 1960 MHz)
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TRF3750
www.ti.com
SLWS146A − MARCH 2004 − REVISED NOVEMBER 2004
TYPICAL CHARACTERISTICS
OUTPUT POWER
vs
FREQUENCY
PHASE NOISE
vs
FREQUENCY
0
−10
−20
−30
−40
−50
−60
−70
−80
−90
−100
−110
−120
−40
−50
AV
I
= AV
= 5 mA
= 3.3 V
DD
RMS = 0.98°
PFD = 200 kHz
Loop BW = 20 kHz
DD
Reference Level = −7.0 dBm
CP
Res. Bandwidth = 1 kHz
Video Bandwidth = 1 kHz
Average = 25
PFD = 200 kHz
Loop BW = 20 kHz
−60
−70
−80
−90
−90 dBc
−100
−110
−120
−130
−140
−500−400−300−200−100
0
100 200 300 400 500
100
1k
10k
100k
1M
f − Frequency Offset from 2200 MHz Carrier − kHz
f − Frequency Offset from 2200 MHz Carrier − Hz
Figure 18. Reference Spurs
(RFOUT = 2200 MHz)
Figure 19. Integrated Phase Noise
(RFOUT = 2200 MHz)
PHASE NOISE
vs
FREE-AIR TEMPERATURE
REFERENCE SPUR LEVEL
vs
FREE-AIR TEMPERATURE
−75
−90
−95
VCP = 7 V
VCP = 7 V
1960 MHz, AV = DV = 3.3 V
DD
DD
−80
−85
1960 MHz, AV = DV = 3.3 V
DD DD
1960 MHz, AV = DV = 5 V
DD
DD
−100
−105
−110
−115
−120
1960 MHz, AV = DV = 5 V
DD
DD
900 MHz, AV = DV = 5 V
DD
DD
−90
900 MHz, AV = DV = 5 V
DD
DD
900 MHz, AV = DV = 3.3 V
DD
DD
900 MHz, AV = DV = 3.3 V
DD
DD
−95
−100
−40
−20
0
20
40
60
80
100
−40
−20
0
20
40
60
80
100
T
A
− Free-Air Temperature − °C
T
A
− Free-Air Temperature − °C
Figure 20.
Figure 21.
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TRF3750
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SLWS146A − MARCH 2004 − REVISED NOVEMBER 2004
TYPICAL CHARACTERISTICS
REFERENCE SPURS
CURRENT
vs
PRESCALER SETTING
vs
VTUNE
0
−10
−20
−30
−40
−50
−60
−70
−80
−90
−100
12
10
8
I
AVDD
I
DVDD
6
4
V
CP
= 7 V
V
CP
= 5 V
2
−110
0
1
2
3
4
0
8
16
24
32
40
48
56
64
VTUNE − V
Prescaler Setting
Figure 22.
Figure 23.
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TRF3750
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SLWS146A − MARCH 2004 − REVISED NOVEMBER 2004
Table 1. S Data for RFIN Buffer
11
FREQ (Hz)
MAG(S )
11
PHASE(S )
11
300M
849.388m
848.792m
848.317m
847.916m
847.565m
847.25m
1.07722
344M
1.02901
388M
998.914m
981.324m
972.594m
970.294m
972.761m
978.834m
987.691m
998.737m
1.01154
1.02578
1.04122
1.05768
1.07502
1.09312
1.11191
1.13131
1.15127
1.17173
1.19267
1.21403
1.2358
432M
476M
520M
564M
846.962m
846.696m
846.448m
846.217m
846m
608M
652M
696M
740M
784M
845.797m
845.605m
845.425m
845.255m
845.094m
844.943m
844.8m
828M
872M
916M
960M
1.004G
1.048G
1.092G
1.136G
1.18G
1.224G
1.268G
1.312G
1.356G
1.4G
844.664m
844.535m
844.413m
844.296m
844.185m
844.079m
843.978m
843.88m
1.25795
1.28045
1.30327
1.32641
1.34985
1.37355
1.39752
1.42174
1.44619
1.47086
1.49574
1.52082
1.54608
1.57152
1.59713
1.62291
1.64883
1.6749
1.444G
1.488G
1.532G
1.576G
1.62G
1.664G
1.708G
1.752G
1.796G
1.84G
1.884G
1.928G
1.972G
2.016G
2.06G
2.104G
2.148G
2.192G
2.236G
2.28G
2.324G
2.368G
2.412G
2.456G
2.5G
843.787m
843.697m
843.61m
843.526m
843.444m
843.365m
843.288m
843.214m
843.14m
843.069m
842.999m
842.93m
842.862m
842.796m
842.73m
842.665m
842.601m
842.537m
842.474m
842.411m
842.349m
842.287m
842.225m
842.164m
842.103m
1.70111
1.72744
1.7539
1.78048
1.80717
1.83397
1.86086
1.88786
1.91494
1.94211
14
TRF3750
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SLWS146A − MARCH 2004 − REVISED NOVEMBER 2004
FUNCTIONAL DESCRIPTION
REFIN Stage
This input typically comes from an external oscillator and is the reference used to synthesize the desired
frequency on the output of the complete PLL. The equivalent schematic of this section is given in Figure 24.
The output of this section goes to the R divider, so that the desired PFD frequency can be implemented.
PDZ
PDZ
PD
R
PD
Figure 24. REFIN Stage
RFIN Stage
Figure 25 shows the input stage of the TRF3750. This is where the output of the external VCO is fed back to the
synthesizer. The RFIN signal subsequently feeds the prescaler section.
AVDD
RFIN
V
BIAS
RFINB
Figure 25. RFIN Stage
Prescaler Stage
This stage divides down the RFIN frequency before the A and B counters. This is a dual-modulus prescaler and the
user can select any of the following settings: 8/9, 16/17, 32/33, and 64/65.
A and B Counter Stage
The TRF3750 includes a 6-bit A counter and a 13-bit B counter that operate on the output of the prescaler. The A
counter can take values from 0 to 63, while the B counter can take values from 3 to 8191. Also, the value for the B
counter has to be greater than or equal to the value for the A counter. These are CMOS devices, and can easily
operate up to 200 MHz. The selection of the prescaler needs to be such that the resultant frequency does not exceed
the rated 200-MHz threshold.
R Divider
The output of the REFIN stage is fed into the R divider stage. The 14-bit R divider allows the input reference frequency
to be divided down to produce the reference clock to the phase frequency detector (PFD). Division ratios from 1 to
16,383 are allowed.
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Phase Frequency Detector (PFD) and Charge Pump Stage
The outputs of the R divider and the N counter (please see pulse swallow section) are fed into the PFD stage, where
the two signals are compared in frequency and phase. The TRF3750 features an anti-backlash pulse, whose width
is controllable by the user, in order to optimize phase and spurious performance. The PFD feeds the charge pump,
which is the final output of the TRF3750. The charge pump output pulses need to be fed into an external loop filter,
which eventually produces the tuning voltage needed to control the external VCO to the desired frequency.
Pulse Swallow/Frequency Synthesis
The different stages of the TRF3750 enable the user to synthesize a large range of frequencies at the output of a
complete PLL. For a given reference frequency (f ), the user’s choice of the R divider yields the PFD frequency
REFIN
(f
), which is the step by which the resultant output frequency can be incremented or decremented. The choice
PFD
of prescaler, and A and B counters yields the output frequency at the external VCO (RFOUT) as shown below.
RFOUT = f x N = (f / R) x (A + P x B)
PFD
REFIN
MUXOUT Stage
The TRF3750 features a multiplexer that allows programmable access to several signals. Table 5 and Table 6 show
the truth tables. Some of the different signals available are detailed below.
Digital Lock Detect
This is an active high digital output that indicates when the device has achieved lock. The user can choose between
two precision settings for the lock detection, through the reference counter latch. A 0 on the lock detect precision
means that the digital lock detect output goes high only if three contiguous cycles of the PFD have an error of less
than 15 ns. A 1 would require five contiguous cycles (a more stringent condition). Any error of greater than 25 ns,
even on one cycle, would produce a 0 in the digital lock detect signal, indicating loss of lock.
Analog Lock Detect
Selecting the analog lock detect option at the output of the output multiplexer requires an external pull-up resistor
(≈10 kΩ) to be placed on the output (MUXOUT, pin 14).
Fastlock Mode
The TRF3750 features two Fastlock Modes, which the user may select depending on the particular application.
There are two separate charge pump current settings (1 and 2) that can be programmed, and the Fastlock
Modes, when activated, enable the device to quickly switch from current setting 1 to current setting 2. The two
Fastlock Modes (1 and 2) differ in the way the device reverts back to current setting 1. In normal (steady-state)
operation, current setting 1 is used. For transient situations such as frequency jumps, current setting 2 can be
used.
Fastlock Mode 1
As soon as Fastlock Mode 1 is entered, the charge pump current is switched to the preprogrammed setting 2
and stays there until the charge pump gain programming bit is set to 0 in the N counter latch. This way, the user
has immediate software control of the transition between charge pump setting 1 and 2.
Fastlock Mode 2
As soon as Fastlock Mode 2 is entered, the charge pump current is switched to the preprogrammed setting 2
and stays there until the timer counter has expired. The timer counter is programmed by the user and counts
how many PFD cycles the device spends in current setting 2 in Fastlock Mode 2. The number of timer cycles
can be set in increments of four cycles in the range of 3 to 63. When the counter has expired, the device returns
to normal operation (fastlock disabled and charge pump current setting 1). This way no extra programming is
needed in order for the device to exit fastlock.
3-Wire Serial Programming
The TRF3750 features an industry-standard 3-wire serial interface that controls an internal 24-bit shift register.
There are a total of 3 signals that need to be applied: the clock (CLK, pin 11), the serial data (DATA, pin 12)
and the load enable (LE, pin13). The DATA (DB0−DB23) is loaded MSB first and is read on the rising edge of
the CLK. The LE signal is asynchronous to the clock and at its rising edge the DATA gets loaded onto the
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selected latch. The last two bits of the serial data (DB0 and DB1) are the bits that control one of the four available
latches (R counter latch, N counter latch, function latch, and initialization latch). The truth table for selecting
the appropriate latch is shown in Table 2.
Table 2. Latch Selection Truth Table
DB1 (C2)
DB0 (C1)
SELECTED DATA LATCH
0
0
1
1
0
1
0
1
R counter
N counter
Function
Initialization
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SLWS146A − MARCH 2004 − REVISED NOVEMBER 2004
Latch Description
Table 3. R Counter Latch
Lock
Detect
Precision
Test
Mode
Bits
Anti
Backlash
Pulse Width
Control
Bits
Reserved
14-Bit Reference Counter, R
DB23 DB22 DB21
†
DB20
LDP
DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2
DB1
DB0
X
DLY SYNC
T2
T1
ABP2 ABP1 R14
R13
R12
R11
R10
R9
R8
R7
R6
R5
R4
R3
R2
R1
C2(0) C1(0)
Set to 00
Divide
R1
• • •
R14
R13 R12
R3
R2
Ratio
• • •
• • •
• • •
• • •
0
0
0
0
•
0
0
0
0
•
0
0
0
0
•
0
0
0
1
•
0
1
1
0
•
1
1
0
1
0
•
2
ABP2
ABP1
AntiBacklash Pulse Width
3
0
0
1
1
0
1
0
1
3 ns
1.5 ns
6 ns
4
•
• • •
• • •
• • •
• • •
• • •
• • •
• • •
•
•
•
•
•
•
•
3 ns
•
•
•
•
•
•
•
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
1
1
16380
16381
16382
16383
0
1
0
1
LDP
Operation
3 contiguous cycles of phase delay < 15 ns
must occur before Lock Detect is set.
0
1
5 contiguous cycles of phase delay < 15 ns
must occur before Lock Detect is set.
DLY
SYNC
Operation
0
0
1
1
0
1
0
1
Normal operation
Prescaler resynchronized with nondelayed
form of RF input
Normal operation
Prescaler resynchronized with delayed form
of RF input
†
X = Don’t Care
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SLWS146A − MARCH 2004 − REVISED NOVEMBER 2004
Latch Description (Continued)
Table 4. AB Counter Latch
CP
Reserved
Control
13-Bit B Counter
6-Bit A Counter
Bits
Gain
DB23 DB22
DB21
G1
DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2
DB1
DB0
†
†
X
X
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
A6
A5
A4
A3
A2
A1
C2(0) C1(1)
B ≥ A
B Counter
Divide Ratio
• • •
• • •
• • •
• • •
• • •
• • •
• • •
• • •
• • •
• • •
• • •
B13
B12
B11
B3
0
0
0
0
1
•
B2
0
0
1
1
0
•
B1
0
1
0
1
0
•
A6
A5
A2
0
0
1
1
•
A1
0
1
0
1
•
A Counter
N/A
N/A
N/A
3
0
1
0
0
0
0
0
•
0
0
0
0
0
•
0
0
0
0
0
•
0
0
0
0
•
0
0
0
0
•
2
3
• • •
• • •
• • •
• • •
• • •
• • •
• • •
•
4
• • •
• • •
• • •
• • •
• • •
• • •
• • •
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
60
61
62
63
1
1
1
1
1
1
1
1
0
0
1
1
0
1
0
1
8188
8189
8190
8191
1
1
1
1
1
1
1
1
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
F4 (Function Latch D89)
Fastlock Enable
CP
Gain
Charge Pump Current Setting Operation
Current setting 1 is always used
Current setting 2 is always used
Current setting 1 used
0
0
1
1
0
1
0
1
Current setting 2 is used until fastlock mode exits (returns to current setting 1)
†
X = Don’t Care
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SLWS146A − MARCH 2004 − REVISED NOVEMBER 2004
Latch Description (Continued)
Table 5. Function Latch
Power
Down
2
Power
Down
1
Prescaler
Value
Current
Setting 2
Current
Setting 1
Fastlock Fastlock
CP
Tri-State
Reser-
ved
MUXOUT
Control
Counter
Reset
Control
Bits
Timer Counter Control
Mode
Enable
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11
DB10
F5
DB9
F4
DB8
F3
DB7
DB6 DB5 DB4
DB3
PD1
DB2
F1
DB1 DB0
{
P2
P1
PD2 CP16 CP15 CP14 CP13 CP12 CP11 TC4 TC3 TC2 TC1
X
M3 M2
M1
C2(1) C1(0)
I
max (mA)
CPOUT
F1
0
Counter Operation
CP16 CP15 CP14
CP13 CP12 CP11
2.7 kΩ
4.7 kΩ
10 kΩ
Normal
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1.09
0.63
1.25
1.88
2.50
3.13
3.75
4.38
5.00
0.29
0.59
0.88
1.76
1.47
1.76
2.06
2.35
R, A, B counters
reset
1
2.18
3.26
4.35
5.44
6.53
7.62
8.70
F3
0
Charge Pump Output
Normal
M3
M2
M1
0
Output
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
3-State output
1
Tri-State
1
Digital lock detect
N divider output
DVDD
F4
F5
Fastlock Mode
Fastlock disable
Fastlock mode 1
Fastlock mode 2
0
†
0
1
1
X
1
0
1
0
R divider output
1
Analog lock detect
Serial data output
DGND
P2
0
P1
0
Prescaler Value
Timeout
(PFD Cycles)
TC4 TC3 TC2 TC1
0
8/9
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
0
1
3
1
0
1
16/17
32/33
64/65
7
1
0
11
15
19
23
27
31
35
39
43
47
51
55
59
63
1
1
CE
(Pin 10)
PD2 PD1
Mode
†
†
†
0
X
X
X
Asynchronous power down
Normal operation
1
1
1
0
0
1
1
Asynchronous power down
Synchronous power down
1
†
X = Don’t Care
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SLWS146A − MARCH 2004 − REVISED NOVEMBER 2004
Latch Description (Continued)
Table 6. Initialization Latch
Power
Down
2
Power
Down
1
Prescaler
Value
Current
Setting 2
Current
Setting 1
Fastlock Fastlock
CP
3-State
MUXOUT
Control
Counter
Reset
Control
Bits
Reser-
ved
Timer Counter Control
Mode
Enable
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11
DB10
F5
DB9
F4
DB8
F3
DB7
DB6 DB5 DB4
DB3
PD1
DB2
F1
DB1 DB0
{
P2
P1
PD2 CP16 CP15 CP14 CP13 CP12 CP11 TC4 TC3 TC2 TC1
M3 M2
M1
C2(1) C1(1)
X
I
m,ax (mA)
CPOUT
F1
0
Counter Operation
CP16 CP15 CP14
CP13 CP12 CP11
2.7 kΩ
4.7 kΩ
10 kΩ
Normal
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1.09
0.63
0.29
0.59
0.88
1.76
1.47
1.76
2.06
2.35
R, A, B counters
reset
1
2.18
3.26
4.35
5.44
6.53
7.62
8.70
1.25
1.88
2.50
3.13
3.75
4.38
5.00
F3
0
Charge Pump Output
Normal
M3
M2
M1
0
Output
3-State output
Digital lock detect
N divider output
DVDD
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
1
3-State
1
F4
F5
X
Fastlock Mode
Fastlock disable
Fastlock mode 1
Fastlock mode 2
0
0
1
1
1
0
0
R divider output
1
1
Analog lock detect
Serial data output
DGND
P2
0
P1
0
Prescaler Value
Timeout
(PFD Cycles)
TC4 TC3 TC2 TC1
0
8/9
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
0
1
3
1
0
1
16/17
32/33
64/65
7
1
0
11
15
19
23
27
31
35
39
43
47
51
55
59
63
1
1
CE
PD2 PD1
Mode
(Pin 10)
0
X
X
0
1
X
0
1
1
Asynchronous power down
Normal operation
1
1
1
Asynchronous power down
Synchronous power down
†
X = Don’t Care
21
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R Counter Latch
By selecting (0,0) for the control bits DB0 and DB1, the R counter latch is selected. Table 7 shows the setup
of the R counter latch.
Table 7. R Counter Latch
Anti
Backlash
Width
Lock
Detect
Precision
Control
Bits
Test
Mode Bits
DLY SYNC
14-Bit Reference Counter; R
DB23 DB22 DB21 DB20
DLY SYNC LDP
DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
T2 T1 ABP2 ABP1 R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 C2(0) C1(0)
X
R Value
This latch is used primarily to select the R divider for the input reference signal (REFIN). DB2 through DB15
are used to select the chosen value for the 14-bit counter. DB2 is the LSB and DB15 the MSB.
Anti-backlash Pulse
DB16 and DB17 can be used to select the width of the anti-backlash pulse in the PFD. In any PFD
implementation, there is an inherent risk of backlash, a phenomenon that can occur when the device is almost
in lock. In order to ensure that there are always pulses coming out of the charge pump and that therefore the
VCO cannot drift out of lock, the TRF3750 employs an anti-backlash pulse. The user can select the width of
the anti-backlash pulse; the values allowed are 1.5 ns, 3 ns, and 6 ns.
Lock Detect Precision
Setting DB20 of the R counter latch to 0 results in a precision of three cycles for the lock detect, while setting
it to 1 results in a precision of five cycles.
Sync / Delay
DB21−22 control the sync/delay operation of the device. If DB21 is 0, then the device is in normal operation.
Assuming DB21 is set to 1, setting DB22 to 0 utilizes a non-delayed form of the RF signal for the
resynchronization of the prescaler output, whereas setting DB22 to 1 utilizes a delayed form.
Reserved Bits
Bits DB18, DB19 and DB23 of the R counter latch are reserved. It is recommended to keep those bits 0 for
normal operation.
N Counter Latch
Setting (DB1, DB0) = (0,1) for the latch control bits selects the N counter latch. Table 8 shows the setup of the
N counter latch.
Table 8. N Counter Latch
CP
Gain
Control
Bits l
6-Bit B Counter
13-Bit B Counter
Reserved
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
G1 B13 B12 B11 D10 B9 B8 B7 B6 B5 B4 B3 B2 B1 A6 A5 A4 A3 A2 A1 C2(0) C1(0)
X
X
A Counter
The 6 bits DB2−DB7 control the value of the A counter. The valid range is from 0 to 63. For example,
programming (DB7, DB6, DB5, DB4, DB3,DB2) = (0,0,0,0,1,0) results in a value of 2 for the A counter.
B Counter
The 13 bits DB8−DB20 of the N counter latch control the value of the B counter. The valid range is from 3 to
8191. For example, (DB20, DB19, …, DB10, DB9, DB8) = (0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0) results in a value
of 4 for the B counter.
Charge Pump Gain
DB21 of the N counter latch determines when the TRF3750 enters Fastlock Mode. When this bit is 1, the device
switches into fastlock and when this bit is 0, the device exits fastlock (fastlock mode 1).
22
TRF3750
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SLWS146A − MARCH 2004 − REVISED NOVEMBER 2004
Reserved Bits
Bits DB22−DB23 of the N counter latch are reserved and can be treated as don’t cares by the user.
Function Latch
Table 9 depicts the function latch. By selecting (0,1) for the control bits DB0 and DB1, the function latch is
selected.
Table 9. Function Latch
Power
Down
2
CP
Tri−
State
Power
Down
1
Prescaler
Value
MUXOUT
Control
Control
Bits
Current
Setting 2
Timer Counter
Control
Fasklock Fasklock
Counter
Reset
Current
Setting 1
Reserved
Mode
Enable
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10
P2 P1 PD2 CPI6 CPI5 CPI4 CPI3 CPI2 CPI1 TC4 TC3 TC2 TC1 F5
DB9
F4
DB8 DB7
F3
DB6 DB5 DB4 DB3
M3 M2 M1 PD1
DB2
F1
DB1 DB0
C2(1) C1(0)
X
Counter Reset Bit
When this bit is set to 1, all the counters in the PLL are reset. This includes the R, A, and B counters. In a typical
application, this bit should be set to 0.
Power Down
The complete power down functionality of the TRF3750 is controlled in software by the two bits DB3 and DB21
in the function latch and in hardware by the external pin CE (pin 10). When the TRF3750 enters the power down
state, the power consumption is lowered, the charge pump is 3-stated, but the registers are still operational
enabling programming of the device. The hardware power down (CE set to 0) is immediate and asynchronous.
Assuming that CE is set to 1, the two bits can select between the software power down options available. Setting
DB3 to 0 enables normal operation of the PLL. When (DB21, DB3) = (0,1), then the asynchronous power down
is selected, which means that the device powers down as soon as the programming is read. When (DB21, DB3)
= (1,1), then the synchronous power down is enabled. In this mode, the device enters power down on the next
cycle of the charge pump. This is a more controlled power down, as it avoids potential transients or erroneous
output frequencies.
MUXOUT
Bits DB4, DB5, and DB6 determine what signal appears at the output of the internal multiplexer, as described
in Table 5. For example, the most widely used output signal on this pin would be the digital lock detect signal,
which goes high when lock has been achieved. In order to program this mode, the user has to set (DB4, DB5,
DB6) = (1,0,0).
Charge Pump 3-state
DB8 of the function latch can set the output of the charge pump in a 3-state mode, if set to 1. Normal operation
of the device is attained when this bit is 0.
Fastlock Enable and Mode
Setting DB9 of the function latch to 1 enables the Fastlock Mode, whereas setting it to 0 deactivates this feature
altogether. Assuming that DB9 is 1, DB10 selects between the two possible Fastlock Modes: Fastlock Mode
1 is selected when DB10 is 0, whereas Fastlock Mode 2 is selected when DB10 is 1. The device actually enters
fastlock when the charge pump gain bit in the N counter latch (DB21) is set to 1. Once in Fastlock Mode 1, the
device switches back when DB21 of the N counter latch is set to 0. Conversely, once in Fastlock Mode 2, the
device switches back after the timeout condition has been reached, at which point DB21 of the N counter latch
is automatically set to 0.
Timer Counter Control
DB11−DB14 of the function latch control the timer counter, in case the Fastlock Mode 2 was selected. These
four bits give the user the capability to program the number of PFD cycles that elapse before the device exits
the Fastlock Mode. Valid values for this are 3 to 63, in steps of 4 cycles. For example, programming (DB14,
DB13, DB12, DB11) = (0,0,1,0) results in 11 cycles before the Fastlock Mode times out.
Current Settings 1 and 2
DB15−DB17 control the maximum charge pump current setting 1, while DB18−20 control current setting 2. The
actual value of the maximum charge pump current will be dictated by the resistor placed outside on R
(pin1).
SET
23
TRF3750
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SLWS146A − MARCH 2004 − REVISED NOVEMBER 2004
Prescaler Selection
DB22−DB23 of the function latch controls the prescaler value for the device. There are four possible settings
(9/9, 16/17, 32/33, 64/65). For example, setting (DB23, DB22) = (1,0) results in a prescaler choice of 32/33.
Initialization Latch / Programming After Power Up
Setting (DB1, DB0) = (1,1) selects the initialization latch. The make-up and programming of the initialization
latch is identical to that of the function latch. The difference here is that this latch can be used in order to program
the device at power up. When the initialization latch is programmed, an internal reset occurs at all the counters
(R, A, B) who become ready to get loaded, assuring that the next time data is loaded for the A and B counters
the device begins counting efficiently. Subsequent programming of the A and B counters will not, however,
cause this internal pulse to recur. This pulse is also used to gate the synchronous power down when that mode
is engaged. As soon as the device exits power down, the counting resumes promptly.
Alternate Ways of Programming After Power Up
In addition to the method of using the initialization latch described above, the user can also utilize the CE pin
to achieve initialization. Since the CE does not halt the operation of the serial port, the user can preprogram
the counters and as soon as the device is enabled, the counters operate and the device reaches a steady-state
and functions normally.
A third option in power up is the counter reset method. The function latch is programmed with the desired data,
and in addition DB2 (the counter reset bit) is set to 1. The R counter latch is programmed next, followed by the
N counter latch. Finally, the function latch is programmed again, but this time with a 0 in the bit DB2, disabling
the counter reset. The charge pump is 3-stated during the reset, but the synchronous power down is not
triggered.
Prescaler Resynchronization
DB22 and DB21 of the R counter latch are used to control the delay (DLY) and resynchronization (SYNC)
functions of the device. If SYNC is set to 1, then the output of the prescaler is resynchronized with the RF input.
In addition, if DLY is also 1, the output of the prescaler gets resynchronized with a delayed form of the RF input
signal. In either case, taking the SYNC to 0 reverts the device to normal operation.
The use of the SYNC and DLY functionality can improve the device’s phase noise performance by a few dBs.
It is, however, susceptible to potential malfunction, in case the chosen edge of the RF input coincides with the
prescaler. This phenomenon may be mitigated by using the DLY function, but is nonetheless unpredictable and
care should be applied, as fluctuations in temperature, supply and frequency can alter the point at which the
feature fails to operate. The normal operation of the device calls for both DLY and SYNC to be set to 0, which
is the way the TRF3750 has been characterized.
24
TRF3750
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SLWS146A − MARCH 2004 − REVISED NOVEMBER 2004
APPLICATION INFORMATION
SYNTHESIZING A SELECTED FREQUENCY
The TRF3750 is an integer-N PLL synthesizer, and because of its flexibility (14-bit R, 6-bit A, 13-bit B counter,
and dual modulus prescaler), is ideal for synthesizing virtually any desired frequency. Let us assume that we
need to synthesize a 900-MHz local oscillator, with spacing capability (minimum frequency increment) of 200
kHz, as in a typical GSM application. The choice of the external reference oscillator to be used is beyond the
scope of this section, but assuming that a 10-MHz reference is selected, we calculate the settings that yield
the desired output frequency and channel spacing. There is usually more than one solution to a specific set of
conditions, so below is one way of achieving the desired result.
First, select the appropriate R counter value. Since a channel spacing of 200 kHz is desired, the PFD can also
be set to 200 kHz. Calculate the R value through R = REFIN/PFD = 10 MHz / 200 kHz = 50. Assume a prescaler
value of 8/9 is selected. This is a valid choice, since the prescaler output will be well within the 200-MHz limit
(900 MHz / 8 = 112.5 MHz). Select the appropriate A and B counter values. We know that RFOUT = f
x N
PFD
= (f
/ R) x (A + P x B). Therefore, we need to solve the following equation:
REFIN
900 MHz = 200 kHz x (A + 8 x B)
Clearly there are many solutions to this single equation with two unknowns; there are some basic constraints
on the solution, since 3 ≤ B ≤ 8191, and also B ≥ A. So, if we pick A = 4, solving the equation yields B = 562.
Thus, one complete solution would be to choose: R = 50, A = 4, B = 562, and P = 8/9, resulting in the desired
N = 4500.
The GUI software accompanying the evaluation board of the TRF3750 includes an easy Parameter Selection
Assistant that can directly propose appropriate values for all the counters given the user’s requirements. In
addition, the software can configure all the possible settings of the TRF3750 and can output the data stream
required, so that the user has a reference when programming the serial port.
To complete the example, the serial port has to be programmed in order for the correct frequency to appear
at the output of the complete PLL. Assuming that the user wanted to program the same modes as used in the
RF Performance Specifications section, a possible sequence of serial data going into the device could be the
one listed below for the three different latches (note that the initialization latch is not used in this example):
Table 10. R Counter Latch Programming Example
DB DB DB DB DB DB DB DB DB DB DB DB DB DB
DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
23 22 21 20 19 18 17 16 15 14 13 12 11 10
0
0
0
1
0
0
0
1
0
0
0
0
0
0
0
0
1
1
0
0
1
0
0
0
Table 11. N Counter Latch Programming Example
DB DB DB DB DB DB DB DB DB DB DB DB DB DB
23 22 21 20 19 18 17 16 15 14 13 12 11 10
DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
0
0
0
0
0
1
0
0
0
1
1
0
0
1
0
0
0
0
1
0
0
0
1
Table 12. Function Latch Programming Example
DB DB DB DB DB DB DB DB DB DB DB DB DB DB
23 22 21 20 19 18 17 16 15 14 13 12 11 10
DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
0
0
1
1
1
1
1
1
0
0
0
1
0
0
0
1
0
0
1
0
0
1
0
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TRF3750
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SLWS146A − MARCH 2004 − REVISED NOVEMBER 2004
Building a Complete PLL Using the TRF3750
This application of the TRF3750 is just one of many possible ways in which a wireless infrastructure transmitter
LO can be implemented for GSM applications and beyond.
Supplies/Decoupling
Appropriate decoupling is important in ensuring optimum noise performance of the device. Ideally, the AVDD
and DVDD supplies should be separated through a ferrite and be at the same potential. A larger capacitor, in
the order of a 10 µF, should be placed in the supply chain, followed by a couple of small value decoupling
capacitors very close to the device’s supply pins. Typical values are 0.1 µF and 10 pF. The decoupling capacitors
should not be shared and should be chosen to have low ESR. The V supply needs to be at least 1 V greater
CP
than the AVDD and DVDD supplies and similar decoupling should be applied.
Reference
A large range of frequencies can be used for the reference input. In this example, an external TCXO of 10 MHz
is used to provide the stable reference frequency for the REFIN pin of the device. The quality of the reference
oscillator is important, and its phase noise needs to be significantly lower than what is expected of the entire
loop as it does not get attenuated in the loop. Typically, such devices do not require 50-Ω terminations and can
be taken into the PLL ac coupled. The TRF3750 has a large range of power levels that it can accept at the REFIN
input; however stronger signals result typically in better phase noise performance. Values of +5 dBms (referred
to 50 Ω) should yield excellent performance. The TRF3750 is compatible with most commercially available
oscillators.
VCO Selection
Plenty of VCOs exist in the market that can cover the frequency range of all wireless applications today. One
clear advantage of the TRF3750 is that it features an extended charge pump supply, allowing interface to VCOs
with larger tuning ranges. V can be as high as 8 V, which implies that VCOs with tuning voltage ranges of
CP
7 V can easily be accommodated. In closing the loop with the VCO, it is important to ensure that proper
termination is observed, especially in the higher range of frequency operation. A standard resistive splitter
implementation works well, where each of the three Rs in the classic T connection assume the value of 16.6 Ω.
In other cases where impedance matching is less critical than getting maximum power out of the whole PLL
loop, the user may decide to leave the resistors out and just tap off a trace from the VCO output and feed it back
to the synthesizer. Additionally, a small series resistor can be placed in the feedback path towards the TRF3750
so as to reduce the relative power delivered to the PLL versus that available for the transmitter. The VCO’s
supply should also be decoupled as recommended by the manufacturer.
Loop Filter Design
Numerous methodologies and design techniques exist for designing optimized loop filters for particular
applications. The loop filter design can affect the stability of the loop, the lock time, the bandwidth, the extra
attenuation on the reference spurs, etc. The role of the loop filter is to integrate and lowpass the pulses of the
charge pump and eventually yield an output tuning voltage that drives the VCO. Several filter topologies can
be implemented, including both passive and active. In this section, we use a third-order passive filter. For this
example, we assume several design parameters. First, the VCO’s manufacturer should specify the device’s
K , which is given in MHz/V. Here we assume a value of 12 MHz/V, meaning that in the linear region, changing
V
the tuning voltage of the VCO by 1 V induces a change of the output frequency of about 12 MHz. We already
know that N = 4500 and that our f
= 200 kHz. We also further assume that current setting 1 will be used
PFD
and be set to maximum current of 5 mA. In addition, we need to determine the bandwidth of the loop filter. This
is a critical consideration as it affects (among other things) the lock time of the system. Assuming an
approximate bandwidth of around 20 kHz is needed, and that for stability we desire a phase margin of about
45 degrees, the following values for the components of the loop filter can be derived. These values, along with
the rest of the example circuitry, are shown in Figure 26. It is important to note here that there are almost infinite
solutions to the problem of designing the loop filter and the designer is called to make tradeoff decisions for each
application.
26
TRF3750
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SLWS146A − MARCH 2004 − REVISED NOVEMBER 2004
Layout/PCB Considerations
This section of the design of the complete PLL is of paramount importance in achieving the desired
performance. Wherever possible, a multi-layer PCB board should be used, with at least one dedicated ground
plane. A dedicated power plane (split between the supplies if necessary) is also recommended. The impedance
of all RF traces (the VCO output and feedback into the PLL) should be controlled to 50 Ω. All small value
decoupling capacitors should be placed as close to the device pins as possible. It is also recommended that
both top and bottom layers of the circuit board be flooded with ground, with plenty of ground vias dispersed as
appropriate. The most sensitive part of any PLL is the section between the charge pump output and the input
to the VCO. This of course includes the loop filter components, and the corresponding traces. The charge pump
is a precision element of the PLL and any extra leakage on its path can adversely affect performance. Extra
care should be given to ensure that parasitics are minimized in the charge pump output, and that the trace runs
are short and optimized. Similarly, it is also recommend that extra care is taken in ensuring that any flux residue
is thoroughly cleaned and moisture baked out of the PCB. From an EMI perspective, and since the synthesizer
is typically a small portion of a bigger, complex circuit board, shielding is recommended to minimize EMI effects.
DVDD
+
VCP
10 pF
AVDD
+
VVCO
LO Output
to 50-W Load
+
0.1 mF
0.1 mF
10 mF
10 pF
10 mF
10 pF
+
10 pF
10 mF
0.1 mF
0.1 mF
10 mF
100 pF
SUPPLY
10
8
16
2
CE
VCP
16.5 W
1 nF
20 kW
16.5 W
V TUNE
OUT
TCXO
(10-MHz
Reference)
REFIN
CPOUT
1 nF
10 nF
82 pF
GND
100 pF
GND
GND
VCO
TRF3750
16.5 W
3.9 kW
1
6
RSET
RSET
4.7 kW
DECOUPLING NOT SHOWN
CLK
11
12
13
CLK
RFINA
100 pF
DATA
LE
14 LOCK DETECT
5
DATA
MUXOUT
49.9 W
LE
3
RFINB
9
4
100 pF
Figure 26. Example Application of the TRF3750 for GSM Wireless Infrastructure Transceivers
Application Example for Direct IQ Upconversion Wireless Infrastructure Transmitter
Much in the same way as described above, the TRF3750 is an ideal synthesizer to use in implementing a
complete direct upconversion transmitter. Using a complete suite of high performance Texas Instruments
components, a state-of-the-art transmitter can be implemented featuring excellent performance. Texas
Instruments offers ideal solutions for the DSP portion of transceivers, for the digital upconverters,
serializers/deserializers, and for the analog, mixed-signal, and RF components needed to complete the
transmitter. The baseband digital data is converted to I and Q signals through the dual DAC5686, which features
offset and gain adjustments in order to optimize the carrier and sideband suppressions of the direct IQ
modulator. If additional gain is desired at the output of the DAC or if the user’s existing solution does not offer
differential signals, the THS4503 differential amplifier can be used between the DAC and the modulator. The
LO input of the IQ modulator is generated by the TRF3750 synthesizer in combination with an external VCO
centered at the frequency of interest. The same considerations as the ones listed in the previous example still
apply. In addition, the CDC7005 clocking solution can be used to clock the DAC and other portions of the
transmitter. A block diagram of the proposed architecture is shown in Figure 27. For more details, contact Texas
Instruments directly.
27
TRF3750
www.ti.com
SLWS146A − MARCH 2004 − REVISED NOVEMBER 2004
Application Example for Direct IQ Upconversion Wireless Infrastructure Transmitter (Continued)
Main
Diversity
DAC2904
or
DAC5686
TRF370x
GC5016
DUC
PA
Main
DAC
DAC
SERDES
SERDES
I/Q
I/Q
I/Q
I/Q
PA
Diversity
DAC
DAC
DUC
TRF3750
PLL
THS4503
Antenna
Interface
Unit
Baseband
VCO
Channel
CDC7005
Processor
Figure 27. Texas Instruments’ Proposed Direct Upconversion Wireless
Infrastructure Transmitter Architecture
28
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
M
0,10
0,65
14
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
8
14
16
20
24
28
DIM
3,10
2,90
5,10
4,90
5,10
4,90
6,60
6,40
7,90
9,80
9,60
A MAX
A MIN
7,70
4040064/F 01/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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