TRF3761-FIRHARG4_技术文档

TRF3761

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SLWS181F–OCTOBER 2005–REVISED JANUARY 2007

INTEGER-N PLL WITH INTEGRATED VCO

FEATURES

(See Note A)

R2

•

Fully Integrated VCO

C1

C3

R1

C2

•

Low Phase Noise: –137dBc/Hz (at 600kHz, f_VCO

of 1.9GHz )

C4

1000 pF

•

Low Noise Floor: –158dBc/Hz at 10MHz Offset

Integer-N PLL

Input Reference Frequency range: 10MHz to

104MHz

40 39 38 37 36 35 34 33 32 31

PD_OUTBUF

CHIP_EN

CLOCK

1

30

29

28

27

26

25

24

23

22

21

GND

R3

2.37 kΩ

2

AVDD_BIAS

RBIAS1

3

•

VCO Frequency Divided by 2-4 Output

Output Buffer Enable Pin

4

DATA

GND

5

STROBE

DGND

VCTRL_IN

AVDD_VCO

AVDD_BUF

TRF3761

(TOP VIEW)

6

Programmable Charge Pump Current

Hardware and Software Power Down

3-Wire Serial Interface

7

DGND

8

DVDD1

AVDD_CAPARRAY

GND

9

AVDD_PRES

GND

10

AVDD

11 12 13 14 15 16 17 18 19 20

Single Supply: 4.5V to 5.25V Operation

APPLICATIONS

•

Wireless Infrastructure

R4

4.75 kΩ

C7

1000 pF

R5

120 Ω

R6

120 Ω

–

WCDMA, CDMA, GSM

Wideband Transceivers

Wireless Local Loop

RFID Transceivers

Clock generation

V

DD

V

DD

C5

10 pF

C6

10 pF

LOAD

A. See the Application Information section for

Loop Filter Design procedures.

IF LO generation

AVAILABLE DEVICE OPTIONS

Div by 1

Div by 2

Div by 4

PART NUMBER

Fstart

1493

1595

1660

1740

1805

1850

1920

2028

2140

2225

Fstop

1608

1711

1790

1866

1936

1984

2059

2175

2295

2386

Fstart

746.5

797.5

830

Fstop

804

Fstart

373.25

398.75

415

Fstop

402

TRF3761-A

TRF3761-B

TRF3761-C

TRF3761-D

TRF3761-E

TRF3761-F

TRF3761-G

TRF3761-H

TRF3761-J

TRF3761-K

855.5

895

427.75

447.5

466.5

484

870

933

435

902.5

925

968

451.25

462.5

480

992

496

960

1029.5

1087.5

1147.5

1193

514.75

543.75

573.75

596.5

1014

1070

1112.5

507

535

556.25

DESCRIPTION

TRF3761 is a family of high performance, highly integrated frequency synthesizers, optimized for high

performance applications. The TRF3761 includes a low-noise, voltage-controlled oscillator (VCO) and an

integer-N PLL.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

TRF3761

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SLWS181F–OCTOBER 2005–REVISED JANUARY 2007

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be

more susceptible to damage because very small parametric changes could cause the device not to meet its published

specifications.

DESCRIPTION CONTINUED

TRF3761 integrates divide-by 1, 2, or 4 options for a more flexible output frequency range. It is controlled

through a 3-wire serial-programming-interface (SPI) interface. For power sensitive applications the TRF3761 can

be powered down by the SPI interface or externally via chip_en pin 2.

PACKAGE/ORDERING INFORMATION⁽¹⁾

SPECIFIED

TEMPERATURE

RANGE

PACKAGE

LEAD

PACKAGE

MARKINGS

ORDERING

NUMBER

TRANSPORT MEDIA,

QUANTITY

PRODUCT

DESIGNATOR⁽²⁾

TRF3761-AIRHAR

TRF3761-AIRHAT

TRF3761-BIRHAR

TRF3761-BIRHAT

TRF3761-CIRHAR

TRF3761-CIRHAT

TRF3761-DIRHAR

TRF3761-DIRHAT

TRF3761-EIRHAR

TRF3761-EIRHAT

TRF3761-FIRHAR

TRF3761-FIRHAT

TRF3761-GIRHAR

TRF3761-GIRHAT

TRF3761-HIRHAR

TRF3761-HIRHAT

TRF3761-JIRHAR

TRF3761-JIRHAT

TRF3761-KIRHAR

TRF3761-KIRHAT

Tape and Reel, 2500

Tape and Reel, 250

Tape and Reel, 2500

Tape and Reel, 250

Tape and Reel, 2500

Tape and Reel, 250

Tape and Reel, 2500

Tape and Reel, 250

Tape and Reel, 2500

Tape and Reel, 250

Tape and Reel, 2500

Tape and Reel, 250

Tape and Reel, 2500

Tape and Reel, 250

Tape and Reel, 2500

Tape and Reel, 250

Tape and Reel, 2500

Tape and Reel, 250

Tape and Reel, 2500

Tape and Reel, 250

TRF3761-A

TRF3761-B

TRF3761-C

TRF3761-D

TRF3761-E

TRF3761-F

TRF3761-G

TRF3761-H

TRF3761-J

TRF3761-K

QFN-40

RHA

–40°C to 85°C

-40°C to 85°C

–40°C to 85°C

TRF3761-A

TRF3761-B

TRF3761-C

TRF3761-D

TRF3761-E

TRF3761-F

TRF3761-G

TRF3761-H

TRF3761-J

TRF3761-K

(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI

website at www.ti.com.

(2) Thermal pad size: 177 × 177 mils.

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Functional Block Diagram

39

3

4

5

Lock

Det

Serial

Interface

38

R Div

REF_IN

Charge

Pump

34

26

PFD

CPOUT

N−Divider

B−

counter

A−

counter

Prescaler

div p/p+1

VCTRL_IN

14

13

VCO_OUTM

VCO_OUTP

Div1/2/4

Power

Down

2

CHIP_EN

18

1

3

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RHA PACKAGE

(TOP VIEW)

40 39 38 37 36 35 34 33 32 31

1

30

29

28

27

26

25

24

23

22

21

PD_OUTBUF

CHIP_EN

CLOCK

GND

2

AVDD_BIAS

RBIAS1

3

4

DATA

GND

5

STROBE

DGND

VCTRL_IN

AVDD_VCO

AVDD_BUF

AVDD_CAPARRAY

GND

6

7

DGND

8

DVDD1

9

AVDD_PRES

GND

10

AVDD

11 12 13 14 15 16 17 18 19 20

TERMINAL FUNCTIONS

TERMINAL⁽¹⁾

I/O

DESCRIPTION

NAME

NO.

Once configured in register 1, this pin will control the output buffer. Logic level 0

turns on the buffer and logic level 1 turns off the buffer.

PD_OUTBUF

1

I

This pin requires 4.5 to 5.25v applied for normal operation. Grounding this pin will

disable the chip.

CHIP_EN

CLOCK

DATA

2

3

4

I

I/O

I

Serial-programming-interface clock

Serial-programming-interface data, used for programming the frequency and other

features.

STROBE

DGND

5

Serial-programming-interface strobe required to write the data to the chip

Digital ground

6, 7

Digital power supply, requires 4.5 to 5.25 V, Suggested decoupling, 0.1uF and

10pF capacitors in parallel.

DVDD1

8

Power supply for prescaler circuit, requires 4.5 to 5.25 V, Suggested decoupling,

0.1uF and 10pF capacitors in parallel.

AVDD_PRES

VCO_OUTP

VCO_OUTM

AVDD_OUTBUF

9

VCO output, can be used single ended matched to 50 ohms or in conjuction with

VCO_OUTM (pin 14) with a balun.

13

14

15

17

18

19

O

VCO output, can be used single ended matched to 50 ohms or in conjunction with

VCO_OUTP (pin 13) with a balun.

Power supply for output buffers, requires 4.5 to 5.25 V, Suggested decoupling,

0.1uF and 10pF capacitors in parallel.

Power supply for VCO buffers, requires 4.5 to 5.25 V, Suggested decoupling,

0.1uF and 10pF capacitors in parallel.

AVDD_VCOBUF

EXT_VCO_IN

RBIAS2

External VCO input to prescaler, If using an external VCO instead of the internal

VCO.

I

External bias resistor for setting the internal reference current requires a 4.75K

ohm resister to ground.

I/O

(1) Power Supply=Vcc=(DVDD1, AVDD1, AVDD_PRES, AVDD_VCOBUF, AVDD, AVDD_CAPARRAY, AVDD_BUF, AVDD_VCO,

AVDD_BIAS, AVDD_CP, AVDD_REF, DVDD2)

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TERMINAL FUNCTIONS (continued)

TERMINAL⁽¹⁾

I/O

DESCRIPTION

NAME

AVDD

NO.

Analog power supply, requires 4.5 to 5.25 V, Suggested decoupling, 0.1uF and

10pF capacitors in parallel.

21

Power supply for VCO core and buffer, requires 4.5 to 5.25 V, Suggested

decoupling, 0.1uF and 10pF capacitors in parallel.

AVDD_CAPARRAY

AVDD_BUF

23

24

Power supply for VCO core and buffer, requires 4.5 to 5.25 V, Suggested

decoupling, 0.1uF and 10pF capacitors in parallel.

Power supply for VCO core and buffer, requires 4.5 to 5.25 V, Suggested

decoupling, 0.1uF and 10pF capacitors in parallel.

AVDD_VCO

VCTRL_IN

RBIAS1

25

26

28

I

VCO control voltage, the output of the loop filter is applied to this pin.

External bias resistor for setting charge pump reference current, requires 2.37K

ohm resistor to ground.

I/O

Power supply for band gap current bias, requires 4.5 to 5.25 V, Suggested

decoupling, 0.1uF and 10pF capacitors in parallel.

AVDD_BIAS

GND

29

10, 11, 12, 16, 20, 22,

27, 30, 31, 33, 37

Analog ground

Power supply for FUSE cell, requires 4.5 to 5.25V. Suggested decoupling, 0.1uF,

1nF and 1pF capacitors in parallel.

AVDD

32

34

35

CPOUT

AVDD_CP

O

Charge pump output, connected to the input of loop filter.

Analog power supply for charge pump, requires 4.5 to 5.25 V, Suggested

decoupling, 0.1uF and 10pF capacitors in parallel

Power supply for REF_IN circuitry, requires 4.5 to 5.25 V, Suggested decoupling,

0.1uF and 10pF capacitors in parallel.

AVDD_REF

REF_IN

36

38

39

I

Reference signal input, reference oscillator input of 10MHz to 104MHz.

Generally used for digital lock detect, can be used to verify locked condition by

microcontroller, high = locked, low = unlocked.

MUX_OUT

O

Power supply for the digital regulator, requires 4.5 to 5.25 V, Suggested

decoupling, 0.1uF and 10pF capacitors in parallel.

DVDD2

40

THERMAL CHARACTERISTICS

over operating free-air temperature range (unless otherwise noted)

PARAMETER⁽¹⁾

TEST CONDITIONS

MIN

TYP

26

MAX

UNIT

°C/W

Soldered slug, no airflow

θ_JA

Thermal derating, junction-to-ambient

Soldered slug, 200-LFM airflow

Soldered slug, 400-LFM airflow

20.1

17.4

(1) Determined using JEDEC standard JESD-51 with High K board

ABSOLUTE MAXIMUM RATINGS

Over operating free-air temperature range (unless otherwise noted)⁽¹⁾

VALUE

UNIT

Supply voltage range⁽²⁾

Digital I/O voltage range

–0.3 to 5.5

–0.3 to V_CC+0.3

–40 to 150

V

T_J

Operating virtual junction temperature range

Storage temperature range

°C

T_stg

–65 to 150

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating

conditions is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability.

(2) All voltage values are with respect to network ground terminal.

5

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RECOMMENDED OPERATING CONDITIONS

Over operating free-air temperature range (unless otherwise noted)

MIN

NOM

MAX

UNIT

V

V_CC

Power supply voltage

4.5

5

5.25

940

85

Power supply voltage ripple

µV_pp

°C

T_A

T_J

Operating free air temperature range

Operating virtual junction temperature range

–40

150

°C

ELECTRICAL CHARACTERISTICS

Supply voltage = V_CC= 4.5V to 5.25V, T_A= –40 to 85 °C (unless otherwise noted)

PARAMETER

DC Parameters

TEST CONDITIONS

MIN

TYP

MAX UNIT

Divide by 1 output

Divide by 2 output

Divide by 4 output

130

140

150

mA

I_CC

Total supply current

T_A= 25°C

Reference Oscillator Parameters

f_ref

Reference frequency

10

104 MHz

2.5 Vpp

Reference input sensitivity (REF_IN)

0.2

Parallel capacitance

Parallel resistance

5

6.52

pF

Reference input impedance (REF_IN)

3913

Ω

PFD Charge Pump

PFD frequency

30 MHz

mA

Charge pump current (I_{CP_OUT}

)

SPI programmable

5.6

Digital Interface (PD_OUTBUF, CHIP_EN, CLOCK, DATA, STROBE)

V_IH

V_IL

High-level input voltage

Low-level input voltage

2.5

0

V_CC

V

0.8

V_OHHigh-level output voltage

V_OLLow-level output voltage

Output Power

0.8V_CC

0.2V_CC

Single ended

0

3

dBm

Differential

TIMING REQUIREMENTS

Supply voltage = V_CC= 4.5V to 5.25V, T_A= –40 to 85 °C

PARAMETER

TEST CONDITIONS

MIN

50

TYP

MAX UNIT

t_(CLK)

t_su1

t_h

Clock period

ns

Setup time, data

Hold time, data

10

t_w

Pulse width, STROBE

Setup time, STROBE

20

t_su2

10

6

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t

h

su1

t

(CLK)

1” Clock Pike

CLOCK

DATA

DB0 (LSB)

Address bit 1

DB1

Address bit 2

DB2

Address bit 3

DB29

Cmd bit 30

DB30

Cmd bit 31

DB31 (MSB)

Cmd bit 32

t

su2

w

STROBE

A. The first 4 bits, DB(3-0), of data are Address bits. The 28 remaining bits, DB(31-4), are part of the command. The

command is little endian or lower bits first.

Figure 1. Serial Programming Timing Diagram

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TRF3761-B ELECTRICAL CHARACTERISTICS

Supply voltage = V_CC= 5V, T_A= –40 to 85 °C (unless otherwise noted)

PARAMETER

NOISE CHARACTERISTICS

TEST CONDITIONS

MIN

TYP

MAX

UNIT

100kHz offset

600kHz offset

1MHz offset

6MHz offset

10MHz offset

100kHz offset

600kHz offset

1MHz offset

6MHz offset

10MHz offset

100kHz offset

600kHz offset

1MHz offset

6MHz offset

10MHz offset

1kHz offset

–119.34

–139

VCO phase noise,

Free running VCO direct output

f_VCO= 1651MHz,

f_O= 1651MHz

-142.1

–156.6

-158.6

-127.8

–146.5

–149

dBc/Hz

VCO phase noise,

Free running VCO divide-by-2 output

f_VCO= 1651MHz,

f_O= 825.5 MHz

–156.2

–158.4

–127.3

-151.4

-153

VCO phase noise,

Free running VCO divide-by-4 output

f_VCO= 1651MHz,

f_O= 412.75 MHz

dBc/Hz

–155.5

–155.9

–83.5

600kHz offset

1MHz offset

10MHz offset

–138

VCO phase noise,

f_VCO= 1651MHz,

f_O= 1651MHz

Closed loop phase noise direct output^(1)(2)(3)

–141.8

–158.2

RMS phase error

100Hz to 10MHz

f_VCO= 1651MHz,

0.85°

Closed loop phase noise direct output⁽³⁾

1kHz offset

–90.2

–146

600kHz offset

1MHz offset

10MHz offset

VCO phase noise,

dBc/Hz

Closed loop phase noise divide-by-2 output^(1)(2)(3)f_O= 825.5 MHz

–147.39

–158.25

RMS phase error

100Hz to 10MHz

0.53°

Closed loop phase noise divide-by-2 output⁽³⁾

1kHz offset

-95.7

–151

–154

–156

600kHz offset

1MHz offset

10MHz offset

VCO phase noise,

f_VCO= 1651MHz,

Closed loop phase noise divide-by-4 output^(1)(2)(3)f_O= 412.75 MHz

RMS phase error

100Hz to 10MHz

0.33°

Closed loop phase noise divide-by-4 output⁽³⁾

VCO gain, Kv

Reference spur⁽²⁾

VCO free running

23

MHz/V

dBc

–80

(1) See Application Circuit Figure 78.

(2) PFD = 200kHz, Loop Filter BW = 15kHz, Output frequency step = 200kHz.

(3) Reference oscillator RMS phase error = 0.008250°, RMS jitter = 881.764 fs.

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TRF3761-C ELECTRICAL CHARACTERISTICS

Supply voltage = V_CC= 5V, T_A= –40 to 85 °C (unless otherwise noted)

PARAMETER

NOISE CHARACTERISTICS

TEST CONDITIONS

MIN

TYP

MAX

UNIT

100kHz offset

600kHz offset

1MHz offset

6MHz offset

10MHz offset

100kHz offset

600kHz offset

1MHz offset

6MHz offset

10MHz offset

100kHz offset

600kHz offset

1MHz offset

6MHz offset

10MHz offset

1kHz offset

–119.5

–138.8

-143.9

–155.3

–157.5

–126

VCO phase noise,

Free running VCO direct output

f_VCO= 1723MHz,

f_O= 1700MHz

dBc/Hz

–145.2

–149.5

–157.2

–158

VCO phase noise,

Free running VCO divide-by-2 output

f_VCO= 1723MHz,

f_O= 861.5 MHz

dBc/Hz

–133

-151

VCO phase noise,

Free running VCO divide-by-4 output

f_VCO= 1723MHz,

f_O= 430.75 MHz

-153.8

–156

–156.5

–85

600kHz offset

–138.3

4

VCO phase noise,

f_VCO= 1723MHz,

f_O= 1723MHz,

dBc/Hz

Closed loop phase noise direct output^(1)(2)(3)

1MHz offset

–142.6

8

10MHz offset

–157.3

RMS phase error

100Hz to 10MHz

f_VCO= 1723MHz,

0.87°

Closed loop phase noise direct output⁽³⁾

1kHz offset

–90.1

–145

600kHz offset

1MHz offset

10MHz offset

VCO phase noise,

dBc/Hz

Closed loop phase noise divide-by-2 output^(1)(2)(3)f_O= 861.5 MHz

–148.6

–158

RMS phase error

100Hz to 10MHz

0.53°

Closed loop phase noise divide-by-2 output⁽³⁾

1kHz offset

–96.2

–151

–153

–156

600kHz offset

1MHz offset

10MHz offset

VCO phase noise,

f_VCO= 1723MHz,

Closed loop phase noise divide-by-4 output^(1)(2)(3)f_O= 430.75 MHz

RMS phase error

100Hz to 10MHz

0.33°

Closed loop phase noise divide-by-4 output⁽³⁾

VCO gain, Kv

Reference spur⁽²⁾

VCO free running

23

MHz/V

dBc

–80

(1) See Application Circuit Figure 78.

(2) PFD = 200kHz, Loop Filter BW = 15kHz, Output frequency step = 200kHz.

(3) Reference oscillator RMS phase error = 0.008250°, RMS jitter = 881.764 fs.

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TRF3761-D ELECTRICAL CHARACTERISTICS

Supply voltage = V_CC= 5V, T_A= –40 to 85 °C (unless otherwise noted)

PARAMETER

NOISE CHARACTERISTICS

TEST CONDITIONS

MIN

TYP

MAX

UNIT

100kHz offset

600kHz offset

1MHz offset

6MHz offset

10MHz offset

100kHz offset

600kHz offset

1MHz offset

6MHz offset

10MHz offset

100kHz offset

600kHz offset

1MHz offset

6MHz offset

10MHz offset

1kHz offset

–118

–138.5

-144

VCO phase noise,

Free running VCO direct output

f_VCO= 1817MHz,

f_O= 1817MHz

dBc/Hz

–156

–158

–124.8

–145.2

–148

VCO phase noise,

Free running VCO divide-by-2 output

f_VCO= 1817MHz,

f_O= 908.5MHz

–157.8

–158.2

–132

-151

VCO phase noise,

Free running VCO divide-by-4 output

f_VCO= 1817MHz,

f_O= 454.25MHz

-154

dBc/Hz

–157

–157.5

–85

600kHz offset

1MHz offset

10MHz offset

–139

VCO phase noise,

f_VCO= 1817MHz,

f_O= 1817MHz

Closed loop phase noise direct output^(1)(2)(1)

–144

–159

RMS phase error

100Hz to 10MHz

0.85°

Closed loop phase noise direct output⁽³⁾

1kHz offset

–91

–146

–149

–159

VCO phase noise,

600kHz offset

1MHz offset

10MHz offset

f_VCO= 1817MHz,

f_O= 908.5MHz

Closed loop phase noise divide-by-2

dBc/Hz

output^(1)(2)(3)

RMS phase error

100Hz to 10MHz

0.47°

Closed loop phase noise divide-by-2 output⁽³⁾

1kHz offset

–97

–151

–154

–157

VCO phase noise,

600kHz offset

1MHz offset

10MHz offset

f_VCO= 1817MHz,

f_O= 454.25MHz

Closed loop phase noise divide-by-4

output^(1)(2)(3)

RMS phase error

100Hz to 10MHz

VCO free running

0.34°

Closed loop phase noise divide-by-4 output⁽³⁾

VCO gain, Kv

23

MHz/V

dBc

Reference spur⁽²⁾

–80

(1) See Application Circuit Figure 78.

(2) PFD = 200kHz, Loop Filter BW = 15kHz, Output frequency step = 200kHz.

(3) Reference oscillator RMS phase error = 0.008250°, RMS jitter = 881.764 fs.

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TRF3761-E ELECTRICAL CHARACTERISTICS

Supply voltage = V_CC= 5V, T_A= –40 to 85 °C (unless otherwise noted)

PARAMETER

NOISE CHARACTERISTICS

TEST CONDITIONS

MIN

TYP

MAX

UNIT

100kHz offset

600kHz offset

1MHz offset

6MHz offset

10MHz offset

100kHz offset

600kHz offset

1MHz offset

6MHz offset

10MHz offset

100kHz offset

600kHz offset

1MHz offset

6MHz offset

10MHz offset

1kHz offset

–118

–138

VCO phase noise,

Free running VCO direct output

f_VCO= 1869MHz,

f_O= 1869MHz

–142

dBc/Hz

–155

–157.3

–126

–144

VCO phase noise,

Free running VCO divide-by-2 output

f_VCO= 1869MHz,

f_O= 934.5MHz

–149

dBc/Hz

–158

–158.2

–132

–150

VCO phase noise,

Free running VCO divide-by-4 output

f_VCO= 1869MHz,

f_O= 467.25MHz

–154

dBc/Hz

-157

–157.3

–84.5

–140

600kHz offset

1MHz offset

10MHz offset

VCO phase noise,

f_VCO= 1869MHz,

f_O= 1869MHz

Closed loop phase noise direct output^(1)(2)(3)

–143.6

–157

RMS phase error

100Hz to 10MHz

0.9°

Closed loop phase noise direct output⁽³⁾

1kHz offset

–90.7

–144

600kHz offset

1MHz offset

10MHz offset

VCO phase noise,

f_VCO= 1869MHz,

f_O= 934.5MHz

dBc/Hz

Closed loop phase noise divide-by-2 output^(1)(2)(3)

–148.5

–158

RMS phase error

100Hz to 10MHz

0.53°

Closed loop phase noise divide-by-2 output⁽³⁾

1kHz offset

–95

–150

–154

–157

600kHz offset

1MHz offset

10MHz offset

VCO phase noise,

f_VCO= 1869MHz,

f_O= 467.25MHz

Closed loop phase noise divide-by-4 output^(1)(2)(3)

RMS phase error

100Hz to 10MHz

VCO free running

0.35°

Closed loop phase noise divide-by-4 output⁽³⁾

VCO gain, Kv

23

MHz/V

dBc

Reference spur⁽²⁾

–80

(1) See Application Circuit Figure 78.

(2) PFD = 200kHz, Loop Filter BW = 15kHz, Output frequency step = 200kHz.

(3) Reference oscillator RMS phase error = 0.008250°, RMS jitter = 881.764 fs.

11

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SLWS181F–OCTOBER 2005–REVISED JANUARY 2007

TRF3761-F ELECTRICAL CHARACTERISTICS

Supply voltage = V_CC= 5V, T_A= –40 to 85 °C (unless otherwise noted)

PARAMETER

NOISE CHARACTERISTICS

TEST CONDITIONS

MIN

TYP

MAX

UNIT

100kHz offset

600kHz offset

1MHz offset

6MHz offset

10MHz offset

100kHz offset

600kHz offset

1MHz offset

6MHz offset

10MHz offset

100kHz offset

600kHz offset

1MHz offset

6MHz offset

10MHz offset

1kHz offset

-116

-137

-141

-155

-157

-113

-136

-147.5

-155

-157.5

-128

-148

-150

-155

-156

-82.5

-136.7

-142

-157

VCO phase noise,

Free running VCO direct output

f_VCO= 1916MHz,

f_O= 1916MHz

dBc/Hz

VCO phase noise,

Free running VCO divide-by-2 output

f_VCO= 1916MHz,

f_O= 958MHz

VCO phase noise,

Free running VCO divide-by-4 output

f_VCO= 1916MHz,

f_O= 479MHz

dBc/Hz

600kHz offset

1MHz offset

10MHz offset

VCO phase noise,

f_VCO= 1916MHz,

f_O= 1916MHz

Closed loop phase noise direct output^(1)(2)(3)

RMS phase error

100Hz to 10MHz

f_VCO= 1916MHz,

0.947°

Closed loop phase noise direct output⁽³⁾

1kHz offset

-88.6

-142.6

-148.2

-158

600kHz offset

1MHz offset

10MHz offset

VCO phase noise,

dBc/Hz

Closed loop phase noise divide-by-2 output^(1)(2)(3)f_O= 958MHz

RMS phase error

100Hz to 10MHz

0.477°

Closed loop phase noise divide-by-2 output⁽³⁾

1kHz offset

-95

-148

-152

-156

600kHz offset

1MHz offset

10MHz offset

VCO phase noise,

f_VCO= 1916MHz,

Closed loop phase noise divide-by-4 output^(1)(2)(3)f_O= 479MHz

RMS phase error

100Hz to 10MHz

0.231°

Closed loop phase noise divide-by-4 output⁽³⁾

VCO gain, Kv

Reference spur⁽²⁾

VCO free running

23

MHz/V

dBc

–80

(1) See Application Circuit Figure 78.

(2) PFD = 200kHz, Loop Filter BW = 15kHz, Output frequency step = 200kHz.

(3) Reference oscillator RMS phase error = 0.008250°, RMS jitter = 881.764 fs.

12

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SLWS181F–OCTOBER 2005–REVISED JANUARY 2007

TRF3761-G ELECTRICAL CHARACTERISTICS

Supply voltage = V_CC= 5V, T_A= –40 to 85 °C (unless otherwise noted)

PARAMETER

NOISE CHARACTERISTICS

TEST CONDITIONS

MIN

TYP

MAX

UNIT

100kHz offset

600kHz offset

1MHz offset

6MHz offset

10MHz offset

100kHz offset

600kHz offset

1MHz offset

6MHz offset

10MHz offset

100kHz offset

600kHz offset

1MHz offset

6MHz offset

10MHz offset

1kHz offset

-115

-136

VCO phase noise,

Free running VCO direct output

f_VCO= 1989MHz,

f_O= 1989MHz

-141.2

-155.6

-159

dBc/Hz

-121.3

-142.4

-141.5

-157.2

-158

VCO phase noise,

Free running VCO divide-by-2 output

f_VCO= 1989MHz,

f_O= 994.5MHz

dBc/Hz

-128

-148

VCO phase noise,

Free running VCO divide-by-4 output

f_VCO= 1989MHz,

f_O= 497.25MHz

-151

dBc/Hz

-156.8

-157

-83

600kHz offset

1MHz offset

10MHz offset

-136

VCO phase noise,

f_VCO= 1989MHz,

f_O= 1989MHz

Closed loop phase noise direct output^(1)(2)(3)

-141

-159

RMS phase error

100Hz to 10MHz

f_VCO= 1989MHz,

1°

Closed loop phase noise direct output⁽³⁾

1kHz offset

-88.7

-141.9

-147.5

-158

600kHz offset

1MHz offset

10MHz offset

VCO phase noise,

dBc/Hz

Closed loop phase noise divide-by-2 output^(1)(2)(3)f_O= 994.5MHz

RMS phase error

100Hz to 10MHz

0.509°

Closed loop phase noise divide-by-2 output⁽³⁾

1kHz offset

-95

-147.9

-151.3

-156

600kHz offset

1MHz offset

10MHz offset

VCO phase noise,

f_VCO= 1989MHz,

Closed loop phase noise divide-by-4 output^(1)(2)(3)f_O= 497.25MHz

RMS phase error

100Hz to 10MHz

0.252°

Closed loop phase noise divide-by-4 output⁽³⁾

VCO gain, Kv

Reference spur⁽²⁾

VCO free running

23

MHz/V

dBc

–80

(1) See Application Circuit Figure 78.

(2) PFD = 200kHz, Loop Filter BW = 15kHz, Output frequency step = 200kHz.

(3) Reference oscillator RMS phase error = 0.008250°, RMS jitter = 881.764 fs.

13

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SLWS181F–OCTOBER 2005–REVISED JANUARY 2007

TRF3761-H ELECTRICAL CHARACTERISTICS

Supply voltage = V_CC= 5V, T_A= –40 to 85 °C (unless otherwise noted)

PARAMETER

NOISE CHARACTERISTICS

TEST CONDITIONS

MIN

TYP

MAX

UNIT

100kHz offset

600kHz offset

1MHz offset

6MHz offset

10MHz offset

100kHz offset

600kHz offset

1MHz offset

6MHz offset

10MHz offset

100kHz offset

600kHz offset

1MHz offset

6MHz offset

10MHz offset

1kHz offset

–116

–136

VCO phase noise,

Free running VCO direct output

f_VCO= 2116MHz,

f_O= 2116MHz

-142

dBc/Hz

–154.2

–156

–123.3

–143

VCO phase noise,

Free running VCO divide-by-2 output

f_VCO= 2116MHz,

f_O= 1058

–147.6

–157

–158.3

–129.4

-149.8

-152.7

–157.7

–158

VCO phase noise,

Free running VCO divide-by-4 output

f_VCO= 2116MHz,

f_O= 529MHz

dBc/Hz

–84

600kHz offset

1MHz offset

10MHz offset

–136

VCO phase noise,

f_VCO= 2116MHz,

f_O= 2116MHz

Closed loop phase noise direct output^(1)(2)(3)

–141

–157

RMS phase error

100Hz to 10MHz

0.99°

Closed loop phase noise direct output⁽³⁾

1kHz offset

-89

–143

–148

–159

600kHz offset

1MHz offset

10MHz offset

VCO phase noise,

f_VCO= 2116MHz,

f_O= 1058MHz

dBc/Hz

Closed loop phase noise divide-by-2 output^(1)(2)(3)

RMS phase error

100Hz to 10MHz

0.54°

Closed loop phase noise divide-by-2 output⁽³⁾

1kHz offset

–95

–149.5

–153

600kHz offset

1MHz offset

10MHz offset

VCO phase noise,

f_VCO= 2116MHz,

f_O= 529MHz

Closed loop phase noise divide-by-4 output^(1)(2)(3)

–158

RMS phase error

100Hz to 10MHz

VCO free running

0.35°

Closed loop phase noise divide-by-4 output⁽³⁾

VCO gain, Kv

23

MHz/V

dBc

Reference spur⁽²⁾

–80

(1) See Application Circuit Figure 78.

(2) PFD = 200kHz, Loop Filter BW = 15kHz, Output frequency step = 200kHz.

(3) Reference oscillator RMS phase error = 0.008250°, RMS jitter = 881.764 fs.

14

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SLWS181F–OCTOBER 2005–REVISED JANUARY 2007

TRF3761-J ELECTRICAL CHARACTERISTICS

Supply voltage = V_CC= 5V, T_A= –40 to 85 °C (unless otherwise noted)

PARAMETER

NOISE CHARACTERISTICS

TEST CONDITIONS

MIN

TYP

MAX

UNIT

100kHz offset

600kHz offset

1MHz offset

6MHz offset

10MHz offset

100kHz offset

600kHz offset

1MHz offset

6MHz offset

10MHz offset

100kHz offset

600kHz offset

1MHz offset

6MHz offset

10MHz offset

1kHz offset

–116.7

–135.4

-141

VCO phase noise,

Free running VCO direct output

f_VCO= 2289MHz,

f_O= 2289MHz

dBc/Hz

–153.8

–156.4

–123

–142

VCO phase noise,

Free running VCO divide-by-2 output

f_VCO= 2289MHz,

f_O= 1144.5

–147

dBc/Hz

–156.2

–157.5

–129

-149

VCO phase noise,

Free running VCO divide-by-4 output

f_VCO= 2289MHz,

f_O= 572.25MHz

-153

dBc/Hz

–157.5

–158

–83

600kHz offset

1MHz offset

10MHz offset

–135

VCO phase noise,

f_VCO= 2289MHz,

f_O= 2289MHz

Closed loop phase noise direct output^(1)(2)(3)

–140

–156

RMS phase error

100Hz to 10MHz

f_VCO= 2289MHz,

1.1°

Closed loop phase noise direct output⁽³⁾

1kHz offset

–89

-141

600kHz offset

1MHz offset

10MHz offset

VCO phase noise,

dBc/Hz

Closed loop phase noise divide-by-2 output^(1)(2)(3)f_O= 1144.5MHz

–145.7

–158

RMS phase error

100Hz to 10MHz

0.59°

Closed loop phase noise divide-by-2 output⁽³⁾

1kHz offset

–95

–148

600kHz offset

1MHz offset

10MHz offset

VCO phase noise,

f_VCO= 2289MHz,

Closed loop phase noise divide-by-4 output^(1)(2)(3)f_O= 572.25MHz

–152

–158.1

RMS phase error

100Hz to 10MHz

0.37°

Closed loop phase noise divide-by-4 output⁽³⁾

VCO gain, Kv

Reference spur⁽²⁾

VCO free running

23

MHz/V

dBc

–80

(1) See Application Circuit Figure 78.

(2) PFD = 200kHz, Loop Filter BW = 15kHz, Output frequency step = 200kHz.

(3) Reference oscillator RMS phase error = 0.008250°, RMS jitter = 881.764 fs.

15

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SLWS181F–OCTOBER 2005–REVISED JANUARY 2007

TRP3761-B TYPICAL CHARACTERISTICS

(See Figure 78)

Closed Loop VCO Phase Noise

Open Loop VCO Phase Noise

−70

−80

−60

CL = 1651 MHz

OL = 1651 MHz

−70

−80

−90

−100

−110

−120

−130

−140

−150

−160

−100

−110

−120

−130

−140

−150

−160

1k

10k

100k

1M

10M

1k

10k

100k

1M

10M

f − Frequency − Hz

Figure 2.

Figure 3.

Closed Loop VCO Phase Noise

Open Loop VCO Phase Noise

−70

−80

−60

−70

CL = 825.5 MHz

OL = 825.5 MHz

−80

−90

−100

−110

−120

−130

−140

−150

−160

−100

−110

−120

−130

−140

−150

−160

10k

100k

1M

10k

100k

1M

f − Frequency − Hz

Figure 4.

Figure 5.

Closed Loop VCO Phase Noise

Open Loop VCO Phase Noise

−70

−80

−70

−80

CL = 412.75 MHz

OL = 412.75 MHz

−90

−100

−110

−120

−130

−140

−150

−160

−100

−110

−120

−130

−140

−150

−160

10k

100k

1M

10k

100k

1M

f − Frequency − Hz

Figure 6.

Figure 7.

16

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SLWS181F–OCTOBER 2005–REVISED JANUARY 2007

TRP3761-B TYPICAL CHARACTERISTICS

(See Figure 78) (continued)

Direct Output: PFD Frequency Spurs

Figure 8.

Divide-By-2 Output: PFD Frequency Spurs

Figure 9.

Divide-By-4 Output: PFD Frequency Spurs

Figure 10.

17

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SLWS181F–OCTOBER 2005–REVISED JANUARY 2007

TRP3761-C TYPICAL CHARACTERISTICS

(See Figure 78)

Closed Loop VCO Phase Noise

Open Loop VCO Phase Noise

−70

−80

−60

CL = 1723 MHz

OL = 1723

MHz

−70

−80

−90

−100

−110

−120

−130

−140

−150

−160

−100

−110

−120

−130

−140

−150

−160

1k

10k

100k

1M

10M

1k

10k

100k

1M

10M

f − Frequency − Hz

Figure 11.

Figure 12.

Closed Loop VCO Phase Noise

Open Loop VCO Phase Noise

−70

−80

−60

−70

CL = 861.5 MHz

OL = 861.5 MHz

−80

−90

−100

−110

−120

−130

−140

−150

−160

−100

−110

−120

−130

−140

−150

−160

10k

100k

1M

10k

100k

1M

10M

f − Frequency − Hz

Figure 13.

Figure 14.

Closed Loop VCO Phase Noise

Open Loop VCO Phase Noise

−70

−80

−60

−70

CL = 430.75 MHz

OL = 430.75 MHz

−80

−90

−100

−110

−120

−130

−140

−150

−160

−100

−110

−120

−130

−140

−150

−160

10k

100k

1M

10k

100k

1M

10M

f − Frequency − Hz

Figure 15.

Figure 16.

18

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SLWS181F–OCTOBER 2005–REVISED JANUARY 2007

TRP3761-C TYPICAL CHARACTERISTICS

(See Figure 78) (continued)

Direct Output: PFD Frequency Spurs

Figure 17.

Divide-By-2 Output: PFD Frequency Spurs

Figure 18.

Divide-By-4 Output: PFD Frequency Spurs

Figure 19.

19

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SLWS181F–OCTOBER 2005–REVISED JANUARY 2007

TRF3761-D TYPICAL CHARACTERISTICS

(See Figure 78)

Closed Loop VCO Phase Noise

Open Loop VCO Phase Noise

−70

−80

−60

CL = 1801 MHz

OL = 1801 MHz

−70

−80

−90

−100

−110

−120

−130

−140

−150

−160

−100

−110

−120

−130

−140

−150

−160

1k

10k

100k

1M

10M

1k

10k

100k

1M

10M

f − Frequency − Hz

Figure 20.

Figure 21.

Closed Loop VCO Phase Noise

Open Loop VCO Phase Noise

−70

−80

−60

−70

CL = 900.5 MHz

OL = 900.5 MHz

−80

−90

−100

−110

−120

−130

−140

−150

−160

−100

−110

−120

−130

−140

−150

−160

10k

100k

1M

10k

100k

1M

f − Frequency − Hz

Figure 22.

Figure 23.

Closed Loop VCO Phase Noise

Open Loop VCO Phase Noise

−70

−80

−60

−70

CL = 450.25 MHz

OL = 450.25 MHz

−80

−90

−100

−110

−120

−130

−140

−150

−160

−100

−110

−120

−130

−140

−150

−160

10k

100k

1M

10k

100k

1M

f − Frequency − Hz

Figure 24.

Figure 25.

20

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SLWS181F–OCTOBER 2005–REVISED JANUARY 2007

TRF3761-D TYPICAL CHARACTERISTICS (Continued)

Direct Output: PFD Frequency Spurs

Figure 26.

Divide-By-2 Output: PFD Frequency Spur

Figure 27.

Divide-By-4 Output: PFD Frequency Spurs

Figure 28.

21

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SLWS181F–OCTOBER 2005–REVISED JANUARY 2007

TRP3761-E TYPICAL CHARACTERISTICS

(See Figure 78)

Closed Loop VCO Phase Noise

Open Loop VCO Phase Noise

−70

−80

−60

CL = 1869 MHz

OL = 1869 MHz

−70

−80

−90

−100

−110

−120

−130

−140

−150

−160

−100

−110

−120

−130

−140

−150

−160

1k

10k

100k

1M

10M

1k

10k

100k

1M

10M

f − Frequency − Hz

Figure 29.

Figure 30.

Closed Loop VCO Phase Noise

Open Loop VCO Phase Noise

−70

−80

−60

−70

CL = 934.5 MHz

OL = 934.5 MHz

−80

−90

−100

−110

−120

−130

−140

−150

−160

−100

−110

−120

−130

−140

−150

−160

10k

100k

1M

10k

100k

1M

f − Frequency − Hz

Figure 31.

Figure 32.

Closed Loop VCO Phase Noise

Open Loop VCO Phase Noise

−70

−80

−60

−70

CL = 467.25 MHz

OL = 467.25 MHz

−80

−90

−100

−110

−120

−130

−140

−150

−160

−100

−110

−120

−130

−140

−150

−160

10k

100k

1M

10k

100k

1M

f − Frequency − Hz

Figure 33.

Figure 34.

22

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TRP3761-E TYPICAL CHARACTERISTICS

(See Figure 78) (continued)

Direct Output: PFD Frequency Spurs

Figure 35.

Divide-By-2 Output: PFD Frequency Spurs

Figure 36.

Divide-By-4 Output: PFD Frequency Spurs

Figure 37.

23

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SLWS181F–OCTOBER 2005–REVISED JANUARY 2007

TRP3761-F TYPICAL CHARACTERISTICS

(See Figure 78)

Closed Loop VCO Phase Noise

Open Loop VCO Phase Noise

−70

−80

−60

CL = 1916 MHz

OL = 1916 MHz

−70

−80

−90

−100

−110

−120

−130

−140

−150

−160

−100

−110

−120

−130

−140

−150

−160

1k

10k

100k

1M

10M

1k

10k

100k

1M

10M

f − Frequency − Hz

Figure 38.

Figure 39.

Closed Loop VCO Phase Noise

Open Loop VCO Phase Noise

−70

−80

−60

−70

CL = 958 MHz

OL = 958 MHz

−80

−90

−100

−110

−120

−130

−140

−150

−160

−100

−110

−120

−130

−140

−150

−160

1k

10k

100k

1M

1k

10k

100k

1M

f − Frequency − Hz

Figure 40.

Figure 41.

Closed Loop VCO Phase Noise

Open Loop VCO Phase Noise

−70

−80

−60

−70

CL = 479 MHz

OL = 479 MHz

−80

−90

−100

−110

−120

−130

−140

−150

−160

−100

−110

−120

−130

−140

−150

−160

1k

10k

100k

1M

1k

10k

100k

1M

f − Frequency − Hz

Figure 42.

Figure 43.

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TRP3761-F TYPICAL CHARACTERISTICS

(See Figure 78) (continued)

Direct Output: PFD Frequency Spurs

Figure 44.

Divide-By-2 Output: PFD Frequency Spurs

Figure 45.

Divide-By-4 Output: PFD Frequency Spurs

Figure 46.

25

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SLWS181F–OCTOBER 2005–REVISED JANUARY 2007

TRP3761-G TYPICAL CHARACTERISTICS

(See Figure 78)

Closed Loop VCO Phase Noise

Open Loop VCO Phase Noise

−70

−80

−60

CL = 1989 MHz

OL = 1989 MHz

−70

−80

−90

−100

−110

−120

−130

−140

−150

−160

−100

−110

−120

−130

−140

−150

−160

1k

10k

100k

1M

10M

1k

10k

100k

1M

10M

f − Frequency − Hz

Figure 47.

Figure 48.

Closed Loop VCO Phase Noise

Open Loop VCO Phase Noise

−70

−80

−60

−70

CL = 994.5 MHz

OL = 994.5 MHz

−80

−90

−100

−110

−120

−130

−140

−150

−160

−100

−110

−120

−130

−140

−150

−160

10k

100k

1M

10k

100k

1M

f − Frequency − Hz

Figure 49.

Figure 50.

Closed Loop VCO Phase Noise

Open Loop VCO Phase Noise

−70

−80

−60

−70

CL = 497.25 MHz

OL = 497.25 MHz

−80

−90

−100

−110

−120

−130

−140

−150

−160

−100

−110

−120

−130

−140

−150

−160

10k

100k

1M

10k

100k

1M

f − Frequency − Hz

Figure 51.

Figure 52.

26

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TRP3761-G TYPICAL CHARACTERISTICS

(See Figure 78) (continued)

Direct Output: PFD Frequency Spurs

Figure 53.

Divide-By-2 Output: PFD Frequency Spurs

Figure 54.

Divide-By-4 Output: PFD Frequency Spurs

Figure 55.

27

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TRP3761-H TYPICAL CHARACTERISTICS

(See Figure 78)

Closed Loop VCO Phase Noise

Open Loop VCO Phase Noise

−70

−80

−60

CL = 2100 MHz

OL = 2100 MHz

−70

−80

−90

−100

−110

−120

−130

−140

−150

−160

−100

−110

−120

−130

−140

−150

−160

1k

10k

100k

1M

10M

1k

10k

100k

1M

10M

f − Frequency − Hz

Figure 56.

Figure 57.

Closed Loop VCO Phase Noise

Open Loop VCO Phase Noise

−70

−80

−60

−70

CL = 1050 MHz

OL = 1050 MHz

−80

−90

−100

−110

−120

−130

−140

−150

−160

−100

−110

−120

−130

−140

−150

−160

10k

100k

1M

10k

100k

1M

f − Frequency − Hz

Figure 58.

Figure 59.

Closed Loop VCO Phase Noise

Open Loop VCO Phase Noise

−70

−80

−60

−70

CL = 525 MHz

OL = 525

MHz

−80

−90

−100

−110

−120

−130

−140

−150

−160

−100

−110

−120

−130

−140

−150

−160

10k

100k

1M

10k

100k

1M

f − Frequency − Hz

Figure 60.

Figure 61.

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TRP3761-H TYPICAL CHARACTERISTICS

(See Figure 78) (continued)

Direct Output: PFD Frequency Spurs

Figure 62.

Divide-By-2 Output: PFD Frequency Spurs

Figure 63. Divide-By-2 Output: PFD Frequency Spurs

Divide-By-4 Output: PFD Frequency Spurs

Figure 64.

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TRP3761-J TYPICAL CHARACTERISTICS

(See Figure 78)

Closed Loop VCO Phase Noise

Open Loop VCO Phase Noise

−70

−80

−60

CL = 2216 MHz

OL = 2216 MHz

−70

−80

−90

−100

−110

−120

−130

−140

−150

−160

−100

−110

−120

−130

−140

−150

−160

1k

10k

100k

1M

10M

1k

10k

100k

1M

10M

f − Frequency − Hz

Figure 65.

Figure 66.

Closed Loop VCO Phase Noise

Open Loop VCO Phase Noise

−70

−80

−60

−70

CL = 1108 MHz

OL = 1108 MHz

−80

−90

−100

−110

−120

−130

−140

−150

−160

−100

−110

−120

−130

−140

−150

−160

1k

10k

100k

1M

1k

10k

100k

1M

f − Frequency − Hz

Figure 67.

Figure 68.

Closed Loop VCO Phase Noise

Open Loop VCO Phase Noise

−70

−80

−60

−70

CL = 554 MHz

OL = 554 MHz

−80

−90

−100

−110

−120

−130

−140

−150

−160

−100

−110

−120

−130

−140

−150

−160

1k

10k

100k

1M

1k

10k

100k

1M

f − Frequency − Hz

Figure 69.

Figure 70.

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TRP3761-J TYPICAL CHARACTERISTICS

(See Figure 78) (continued)

Direct Output: PFD Frequency Spurs

Figure 71.

Divide-By-2 Output: PFD Frequency Spurs

Figure 72.

Divide-By-4 Output: PFD Frequency Spurs

Figure 73.

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SERIAL INTERFACE PROGRAMMING REGISTERS DEFINITION

The TRF3761 features a 3-wire serial programming interface that controls an internal, 32-bit shift register. There

are a total of 3 signals that need to be applied: the CLOCK (pin 3), the serial DATA (pin 4) and the STROBE

(pin 5). The DATA (DB0-DB31) is loaded LSB first and is read on the rising edge of the CLOCK. The STROBE

is asynchronous to the CLOCK and at its rising edge the data in the shift register gets loaded onto the selected

internal register. The first four bits (DB0-DB3) is the address to select the available internal registers.

t

h

su1

t

(CLK)

1” Clock Pike

CLOCK

DATA

DB0 (LSB)

Address bit 1

DB1

Address bit 2

DB2

Address bit 3

DB29

Cmd bit 30

DB30

Cmd bit 31

DB31 (MSB)

Cmd bit 32

t

su2

w

STROBE

A. The first 4 bits, DB(3-0), of data are Address bits. The 28 remaining bits, DB(31-4), are part of the command. The

command is little endian or lower bits first.

Figure 74. Serial Programming Timing Diagram

Register Address

REST

DB4

Charge Pump Current

Select

Output Mode

DB8 DB9

OUTBUF

EN_SEL BUFOUT

PD

Reference Clock Divider (RDiv)

DB12 DB13 DB14 DB15

DB0

DB1

DB2

DB3

DB5

DB6

DB7

DB10 DB11

Reference Clock Divider (RDiv)

DB19 DB20 DB21 DB22

Anti Backlash

DB26 DB27

PFD_P TRIS_C CP_TE Full Cal

OL

P

ST

Req

DB16

DB17

DB18

DB23

DB24

DB25

DB28

DB29

DB30

DB31

Figure 75. Register 1

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Table 1. Register 1: Device Setup

REGISTER 1 MAPPING

Data Field DB31

FULL_CAL_REQ

This is a read only bit, that indicates if a 0 power-up cal is not required

power-up cal is required

1 power-up cal is required

DB30

DB29

CP_TEST

TRIS_CP

TI internal use only

1 test enabled

High-impedance state charge pump

output

1 CP high-impedance state

0 for normal operation

DB28

PFD_POL

Selects Polarity of PFD, should match

polarity of VCO gain. If using external

VCO with Negative gain then set to 0

and vise versa. The internal VCO has

positive gain so set to positve(1)

0 negative

1 positive

DB27

ABPW1

ABPW<1,0>: anti-backlash pulse width

00 1.5ns delay

01 0.9ns delay

10 3.8ns delay

11 2.7ns delay

DB26

DB25

DB24

DB23

DB22

DB21

DB20

DB19

DB18

DB17

DB16

DB15

DB14

DB13

DB12

DB11

ABPW0

RDIV_13

RDIV_12

RDIV_11

RDIV_10

RDIV_9

RDIV_8

RDIV_7

RDIV_6

RDIV_5

RDIV_4

RDIV_3

RDIV_2

RDIV_1

RDIV_0

PD_BUFOUT

14-bit reference clock divider

RDIV<13,0>:00...01: divide by 1

RDIV<13,0>:00...10: divide by 2

RDIV<13,0>:00...11: divide by 3

If DB10 = 0 then it controls power down <DB10:11>:

of output buffer

00 default; output buffer on

01 output buffer off

1x output buffer on/off controlled by

OUTBUF_EN pin

DB10

OUTBUF_EN_SEL

Select Output Buffer enable control:

0 internal

1 through OUTBUF_EN pin

DB9

DB8

OUT_MODE_1

OUT_MODE_0

OUTBUFMODE<1,0>: Selection of RF

output buffer division ratio

00 divide by 1

01 divide by 2

10 divide by4

DB7

DB6

DB5

DB4

ICP2

ICP<2,0>: select charge pump current

(1 mA step). From 1.4mA to 11.2mA

with Rbias set to 2.37Kohms.

ICP1

ICP0

RESET

Registers reset

1 high

0 low for normal operation

Address

Bits

DB3

DB2

DB1

DB0

Address Bits <3,0>=0000 for register 1

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OUT_MODE<1,0>: TRF3761 has an optional divide by 2 or 4 output, which is selectable by programming bits

<OUT_MODE_1, OUT_MODE_0> of register 1 (see Table 1).

CP_TEST: By setting bit DB30 to 1 it is possible to test the PFD up or down pulses. Internal TI use only.

TRIS_CP: If bit DB29 is set to 1, the charge pump output goes in tri-state. For normal operation, DB29 must be

set to 0.

ABPW: Bits <DB27, DB26> are used to program the width of the anti-backlash pulses of the PFD. The user

selects one of the following values: 0.9ns, 1.5ns, 2.7ns and 3.8ns. Backlash can occur when Fpfd becomes

phase aligned with Fout of the VCO. This will cause a high impedance state on the phase detector and allow the

output frequency to drift until the phase difference is enough to cause the phase detector to start sending signals

to the charge pump to correct the difference. This slight variation will show up as a sub harmonic of the pfd

signal in the passband of the loop filter which would result in a significant spur in the output of the VCO. It is

recommended that the anti-backlash pulse be set to the 1.5ns which gives the best spur reduction for the

TRF3761.

PFD_POL: Bit DB28 of register 1 sets the polarity of the PFD. A Low (0) selects a negative polarity, and a High

(1) selects a positive polarity. By choosing the correct polarity, the TRF3761 will works with an external VCO

having both positive and negative gain (Kv). For example if an external VCO has a Kv = -23MHz/V then the PFD

polarity would need to be negative, so DB28 would be set to a Low (0). When using the internal VCO with a Kv

of 23MHz/V, the PDF_POL should be set to 1.

RDiv: A 14-bit word programs the RDiv for the reference signal, DB25 is the MSB and DB12 is the LSB. RDiv

value is determined by dividing the reference frequency by the channel step size. For example if the reference

frequency is 10MHz and the channel step size is 200KHz then RDiv would be 50. This sets up the Fpfd for the

phase detector, in other words the reference frequency will be divided down by a factor of RDiv which in this

example is 50.

ICP: Bits <DB7, DB5> set the charge pump current.

1.2 V

22.168

I

=

× (N + 1) ×

CP

R

8

bias1

(1)

which reduces to:

3.3252 × N + 1

(

)

I

=

CP

R

bias1

(2)

where N = decimal value of [Reg1 DB<7:5>]. The range is set by N and Rbias2. It is recommended that Icp be

set to 7mA or <DB7, DB5>=101.

OUTBUF_EN_SEL: Output buffer on/off state is controlled through serial interface or an external pin. If bit DB10

is a 0 (default state) the output buffers state is elected through bit DB11. If DB10 is a 1, the buffers on/off are

directly controlled by the OUTBU_EN pin.

RESET: Setting bit DB4 to 1, all registers are reset to default values.

Refer to Register 1 under the Application Information section.

Register Address

Reference Frequency (Integer Part)

Refernece Frequency (Fractional Part)

DB0

DB1

DB2

DB3

DB4

DB5

DB6

DB7

DB8

DB9

DB10

DB26

DB11

DB12

DB13

DB14

DB15

Reference

Frequency

Continued

VCO Frequency in MHz

START

_CAL

DB16

DB17

DB18

DB19

DB20

DB21

DB22

DB23

DB24

DB25

DB27

DB28

DB29

DB30

DB31

Figure 76. Register 2

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Table 2. Register 2: VCO Calibration

REGISTER 2 MAPPING

Data Field DB31

DB30

DB29

DB28

DB27

DB26

DB25

DB24

DB23

DB22

DB21

DB20

DB19

DB18

DB17

DB16

DB15

DB14

DB13

DB12

DB11

DB10

DB9

START_CAL

FOUT12

FOUT11

FOUT10

FOUT9

FOUT8

FOUT7

FOUT6

FOUT5

FOUT4

FOUT3

FOUT2

FOUT1

FOUT0

REF_FRAC6

REF_FRAC5

REF_FRAC4

REF_FRAC3

REF_FRAC2

REF_FRAC1

REF_FRAC0

REF6

1 start calibration

VCO frequency in MHz start calibration

Reference frequency in MHz (fractional 0000000 = 0.00MHz

part)

0000001 = 0.01MHz

0000010 = 0.02MHz

. . . . .

1100011 = 0.99MHz

Reference frequency in MHz (integer

part)

0001010 =10MHz

0001011 =11MHz

. . . . .

REF5

DB8

REF4

1101000 = 104MHz

DB7

REF3

DB6

REF2

DB5

REF1

DB4

REF0

Address

Bits

DB3

DB2

DB1

DB0

0

Address Bits <3,0>=0001 for register 2

0

1

Reference Frequency: The 14 bits <DB17, DB4> are used to specify the input reference frequency as multiples

of 10kHz. Bits <DB10,DB4> specify the integer part of the reference frequency expressed in MHz. Bits

<DB17,DB11> set the fraction part. Those values are then used during the calibration of the internal VCO. For

example if using a 20MHz reference oscillator then bits<DB10,DB4> would be 0010100 and bits<DB17,DB11>

would be 0000000. If the reference oscillator is 13.1MHz then bits<DB10,DB4> would be 0001101 and

bits<DB17,DB11> would be 0001010.

Start Calibration: A 1 in DB31 starts the internal VCO calibration. When the calibration is complete, DB31 bit is

internally reset to 0.

FOUT<12,0>: This 13-bit word <DB30,DB18> specifies the VCO output frequency in MHz. If output frequency is

not a integer multiple of MHz, this value must be approximated to the closest integer in MHz.

Refer to Register 2 under the Application Information section.

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Register Address

Dual-Modulus

Prescalar Mode

A-Counter

DB8 DB9

B-Counter

DB0

DB1

DB2

DB3

DB4

DB5

DB6

DB7

DB10

DB11

DB27

DB12

DB28

DB13

DB14

DB15

B-Counter

DB20

Test MUX

Lock

PLL

RSRV

DB30

RSRV

DB31

DB16

DB17

DB18

DB19

DB21

DB22

DB23

DB24

DB25

DB26

DB29

Figure 77. Register 3

Table 3. Register 3: A and B Counters

REGISTER 3 MAPPING

Data Field DB31

DB30

DB29

DB28

DB27

DB26

DB25

DB24

DB23

DB22

DB21

DB20

DB19

DB18

DB17

DB16

DB15

DB14

DB13

DB12

DB11

DB10

DB9

Rsrv

Reserved

START_LK

Lock PLL to frequency

1 active

TEST_MUX_3

See Table 4 for descriptions and

settings.

0001 = LOCK_DETECT enabled

TEST_MUX_2

TEST_MUX_1

TEST_MUX_0

B_12

B_11

B_10

B_9

13-bit B counter

B_8

B_7

B_6

B_5

B_4

B_3

B_2

B_1

B_0

A_5

6-bit A counter

A_4

A_3

DB8

A_2

DB7

A_1

DB6

A_0

DB5

PRESC_MOD1

PRESC_MOD0

Dual-modulus prescaler mode

Address Bits

<B5,B4>:00 for 8/9

<B5,B4>:01 for 16/17

<B5,B4>:10 for 32/33

<B5,B4>:11 for 64/65

DB4

Address

Bits

DB3

DB2

DB1

DB0

0

1

0

<3,0>=0010 for register 3

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B<12,0>: This 13-bit word <DB24,DB12> controls the value of the B counter of the N divider. The valid range is

from 3 to 8191.

A<5,0>: These 6 bits <DB11,DB6> control the value of the A counter. The valid range is from 0 to 63.

PRESC_MOD<1,0>: These bits <DB5,DB4> define the mode of the dual-modulus prescaler according to

Table 3.

START_LK: TRF3761 does not load the serial interface registers values into the dividers registers until bit DB29

of register 3 is set to 1. After TRF3761 is locked to the new frequency, bit DB29 is internally reset to 0.

Refer to Register 3 under the Application Information section.

FUNCTIONAL DESCRIPTION

VCO

The TRF3761 integrates a high-performance, LC tank, voltage-controlled oscillator (VCO). For each of the

devices of the TRF3761 family, the inductance and capacitance of the tank are optimized to yield the best

phase-noise performance. The VCO output is fed externally and to the prescaler through a series of very low

noise buffers, that greatly reduce the effect of load pulling onto the VCO.

Divide by 2, by 4, and Output Buffer

To extend the frequency coverage, the TRF3761 integrates a divide by 2 and by 4 with very low noise floor. The

VCO signal is fed externally through a final open-collector differential-output buffer. This buffer is able to provide

up to 3dBm (typical) of power into a 200Ω differential resistive load. The open-collector structure gives the

flexibility to choose different load configurations to meet different requirements.

N-Divider

Prescaler Stage

This stage divides down the VCO frequency before the A and B counters. This is a dual-modulus prescaler

and the user can select any of the following settings: 8/9, 16/17, 32/33, and 64/65. Prescaling is used due to

the fact that the internal devices are limited in frequency operations of 200MHz. To determine the proper

prescaler value, Fout which is the frequency out of the VCO is divided by the numerator of the prescaler if

the answer is less than 200MHz then that is the prescalar to use, see Equation 3. If the value is higher than

200MHz then repeat this procedure with the next prescalar numerator until a value of 200MHz or less is

achieved. Refer to Synthesizing a Selected Frequency in the Section 9 Register 3.

F

OUT

£ 200MHz

Prescalar

denom

(3)

A and B Counter Stage

The TRF3761 includes a 6-bit A counter and a 13-bit B counter that operate on the output of the prescaler.

The A counter can take values from 0 to 63, while the B counter can take values from 3 to 8191. Also, the

value for the B counter must be greater than or equal to the value for the A counter. The A and B counter

with the prescaler stage create the VCO N-divider, see Equation 4 and Equation 5. Refer to Synthesizing a

Selected Frequency in the Section 9 Register 3.

F_OUT

N =

=

A

(

+ Prescalar × B

num COUNTER

)

COUNTER

F_PFD

(4)

N

= x

´ y

, Þ

decimal

integer

Prescalar

num

B

= x

and A

= Prescalar

num

× y

decimal

COUNTER

integer

COUNTER

(5)

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FUNCTIONAL DESCRIPTION (continued)

Reference Divider

TRF3761 includes a 14-bit RDiv, also known as RDiv, that allows the input reference frequency to be divided

down to produce the reference clock to the phase frequency detector (PFD) this clock is also known as F_PFD

which is also the channel step size. Division ratios from 1 to 16,383 are allowed. To determine RDiv use

Equation 6.

F

REF_IN

R

=

DIV

F

PFD

(6)

(7)

The output frequency (Fout) is determined using Equation 7.

F

REF_IN

F

= F

PFD

× N =

× A

(

+ Prescalar × B

denom COUNTER

)

OUT

COUNTER

R

DIV

Phase Frequency Detector (PFD) and Charge Pump Stage

The outputs of the RDiv and the N counter are fed into the PFD stage, where the two signals are compared in

frequency and phase. The TRF3761 features an anti-backlash pulse, whose width is controllable by the user

through the serial programming interface. The PFD feeds the charge pump, whose output current pulses are fed

into an external loop filter, which eventually produces the tuning voltage needed to control the integrated VCO to

the desired frequency.

Mux Out

MUX_OUT pin (39) provides a communication port to the microcontroller circuit. See Table 4 in the Application

Information section.

Div 1/2/4

Div 1/2/4 is the frequency divider for the TRF3761. This circuit can be programmed thru the serial programming

interface (SPI) to divide the output frequency of the VCO by 1, 2 or 4. This feature allows for the same loop filter

design to be used for any of the 3 divide by modes, 1, 2 and 4. For example, if the VCO is running at 1499MHz

to 1608MHz band then with the same exact circuit, run the output in the divide by 2 mode 749.5MHz to 804MHz

band or in the divide by 4 mode 374.75MHz to 402MHz.

Serial interface

The programming interface pins (3, 4, 5) to the chip are the serial programming interface (SPI). The interface

requires a Clock, Data, and Strobe signal to operate. See timing diagram Figure 74.

CHIP ENABLE

This feature provides a way to shut down the chip when not needed in order to conserve power. CHIP_EN Pin

(2) needs to be High for normal operation.

Buffer Power Down

PD_OUTBUFF pin (1), when enabled in software can provide a -40dB reduction in the output power while the

VCO is locked and running. This feature is to help with isolation between RX and TX.

External VCO IN

EXT_VCO_IN pin (18) allows for the use of an external VCO to use the phase lock loop circuit in the TRF3761.

This feature enables higher frequencies to be synthesized.

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APPLICATION INFORMATION

Initial Calibration and Frequency Setup at Power Up

The integrated high performance VCO requires an internal frequency calibration at power up. To perform such

calibration the following procedure is recommended:

•

Apply 5V power supply to IC.

Apply an input reference frequency to pin (38) and ensure the signal is stable.

Turn on the TRF3761 using the chip enable pin (CHIP_EN, pin 2), by applying 5V.

Register 1

•

Setup the device through Register 1 referencing Table 1.

a. The first 4 bits of the 32-bit code sent to the chip are set DB <3:0> to 0000; which is the address of

register 1.

b. Bit 5, DB4, sets the soft reset for the chip. Soft reset allows for the registers to be reset without

powering down the chip. If a soft reset is used then write to register 1 twice: once with DB4 set high

and once with DB4 set low. Typically, this bit is only used when the chip has been powered up and

registers 1, 2, and 3 have already been written to, so on power-up reset is not required, so DB4 is, by

default, set low.

c. DB <7: 5> sets the charge pump current based on the resistor value on pin 28 of the TRF3761 and

the decimal value of Register 1, DB<7:5> used in Equation 1. This equation reduces to Equation 2,

where N = decimal value of [Reg1 DB<7:5>].

d. DB <9: 8> sets the mode of the chip. The mode is how the device will or will not divide down the

VCO’s frequency. There are 3 choices for the mode setting, divide by 1, 2 or 4 per Table 1. For

example if 525MHz is required from the TRF3761 which has a main frequency of 1575MHz then the

divide-by-4 mode is chosen by setting DB <9: 8> to 10.

e. DB <11:10> controls the output buffer. Both of these are set to 00 by default, so the buffer is

controlled internally. See Table 1 for more information.

f. DB <25:12> sets the RDiv value. Once the calculations under the Synthesizing a Selected Frequency

section have been completed the value is known, based on the external reference oscillator. The

value for R is entered into the DB <25:12>. For example, if the reference oscillator is at a frequency

(F_{REF_IN}) of 61.44MHz and a channel step size of 120kHz is required, which is also the frequency

(F_PFD) the phase frequency detector will use to compare against the VCO's output frequency (F_OUT),

then F_{REF_IN}/F_PFD= 512, which is entered as follows: MSB: LSB 0001000000000.

g. By default, DB <27:26> are set to 00 for a 1.5ns delay on the anti-backlash pulse width. See Table 1

for more information.

h. DB 28 is set to 1 for positive by default. See Table 1 for more information.

i. DB 29 is set to 0 for normal operation. See Table 1 for more information.

j. DB 30 is set to 0 by default. See Table 1 for more information.

k. DB 31 is set to 0 by default. See Table 1 for more information.

Register 2

•

Initiate calibration procedure by programming register 2 as follows: Reference Table 2

a. The first 4 bits of the 32-bit code sent to the chip are set DB <3:0> to 0001; which is the address of

register 2.

b. Use bits DB<17, 4> of register 2 to specify the input reference frequency in MHz. The value is split

into an integer and a fraction part. For example: to insert a f_REFof 30.72MHz, set:

–

DB<10, 4> (integer part) equal to 0011110 (30) and

DB<17, 11> (fraction part) equal to 1001000 (72).

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APPLICATION INFORMATION (continued)

c. Set DB<30:18> of register 2 to the desired frequency. For example: 2200MHz would be

0100010011000 (2200).

d. Set DB31of register 2 to 1 to start the calibration. The VCO calibration runs for 5ms. During the cal

procedure it will not be possible to program register 2 and 3. At the end of the calibration, bit DB31 of

register 2 resets to 0.

e. Subsequent frequency programming requires DB31 to be set to 0.

Register 3

•

Completion of the frequency set up, on initial calibration, cannot proceed until 5ms has elapsed, due to full

calibration, then it will require that the A and B values, the prescalar ratio, be known. See Synthesizing a

Selected Frequency section below for calculation. Reference Table 3.

a. The first 4 bits of the 32-bit code sent to the chip are set DB <3:0> to 0010; which is the address of

register 3.

b. DB<5:4> sets the prescalar ratio, 8/9, 16/17, 32/33, 64/65. For example: if 16/17 are required, set the

register bits DB<5:4> to 01.

c. DB<11:6> sets the A value for the N counter. For example: if A is 4, set DB<11:6> as follows: 000100

(4).

d. DB<24:12> sets the B value for the N counter. For example: if B is 1156, set DB<24:12> as follows:

0010010000100 (4).

e. DB<28:25> sets the TEST_MUX. This allows the user to check via the microcontroller the state of the

TRF3761 by programming it to one of 6 states. The most common state to use is the Digital lock

Detect which places the pin in a logic high state with indicates the VCO is locked.

Table 4. MUX-Out Settings

STATE

DB<28:25>

0000

STATE

DB<28:25>

0100

3-state o/p ( High impedance state on Pin 39)

Digital lock Detect (High when locked on Pin 39)

N-Divider o/p (Shows N-value on Pin 39)

DVDD (internal TI use)

RDiv o/p (Shows R-value on Pin 39)

Analog lock detect (High when locked on Pin 39)

Read back ( read back register settings)

DGND (internal TI use)

0001

0101

0010

0110

0011

0111

f. DB29 sets the START LOCK, which is set to 0, on the initial frequency setup and then set to 1 on

additional frequency changes.

Once all registers are written, the TRF3761 will lock to the desired frequency. In order to change the frequency

once the initial calibration is complete, only registers 2 and 3 need to be reprogrammed. No calibration is

required.

Re-Calibration After Power Up

Assuming the TRF3761 is powered up and operational, a VCO calibration is also possible without powering

down the IC. To perform such calibration the following procedure is recommended:

•

Set bit DB4 (RESET) of register 1 to 1. This performs a software reset and clears all registers of VCO

calibration data. Once the reset command is issued then DB4 of register 1 will need to be set to 0.

•

Repeat the Initial Calibration and Frequency setup at Power up section, skipping the power up section and

performing the register programming sequence.

40

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Synthesizing a Selected Frequency

The TRF3761 is an integer-N PLL synthesizer, and because of its flexibility (14-bit RDiv, 6-bit A counter, 13-bit B

counter, and dual modulus prescaler), is ideal for synthesizing virtually any desired frequency. If synthesizing a

900MHz local oscillator, with spacing capability (minimum frequency increment) of 200kHz, as in a typical GSM

application, the choice of the external reference oscillator is beyond the scope of this section. However, if a

10MHz reference is selected, the settings are calculated to yield the desired output frequency and channel

spacing. There is more than one solution to a specific set of conditions, so below is one way of achieving the

desired result. First, select the appropriate RDiv counter value. Since a channel spacing of 200kHz is desired,

the F_PFDis set to 200kHz. Calculate the RDiv value through:

RDiv = F_REFIN/F_PFD= 10MHz/ 200kHz = 50.

Assume a prescaler value of 8/9 is selected. This is a valid choice, since the prescaler output is well within the

200MHz limit (900MHz / 8 = 112.5MHz). Select the appropriate A and B counter values.

RFOUT = F_PFD× N = (F_REFIN/ RDiv) × (A counter + Prescalar numerator × B counter).

Therefore, the following equation must be solved:

900MHz = 200kHz x (A + 8 × B).

There are many solutions to this single equation with two unknowns; there are some basic constraints on the

solution, since 3 ≤ B ≤ 8191, and also B ≥ A. So, if A = 4, solving the equation yields B = 562. One complete

solution would be to choose:

RDiv = 50, A counter = 4, Bcounter = 562 and Prescalar = 8/9

resulting in the desired N counter value = 4500. This is how the A counter, B counter and prescalar make up the

N counter.

When this procedure is complete the values for the N counter , R, and the prescalar ratio should be known.

Registers 2 and 3 need to be set up for operation of the chip. See Table 2 and Table 3 for this procedure.

Register 2 bits <DB30:DB18> 12:0 set the output frequency of the device along with register 3. See the

N-Divider section under the Functional Description.

Application Schematic

Figure 78 shows a typical application schematic for the TRF3761. In this example, the output signal is taken

differential using the 2 resistive pull-up resistors of the final output buffer. A single-ended and tuned load

configuration is also available.

The loop filter components:

C1 = 303pF, R1 = 8.87kΩ, C2 = 1650pF, R2 = 3.4kΩ, C3 = 330pF

are typical ones used for the plots shown above. Those values can be optimized differently according to the

requirements of the different applications.

41

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(See Note A)

R2

C1

C3

R1

C2

C4

1000 pF

40 39 38 37 36 35 34 33 32 31

1

30

29

28

27

26

25

24

23

22

21

PD_OUTBUF

CHIP_EN

CLOCK

GND

R3

2.37 kΩ

2

AVDD_BIAS

RBIAS1

3

4

DATA

GND

5

STROBE

DGND

VCTRL_IN

AVDD_VCO

AVDD_BUF

TRF3761

(TOP VIEW)

6

7

DGND

8

DVDD1

AVDD_CAPARRAY

GND

9

AVDD_PRES

GND

10

AVDD

11 12 13 14 15 16 17 18 19 20

R4

4.75 kΩ

C7

1000 pF

R5

120 Ω

R6

120 Ω

V

DD

V

DD

C5

10 pF

C6

10 pF

LOAD

A. Refer to the Application Information section Loop Filter Design.

Figure 78. TRF3761 Application Schematic

Loop Filter Design

Numerous methodologies and design techniques exist for designing optimized loop filters for particular

applications. The loop filter design can affect the stability of the loop, the lock time, the bandwidth, the extra

attenuation on the reference spurs, etc. The role of the loop filter is to integrate and lowpass the pulses of the

charge pump and eventually yield an output tuning voltage that drives the VCO. Several filter topologies can be

implemented, including both passive and active. In this section, a third-order passive filter is used. For this

example, assume these several design parameters. The internal VCO has a value of 23MHz/V, meaning that in

the linear region, changing the tuning voltage of the VCO by 1V induces a change of the output frequency of

42

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about 23MHz. It is known that N = 4500 and Fpfd = 200kHz from our previous example. It is assumed that

current setting in register 1 <DB7:DB5> is set to 100 and sets a maximum current of 5.6mA.TI recommends an

Icp of 5.6mA, which give the best spur performance, but can be changed for different application. In addition, the

bandwidth of the loop filter must be determined. This is a critical consideration as it affects the lock time of the

system. Assuming an approximate bandwidth of around 20kHz is required and that for stability a phase margin

of about 45 degrees is desired, the following values for the components of the loop filter can be derived. There is

almost an infinite number of solutions to the problem of designing the loop filter and the designer is called to

make tradeoff decisions for each application. Texas Instruments has provided a loopfilter program in the product

folder for the TRF3761.

Some terms are interchangeable and are described and equated here:

•

F_com= F_PDFwhich identify the comparing frequency or phase detector frequency which is also equal to the

system channel step size. F_OUTmust be a multiple of F_com

F_minis the lower frequency of the design band.

F_maxis the upper frequency of the design band.

.

•

F_refis the reference frequency for the PLL. Fref must be a multiple of F_com

.

K_vco= Kv expressed in MHz per Volt (MHz/V) which is the gain of the VCO. The TRF3761 internal VCO has

a Kv = 23MHz/V.

•

I_cpis the charge pump current. The TRF3761 is typically set to 5.6mA.

F_cis the loop filter bandwidth which should be no more than 1/10 F_com

.

φ is phase margin in degrees. Values should be between 30 and 70. The higher the phase margin the better

the stability of the PLL but the slower the lock time. 45 degrees is a good tradeoff.

•

T3/T1 in percent is the percentage of the poles in the loop filter. Usually set to 45%. The higher the value

(closer to 100%) the more the spurs are attenuated, but peaking occurs in the pass band of the loop filter.

F

=

F F

min max

OUT

(8)

F

OUT

N =

F

com

(9)

v

= 2πF

c

(10)

æ

ö

1

cosf

æ

- tanf

ç

è

÷

ø

T1=

T3

ö

v

1 +

c ç

÷

T1

è

ø

(11)

(12)

T3

T1

æ

ö

T3 =

T

1

ç

÷

è

ø

1

T2 =

2

c

v

T1+T3

(

)

(13)

1

2

é

ê

ù

ú

2

1 + v T2

K

Kf

x

(

)

T1

T2

c

VCO

C1 =

×

2

c

2

v N

1 + v T1

1 + v T3

c

( )( )

c

ê

ú

ë

û

(14)

T2

T1

C1

æ

ö

÷

C2 = C1

- 1 , C3 =

ø

ç

10

è

(15)

(16)

T2

T3

R1 =

, R2 =

C2

C3

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Loop filter components:

C1 = 303pF

R1 = 8.87kW

R2 = 3.4kW

C2 = 1650pF

C3 = 330pF

Frequency jump from

1046MHz to 1085MHz:

Locktime freq ~ 250mS

Figure 79. Frequency Locktime

Loop Filter Design Example

Given these parameters which were used for the lock time plot Figure 79:

•

F_min= 2085 MHz

F_max= 2175 MHz

F_com= 400 KHz

Icp = 4.2mA

Kvco = 23 MHz

Fc = 20 KHz

Phase Margin = 45 degrees

T3/T1 = 45%

Calculate F_OUTof design

F

=

F

F = 2130MHz (rounded up)

OUT

min max

(17)

Next calculate N

F

OUT

N =

= 5325

F

com

(18)

(19)

Then calculate ωc

= 2πF = 125.66 x 10

3

v

c

Now calculate T1-T3 to give the RC time constants.

æ

ö

1

cosf

æ

- tanf

ç

è

÷

ø

-6

T =

1

= 2.3 x 10

T

ö

3

v

1 +

ç

÷

c

T

1

è

ø

(20)

(21)

Use T1 to find T3

T

æ

ö

÷

ø

-6

3

T

=

T = 1 x 10

1

ç

3

T

1

è

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Then use T1 and T3 to find T2

1

-6

T

=

= 19.2 x 10

2

C

v

T + T

1 3

(

)

(22)

Now C1, C2, C3, R1, and R2 are calculated using T1, T2, and T3.

1

é

ê

ù

ú

2

1 + v T

K

Kf

(

)

T

c 2

1

VCO

C1 =

×

= 338.75pF

2

c

T

2

2 2

2

v N

1 + v T

c

1 + v T

( )( )

c

ê

ú

1

3

ë

û

(23)

æ

ö

T

2

C2 = C1

- 1 = 2524.14pF

ç

÷

T

1

è

ø

(24)

(25)

C1

C3 =

= 33.87pF

10

Now using C2 and T2, find R2. Use C3 and T3 to find R3

T

2

R2 =

= 7.61kΩ

C

2

(26)

(27)

T

3

R3 =

= 30.2kΩ

C

3

R2 x C3 can be scaled using T3, so if C3 = 330pF, then R2 = 3.03 kΩ => 3.4 kΩ in the loop filter. R1 x C2 can

be scaled using T2. Scaling these values helps to improve the lock time. The actual values used in the lock time

plot were optimized for lock time as well as using real valued components. The values in figure 62 were taken

from the current EVM schematic.

Layout/PCB Considerations

This section of the design of the complete PLL is of paramount importance in achieving the desired

performance. Wherever possible, a multi-layer PCB board should be used, with at least one dedicated ground

plane. A dedicated power plane (split between the supplies if necessary) is also recommended. The impedance

of all RF traces (the VCO output and feedback into the PLL) should be controlled to 50Ω. All small value (10pF

and 0.1uF) decoupling capacitors should be placed as close to the device pins as possible. It is also

recommended that both top and bottom layers of the circuit board be flooded with ground, with plenty of ground

vias dispersed as appropriate. Because the digital lines are not in use during normal operation of the device and

are only used to program the device on start up and during frequency changes the analog grounds (GND) and

digital grounds (DGND) are tied to the same ground plain. The most sensitive part of any PLL is the section

between the charge pump output and the input to the VCO. This includes the loop filter components, and the

corresponding traces. The charge pump is a precision element of the PLL and any extra leakage on its path can

adversely affect performance. Extra care should be given to ensure that parasitics are minimized in the charge

pump output, and that the trace runs are short and optimized. Similarly, it is also recommend that extra care is

taken in ensuring that any flux residue is thoroughly cleaned and moisture baked out of the PCB. From an EMI

perspective, and since the synthesizer is typically a small portion of a bigger, complex circuit board, shielding is

recommended to minimize EMI effects.

45

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Via to bottom ground

BOTTOM

GND

TOP

GND

De-coupling

Capacitor’s

on back side

of board

De-coupling

Capacitor’s

on top side

of board

BOTTOM

GND

A. See the Application Information section for Loop Filter Design procedures.

Figure 80. TRF3761 Layout

Application Example for a High Performance RF Transmit Signal Chain

Much in the same way as described above, the TRF3761 is an ideal synthesizer to use in implementing a

complete high performance RF transmitter chain such as the TSW3000 and TSW3003 Demonstration kits.

Using a complete suite of high performance Texas Instruments components, a state-of-the-art transmitter can be

implemented featuring excellent performance. Texas Instruments offers ideal solutions for the digital-to-analog

conversion portion of transmitter as well as the analog and RF components needed to complete the transmitter.

The baseband digital data is converted to I and Q signals through the dual DAC5687, which features a 16-bit

interpolating dual digital-to-analog converter (DAC). The device incorporates a digital modulator, independent

differential offset control, and I/Q amplitude control. The device is typically used in baseband mode or in low IF

mode in conjunction with an analog quadrature modulator. The DAC5687, after filtering, feeds a TRF3703, which

is a direct, upconversion IQ modulator. This device accepts a differential input voltage quadrature signal at

baseband or low IF frequencies and outputs a modulated RF signal based on the LO drive frequency. The LO

46

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drive input of the IQ modulator is generated by the TRF3761. The TRF3761 is a family of high performance,

highly integrated frequency synthesizers, optimized for wireless infrastructure applications. The TRF3761

includes an integrated VCO and integer-N PLL. Different members of the TRF3761 family can be chosen for

application specific VCO frequency ranges. In addition, the CDC7005 clocking solution can be used to clock the

DAC and other portions of the transmitter. A block diagram of the proposed architecture is shown in Figure 81

and Figure 82. For more details, contact Texas Instruments directly.

Digital-to-RF Up Converter

Gain and Power Amplifier

TX

DAC

LPA

ANT

0°

90°

I/Q

Modulator

Diplexer

I/Q

Demod

A/D

RX

LNA

LO-to-Digital Conveter

Low Noise Amplifier and

RF-to-LO Down Converter

Figure 81. Transmit Chain Block Diagram

16

TRF3703

I/Q

RF Out

DAC5687

Modulator

16

CLK1

CLK2

CDCM7005

Clock Generator

VCXO

TRF3761

PLL

LO Generator

Ref Osc

Figure 82. Transmit Chain Block Diagram

47

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PACKAGE OPTION ADDENDUM

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16-Mar-2007

PACKAGING INFORMATION

Orderable Device

Status ⁽¹⁾

Package Package

Pins Package Eco Plan ⁽²⁾Lead/Ball Finish MSL Peak Temp ⁽³⁾

Qty

Type

QFN

Drawing

TRF3761-AIRHAR

TRF3761-AIRHAT

TRF3761-BIRHAR

PREVIEW

ACTIVE

RHA

40

2500

250

TBD

Call TI

RHA

2500 Green (RoHS & CU NIPDAU Level-3-260C-168 HR

no Sb/Br)

TRF3761-BIRHARG4

TRF3761-BIRHAT

TRF3761-BIRHATG4

TRF3761-CIRHAR

TRF3761-CIRHARG4

TRF3761-CIRHAT

TRF3761-CIRHATG4

TRF3761-DIRHAR

TRF3761-DIRHARG4

TRF3761-DIRHAT

TRF3761-DIRHATG4

TRF3761-EIRHAR

TRF3761-EIRHARG4

TRF3761-EIRHAT

TRF3761-EIRHATG4

TRF3761-FIRHAR

TRF3761-FIRHARG4

TRF3761-FIRHAT

ACTIVE

QFN

RHA

40

2500 Green (RoHS & CU NIPDAU Level-3-260C-168 HR

no Sb/Br)

250 Green (RoHS & CU NIPDAU Level-3-260C-168 HR

no Sb/Br)

250 Green (RoHS & CU NIPDAU Level-3-260C-168 HR

no Sb/Br)

2500 Green (RoHS & CU NIPDAU Level-3-260C-168 HR

no Sb/Br)

2500 Green (RoHS & CU NIPDAU Level-3-260C-168 HR

no Sb/Br)

250 Green (RoHS & CU NIPDAU Level-3-260C-168 HR

no Sb/Br)

250 Green (RoHS & CU NIPDAU Level-3-260C-168 HR

no Sb/Br)

2500 Green (RoHS & CU NIPDAU Level-3-260C-168 HR

no Sb/Br)

2500 Green (RoHS & CU NIPDAU Level-3-260C-168 HR

no Sb/Br)

250 Green (RoHS & CU NIPDAU Level-3-260C-168 HR

no Sb/Br)

250 Green (RoHS & CU NIPDAU Level-3-260C-168 HR

no Sb/Br)

2500 Green (RoHS & CU NIPDAU Level-3-260C-168 HR

no Sb/Br)

2500 Green (RoHS & CU NIPDAU Level-3-260C-168 HR

no Sb/Br)

250 Green (RoHS & CU NIPDAU Level-3-260C-168 HR

no Sb/Br)

250 Green (RoHS & CU NIPDAU Level-3-260C-168 HR

no Sb/Br)

2500 Green (RoHS & CU NIPDAU Level-3-260C-168 HR

no Sb/Br)

2500 Green (RoHS & CU NIPDAU Level-3-260C-168 HR

no Sb/Br)

250 Green (RoHS & CU NIPDAU Level-3-260C-168 HR

no Sb/Br)

TRF3761-FIRHATG4

TRF3761-GIRHAR

TRF3761-GIRHARG4

TRF3761-GIRHAT

TRF3761-GIRHATG4

250 Green (RoHS & CU NIPDAU Level-3-260C-168 HR

no Sb/Br)

2500 Green (RoHS & CU NIPDAU Level-3-260C-168 HR

no Sb/Br)

2500 Green (RoHS & CU NIPDAU Level-3-260C-168 HR

no Sb/Br)

250 Green (RoHS & CU NIPDAU Level-3-260C-168 HR

no Sb/Br)

250 Green (RoHS & CU NIPDAU Level-3-260C-168 HR

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

16-Mar-2007

Orderable Device

Status ⁽¹⁾

Package Package

Pins Package Eco Plan ⁽²⁾Lead/Ball Finish MSL Peak Temp ⁽³⁾

Qty

Type

Drawing

no Sb/Br)

TRF3761-HIRHAR

TRF3761-HIRHARG4

TRF3761-HIRHAT

TRF3761-HIRHATG4

TRF3761-JIRHAR

TRF3761-JIRHARG4

TRF3761-JIRHAT

ACTIVE

QFN

RHA

40

2500 Green (RoHS & CU NIPDAU Level-3-260C-168 HR

no Sb/Br)

2500 Green (RoHS & CU NIPDAU Level-3-260C-168 HR

no Sb/Br)

250 Green (RoHS & CU NIPDAU Level-3-260C-168 HR

no Sb/Br)

250 Green (RoHS & CU NIPDAU Level-3-260C-168 HR

no Sb/Br)

2500 Green (RoHS & CU NIPDAU Level-3-260C-168 HR

no Sb/Br)

2500 Green (RoHS & CU NIPDAU Level-3-260C-168 HR

no Sb/Br)

250 Green (RoHS & CU NIPDAU Level-3-260C-168 HR

no Sb/Br)

TRF3761-JIRHATG4

250 Green (RoHS & CU NIPDAU Level-3-260C-168 HR

no Sb/Br)

TRF3761-KIRHAR

TRF3761-KIRHAT

PREVIEW

QFN

RHA

40

2500

250

TBD

Call TI

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered

at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and

package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS

compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame

retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is

provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the

accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take

reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on

incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited

information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI

to Customer on an annual basis.

Addendum-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

17-May-2007

TAPE AND REEL INFORMATION

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

17-May-2007

Device

Package Pins

Site

TAI

Reel

Diameter Width

(mm)

Reel

A0 (mm)

6.3

B0 (mm)

6.3

K0 (mm)

1.5

P1

W

Pin1

(mm) (mm) Quadrant

(mm)

TRF3761-BIRHAR

TRF3761-BIRHAT

TRF3761-CIRHAR

TRF3761-CIRHAT

TRF3761-DIRHAR

TRF3761-DIRHAT

TRF3761-EIRHAR

TRF3761-EIRHAT

TRF3761-FIRHAR

TRF3761-FIRHAT

TRF3761-GIRHAR

TRF3761-GIRHAT

TRF3761-HIRHAR

TRF3761-HIRHAT

TRF3761-JIRHAR

TRF3761-JIRHAT

RHA

40

330

16

12

16 PKGORN

T2TR-MS

P

330

16

6.3

1.5

16 PKGORN

T2TR-MS

P

6.3

1.5

16 PKGORN

T2TR-MS

P

6.3

1.5

16 PKGORN

T2TR-MS

P

6.3

1.5

16 PKGORN

T2TR-MS

P

6.3

1.5

16 PKGORN

T2TR-MS

P

6.3

1.5

16 PKGORN

T2TR-MS

P

6.3

1.5

16 PKGORN

T2TR-MS

P

6.3

1.5

16 PKGORN

T2TR-MS

P

6.3

1.5

16 PKGORN

T2TR-MS

P

6.3

1.5

16 PKGORN

T2TR-MS

P

6.3

1.5

16 PKGORN

T2TR-MS

P

6.3

1.5

16 PKGORN

T2TR-MS

P

6.3

1.5

16 PKGORN

T2TR-MS

P

6.3

1.5

16 PKGORN

T2TR-MS

P

6.3

1.5

16 PKGORN

T2TR-MS

P

Pack Materials-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

17-May-2007

TAPE AND REEL BOX INFORMATION

Device

Package

Pins

Site

Length (mm) Width (mm) Height (mm)

TRF3761-BIRHAR

TRF3761-BIRHAT

TRF3761-CIRHAR

TRF3761-CIRHAT

TRF3761-DIRHAR

TRF3761-DIRHAT

TRF3761-EIRHAR

TRF3761-EIRHAT

TRF3761-FIRHAR

TRF3761-FIRHAT

TRF3761-GIRHAR

TRF3761-GIRHAT

TRF3761-HIRHAR

TRF3761-HIRHAT

TRF3761-JIRHAR

TRF3761-JIRHAT

RHA

40

TAI

342.9

336.6

28.58

Pack Materials-Page 3

PACKAGE MATERIALS INFORMATION

www.ti.com

17-May-2007

Pack Materials-Page 4

IMPORTANT NOTICE

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Following are URLs where you can obtain information on other Texas Instruments products and application solutions:

Products

Amplifiers

Data Converters

DSP

Applications

Audio

amplifier.ti.com

dataconverter.ti.com

dsp.ti.com

www.ti.com/audio

Automotive

Broadband

Digital Control

Military

www.ti.com/automotive

www.ti.com/broadband

www.ti.com/digitalcontrol

www.ti.com/military

Interface

interface.ti.com

logic.ti.com

Logic

Power Mgmt

Microcontrollers

RFID

power.ti.com

Optical Networking

Security

www.ti.com/opticalnetwork

www.ti.com/security

www.ti.com/telephony

www.ti.com/video

microcontroller.ti.com

www.ti-rfid.com

www.ti.com/lpw

Telephony

Low Power

Wireless

Video & Imaging

Wireless

www.ti.com/wireless

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	TRF3761-FIRHARG4
厂家：	TEXAS INSTRUMENTS
描述：	INTEGER-N PLL WITH INTEGRATED VCO 集成VCO的整数N分频PLL 信号电路锁相环或频率合成电路
文件：	总56页 (文件大小：1456K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

TRF3761-FIRHARG4 [TI]

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