TRF376117IRHAR [TI]
IC,FREQUENCY SYNTHESIZER,LLCC,40PIN,PLASTIC;
| 型号： | TRF376117IRHAR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | IC,FREQUENCY SYNTHESIZER,LLCC,40PIN,PLASTIC |
| 文件： | 总36页 (文件大小：1125K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TRF3761
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SLWS181A–OCTOBER 2005–REVISED AUGUST 2006
INTEGER-N PLL WITH INTEGRATED VCO
FEATURES
RHA PACKAGE
(TOP VIEW)
•
Fully Integrated VCO
•
Low Phase Noise: –138dBc/Hz (at 600kHz,
fVCO of 1.9GHz )
•
•
•
Low Noise Floor: –160dBc/Hz at 10MHz Offset
Integer-N PLL
40 39 38 37 36 35 34 33 32 31
1
30
29
28
27
26
25
24
23
22
21
PD_OUTBUF
CHIP_EN
CLOCK
DATA
GND
Input Reference Frequency range: 10MHz to
104MHz
2
AVDD_BIAS
RBIAS1
3
•
•
•
•
•
•
•
VCO Frequency Divided by 2-4 Output
Output Buffer Enable Pin
4
GND
5
STROBE
GND
VCTRL_IN
AVDD_VCO
AVDD_BUF
AVDD_CAPARRAY
GND
Programmable Charge Pump Current
Hardware and Software Power Down
3-Wire Serial Interface
6
7
GND
8
DVDD1
AVDD_PRES
GND
9
Single Supply: 4.5V to 5.25V Operation
Silicon Germanium Technology
10
AVDD
11 12 13 14 15 16 17 18 19 20
APPLICATIONS
•
Wireless Infrastructure
– WCDMA
– CDMA
– GSM
AVAILABLE DEVICE OPTIONS
PART NUMBER
DIV1 MODE
DIV2 MODE
Fstart
DIV4 MODE
Fstart
Fstart
1500
1600
1726
1850
2080
2175
Fstop
1658
1700
1908
2045
2180
2404
Fstop
829.0
850
Fstop
414.50
425
TRF3761-1579
TRF3761-1700
TRF3761-1817
TRF3761-1947
TRF3761-2116
TRF3761-2289
750.0
800
375.00
400
863.0
925.0
1040
954.0
1022.5
1090
431.50
462.50
520
477.00
511.25
545
1087.5
1202.0
543.75
601.00
DESCRIPTION
TRF3761 is a family of high performance, highly integrated frequency synthesizers, optimized for wireless
infrastructure applications. The TRF3761 includes a low-noise, voltage-controlled oscillator (VCO) and an
integer-N PLL.
TRF3761 integrates divide-by 1, 2, or 4 options for a more flexible output frequency range. It is controlled
through a 3-wire serial-interface-programming (SPI) interface. It can be powered down when not used by the
SPI or external pin.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCT PREVIEW information concerns products in the
Copyright © 2005–2006, Texas Instruments Incorporated
formative or design phase of development. Characteristic data and
other specifications are design goals. Texas Instruments reserves
the right to change or discontinue these products without notice.
TRF3761
www.ti.com
SLWS181A–OCTOBER 2005–REVISED AUGUST 2006
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be
more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
VCOs
Lock
Det
Serial
Interface
GNDs
REF_IN
R Div
Charge
Pump
PFD
CPOUT
VCTRL
N−Divider
B−
counter
A−
counter
Prescaler
div p/p+1
VCO_OUTM
VCO_OUTP
Div1/2/4
Power
Down
CHIP_ENABLE
2
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TRF3761
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SLWS181A–OCTOBER 2005–REVISED AUGUST 2006
DEVICE INFORMATION
TERMINAL FUNCTIONS
TERMINAL
I/O
DESCRIPTION
NAME
NO.
1
PD_OUTBUF
CHIP_EN
CLOCK
I
Output buffer power down
Chip enable
2
I
3
I
I/O
I
Serial interface clock
Serial interface data
Serial interface strobe
Digital ground
DATA
4
STROBE
5
GND
6, 7
8
DVDD1
Power supply for DIG regulator
Power supply for prescaler
VCO output
AVDD_PRES
VCO_OUTP
VCO_OUTM
AVDD_OUTBUF
AVDD_VCOBUF
EXT_VCO_IN
RBIAS2
9
13
14
15
17
18
19
21
23
24
25
26
28
29
O
O
VCO output
Power supply for output buffers
Power supply for VCO buffers
External VCO input to prescaler
External bias resistor
Analog power supply
I
I/O
AVDD
AVDD_CAPARRAY
AVDD_BUF
AVDD_VCO
VCTRL_IN
Power supply for VCO core and buffer
Power supply for VCO core and buffer
Power supply for VCO core and buffer
VCO control voltage
I
RBIAS1
I/O
External bias resistor
AVDD_BIAS
Power supply for BG current bias
10, 11, 12, 16, 20, 22,
27, 30, 31, 33, 37
GND
Analog ground
AVDD
32
34
35
36
38
39
40
Power supply for FUSE cell
Charge pump output
CPOUT
O
AVDD_CP
AVDD_REF
REF_IN
Analog power supply for charge pump
Power supply for REF FREQ block
Reference signal input
I
LOCK_DETECT
DVDD2
O
Lock detect output
Power supply for DIG regulator
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)(1)
VALUE
–0.3 to 5.5
–0.3 to VI +0.3
–40 to 150
–40 to 85
UNIT
V
Supply voltage range(2)
Digital I/O voltage range
V
TJ
Operating virtual junction temperature range
Operating free-air temperature range
Storage temperature range
°C
°C
°C
TA
Tstg
–65 to 150
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to network ground terminal.
3
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SLWS181A–OCTOBER 2005–REVISED AUGUST 2006
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
5.25
UNIT
VCC
Power supply voltage
4.5
5
V
PACKAGE/ORDERING INFORMATION(1)
SPECIFIED
TEMPERATURE
RANGE
PACKAGE
LEAD
PACKAGE
PACKAGE
MARKINGS
ORDERING
NUMBER
TRANPORT MEDIA,
QUANITY
PRODUCT
DESIGNATOR(2)
TRF376115IRHAR
TRF376115IRHAT
TRF376117IRHAR
TRF376117IRHAT
TRF376118IRHAR
TRF376118IRHAT
TRF376119IRHAR
TRF376119IRHAT
TRF376121IRHAR
TRF376121IRHAT
TRF376122IRHAR
TRF376122IRHAT
Tape and Reel, 2500
Tape and Reel, 250
Tape and Reel, 2500
Tape and Reel, 250
Tape and Reel, 2500
Tape and Reel, 250
Tape and Reel, 2500
Tape and Reel, 250
Tape and Reel, 2500
Tape and Reel, 250
Tape and Reel, 2500
Tape and Reel, 250
TRF3761-1579
TRF3761-1700
TRF3761-1817
TRF3761-1947
TRF3761-2116
TRF3761-2289
QFN-40
RHA
–40°C to 85°C
–40°C to 85°C
–40°C to 85°C
-40°C to 85°C
–40°C to 85°C
–40°C to 85°C
TRF3761-1579
TRF3761-1700
TRF3761-1817
TRF3761-1947
TRF3761-2116
TRF3761-2289
QFN-40
QFN-40
QFN-40
QFN-40
QFN-40
RHA
RHA
RHA
RHA
RHA
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
(2) Thermal pad size: 177 × 177 mils.
THERMAL CHARACTERISTICS
over operating free-air temperature range (unless otherwise noted)
PARAMETER(1)
TEST CONDITIONS
Soldered slug, no airflow
MIN
TYP
26
MAX
UNIT
°C/W
°C/W
°C/W
θJA
Thermal derating, junction-to-ambient
Soldered slug, 200-LFM airflow
Soldered slug, 400-LFM airflow
20.1
17.4
(1) Determined using JEDEC standard JESD-51 with High K board
4
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SLWS181A–OCTOBER 2005–REVISED AUGUST 2006
ELECTRICAL CHARACTERISTICS
Supply voltage = 4.5V to 5.25V, over operating free-air temperature range (unless otherwise noted)
PARAMETER
DC Parameters
TEST CONDITIONS
MIN
TYP
MAX UNIT
Divide by 1 output
Divide by 2 output
Divide by 4 output
130
140
150
mA
mA
mA
ICC
Total supply current
TA = 25°C
Reference Oscillator Parameters
fref
Reference frequency
10
104 MHz
2.5 Vpp
Reference input sensitivity
0.2
Parallel capacitance
Parallel resistance
5
6.52
pF
Reference input impedance
3913
Ω
PFD Charge Pump
PFD frequency
30 MHz
mA
Charge pump current
Digital Interface
SPI programmable
5.6
VIH
VIL
High-level input voltage
Low-level input voltage
2.5
0
VCC
V
V
V
0.8
VOH High-level output voltage
0.8VC
C
VOL Low-level output voltage
0.2VCC
V
TIMING REQUIREMENTS
Supply voltage = 4.5V to 5.25V, over operating free-air temperature range (unless otherwise noted)
PARAMETER
Clock period
TEST CONDITIONS
MIN
50
TYP
MAX UNIT
t(CLK)
tsu1
th
ns
ns
ns
ns
ns
Setup time, data
10
Hold time, data
10
tw
Pulse width, STROBE
Setup time, STROBE
20
tsu2
10
t
t
h
su1
t
(CLK)
1” Clock Pike
CLOCK
DB0 (LSB)
Address bit 1
DB1
Address bit 2
DB2
Address bit 3
DB29
Cmd bit 30
DB30
Cmd bit 31
DB31 (MSB)
Cmd bit 32
DATA
t
t
su2
w
STROBE
A. The first 4 bits, DB(3-0), of data are Address bits. The 28 remaining bits, DB(31-4), are part of the command. The
command is little endian or lower bits first.
Figure 1. Serial Programming Timing Diagram
5
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TRF3761
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SLWS181A–OCTOBER 2005–REVISED AUGUST 2006
TRF3761-1579 ELECTRICAL CHARACTERISTICS
Supply voltage = 5V, over operating free-air temperature range (unless otherwise noted)
PARAMETER
NOISE CHARACTERISTICS
TEST CONDITIONS
MIN
TYP
MAX
UNIT
100kHz offset
–116
–138.5
-141
600kHz offset
1MHz offset
6MHz offset
10MHz offset
100kHz offset
600kHz offset
1MHz offset
6MHz offset
10MHz offset
100kHz offset
600kHz offset
1MHz offset
6MHz offset
10MHz offset
1kHz offset
VCO phase noise,
Free running VCO direct output
fVCO = 1579MHz,
fO = 1579MHz
dBc/Hz
dBc/Hz
–156
–159.5
–122
–143
VCO phase noise,
Free running VCO divide-by-2 output
fVCO = 1579MHz,
fO = c
–148
–157.5
–158.5
–126
-149
VCO phase noise,
Free running VCO divide-by-4 output
fVCO = 1579MHz,
fO = 394.75MHz
-152.4
–155.5
–155.7
–85.5
–136
dBc/Hz
dBc/Hz
600kHz offset
1MHz offset
10MHz offset
VCO phase noise,
fVCO = 1579MHz,
fO = 1579MHz
Closed loop phase noise direct output(1)(2)(3)
–140.5
–158.9
RMS phase error
100Hz to 10MHz
fVCO = 1579MHz,
0.84°
Closed loop phase noise direct output(3)
1kHz offset
–91.5
–143.5
–147
600kHz offset
1MHz offset
10MHz offset
VCO phase noise,
dBc/Hz
dBc/Hz
Closed loop phase noise divide-by-2 output(1)(2)(3) fO = 789.5MHz
–158.3
RMS phase error
100Hz to 10MHz
0.37°
Closed loop phase noise divide-by-2 output(3)
1kHz offset
-97.5
–149
600kHz offset
1MHz offset
10MHz offset
VCO phase noise,
fVCO = 1579MHz,
Closed loop phase noise divide-by-4 output(1)(2)(3) fO = 394.75MHz
–152
–155.7
RMS phase error
100Hz to 10MHz
0.17°
Closed loop phase noise divide-by-4 output(3)
VCO gain
Reference spur(2)
VCO free running
30
MHz/V
dBc
–80
(1) See Application Circuit
(2) PFD = 200kHz, Loop Filter BW = 15kHz, Output frequency step = 200kHz.
(3) Reference oscillator RMS phase error = 0.008250°, RMS jitter = 881.764 fs.
6
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SLWS181A–OCTOBER 2005–REVISED AUGUST 2006
TRF3761-1700 ELECTRICAL CHARACTERISTICS
Supply voltage = 5V, over operating free-air temperature range (unless otherwise noted)
PARAMETER
NOISE CHARACTERISTICS
TEST CONDITIONS
MIN
TYP
MAX
UNIT
100kHz offset
–120
–138
600kHz offset
1MHz offset
6MHz offset
10MHz offset
100kHz offset
600kHz offset
1MHz offset
6MHz offset
10MHz offset
100kHz offset
600kHz offset
1MHz offset
6MHz offset
10MHz offset
1kHz offset
VCO phase noise,
Free running VCO direct output
fVCO = 1700MHz,
fO = 1700MHz
-143
dBc/Hz
–156
–158
–127
–144.5
–149.5
–157.5
–158.4
–134
VCO phase noise,
Free running VCO divide-by-2 output
fVCO = 1700MHz,
fO = 850
dBc/Hz
-150.5
-153.8
–156
VCO phase noise,
Free running VCO divide-by-4 output
fVCO = 1700MHz,
fO = 425MHz
dBc/Hz
dBc/Hz
–156.3
–84
600kHz offset
1MHz offset
10MHz offset
–138
VCO phase noise,
fVCO = 1700MHz,
fO = 1700MHz
Closed loop phase noise direct output(1)(2)(3)
–141
–157.5
RMS phase error
100Hz to 10MHz
fVCO = 1700MHz,
0.86°
Closed loop phase noise direct output(3)
1kHz offset
–90
–144.5
–148
600kHz offset
1MHz offset
10MHz offset
VCO phase noise,
dBc/Hz
dBc/Hz
Closed loop phase noise divide-by-2 output(1)(2)(3) fO = 850MHz
–158
RMS phase error
100Hz to 10MHz
0.39°
Closed loop phase noise divide-by-2 output(3)
1kHz offset
–97.5
–150
–159
–156
600kHz offset
1MHz offset
10MHz offset
VCO phase noise,
fVCO = 1700MHz,
Closed loop phase noise divide-by-4 output(1)(2)(3) fO = 425MHz
RMS phase error
100Hz to 10MHz
0.17°
Closed loop phase noise divide-by-4 output(3)
VCO gain
Reference spur(2)
VCO free running
30
MHz/V
dBc
–80
(1) See Application Circuit
(2) PFD = 200kHz, Loop Filter BW = 15kHz, Output frequency step = 200kHz.
(3) Reference oscillator RMS phase error = 0.008250°, RMS jitter = 881.764 fs.
7
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SLWS181A–OCTOBER 2005–REVISED AUGUST 2006
TRF3761-1817 ELECTRICAL CHARACTERISTICS
Supply voltage = 5V, over operating free-air temperature range (unless otherwise noted)
PARAMETER
NOISE CHARACTERISTICS
TEST CONDITIONS
MIN
TYP
MAX
UNIT
100kHz offset
–120
–138.5
-143.5
–157
600kHz offset
1MHz offset
6MHz offset
10MHz offset
100kHz offset
600kHz offset
1MHz offset
6MHz offset
10MHz offset
100kHz offset
600kHz offset
1MHz offset
6MHz offset
10MHz offset
1kHz offset
VCO phase noise,
Free running VCO direct output
fVCO = 1817MHz,
fO = 1817MHz
dBc/Hz
dBc/Hz
–159
–126.5
–145
VCO phase noise,
Free running VCO divide-by-2 output
fVCO = 1817MHz,
fO = 908.5MHz
–150
–156.5
–159
–131
-149.5
-154
VCO phase noise,
Free running VCO divide-by-4 output
fVCO = 1817MHz,
fO = 454.25MHz
dBc/Hz
dBc/Hz
–159
–159
–84
600kHz offset
1MHz offset
10MHz offset
–138.5
–143.5
–159
VCO phase noise,
fVCO = 1817MHz,
fO = 1817MHz
Closed loop phase noise direct output(1)(2)(1)
RMS phase error
100Hz to 10MHz
1°
Closed loop phase noise direct output(1)
1kHz offset
–94
–145
–150
–159
VCO phase noise,
600kHz offset
1MHz offset
10MHz offset
fVCO = 1817MHz,
fO = 908.5MHz
Closed loop phase noise divide-by-2
dBc/Hz
dBc/Hz
output(1)(3)(4)
RMS phase error
100Hz to 10MHz
0.35°
Closed loop phase noise divide-by-2 output(3)
1kHz offset
–100
–149.5
–154
VCO phase noise,
600kHz offset
1MHz offset
10MHz offset
fVCO = 1817MHz,
fO = 454.25MHz
Closed loop phase noise divide-by-4
output(1)(3)(5)
–159
RMS phase error
100Hz to 10MHz
VCO free running
0.19°
Closed loop phase noise divide-by-4 output(3)
VCO gain
30
MHz/V
dBc
Reference spur(2)
–80
(1) See Application Circuit
(2) PFD = 200kHz, Loop Filter BW = 15kHz, Output frequency step = 200kHz.
(3) Reference oscillator RMS phase error = 0.008250°, RMS jitter = 881.764 fs.
(4) PFD = 400kHz, Loop Filter BW = 15kHz, Output frequency step = 200kHz.
(5) PFD = 400kHz, Loop Filter BW = 15kHz, Output frequency step = 100kHz.
8
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SLWS181A–OCTOBER 2005–REVISED AUGUST 2006
TRF3761-1947 ELECTRICAL CHARACTERISTICS
Supply voltage = 5V, over operating free-air temperature range (unless otherwise noted)
PARAMETER
NOISE CHARACTERISTICS
TEST CONDITIONS
MIN
TYP
MAX
UNIT
100kHz offset
–117
–133
-141
600kHz offset
1MHz offset
6MHz offset
10MHz offset
100kHz offset
600kHz offset
1MHz offset
6MHz offset
10MHz offset
100kHz offset
600kHz offset
1MHz offset
6MHz offset
10MHz offset
1kHz offset
VCO phase noise,
Free running VCO direct output
fVCO = 1947MHz,
fO = 1947MHz
dBc/Hz
–155
–158.5
–125
–144
–148
–158
–159
–131
-150
VCO phase noise,
Free running VCO divide-by-2 output
fVCO = 1947MHz,
fO = 973.5
dBc/Hz
VCO phase noise,
Free running VCO divide-by-4 output
fVCO = 1947MHz,
fO = 486.75MHz
-153
dBc/Hz
dBc/Hz
–156.5
–157
–83.7
–136
–140
–158
600kHz offset
1MHz offset
10MHz offset
VCO phase noise,
fVCO = 1947MHz,
fO = 1947MHz
Closed loop phase noise direct output(1)(2)(3)
RMS phase error
100Hz to 10MHz
1°
Closed loop phase noise direct output(3)
1kHz offset
-89.5
–143.5
–147.4
–159
600kHz offset
1MHz offset
10MHz offset
VCO phase noise,
fVCO = 1947MHz,
fO = 973.5MHz
dBc/Hz
dBc/Hz
Closed loop phase noise divide-by-2 output(1)(2)(3)
RMS phase error
100Hz to 10MHz
0.43°
Closed loop phase noise divide-by-2 output(3)
1kHz offset
–95.5
–149
600kHz offset
1MHz offset
10MHz offset
VCO phase noise,
fVCO = 1947MHz,
fO = 486.75MHz
Closed loop phase noise divide-by-4 output(1)(2)(3)
–152.5
-157
RMS phase error
100Hz to 10MHz
VCO free running
0.2°
Closed loop phase noise divide-by-4 output(3)
VCO gain
30
MHz/V
dBc
Reference spur(2)
–80
(1) See Application Circuit
(2) PFD = 200kHz, Loop Filter BW = 15kHz, Output frequency step = 200kHz.
(3) Reference oscillator RMS phase error = 0.008250°, RMS jitter = 881.764 fs.
9
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SLWS181A–OCTOBER 2005–REVISED AUGUST 2006
TRF3761-2116 ELECTRICAL CHARACTERISTICS
Supply voltage = 5V, over operating free-air temperature range (unless otherwise noted)
PARAMETER
NOISE CHARACTERISTICS
TEST CONDITIONS
MIN
TYP
MAX
UNIT
100kHz offset
–117
–136
-140
600kHz offset
1MHz offset
6MHz offset
10MHz offset
100kHz offset
600kHz offset
1MHz offset
6MHz offset
10MHz offset
100kHz offset
600kHz offset
1MHz offset
6MHz offset
10MHz offset
1kHz offset
VCO phase noise,
Free running VCO direct output
fVCO = 2116MHz,
fO = 2116MHz
dBc/Hz
dBc/Hz
–154
–156
–124
–142.5
–147
–157.3
–158
–130
-149
VCO phase noise,
Free running VCO divide-by-2 output
fVCO = 2116MHz,
fO = 1058
VCO phase noise,
Free running VCO divide-by-4 output
fVCO = 2116MHz,
fO = 529MHz
-152
dBc/Hz
dBc/Hz
–156.5
–157
–83.5
–136
–139
–157
600kHz offset
1MHz offset
10MHz offset
VCO phase noise,
fVCO = 2116MHz,
fO = 2116MHz
Closed loop phase noise direct output(1)(2)(3)
RMS phase error
100Hz to 10MHz
1.13°
Closed loop phase noise direct output(3)
1kHz offset
-89
–142.5
–146.5
–158
600kHz offset
1MHz offset
10MHz offset
VCO phase noise,
fVCO = 2116MHz,
fO = 1058MHz
dBc/Hz
dBc/Hz
Closed loop phase noise divide-by-2 output(1)(2)(3)
RMS phase error
100Hz to 10MHz
0.5°
Closed loop phase noise divide-by-2 output(3)
1kHz offset
–95
–148.5
–151.5
–157
600kHz offset
1MHz offset
10MHz offset
VCO phase noise,
fVCO = 2116MHz,
fO = 529MHz
Closed loop phase noise divide-by-4 output(1)(2)(3)
RMS phase error
100Hz to 10MHz
VCO free running
0.23°
Closed loop phase noise divide-by-4 output(3)
VCO gain
30
MHz/V
dBc
Reference spur(2)
–80
(1) See Application Circuit
(2) PFD = 200kHz, Loop Filter BW = 15kHz, Output frequency step = 200kHz.
(3) Reference oscillator RMS phase error = 0.008250°, RMS jitter = 881.764 fs.
10
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SLWS181A–OCTOBER 2005–REVISED AUGUST 2006
TRF3761-2289 ELECTRICAL CHARACTERISTICS
Supply voltage = 5V, over operating free-air temperature range (unless otherwise noted)
PARAMETER
NOISE CHARACTERISTICS
TEST CONDITIONS
MIN
TYP
MAX
UNIT
100kHz offset
600kHz offset
–116
–135
VCO phase noise,
Free running VCO direct output
fVCO = 2289MHz,
fO = 2289MHz
1MHz offset
6MHz offset
10MHz offset
100kHz offset
600kHz offset
1MHz offset
6MHz offset
10MHz offset
100kHz offset
600kHz offset
1MHz offset
6MHz offset
10MHz offset
1kHz offset
-138
dBc/Hz
–153
–155
–124
–141
VCO phase noise,
Free running VCO divide-by-2 output
fVCO = 2289MHz,
fO = 1144.5
–145
dBc/Hz
–156
–157.5
–129.5
-147.5
-150.5
–156.5
–157
VCO phase noise,
Free running VCO divide-by-4 output
fVCO = 2289MHz,
fO = 572.25MHz
dBc/Hz
dBc/Hz
–82.5
–134
600kHz offset
1MHz offset
10MHz offset
VCO phase noise,
fVCO = 2289MHz,
fO = 2289MHz
Closed loop phase noise direct output(1)(2)(3)
–137.5
–155
RMS phase error
100Hz to 10MHz
fVCO = 2289MHz,
1.22°
Closed loop phase noise direct output(3)
1kHz offset
–88
-141
600kHz offset
1MHz offset
10MHz offset
VCO phase noise,
dBc/Hz
dBc/Hz
Closed loop phase noise divide-by-2 output(1)(2)(3) fO = 1144.5MHz
–144.5
–157
RMS phase error
100Hz to 10MHz
0.55°
Closed loop phase noise divide-by-2 output(3)
1kHz offset
–94
–147
600kHz offset
1MHz offset
10MHz offset
VCO phase noise,
fVCO = 2289MHz,
Closed loop phase noise divide-by-4 output(1)(2)(3) fO = 572.25MHz
–150.5
–157
RMS phase error
100Hz to 10MHz
0.26°
Closed loop phase noise divide-by-4 output(3)
VCO gain
Reference spur(2)
VCO free running
30
MHz/V
dBc
–80
(1) See Application Circuit
(2) PFD = 200kHz, Loop Filter BW = 15kHz, Output frequency step = 200kHz.
(3) Reference oscillator RMS phase error = 0.008250°, RMS jitter = 881.764 fs.
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TRF3761-1817 TYPICAL CHARACTERISTICS
-70
-80
0
-10
OL = 1817 MHz/1
CL = 1817 MHz/1
-20
-30
-90
-40
-50
-100
-110
-60
-70
-80
-120
-130
-140
-90
-100
-110
-120
-130
-140
-150
-160
-170
-150
-160
-170
1 k
10 k
100 k
1 M
10 M
10 M
10 M
100
100
1 k
10 k
100 k
1 M
10 M
10 M
10 M
f - Offset Frequency - Hz
Frequency Offset - Hz
Figure 2. Open Loop VCO Phase Noise
Figure 3. Closed Loop VCO Phase Noise
0
-10
-70
-80
CL = 908.5 MHz/2
OL = 908.5 MHz/2
-20
-30
-90
-40
-50
-100
-60
-110
-120
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-130
-140
-150
-160
-170
100
1 k
10 k
100 k
1 M
100
1 k
10 k
100 k
1 M
f - Offset Frequency - Hz
f - Frequency Offset - Hz
Figure 4. Open Loop VCO Phase Noise
Figure 5. Closed Loop VCO Phase Noise
0
-10
-20
-30
-40
-50
-60
-70
-70
-80
OL = 454.25 MHz/4
CL = 454.25 MHz/4
-90
-100
-110
-120
-80
-90
-100
-130
-140
-150
-110
-120
-130
-140
-150
-160
-170
-160
-170
100
10 k
f - Frequency Offset - Hz
1 k
100 k
1 M
1 k
10 k
100 k
1 M
100
f - Offset Frequency - Hz
Figure 6. Open Loop VCO Phase Noise
Figure 7. Closed Loop VCO Phase Noise
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TRP3761-1579 TYPICAL CHARACTERISTICS
-7
-8
0
-20
CL = 1579 MHz/1
OL = 1579 MHz/1
-9
-1
-40
-60
-1.1
-1.2
-1.3
-1.4
-1.5
-1.6
-1.7
-80
-100
-120
-140
-160
-180
100
1
10 k
100 k
1 M
10 M
100
1 k
10 k
100 k
1 M
10 M
f - Frequency - Hz
f - Frequency - Hz
Figure 8. Open Loop VCO Phase Noise
Figure 9. Closed Loop VCO Phase Noise
-7
-8
0
-20
CL = 394.75 MHz/2
OL = 394.75 MHz/4
-9
-1
-40
-60
-1.1
-1.2
-1.3
-1.4
-1.5
-1.6
-80
-100
-120
-140
-160
-180
-1.7
100
1 k
10 k
100 k
1 M
10 M
100
1 k
10 k
100 k
1 M
10 M
f - Frequency - Hz
f - Frequency - Hz
Figure 10. Open Loop VCO Phase Noise
Figure 11. Closed Loop VCO Phase Noise
-7
-8
0
-20
CL = 789.5 MHz/2
OL = 789.5 MHz/2
-9
-40
-60
-80
-1
-1.1
-1.2
-1.3
-1.4
-1.5
-100
-120
-140
-1.6
-160
-180
-1.7
100
1 k
10 k
100 k
1 M
10 M
100 k
f - Frequency - Hz
10 k
1 M
10 M
100
1 k
f - Frequency - Hz
Figure 12. Open Loop VCO Phase Noise
Figure 13. Closed Loop VCO Phase Noise
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TRP3761-1579 TYPICAL CHARACTERISTICS (continued)
Figure 14. Direct Output: PFD Frequency Spurs
Figure 15. Divide-By-2 Output: PFD Frequency Spurs
Figure 16. Divide-By-4 Output: PFD Frequency Spurs
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TRP3761-1700 TYPICAL CHARACTERISTICS
-70
-80
0
-20
CL = 1700 MHz/1
OL = 1700 MHz/1
-90
-40
-60
-80
-100
-110
-120
-130
-140
-150
-100
-120
-140
-160
-160
-170
-180
100
1 k
100
10 k
100 k
1 M
10 M
10 M
10 M
1 k
10 k
100 k
1 M
10 M
f - Frequency Offset - Hz
f - Frequency Offset - Hz
Figure 17. Open Loop VCO Phase Noise
Figure 18. Closed Loop VCO Phase Noise
0
-70
-20
-80
-90
CL = 850 MHz/2
OL = 850 MHz/2
-40
-60
-80
-100
-110
-120
-130
-140
-150
-100
-120
-140
-160
-160
-170
-180
100
1 k
10 M
10 k
f - Frequency Offset - Hz
1 M
100 k
100
1 k
10 k
f - Frequency Offset - Hz
1 M
100 k
Figure 19. Open Loop VCO Phase Noise
Figure 20. Closed Loop VCO Phase Noise
0
-70
-20
-80
-90
CL = 425 MHz/4
OL = 425 MHz/4
-40
-60
-80
-100
-110
-120
-130
-140
-150
-100
-120
-140
-160
-160
-170
-180
100
1 k
10 M
10 k
f - Frequency Offset - Hz
1 M
100 k
100
1 k
10 k
f - Frequency Offset - Hz
1 M
100 k
Figure 21. Open Loop VCO Phase Noise
Figure 22. Closed Loop VCO Phase Noise
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TRP3761-1700 TYPICAL CHARACTERISTICS (continued)
Figure 23. Direct Output: PFD Frequency Spurs
Figure 24. Divide-By-2 Output: PFD Frequency Spurs
Figure 25. Divide-By-4 Output: PFD Frequency Spurs
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TRF3761-1817 TYPICAL CHARACTERISTICS (Continued)
Figure 26. Direct Output: PFD Frequency Spurs
Figure 27. Divide-By-2 Output: PFD Frequency Spurs
Figure 28. Divide-By-4 Output: PFD Frequency Spurs
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TRP3761-1947 TYPICAL CHARACTERISTICS
-70
-80
0
-20
CL = 1947 MHZ/1
OL = 1947 MHz/1
-90
-40
-100
-60
-110
-120
-130
-140
-80
-100
-120
-140
-150
-160
-180
-160
-170
100
1 k
10 k
100 k
1 M
10 M
10 M
10 M
100
1 k
10 k
100 k
1 M
10 M
10 M
10 M
f - Frequency Hz
f - Frequency - Hz
Figure 29. Open Loop VCO Phase Noise
Figure 30. Closed Loop VCO Phase Noise
-70
-80
0
-20
CL = 973.5 MHz/2
OL = 973.5 MHz/2
-90
-40
-100
-60
-110
-120
-130
-140
-80
-100
-120
-140
-150
-160
-180
-160
-170
100
1 k
10 k
100 k
1 M
100
1 k
10 k
100 k
1 M
f - Frequency Hz
f - Frequency - Hz
Figure 31. Open Loop VCO Phase Noise
Figure 32. Closed Loop VCO Phase Noise
-70
-80
0
-20
CL = 486.75 MHz/4
OL = 486.75 MHz/4
-90
-40
-100
-110
-120
-130
-140
-150
-60
-80
-100
-120
-140
-160
-180
-160
-170
1 k
100
1 k
10 k
100 k
1 M
100
10 k
100 k
1 M
f - Frequency Offset - Hz
f - Frequency - Hz
Figure 33. Open Loop VCO Phase Noise
Figure 34. Closed Loop VCO Phase Noise
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TRP3761-1947 TYPICAL CHARACTERISTICS (continued)
Figure 35. Direct Output: PFD Frequency Spurs
Figure 36. Divide-By-2 Output: PFD Frequency Spurs
Figure 37. Divide-By-4 Output: PFD Frequency Spurs
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TRP3761-2116 TYPICAL CHARACTERISTICS
-70
-80
0
-20
-40
-60
CL = 2116 MHz/1
OL = 2116 MHz/1
-90
-100
-110
-120
-130
-140
-150
-80
-100
-120
-140
-160
-180
-160
-170
100
1 k
10 k
100 k
1 M
10 M
10 M
10 M
100
1 k
10 k
100 k
1 M
10 M
f - Frequency Offset - Hz
f - Frequency Offset - Hz
Figure 38. Open Loop VCO Phase Noise
Figure 39. Closed Loop VCO Phase Noise
-70
-80
0
-20
CL = 1058 MHz/2
OL = 1058 MHz/2
-90
-40
-60
-100
-110
-120
-130
-140
-150
-80
-100
-120
-140
-160
-180
-160
-170
100
1 k
10 k
100 k
1 M
100
1 k
10 k
100 k
1 M
10 M
f - Frequency Offset - Hz
f - Frequency offset - Hz
Figure 40. Open Loop VCO Phase Noise
Figure 41. Closed Loop VCO Phase Noise
-70
-80
0
-20
-40
-60
CL = 529MHz /4
OL = 529 MHz/4
-90
-100
-110
-120
-130
-140
-150
-80
-100
-120
-140
-160
-180
-160
-170
100
1 k
10 k
100 k
1 M
100
1 k
10 k
100 k
1 M
10 M
f - Frequency Offset - Hz
f - Frequency Offset - Hz
Figure 42. Open Loop VCO Phase Noise
Figure 43. Closed Loop VCO Phase Noise
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TRP3761-2116 TYPICAL CHARACTERISTICS (continued)
Figure 44. Direct Output: PFD Frequency Spurs
Figure 45. Divide-By-2 Output: PFD Frequency Spurs
Figure 46. Divide-By-4 Output: PFD Frequency Spurs
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TRP3761-2289 TYPICAL CHARACTERISTICS
0
-20
-40
-60
-80
-70
-80
CL = 2289 MHz
OL = 2289 MHz
-90
-100
-110
-120
-130
-140
-100
-120
-140
-160
-180
-150
-160
100
1 k
10 k
100 k
1 M
10 M
10 M
10 M
100
1 k
10 k
100 k
1 M
10 M
f - Frequency - Hz
f - Frequency - Hz
Figure 47. Open Loop VCO Phase Noise
Figure 48. Closed Loop VCO Phase Noise
0
-20
-40
-60
-80
-70
-80
CL = 1144p5 MHz/2
OL = 1144p5
-90
-100
-110
-120
-130
-140
-150
-100
-120
-140
-160
-180
-160
-170
100
1 k
10 k
100 k
1 M
100
1 k
10 k
100 k
1 M
10 M
f - Frequency - Hz
f - Frequency - Hz
Figure 49. Open Loop VCO Phase Noise
Figure 50. Closed Loop VCO Phase Noise
-70
0
-20
-40
-60
-80
-90
CL = 572.25 MHz/4
OL = 572.25 MHz/4
-100
-110
-80
-100
-120
-140
-120
-130
-140
-150
-160
-180
-160
-170
100
1 k
10 k
100 k
1 M
10 M
100
1 k
10 k
100 k
1 M
f - Frequency - Hz
f - Frequency - Hz
Figure 51. Open Loop VCO Phase Noise
Figure 52. Closed Loop VCO Phase Noise
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TRP3761-2289 TYPICAL CHARACTERISTICS (continued)
Figure 53. Direct Output: PFD Frequency Spurs
Figure 54. Divide-By-2 Output: PFD Frequency Spurs
Figure 55. Divide-By-4 Output: PFD Frequency Spurs
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SERIAL INTERFACE PROGRAMMING REGISTERS DEFINITION
The TRF3761 features a 3-wire serial programming interface that controls an internal, 32-bit shift register. There
are a total of 3 signals that need to be applied: the CLOCK (pin 3), the serial DATA (pin 4) and the STROBE
(pin 5). The DATA (DB0-DB31) is loaded LSB first and is read on the rising edge of the CLOCK. The STROBE
is asynchronous to the CLOCK and at it's rising edge the data in the shift register gets loaded onto the selected
internal register. The first four bits (DB0-DB3) is the address to select the available internal registers.
Table 1. Register 1: Device Setup
REGISTER 1 MAPPING
Data Field DB31
FULL_CAL_REQ
This is a read only bit, that indicates if a 0 power-up cal is not required
power-up cal is required
1 power-up cal is required
DB30
DB29
CP_TEST
TRIS_CP
Up and down pulse charge pump test
1 test enabled
High-impedance state charge pump
output
1 CP high-impedance state
DB28
DB27
PFD_POL
ABPW1
Select Polarity of PFD
0 negative
1 positive
ABPW<1,0>: antibacklash pulse width
00 1.5ns delay
01 0.9ns delay
10 3.8ns delay
11 2.7ns delay
DB26
DB25
DB24
DB23
DB22
DB21
DB20
DB19
DB18
DB17
DB16
DB15
DB14
DB13
DB12
DB11
ABPW0
RDIV_13
RDIV_12
RDIV_11
RDIV_10
RDIV_9
RDIV_8
RDIV_7
RDIV_6
RDIV_5
RDIV_4
RDIV_3
RDIV_2
RDIV_1
RDIV_0
PD_BUFOUT
14-bit reference clock divider
RDIV<13,0>:00...01: divide by 1
RDIV<13,0>:00...10: divide by 2
RDIV<13,0>:00...11: divide by 3
If Bit10 = 0 then it controls power down <DB10:11>:
of output buffer
00 default; output buffer on
01 output buffer off
1x output buffer on/off controlled by
OUTBUF_EN pin
DB10
DB9
OUTBUF_EN_SEL
OUT_MODE_1
Select Output Buffer enable control:
0 internal
1 through OUTBUF_EN pin
OUTBUFMODE<1,0>: Selection of RF
output buffer division ratio
00 divide by 1
01 divide by 2
10 divide by4
DB8
DB7
DB6
DB5
DB4
OUT_MODE_0
ICP2
ICP<2,0>: select charge pump current
(1 mA step)
ICP1
ICP0
RESET
Registers reset
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Table 1. Register 1: Device Setup (continued)
REGISTER 1 MAPPING
Address
Bits
DB3
DB2
DB1
DB0
0
0
0
0
OUT_MODE<1,0>: TRF3761 has an optional divide by 2 or 4 output, which is selectable by programming bits
<OUT_MODE_1, OUT_MODE_0> of register 1 (see Table 1).
Up and Down Pulse Test: By setting bit DB30 to 1 it is possible to test the PFD up or down pulses.
Charge Pump Tristate: If bit DB29 is set to 1, the charge pump output goes in tri-state. For normal operation,
DB29 must be set to 0.
Anti-Backlash Pulse: Bits <DB27, DB26> are used to program the width of the anti-backlash pulses of the PFD.
The user selects one of the following values: 0.9ns, 1.5ns, 2.7ns and 3.8ns.
PFD Polarity: Bit DB28 of register 0 sets the polarity of the PFD: A 0 selects a negative polarity, and a 1 selects
a positive polarity. By choosing the correct polarity, the TRF3761 works with an external VCO having both
positive and negative Kv.
Reference Divider: A 14-bit word programs the R divider for the reference signal, DB25 is the MSB and DB12 is
the LSB.
Charge Pump Current: Bits <DB7, DB5> set the charge pump current.
OUTBUF_EN_SEL: Output buffer on/off state is controlled through serial interface or an external pin. If bit DB10
is a 0 (default state) the output buffers state is elected through bit DB11. If DB10 is a 1, the buffers on/off are
directly controlled by the OUTBU_EN pin.
Reset: Setting bit DB4 to 1, all registers are reset to default values.
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Table 2. Register 2: VCO Calibration
REGISTER 2 MAPPING
Data Field DB31
DB30
DB29
DB28
DB27
DB26
DB25
DB24
DB23
DB22
DB21
DB20
DB19
DB18
DB17
DB16
DB15
DB14
DB13
DB12
DB11
DB10
DB9
START_CAL
FOUT12
FOUT11
FOUT10
FOUT9
FOUT8
FOUT7
FOUT6
FOUT5
FOUT4
FOUT3
FOUT2
FOUT1
FOUT0
REF_FRAC6
REF_FRAC5
REF_FRAC4
REF_FRAC3
REF_FRAC2
REF_FRAC1
REF_FRAC0
REF6
VCO frequency in MHz start calibration 1 start calibration
Reference frequency in MHz (fractional 0000000 = X.00MHz
part)
0000001 = X.01MHz
0000010 = X.02MHz
. . . . .
1100011 = X.99MHz
Reference frequency in MHz (integer
part)
0001010 =10MHz
0001011 =11MHz
. . . . .
REF5
DB8
REF4
1101000 = 104MHz
DB7
REF3
DB6
REF2
DB5
REF1
DB4
REF0
Address
Bits
DB3
DB2
DB1
DB0
0
0
0
1
Reference Frequency: The 14 bits <DB17, DB4> are used to specify the input reference frequency as multiples
of 10kHz. Bits <DB10,DB4> specify the integer part of the reference frequency expressed in MHz. Bits
<DB17,DB11> set the fraction part. Those values are then used during the calibration of the internal VCO.
Start Calibration: A 1 in DB31 starts the internal VCO calibration. When the calibration is complete, DB31 bit is
internally reset to 0.
FOUT<12,0>: This 13-bit word <DB30,DB18> specifies the VCO output frequency in MHz. If output frequency is
not a integer multiple of MHz, this value must be approximated to the closest integer in MHz.
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Table 3. Register 3: A and B Counters
REGISTER 3 MAPPING
Data Field DB31
DB30
DB29
DB28
DB27
DB26
DB25
DB24
DB23
DB22
DB21
DB20
DB19
DB18
DB17
DB16
DB15
DB14
DB13
DB12
DB11
DB10
DB9
Rsrv
Reserved
Rsrv
Reserved
START_LK
Lock PLL to frequency
1 active
TEST_MUX_3
0001 = LOCK_DETECT enabled
TEST_MUX_2
TEST_MUX_1
TEST_MUX_0
B_12
B_11
B_10
B_9
13-bit B counter
B_8
B_7
B_6
B_5
B_4
B_3
B_2
B_1
B_0
A_5
6-bit A counter
A_4
A_3
DB8
A_2
DB7
A_1
DB6
A_0
DB5
PRESC_MOD1
PRESC_MOD0
Dual-modulus prescaler mode
<B5,B4>:00 8/9
<B5,B4>:01 16/17
<B5,B4>:10 32/33
<B5,B4>:11 64/65
DB4
Address
Bits
DB3
DB2
DB1
DB0
0
0
1
0
B<12,0>: This 13-bit word <DB24,DB12> controls the value of the B counter of the N divider. The valid range is
from 3 to 8191.
A<5,0>: These 6 bits <DB11,DB6> control the value of the A counter. The valid range is from 0 to 63.
PRESC_MOD<1,0>: These bits <DB5,DB4> define the mode of the dual-modulus prescaler according Table 3.
START_LK: TRF3761 does not load the serial interface registers values into the dividers registers until bit DB29
of register 3 is set to 1. After TRF3761 is locked to the new frequency, bit DB29 is internally reset to 0.
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FUNCTIONAL DESCRIPTION
VCO
TRF3761 integrates a high-performance, LC tank, voltage-controlled oscillator (VCO). For each of the devices of
TRF3761 family, the inductance and capacitance of the tank are optimized to yield best phase-noise
performance. The VCO output is fed externally and to the prescaler through a series of very low noise buffers,
that greatly reduce the effect of load pulling onto the VCO.
Divider by 2, by 4, and Output Buffer
To extend the frequency coverage, the TRF3761 integrates a divider by 2 and by 4 with very low noise floor.
The VCO signal is fed externally through a final open-collector differential-output buffer. This buffer is able to
provide up to 3dBm (typical) of power into a 200Ω differential resistive load. The open-collector structure gives
the flexibility to choose different load configurations to meet different requirements.
Prescaler Stage
This stage divides down the VCO frequency before the A and B counters. This is a dual-modulus prescaler and
the user can select any of the following settings: 8/9, 16/17, 32/33, and 64/65.
A and B Counter Stage
The TRF3761 includes a 6-bit A counter and a 13-bit B counter that operate on the output of the prescaler. The
A counter can take values from 0 to 63, while the B counter can take values from 3 to 8191. Also, the value for
the B counter must be greater than or equal to the value for the A counter. The A and B counter with the
prescaler stage create the VCO N-divider.
R Divider
TRF3761 includes a 14-bit R divider that allows the input reference frequency to be divided down to produce the
reference clock to the phase frequency detector (PFD). Division ratios from 1 to 16,383 are allowed.
Phase Frequency Detector (PFD) and Charge Pump Stage
The outputs of the R divider and the N counter are fed into the PFD stage, where the two signals are compared
in frequency and phase. The TRF3761 features an anti-backlash pulse, whose width is controllable by the user
through the serial programming interface. The PFD feeds the charge pump, whose output current pulses are fed
into an external loop filter, which eventually produces the tuning voltage needed to control the integrated VCO to
the desired frequency.
28
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APPLICATION INFORMATION
Initial Calibration and Frequency Setup at Power Up
The integrated high performance VCO requires an internal frequency calibration at power up. To perform such
calibration the following procedure is recommended:
•
•
•
•
Apply 5V power supply to IC.
Apply an input reference frequency and ensure the signal is stable.
Turn on the TRF3761 using the chip enable pin (CHIP_EN, pin 2).
Setup the device through Register 1 referencing Table 1.
a. The first 4 bits of the 32-bit code sent to the chip are set DB <3:0> to 0000; which is the address of
register 1.
b. Bit 5, DB4 sets the soft reset for the chip. If a soft reset is used then write to register 1 twice: once with
DB4 set high and once with DB4 set low. Typically, this bit is only used when the chip has been
powered up and registers 1, 2, and 3 have been already written to, so on power-up reset is not required,
so DB4 is, by default, set low.
c. DB <7: 5> sets the charge pump current based on the resistor value on pin 28 of the TRF3761 and the
decimal value of Register 1, DB<7:5> used in this equation, Icp = (1.2V/Rbias)×((n+1)×22.168)/8, where
n = decimal value of [Reg1 DB<7:5>]. This equation reduces to Icp = 3.3252×(n+1)/Rbias.
d. DB <9: 8> sets the mode of the chip. The mode is how the device will or will not divide down the VCO’s
frequency. There are 3 choices for the mode setting, divide by 1, 2 or 4. For example if 525MHz is
required from the TRF3761 then the divide-by-4 mode is chosen by setting DB <9: 8> to 10. With a
2100MHz VCO frequency set on Register 2 the output frequency will be divided by 4 to give 525MHz.
e. DB <11:10> controls the output buffer. Both of these are set to 00 by default, so the buffer is controlled
internally. See Table 2 for more information.
f. DB <25:12> sets the R-divide value. Once the calculations under the Synthesizing a Selected
Frequency have been completed the value is known, based on the external reference oscillator. The
value for R is entered into the DB <25:12>. For example, if the reference oscillator is at 61.44MHz and a
120kHz step is required, which is also the Fpfd, then Refin /Fpfd = 512, which is entered as follows:
MSB: LSB 0001000000000.
g. By default, DB <27:26> are set to 00 for a 1.5ns delay on the ant backlash pulse width. See Table 1 for
more information.
h. DB 28 is set to 1 for positive by default. See Table 1 for more information.
i. DB 29 is set to 0 for normal operation. See Table 1 for more information.
j. DB 30 is set to 0 by default. See Table 1 for more information.
k. DB 31 is set to 0 by default. See Table 1 for more information.
•
Initiate calibration procedure by programming register 2 as follows: Reference Table 2
a. Use bits DB<17, 4> of register 2 to specify the input reference frequency in MHz. The value is split into
an integer and a fraction part. For example: to insert a fREF of 30.72MHz, set:
b. DB<10, 4> (integer part) equal to 0011110 (30) and
c. DB<17, 11> (fraction part) equal to 1001000 (72).
d. Set DB<30:18> of register 2 to the desired frequency. For example: 2200MHz would be 0100010011000
(2200).
e. Set DB31of register 2 to 1 to start the calibration. The VCO calibration runs for 5ms. During the cal
procedure it will not be possible to program register 2 and 3. At the end of the calibration, bit DB31 of
register 2 resets to 0.
f. Subsequent frequency programming requires DB31 to be set to 0.
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APPLICATION INFORMATION (continued)
•
Completion of the frequency set up, on initial calibration, cannot proceed until 5ms has elapsed, due to full
calibration, then it will require that the A and B values, the prescalar ratio, be known. See Synthesizing a
Selected Frequency section below for calculation. Reference Table 3.
a. Register 3 DB<3:0> is the address of register 3, 0010 (2).
b. DB<5:4> sets the prescalar ratio, 8/9, 16/17, 32/33, 64/65. For example: if 16/17 are required, set the
register bits DB<5:4> to 01.
c. DB<11:6> sets the A value for the N counter. For example: if A is 4, set DB<11:6> as follows: 000100
(4).
d. DB<24:12> sets the B value for the N counter. For example: if B is 1156, set DB<24:12> as follows:
0010010000100 (4).
e. DB<28:25> sets the TEST_MUX.
Table 4. Settings
STATE
DB<28:25>
0000
STATE
DB<28:25>
0100
3-state o/p
Digital lock Detect
N-Divider o/p
DVDD
R-divider o/p
Analog lock detect
Read back
DGND
0001
0101
0010
0110
0011
0111
f. DB29 sets the START LOCK, which is set to 0, on the initial frequency setup and then set to 1 on
additional frequency changes.
Once all registers are written to the TRF3761 will lock to the desired frequency.
Re-Calibration After Power Up
Assuming the TRF3761 is powered up and operational, a VCO calibration is also possible without powering
down the IC. To perform such calibration the following procedure is recommended:
•
Set bit DB4 (RESET) of register 1 to 1. This performs a software reset and clears all registers of VCO
calibration data.
•
Repeat form Initial Calibration and Frequency setup at Power up from above at section A.
Synthesizing a Selected Frequency
The TRF3761 is an integer-N PLL synthesizer, and because of its flexibility (14-bit R, 6-bit A, 13-bit B counter,
and dual modulus prescaler), is ideal for synthesizing virtually any desired frequency. Let us assume that we
need to synthesize a 900MHz local oscillator, with spacing capability (minimum frequency increment) of 200kHz,
as in a typical GSM application. The choice of the external reference oscillator to be used is beyond the scope of
this section, but assuming that a 10MHz reference is selected, the settings are calculated to yield the desired
output frequency and channel spacing. There is more than one solution to a specific set of conditions, so below
is one way of achieving the desired result. First, select the appropriate R counter value. Since a channel spacing
of 200kHz is desired, the PFD is set to 200kHz. Calculate the R value through R = REFIN/PFD = 10MHz/
200kHz = 50. Assume a prescaler value of 8/9 is selected. This is a valid choice, since the prescaler output is
well within the 200MHz limit (900MHz / 8 = 112.5MHz). Select the appropriate A and B counter values. RFOUT
= Fpfd × N = (fREFIN / R) × (A + P × B). Therefore, the following equation must be solved: 900MHz = 200kHz x
(A + 8 × B). There are many solutions to this single equation with two unknowns; there are some basic
constraints on the solution, since 3 ≤ B ≤ 8191, and also B ≥ A. So, if A = 4, solving the equation yields B = 562.
One complete solution would be to choose: R = 50, A = 4, B = 562 and P = 8/9, resulting in the desired N =
4500.
When this procedure is complete the values for A, B, R, and the prescalar ratio should be known. Registers 2
and 3 need to be set up for operation of the chip. See Table 2 and Table 3 for this procedure. Register 2 bits
<DB30:DB18> 12:0 set the output frequency of the device along with register 3.
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Application Schematic
Figure 56 shows a typical application schematic for the TRF3761. In this example, the output signal is taken
differential using the 2 resistive pull-up resistors of the final output buffer. A single-ended and tuned load
configuration is also available.
The loop filter components, shown in the application schematic, are typical ones used for the plots shown above.
Those values can be optimized differently according to the requirements of the different applications.
R2
C1
C3
R1
C2
C4
1000 pF
40 39 38 37 36 35 34 33 32 31
1
30
29
28
27
26
25
24
23
22
21
PD_OUTBUF
CHIP_EN
CLOCK
DATA
GND
R3
2.37 kΩ
2
AVDD_BIAS
RBIAS1
3
4
GND
5
STROBE
GND
VCTRL_IN
AVDD_VCO
AVDD_BUF
TRF3761
(TOP VIEW)
6
7
GND
8
DVDD1
AVDD_PRES
GND
AVDD_CAPARRAY
GND
9
10
AVDD
11 12 13 14 15 16 17 18 19 20
R4
4.75 kΩ
C7
1000 pF
R5
120 Ω
R6
120 Ω
V
DD
V
DD
C5
C6
LOAD
Figure 56. TRF3761 Application Schematic
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Loop Filter Design
Numerous methodologies and design techniques exist for designing optimized loop filters for particular
applications. The loop filter design can affect the stability of the loop, the lock time, the bandwidth, the extra
attenuation on the reference spurs, etc. The role of the loop filter is to integrate and lowpass the pulses of the
charge pump and eventually yield an output tuning voltage that drives the VCO. Several filter topologies can be
implemented, including both passive and active. In this section, a third-order passive filter is used. For this
example, assume these several design parameters. The internal VCO has a value of 23MHz/V, meaning that in
the linear region, changing the tuning voltage of the VCO by 1V induces a change of the output frequency of
about 23MHz. It is known that N = 4500 and Fpfd = 200kHz. It is assumed that current setting 1 will be used and
be set to a maximum current of 5.6mA. In addition, the bandwidth of the loop filter must be determined. This is a
critical consideration as it affects the lock time of the system. Assuming an approximate bandwidth of around
20kHz is required and that for stability a phase margin of about 45 degrees is desired, the following values for
the components of the loop filter can be derived. There is almost an infinite number of solutions to the problem
of designing the loop filter and the designer is called to make tradeoff decisions for each application.
Loop filter components:
C1 = 303pF
R1 = 8.87kW
C2 = 1650pF
C3 = 330pF
Frequency jump from
1046MHz to 1085mHz:
Locktime freq ~ 250mS
Figure 57. Frequency Locktime
Layout/PCB Considerations
This section of the design of the complete PLL is of paramount importance in achieving the desired
performance. Wherever possible, a multi-layer PCB board should be used, with at least one dedicated ground
plane. A dedicated power plane (split between the supplies if necessary) is also recommended. The impedance
of all RF traces (the VCO output and feedback into the PLL) should be controlled to 50Ω. All small value
decoupling capacitors should be placed as close to the device pins as possible. It is also recommended that
both top and bottom layers of the circuit board be flooded with ground, with plenty of ground vias dispersed as
appropriate. The most sensitive part of any PLL is the section between the charge pump output and the input to
the VCO. This includes the loop filter components, and the corresponding traces. The charge pump is a
precision element of the PLL and any extra leakage on its path can adversely affect performance. Extra care
should be given to ensure that parasitics are minimized in the charge pump output, and that the trace runs are
short and optimized. Similarly, it is also recommend that extra care is taken in ensuring that any flux residue is
thoroughly cleaned and moisture baked out of the PCB. From an EMI perspective, and since the synthesizer is
typically a small portion of a bigger, complex circuit board, shielding is recommended to minimize EMI effects.
Application Example for a High Performance RF Transmit Signal Chain
Much in the same way as described above, the TRF3761 is an ideal synthesizer to use in implementing a
complete high performance RF transmitter chain such as the TSW3000 and up-and-coming TSW 3003
Demonstration kits. Using a complete suite of high performance Texas Instruments components, a
state-of-the-art transmitter can be implemented featuring excellent performance. Texas Instruments offers ideal
solutions for the digital-to-analog conversion portion of transmitter as well as the analog and RF components
needed to complete the transmitter. The baseband digital data is converted to I and Q signals through the dual
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DAC5687, which features a 16-bit interpolating dual digital-to-analog converter (DAC). The device incorporates a
digital modulator, independent differential offset control, and I/Q amplitude control. The device is typically used in
baseband mode or in low IF mode in conjunction with an analog quadrature modulator. The DAC5687, after
filtering, feeds a TRF3703, which is a direct, upconversion IQ modulator. This device accepts a differential input
voltage quadrature signal at baseband or low IF frequencies and outputs a modulated RF signal based on the
LO drive frequency. The LO drive input of the IQ modulator is generated by the TRF3761. The TRF3761 is a
family of high performance, highly integrated frequency synthesizers, optimized for wireless infrastructure
applications. The TRF3761 includes an integrated VCO and integer-N PLL. Different members of the TRF3761
family can be chosen for application specific VCO frequency ranges. In addition, the CDC7005 clocking solution
can be used to clock the DAC and other portions of the transmitter. A block diagram of the proposed
architecture is shown in Figure 58 and Figure 59. For more details, contact Texas Instruments directly.
TX
DAC
LPA
ANT
0°
90°
Diplexer
I/Q
Demod
A/D
RX
LNA
Figure 58. Transmit Chain Block Diagram
16
TRF3703
I/Q
RF Out
DAC5687
Modulator
16
CLK1
CLK1
CDCM7005
Clock Generator
VCXO
TRF3761
PLL
LO Generator
Ref Osc
Figure 59. Transmit Chain Block Diagram
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PACKAGE OPTION ADDENDUM
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2-Aug-2006
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
TRF3761IRHAR
PREVIEW
QFN
RHA
40
2500
TBD
Call TI
Call TI
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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Addendum-Page 1
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