TRF37A75IDSGR [TI]
具有断电引脚的 40MHz 至 6000MHz 12dB 射频增益块放大器 | DSG | 8 | -40 to 85;
| 型号： | TRF37A75IDSGR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有断电引脚的 40MHz 至 6000MHz 12dB 射频增益块放大器 | DSG | 8 | -40 to 85 放大器 射频 微波 |
| 文件： | 总19页 (文件大小：1770K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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TRF37A75
ZHCSCF6 –MAY 2014
TRF37A75 40-6000MHz 射频 (RF) 增益块
1 特性
3 说明
1
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•
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40MHz-6000MHz
TRF37A75 采用具有功率降低引脚的 2.00mm x
2.00mm 超薄小外形尺寸无引线 (WSON) 封装，这使
得这款器件非常适合于空间占用和低功率模式十分关键
的应用。
增益版本：12dB
噪声值：4dB
输出 P1dB：2000MHz 时为 18dBm
输出 IP3：2000MHz 时为 32.5dBm
功率降低模式 (Power Down Mode)
单电源：5V
TRF37A75 的设计目的是易于使用。 为了实现最大灵
活性，这个产品系列使用常见的 5V 电源，并且流耗为
80mA。 此外，这一系列在设计时使用了有源偏置电
路，此电路在过程、温度和电压变化范围内提供一个稳
定且可预计的偏置电流。 为了实现增益和线性预算，
此器件被设计成提供一个平坦增益响应，以及频率达到
6000MHz 时的出色 OIP3 输出。 针对空间受限应用，
这一系列与 50Ω 内部匹配，这样简化了使用，并且最
大限度地减小了所需的印刷电路板 (PCB) 面积。
温度范围内的稳定性能
无条件稳定
强健的静电放电 (ESD) 防护：> 1kV 人体模型
(HBM)；> 1kV 充电器件模型 (CDM)
2 应用范围
•
•
•
•
•
•
•
•
•
•
•
•
•
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通用 RF 增益块
消费类产品
器件信息(1)
工业用
产品型号
TRF37A75
封装
封装尺寸（标称值）
WSON (32)
2.00mm x 2.00mm
公用事业计量仪表
低成本无线电产品
蜂窝基站
(1) 要了解所有可用封装，请见数据表末尾的可订购产品附录。
简化电路原理图
无线基础设施
RF 回程
VCC
雷达
电子对抗
软件定义的无线电
测试和测量
R2
Rbias
VCC
1.8R
点对点/多点微波
软件定义的无线电
RF 中继器
L1
RF choke
100nH
1
2
3
4
8
7
6
5
分布式天线系统
本振 (LO) 和 PA 驱动器放大器
无线数据，卫星，直播卫星 (DBS)，有线电视
(CATV)
C1
1000pF
C2
1000pF
PWDN
•
中频 (IF) 放大器
1
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
English Data Sheet: SLOS871
TRF37A75
ZHCSCF6 –MAY 2014
www.ti.com.cn
目录
7.2 Functional Block Diagram ......................................... 8
7.3 Feature Description................................................... 8
7.4 Device Functional Modes.......................................... 8
Applications and Implementation ........................ 9
8.1 Application Information.............................................. 9
8.2 Typical Application ................................................... 9
Power Supply Recommendations...................... 10
1
2
3
4
5
6
特性.......................................................................... 1
应用范围................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 Handling Ratings....................................................... 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information.................................................. 4
6.5 Electrical Characteristics........................................... 5
6.6 Timing Requirements................................................ 5
6.7 Typical Characteristics.............................................. 6
Detailed Description .............................................. 8
7.1 Overview ................................................................... 8
8
9
10 Layout................................................................... 11
10.1 Layout Guidelines ................................................. 11
10.2 Layout Example .................................................... 11
11 器件和文档支持 ..................................................... 12
11.1 Trademarks........................................................... 12
11.2 Electrostatic Discharge Caution............................ 12
11.3 Glossary................................................................ 12
12 机械封装和可订购信息 .......................................... 12
7
4 修订历史记录
日期
修订版本
注释
2014 年 5 月
*
最初发布。
2
Copyright © 2014, Texas Instruments Incorporated
TRF37A75
www.ti.com.cn
ZHCSCF6 –MAY 2014
5 Pin Configuration and Functions
DSG PACKAGE
(TOP VIEW)
1
2
3
4
8
7
6
5
VCC
NC
RFIN
NC
RFOUT
NC
NC
PWDN
Pin Functions
PIN
DESCRIPTION
NAME
VCC
RFIN
NC
NO.
1
2
DC Bias.
RF input. Connect to an RF source through a DC-blocking capacitor. Internally matched to 50 Ω.
3, 4, 6, 8
No electrical connection. Connect pad to GND for board level reliability integrity.
When high the device is in power down state. When LOW or NC the device is in active state. Internal
pulldown resistor to GND.
PWDN
5
RF Output and DC Bias (VCC). Connect to DC supply through an RF choke inductor. Connect to output
load through a DC-blocking capacitor. Internally matched to 50 Ω.
RFOUT
GND
7
PowerPAD™
RF and DC GND. Connect to PCB ground plane.
Copyright © 2014, Texas Instruments Incorporated
3
TRF37A75
ZHCSCF6 –MAY 2014
www.ti.com.cn
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
(1)
MIN
MAX
6
UNIT
V
Supply Input voltage
–0.3
Input Power
With recommended Rbias resistor
10
dBm
°C
Operating virtual junction temperature range
–40
150
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 Handling Ratings
MIN
MAX
UNIT
TSTG
Storage temperature range
Electrostatic discharge
–65
150
°C
Human body model (HBM), per ANSI/ESDA/JEDEC
JS-001, all pins(1)
–1
–1
1
1
kV
kV
VESD
Charged device model (CDM), per JEDEC
(2)
specification JESD22-C101, all pins
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
4.5
NOM
MAX
5.25
125
UNIT
V
Supply Voltage, VCC
5
Operating junction temperature, TJ
–40
°C
6.4 Thermal Information
DSG
THERMAL METRIC(1)
UNIT
8 PINS
79.3
110
49
RθJA
Junction-to-ambient thermal resistance
RθJCtop
RθJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
6
ψJB
49.4
19.2
RθJCbot
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
4
Copyright © 2014, Texas Instruments Incorporated
TRF37A75
www.ti.com.cn
ZHCSCF6 –MAY 2014
6.5 Electrical Characteristics
VCC = 5 V, TA = 25°C, PWDN = Low, RBIAS = 1.8 Ω, LOUT = 100 nH, C1 = C2 = 1000 pF, ZS = ZL = 50 Ω (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DC Parameters
Total supply current
Power down current
Power dissipation
80
125
0.4
95
mA
µA
W
ICC
PWDN = High
Pdiss
RF Frequency Range
Frequency range
40
6000
MHz
dB
fRF = 400 MHz
13
12
12
12
12
11
19
32.5
4
fRF = 2000 MHz
fRF = 3000 MHz
fRF = 4000 MHz
fRF = 5000 MHz
fRF = 6000 MHz
At 2000 MHz
dB
dB
G
Small signal gain
dB
dB
dB
OP1dB
OIP3
NF
Output 1dB compression point
Output 3rd order intercept point
Noise figure
dBm
dBm
dB
At 2000 MHz, 2-tone 10MHz apart
At 2000 MHz
R(LI)
Input return loss
At 2000 MHz
16
13
dB
R(LO)
PWDN Pin
VIH
Output return loss
At 2000 MHz
dB
High level input level
Low level input level
High level input current
Low level input current
2
V
V
VIL
0.8
IIH
30
1
µA
µA
IIL
6.6 Timing Requirements
MIN
TYP
MAX
UNIT
PWDN Pin
tON
Turn-on Time
Turn-off Time
50% TTL to 90% POUT
50% TTL to 10% POUT
0.6
1.4
µs
µs
tOFF
Copyright © 2014, Texas Instruments Incorporated
5
TRF37A75
ZHCSCF6 –MAY 2014
www.ti.com.cn
6.7 Typical Characteristics
0.00
±5.00
±10.00
±15.00
±20.00
±25.00
±30.00
±35.00
±40.00
S11
S12
S21
0
1000
2000
3000
4000
5000
6000
Frequency (MHz)
C016
Freq [10.00 MHz to 6.000 GHz]
VCC = 5 V
Temp = 25°C
40 MHz to 6 GHz
VCC = 5 V
Temp = 25°C
10 MHz to 6 GHz
Data Taken with EVM and Bias T, De-embedded to DUT pin
Data Taken with EVM and Bias T, De-embedded to DUT pin
Figure 2. S11, S12, S21
Figure 1. Smith Chart – S11, S22
14
14.0
±40C
4.5 V
13.5
13
13.5
13.0
12.5
12.0
11.5
11.0
10.5
10.0
25C
85C
4.75 V
5 V
5.25 V
12.5
12
11.5
11
10.5
10
0
1000
2000
3000
4000
5000
6000
0
1000
2000
3000
4000
5000
6000
Frequency (MHz)
Frequency (MHz)
C001
C002
VCC curves
Temp = 25°C
Pin = –10 dBm
Temp curves
VCC = 5 V
Pin = –10 dBm
Figure 3. Gain vs Frequency
Figure 4. Gain vs Frequency
22
22
21
20
19
18
17
16
15
14
13
12
4.5
4.75
5
±40C
25C
85C
21
20
19
18
17
16
15
14
13
12
5.25
0
1000
2000
3000
4000
5000
6000
0
1000
2000
3000
4000
5000
6000
Frequency (MHz)
Freuency (MHz)
C007
C008
VCC curves
Temp = 25°C
Temp curves
VCC = 5 V
Figure 5. OP1dB vs Frequency
Figure 6. OP1dB vs Frequency
6
Copyright © 2014, Texas Instruments Incorporated
TRF37A75
www.ti.com.cn
ZHCSCF6 –MAY 2014
Typical Characteristics (continued)
35
35
33
31
29
27
25
23
21
19
17
15
33
31
29
27
25
23
21
19
17
15
4.5
4.75
5
-40
25
85
5.25
0
1000
2000
3000
4000
5000
6000
0
1000
2000
3000
4000
5000
6000
Frequency (MHz)
Frequency (MHz)
C004
C005
VCC curves
Temp = 25°C Pin = –10 dBm/tone
Figure 7. OIP3 vs Frequency
Temp curves
VCC = 5 V
Pin = –10 dBm/tone
Figure 8. OIP3 vs Frequency
6.0
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
-40
25
85
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
4.5
4.75
5
5.25
0
1000
2000
3000
4000
5000
6000
0
1000
2000
3000
4000
5000
6000
Frequency (MHz)
Frequency (MHz)
C010
C011
VCC curves
Temp = 25°C
Temp curves
VCC = 5 V
Figure 9. NF vs Frequency
Figure 10. NF vs Frequency
90
90
87
84
81
78
75
4.5
4.75
5
±40C
25C
85C
87
84
81
78
75
5.25
0
1000
2000
3000
4000
5000
6000
0
1000
2000
3000
4000
5000
6000
Frequency (MHz)
Frequency (MHz)
C013
C014
VCC curves
Temp = 25°C
Temp curves
VCC = 5 V
Figure 11. ICC vs Frequency
Figure 12. ICC vs Frequency
Copyright © 2014, Texas Instruments Incorporated
7
TRF37A75
ZHCSCF6 –MAY 2014
www.ti.com.cn
7 Detailed Description
7.1 Overview
The device is a 5 V general purpose RF gain block. It is a SiGe Darlington amplifier with integrated 50 Ω input
and output matching. The device contains an active bias circuit to maintain performance over a wide temperature
and voltage range. The included power down function allows the amplifier to shut down saving power when the
amplifier is not needed. Fast shut down and start up enable the amplifier to be used in a host of time division
duplex applications.
7.2 Functional Block Diagram
VCC
VCC
Active Bias and
Temperature
Compensation
Power Down
RF Input
RF Output
7.3 Feature Description
The TRF37A75 is a fixed gain RF amplifier. It is internally matched to 50 Ω on both the input and output. It is a
fully cascadable general purpose amplifier. The included active bias circuitry ensures the amplifier performance
is optimized over the full operating temperature and voltage ranges
7.4 Device Functional Modes
7.4.1 Power Down
The TRF37A75 PWDN pin can be left unconnected for normal operation or a logic-high for disable mode
operation. For applications that use the power down mode, normal 5 V TLL levels are supported.
8
Copyright © 2014, Texas Instruments Incorporated
TRF37A75
www.ti.com.cn
ZHCSCF6 –MAY 2014
8 Applications and Implementation
8.1 Application Information
The TRF37A75 is a wideband, high performance, general purpose RF amplifier. To maximize its performance,
good RF layout and grounding techniques should be employed.
8.2 Typical Application
The TRF37A75 device is typically placed in a system as illustrated in Figure 13.
VCC
DC Bypass
C5
Capacitor
DC Bias
R2
Resistor
C4
RF Bypass
Capacitors
C3
RF Choke
Inductor
L1
VCC
1
2
3
4
8
7
6
5
RFIN
RFOUT
PWDN
RF In
RF Out
C1
C2
DC Blocking
Capacitor
DC Blocking
Capacitor
Figure 13. Typical Application Schematic for TRF37A75
8.2.1 Design Requirements
Table 1. Design Parameters
PARAMETERS
EXAMPLE VALUES
Input power range
Output power
< 3 dBm
< 18 dBm
Operating frequency range
40 — 6000 MHz
8.2.2 Detailed Design Procedure
The TRF37A75 is a simple to use internally matched and cascadable RF amplifier. Following the recommended
RF layout with good quality RF components and local DC bypass capacitors will ensure optimal performance is
achieved. TI provides various support materials including S-Parameter and ADS models to allow the design to be
optimized to the user's particular performance needs.
Copyright © 2014, Texas Instruments Incorporated
9
TRF37A75
ZHCSCF6 –MAY 2014
www.ti.com.cn
8.2.3 Application Curve
22
20
18
16
14
12
10
8
22
20
18
16
14
12
10
8
OP1dB
NF
6
6
4
4
2
2
0
0
0
1000
2000
3000
4000
5000
6000
Frequency (MHz)
C017
Figure 14. OP1dB and NF vs Frequency
9 Power Supply Recommendations
All supplies may be generated from a common nominal 5 V source but should be isolated through decoupling
capacitors placed close to the device. The typical application schematic in Figure 13 is an excellent example.
Select capacitors with self-resonant frequency near the application frequency. When multiple capacitors are used
in parallel to create a broadband decoupling network, place the capacitor with the higher self-resonant frequency
closer to the device. Expensive tantalum capacitors are not needed for optimal performance.
10
Copyright © 2014, Texas Instruments Incorporated
TRF37A75
www.ti.com.cn
ZHCSCF6 –MAY 2014
10 Layout
10.1 Layout Guidelines
Good layout practice helps to enable excellent linearity and isolation performance. An example of good layout is
shown in Figure 15. In the example, only the top signal layer and its adjacent ground reference plane are shown.
•
Excellent electrical connection from the PowerPAD™ to the board ground is essential. Use the recommended
footprint, solder the pad to the board, and do not include solder mask under the pad.
•
•
Connect pad ground to device terminal ground on the top board layer.
Verify that the return DC and RF current path have a low impedance ground plane directly under the package
and RF signal traces into and out of the amplifier.
•
•
•
•
Ensure that ground planes on the top and any internal layers are well stitched with vias.
Do not route RF signal lines over breaks in the reference ground plane.
Avoid routing clocks and digital control lines near RF signal lines.
Do not route RF or DC signal lines over noisy power planes. Ground is the best reference, although clean
power planes can serve where necessary.
•
Place supply decoupling close to the device.
10.2 Layout Example
VCC
DC Bypass
Capacitor
DC Bias
Resistor
Note: Single DC bypass capacitor
can be used as long as it is close to
the pin 1 and is tied to the common
ground plane
RF Bypass
Capacitors
DC Bypass
Capacitor
RF Choke
Inductor
1
1
8
8
VCC
NC
2
7
7
RFIN
NC
RF In
2
RF Out
RFOUT
NC
3
3
6
6
DC Blocking
Capacitor
DC Blocking
Capacitor
4
4
5
PWDN
5
NC
Note: Ensure good RF microstrip or stripline traces are
used to connect the external components to the RF input
and output pins
Note: Ensure all components are connected to a common
RF/DC ground plane with plenty of vias
Figure 15. Layout
Copyright © 2014, Texas Instruments Incorporated
11
TRF37A75
ZHCSCF6 –MAY 2014
www.ti.com.cn
11 器件和文档支持
11.1 Trademarks
PowerPAD is a trademark of Texas Instruments.
11.2 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.3 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms and definitions.
12 机械封装和可订购信息
以下页中包括机械封装和可订购信息。 这些信息是针对指定器件可提供的最新数据。 这些数据会在无通知且不对
本文档进行修订的情况下发生改变。 欲获得该数据表的浏览器版本，请查阅左侧的导航栏。
12
Copyright © 2014, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
11-Aug-2022
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TRF37A75IDSGR
TRF37A75IDSGT
ACTIVE
ACTIVE
WSON
WSON
DSG
DSG
8
8
3000 RoHS & Green
250 RoHS & Green
NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 85
-40 to 85
A75I
A75I
Samples
Samples
NIPDAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
11-Aug-2022
Addendum-Page 2
GENERIC PACKAGE VIEW
DSG 8
2 x 2, 0.5 mm pitch
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224783/A
www.ti.com
PACKAGE OUTLINE
DSG0008A
WSON - 0.8 mm max height
SCALE 5.500
PLASTIC SMALL OUTLINE - NO LEAD
2.1
1.9
B
A
0.32
0.18
PIN 1 INDEX AREA
2.1
1.9
0.4
0.2
ALTERNATIVE TERMINAL SHAPE
TYPICAL
0.8
0.7
C
SEATING PLANE
0.05
0.00
SIDE WALL
0.08 C
METAL THICKNESS
DIM A
OPTION 1
0.1
OPTION 2
0.2
EXPOSED
THERMAL PAD
(DIM A) TYP
0.9 0.1
5
4
6X 0.5
2X
1.5
9
1.6 0.1
8
1
0.32
0.18
PIN 1 ID
(45 X 0.25)
8X
0.4
0.2
8X
0.1
C A B
C
0.05
4218900/E 08/2022
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
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EXAMPLE BOARD LAYOUT
DSG0008A
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
(0.9)
(
0.2) VIA
8X (0.5)
TYP
1
8
8X (0.25)
(0.55)
SYMM
9
(1.6)
6X (0.5)
5
4
SYMM
(1.9)
(R0.05) TYP
LAND PATTERN EXAMPLE
SCALE:20X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4218900/E 08/2022
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
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EXAMPLE STENCIL DESIGN
DSG0008A
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
8X (0.5)
METAL
8
SYMM
1
8X (0.25)
(0.45)
SYMM
9
(0.7)
6X (0.5)
5
4
(R0.05) TYP
(0.9)
(1.9)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 9:
87% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:25X
4218900/E 08/2022
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
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