TRF4903PWRG4 [TI]

315-915 MHz ISM Band RF Transmitter 24-TSSOP -40 to 85;


型号：	TRF4903PWRG4
厂家：	TEXAS INSTRUMENTS
描述：	315-915 MHz ISM Band RF Transmitter 24-TSSOP -40 to 85 电信 ISM频段光电二极管电信集成电路
文件：	总26页 (文件大小：395K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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ꢇꢈ ꢉꢊ ꢋ ꢌꢍꢎꢏꢈ ꢐ ꢑ ꢒꢋꢀ ꢈꢓꢔ ꢉꢕ ꢁꢂ ꢀ ꢁꢔꢉꢇ ꢑ ꢈꢀ ꢀꢌ ꢁ

SWRS023B − MAY 2004 − REVISED MARCH 2005

Single-Chip RF Transmitter for 315-MHz,

433-MHz, 868-MHz, and 915-MHz Industrial,

Scientific, and Medical (ISM) Bands

Programmable Brownout Detector

Integrated Data Bit Synchronizer and Baud

Rate Selection

2.2-V to 3.6-V Operation

Low Power Consumption

FSK/OOK Operation

Flexible 3-Wire Serial Interface

Minimal Number of External Components

Required

Integer-N Synthesizer With Fully Integrated

Voltage Controlled Oscillator (VCO)

24-Pin Plastic Thin-Shrink Small Outline

Package (TSSOP)

On-Chip Reference Oscillator and

Phase-Locked Loop (PLL)

Programmable XTAL Trimming

Lock Detect Indicator

Power Amplifier With 8-dBm Typical Output

Power

Companion Transmitter to the TRF6903

Transceiver

PW PACKAGE

(TOP VIEW)

TX_DATA

MODE

STDBY

PA_OUT

PA_GND1

CLOCK

DATA

STROBE

GND

XTAL_SW

XTAL

DGND

PA_VCC

PA_GND2

VCO_PRE_VCC

VCO_GND

VCO_CORE_VCC

VCO_BYPASS

VCO_TUNE

DVDD

DET_LD_DCLK

CP_GND

CP_OUT

CP_VCC

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the gates.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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SWRS023B − MAY 2004 − REVISED MARCH 2005

description

The TRF4903 single-chip solution is an integrated circuit intended for use as a low-cost multiband FSK or OOK

transmitter to establish a frequency-programmable, half-duplex RF link. The multichannel transmitter is

intended for digital (FSK, OOK) modulated applications in the North American and European 315-MHz,

433-MHz, 868-MHz, and 915-MHz ISM bands. The single-chip operates down to 2.2 V and is designed for low

power consumption. The synthesizer has a typical channel spacing of better than 200 kHz and features a

fully-integrated VCO. Only the PLL loop filter is external to the device.

Two fully-programmable operation modes, Mode0 and Mode1, allow extremely fast switching between two

preprogrammed settings (for example, TX_frequency_0/TX_frequency_1; …) without reprogramming the

device.

ISM band standards

Europe has assigned an unlicensed frequency band of 868 MHz to 870 MHz. This band is specifically defined

for short range devices with duty cycles from 0.1% to 100% in several subbands. The new European frequency

band, due to the duty cycle assignment, allows a reliable RF link and makes many new applications possible.

The North American unlicensed ISM band covers 902 MHz to 928 MHz (center frequency of 915 MHz) and is

suitable for short range RF links.

transmitter

The transmitter consists of an integrated VCO and tank circuit, a complete integer-N synthesizer, and a power

amplifier. The dividers, prescaler, and reference oscillator require only the addition of an external crystal and

a loop filter to provide a complete PLL with a typical frequency resolution of better than 200 kHz.

Since the typical RF output power is approximately 8 dBm, no additional external RF power amplifier is

necessary in most applications.

Four attenuation setting for the power amplifier are offered. This feature allows the user to fine tune the amplifier

for optimal output power.

baseband interface

The TRF4903 can easily be interfaced to a baseband processor such as the Texas Instruments MSP430

ultralow-power microcontroller (see Figure 1). The TRF4903 serial control registers are programmed by the

MSP430 and the MSP430 performs baseband operations in the software.

A synchronized data clock, programmable for most common data rates, is provided by the TRF4903. During

transmit, the data clock can be used to clock the transmit data from the microcontroller to the TRF4903 at

predefined data rates.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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SWRS023B − MAY 2004 − REVISED MARCH 2005

Microcontroller

Section

Antenna

RF Section

Transmit Data

TX_DATA

Brownout Detector, Lock Detect,

Data Clock

DET_LD_DCLK

PA_OUT

TRF4903

Transmitter

RF Out

Mode Select

Standby

MODE

MSP430

Family µC

STDBY

Discretes

Serial Control Data

Serial Control Clock

Serial Control Strobe

DATA

CLOCK

STROBE

Figure 1. System Block Diagram for Interfacing to the MSP430 Microcontroller

functional block diagram

DET_LD_DCLK

Bit Synchronizer

and

Data Clock

MUX

Band-gap

/A-

CLOCK

/Div. CTRL

/B-

Counter

Serial

DATA

STROBE

Interface

STDBY

MODE

Brownout

Detector

/N Prescaler

32/33

Counter

Lock

Detect

Output

Divider

1, 2, 3

PFD

CPs

PA_OUT

/Ref

2...255

TX_DATA

XTAL

Switch

VCO

VCO_TUNE 12

14 CP_OUT

Loop Filter

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SWRS023B − MAY 2004 − REVISED MARCH 2005

Terminal Functions

TERMINAL

I/O

DESCRIPTION

NAME

CLOCK

NO.

Serial interface clock signal input

Charge pump ground

CP_GND

CP_OUT

CP_VCC

DATA

Charge pump output

Charge pump supply voltage

Serial interface data signal input

Brownout detector (active high), PLL lock detect (active high), and data clock multiplexed

output

DET_LD_DCLK

DGND

Digital and XTAL oscillator ground

Digital and XTAL oscillator power supply

Substrate ground

DVDD

GND

MODE

Mode select input

PA_GND1

PA_GND2

PA_OUT

Power amplifier ground

Power amplifier output

PA_VCC

Power amplifier supply voltage

Standby input signal; active low

Serial interface strobe signal

STDBY

STROBE

TX_DATA

VCO_BYPASS

VCO_GND

VCO_TUNE

VCO_CORE_VCC

VCO_PRE_VCC

XTAL

Buffered TX data input

VCO bypass; connect to ground through a 100-pF capacitor

VCO ground

Tuning voltage for the integrated VCO

VCO core supply voltage

Divider and prescaler supply voltage

Connection to an external crystal reference

Connection to external capacitor, which sets the frequency deviation of the transmitted signal

I/O

XTAL_SW

†

absolute maximum ratings over operating free-air temperature (unless otherwise noted)

Supply voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.6 to 4.5 Vdc

Input voltage, logic signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.6 to 4.5 Vdc

Storage temperature range, T

ESD protection, human body model (HBM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 kV

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 65°C to 150°C

stg

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

recommended operating conditions

PARAMETER

Analog supply voltage

TEST CONDITIONS

MIN

2.2

TYP

MAX

3.6

UNIT

Digital supply voltage

2.2

Operating free-air temperature

−40

°C

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SWRS023B − MAY 2004 − REVISED MARCH 2005

dc electrical characteristics, V

= 2.7 V, T = 25°C

supply current

PARAMETER

TEST CONDITIONS

STDBY low

MIN

TYP

0.6

MAX

UNIT

Standby current

µA

315-MHz band

433-MHz band

868-MHz band

915-MHz band

315-MHz band

433-MHz band

868-MHz band

915-MHz band

TX current, PA disabled. PLL, VCO, dividers, and reference active

0-dB attenuation

10-dB attenuation

20-dB attenuation

0-dB attenuation

10-dB attenuation

20-dB attenuation

0-dB attenuation

10-dB attenuation

20-dB attenuation

0-dB attenuation

10-dB attenuation

20-dB attenuation

‡

TX current , PA enabled. PLL, VCO, dividers,

reference, and data clock active

‡

The TX current consumption is dependent upon the external PA matching circuit. The matching network is normally designed to achieve the

highest output power at the 0-dB attenuation setting. Changing the external matching components to optimize the output power for other

attenuation settings alters the typical current consumption from the typical values noted.

digital interface

PARAMETER

High-level input voltage

TEST CONDITIONS

MIN

−0.4

TYP MAX

UNIT

0.4

Low-level input voltage

High-level output voltage

Low-level output voltage

Digital input leakage current

= 0.5 mA

−0.4

0.4

<0.01

µA

VCO/output divider

PARAMETER

TEST CONDITIONS

Low-side injection, A<1:0> = 11

High-side injection, A<1:0> = 10

High-side injection, A<1:0> = 01

Low-side injection, A<1:0> = 01

Frequency offset = 50 kHz

MIN

304

430

868

902

TYP

MAX

316

450

870

928

UNIT

MHz

Frequency range: 315-MHz band

Frequency range: 433-MHz band

Frequency range: 868-MHz band

Frequency range: 915-MHz band

315

433

869

915

−77

−90

Closed loop phase noise

Tuning voltage

dBc/Hz

Frequency offset = 200 kHz

VCC at

terminal 11

0.1

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SWRS023B − MAY 2004 − REVISED MARCH 2005

ac electrical characteristics, V

impedances and loads

= 2.7 V, T = 25°C (continued)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

PA_OUT

See Figure 6

transmitter (XTAL, PLL, VCO, and PA), 315-MHz band

PARAMETER

TEST CONDITIONS

A<1:0> = 11

0-dB attenuation

MIN

TYP

315

MAX

UNIT

TX frequency range

304

316

MHz

10-dB attenuation

20-dB attenuation

Disabled, B<3> = 0

−2

†

Output power

dBm

−12

−80

−25

−30

Second harmonic

Third harmonic

dBc

DCLK active: E<15> = 1,

E<12:11> = 01

DCLK spurious at f

−28

dBc

DCLK

‡

Frequency deviation

FSK

kHz

Power ON-OFF ratio

OOK, 0-dB mode

FSK

Maximum data rate (NRZ)

kbit/s

OOK

†

‡

Matched to 50 Ω using external matching network.

Dependent upon external circuitry.

This spur is only present if DCLK is active. The resulting spur is within modulation (OOK or FSK) bandwidth and is considered a modulation

product. Within the authorized bands, this spur does not violate FCC or ETSI regulatory compliance.

transmitter (XTAL, PLL, VCO, and PA), 433-MHz band

PARAMETER

TEST CONDITIONS

A<1:0> = 10

0-dB attenuation

MIN

TYP

433

MAX

UNIT

TX frequency range

430

450

MHz

10-dB attenuation

20-dB attenuation

Disabled, B<3> = 0

−2

†

Output power

dBm

−12

−80

−25

−30

Second harmonic

Third harmonic

dBc

DCLK active: E<15> = 1,

E<12:11> = 01

DCLK spurious at f

−28

dBc

DCLK

‡

Frequency deviation

FSK

kHz

Power ON-OFF ratio

OOK, 0-dB mode

FSK

Maximum data rate (NRZ)

kbit/s

OOK

†

‡

Matched to 50 Ω using external matching network.

Dependent upon external circuitry.

This spur is only present if DCLK is active. The resulting spur is within modulation (OOK or FSK) bandwidth and is considered a modulation

product. Within the authorized bands, this spur does not violate FCC or ETSI regulatory compliance.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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SWRS023B − MAY 2004 − REVISED MARCH 2005

ac electrical characteristics, V

= 2.7 V, T = 25°C (continued)

transmitter (XTAL, PLL, VCO, and PA), 868-MHz band

PARAMETER

TEST CONDITIONS

A<1:0> = 11

0-dB attenuation

MIN

TYP

869

MAX

UNIT

TX frequency range

868

870

MHz

10-dB attenuation

20-dB attenuation

Disabled, B<3> = 0

−2

†

Output power

dBm

−12

−80

−25

−30

Second harmonic

Third harmonic

dBc

DCLK active: E<15> = 1,

E<12:11> = 01

DCLK spurious at f

−28

dBc

DCLK

‡

Frequency deviation

FSK

ꢀ32

kHz

Power ON-OFF ratio

OOK, 0-dB mode

FSK

Maximum data rate (NRZ)

kbit/s

OOK

†

‡

Matched to 50 Ω using external matching network.

Dependent upon external circuitry.

This spur is only present if DCLK is active. The resulting spur is within modulation (OOK or FSK) bandwidth and is considered a modulation

product. Within the authorized bands, this spur does not violate FCC or ETSI regulatory compliance.

transmitter (XTAL, PLL, VCO, and PA), 915-MHz band

PARAMETER

TEST CONDITIONS

A<1:0> = 11

0-dB attenuation

MIN

TYP

915

MAX

UNIT

TX frequency range

902

928

MHz

10-dB attenuation

20-dB attenuation

Disabled, B<3> = 0

−2

†

Output power

dBm

−12

−80

−25

−30

Second harmonic

Third harmonic

dBc

DCLK active: E<15> = 1,

E<12:11> = 01

DCLK spurious at f

−28

dBc

DCLK

‡

Frequency deviation

FSK

ꢀ32

kHz

Power ON-OFF ratio

OOK, 0-dB mode

FSK

Maximum data rate (NRZ)

kbit/s

OOK

†

‡

Matched to 50 Ω using external matching network.

Dependent upon external circuitry.

This spur is only present if DCLK is active. The resulting spur is within modulation (OOK or FSK) bandwidth and is considered a modulation

product. Within the authorized bands, this spur does not violate FCC or ETSI regulatory compliance.

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ꢁ

SWRS023B − MAY 2004 − REVISED MARCH 2005

ac electrical characteristics, V

= 2.7 V, T = 25°C (continued)

XTAL

PARAMETER

Frequency range

TEST CONDITIONS

MIN

TYP

MAX

UNIT

9.5

MHz

brownout detector

PARAMETER

TEST CONDITIONS

MIN

MAX

UNIT

Voltage threshold, V

Voltage steps (∆V)

Number of steps

Output level

Set by B<2:1>

2.2

2.8

det

200

Connected to typical input port of microcontroller

CMOS

timing data for serial interface

PARAMETER

Clock frequency

MIN

TYP

MAX

UNIT

MHz

(CLOCK)

w(CLKHI)

w(CLKLO)

su(D)

Clock high-time pulse width, clock high

Clock low-time pulse width, clock low

Setup time, data valid before CLOCK↑

Hold time, data valid after CLOCK ↑

h(D)

Delay time of CLOCK low before STROBE high

STROBE high-time pulse width, STROBE high

STROBE low-time pulse width, STROBE low

d(CLKLO)

w(STROBEHI)

w(STROBELO)

Data

Change

Valid

−V

MSB

LSB

DATA

−V

Start of

w(CLKHI)

Next Word

su(D)

h(D)

d(CLKLO)

−V

CLOCK

−V

w(STROBEHI)

w(CLKLO)

w(STROBELOW)

STROBE

−V

Clock Disabled

−V

Shift in Data

Clock Enabled

Note: Most significant bit (MSB) clocked in first to the synthesizer.

Store Data

Strobe Enabled

Figure 2. Timing Data for Serial Interface

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SWRS023B − MAY 2004 − REVISED MARCH 2005

timing data for DCLK and TX_DATA

PARAMETER

MIN

100

TYP

MAX

UNIT

Setup time, TX_DATA valid before DCLK ↑

Hold time, TX_DATA valid after DCLK ↑

su(TX)

h(TX)

Transmit

h(TX)

su(TX)

TX_DATA

Input

DCLK

Output

NOTE: TX_DATA is latched at the rising edge of DCLK.

Figure 3. Timing Data for DCLK and TX_DATA

If transmit capture mode is selected (by setting bit 15 in word E), the data transitions (high-to-low or low-to-high)

on the TXDATA pin is timed to coincide with the falling edge of DCLK. Any microcontroller using the TRF6903

can then latch TXDATA on the rising edge of DCLK. For more details, see the data clock section.

detailed description

bit synchronizer and data clock

When enabled, the integrated bit synchronizer and data clock circuitry provide as an output at terminal 16,

DET_LD_DCLK, a data clock based on a programmable bit rate. The bit rate is programmable via variables D1,

D2, and D3 and is always relative to the master clock (XTAL) frequency, F . Table 1 shows common bit rates

(kbps) vs selected crystal frequencies (MHz) and the respective settings of D1, D2, and D3.

The preprogrammed bit rate can be calculated based on the following equation:

crystal frequency (kHz)

Bit rate (kbps) +

+ f (kHz)

D1 D2 D3

where:

D1 = 1, 5, 6, or 8

D2 = 1, 2, 4, 8, 16, 32, 64, or 128

D3 = 15 or 16

The data clock circuit is designed to reset/clear internally with no user action required.

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SWRS023B − MAY 2004 − REVISED MARCH 2005

detailed description (continued)

Table 1. Common Bit Rates, Corresponding Crystal Frequencies, and Values of D1, D2, and D3

D1, D2, AND D3 MULTIPLIERS FOR COMMON CRYSTAL VALUES (CRYSTAL FREQUENCIES IN MHZ)

BIT RATE

(kbps)

9.8304

12.288

14.7456

15.72864

8x128x15

8x64x15

8x32x15

8x16x15

8x8x15

16.384

19.6608

0.6

0.9

8x128x16

6x128x16

5x128x16

6x64x16

5x64x16

6x32x16

5x32x16

6x16x16

5x16x16

6x8x16

8x128x16

1.024

1.2

5x128x15

8x64x16

6x128x16

8x64x16

8x128x16

1.8

8x64x16

8x32x16

8x16x16

8x8x16

8x4x16

8x2x16

8x1x16

2.048

2.4

5x64x15

8x32x16

5x128x15

8x64x16

6x64x16

8x32x16

3.6

4.096

4.8

5x32x15

8x16x16

5x64x15

8x32x16

6x32x16

8x16x16

7.2

8.192

9.6

5x16x15

8x8x16

5x32x15

8x16x16

6x16x16

8x8x16

14.4

16.384

19.2

28.8

5x8x15

8x4x16

5x16x15

8x8x16

5x8x16

6x8x16

8x4x16

6x4x16

32.768

38.4

57.6

5x4x15

8x2x16

8x4x15

5x8x15

8x4x16

5x4x16

6x4 x16

8x2x16

6x2x16

65.536

76.8

115.2

128

5x2x15

8x1x16

8x2x15

5x4x15

8x2x16

5x2x16

6x2x16

8x1x16

6x1x16

main divider

The main divider is composed of a 5-bit A-counter and a 9-bit B-counter and a prescaler. The A-counter controls

the divider ratio of the prescaler, which divides the VCO signal by either 33 or 32. The prescaler divides by 33

until the A-counter reaches its terminal count and then divides by 32 until the B-counter reaches terminal count,

whereupon both counters reset and the cycle repeats. The total divide-by-N operation is related to the 32/33

prescaler by:

= 33 x A + 32 x (B – A)

TOTAL

where 0 ≤ A ≤ 31 and 31 ≤ B ≤ 511 or, N

= A + 32B

TOTAL

Thus, the N-divider has a range of 992 ≤ N

≤ 16383

TOTAL

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SWRS023B − MAY 2004 − REVISED MARCH 2005

detailed description (continued)

PLL

The phase-locked loop is the radio frequency synthesizer for the TRF4903. It is used to generate the transmit

signal and as the local oscillator for the receive mixer. The signal (F ) from a reference crystal oscillator (XO)

is divided by an integer factor R down to F . The minimum frequency resolution, and thus, the minimum channel

spacing, is F .

F = F ÷ R where 1 ≤ R ≤ 256

The phase-locked loop is an integer-N design. The voltage-controlled oscillator (VCO) signal is divided by an

integer factor N to get a frequency at the phase detector input.

= F

÷ N

VCO

The phase detector compares the divided VCO signal to the divided crystal frequency and implements an error

signal from two charge pumps. The error signal corrects the VCO output to the desired frequency.

As is in any integer-N PLLs, the VCO output has spurs at integer multiples of the reference frequency (nF ).

In applications requiring contiguous frequency channels, the reference frequency is often chosen to be equal

to the channel spacing, thus, channel spacing = F = F ÷ R. When enabled and when the PLL is locked, the

DET_LD_DCLK terminal is high.

With the addition of an output divider for multiband operation, the actual output frequency, F , is given by:

out

VCO

A ) 32B

+ F

out

where F = F

under locked conditions. The actual minimum channel spacing is:

B R

where P = 1, 2, 3 and is set by A<1:0>.

oscillator circuit and reference divider

The reference divider reduces the frequency of the external crystal (F ) by an 8-bit programmable integer

divisor, R, to an internal reference frequency (F ) used for the phase-locked loop. The choice of internal

reference frequency also has implications for lock time, maximum data rate, noise floor, and loop-filter design.

The crystal frequency can be tuned using the F word to control internal trimming capacitors, which are placed

in parallel with the crystal. These offset a small frequency error in the crystal. In an FSK application, an additional

capacitor is placed in parallel (through terminal 19) with the external capacitor that is connected in series with

the crystal, thus, changing the load capacitance as the transmit data switch (TX_DATA, terminal 1) is toggled.

The change in load capacitance pulls the crystal off-frequency by the total frequency deviation.

Hence, the 2-FSK frequency, set by the level of TX_DATA and the external capacitor, can be represented as

follows:

+ TX_DATA Low (XTAL switch closed) ƒ

+ TX_DATA High (XTAL switch open)

out1

out2

Note that the frequencies ƒ

and ƒ

are centered about the frequency ƒ

= (ƒ

+ ƒ

)/2. When

out1

out2

center

out1

out2

transmitting FSK, ƒ

is considered to be the effective carrier frequency and any receiver local oscillator (LO)

center

should be set to the same ƒ

frequency the receiver’s IF frequency (ƒ ) for proper reception and

center

demodulation.

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SWRS023B − MAY 2004 − REVISED MARCH 2005

oscillator circuit and reference divider (continued)

For the case of high-side injection, the receiver LO would be set to ƒ = ƒ

+ ƒ . Using high-side injection,

center

the received data would be inverted from the transmitted data applied at terminal 1, TX_DATA. Conversely, for

low-side injection, the receiver LO would be set to ƒ = ƒ

− ƒ . Using low-side injection, the received data

center

would be the same as the transmitted data.

÷R

Reference

Divider

2...255

Crystal

Oscillator

Circuit

Phase-

Frequency

Detector

External

Loop

Filter

External Crystal

VCO

External Cap

for FSK

Charge Pumps

÷N

Main Divider

A, B Counters

32/33

Output

Divider

P = 1, 2, 3

Fvco

992 ≤ N ≤ 16383

out

Figure 4. TRF4903 PLL and Output Divider

phase detector and charge pumps

The phase detector is a phase-frequency design. The phase-frequency detector gain is given by:

K = I /2π

(CP)

where, I

is the peak charge pump current. The peak charge pump current is programmable with A<3:2> in

(CP)

three steps: 250 µA, 500 µA, and 1000 µA.

loop filter

The loop filter must be carefully chosen for proper operation of the TRF4903. The loop filter is typically a second-

or third-order passive design, and in FSK operation should have a bandwidth wide enough to allow the PLL to

relock quickly as the external crystal frequency is pulled off-center during modulation. The loop filter should also

be wider than the data modulation rate. These requirements should be balanced with making the loop narrow

enough in consideration of the reference frequency. In OOK the VCO frequency is not changed during data

modulation, so the filter bandwidth may be narrower than the modulation bandwidth. Filters can be calculated

using standard formulas in reference literature. Some third-order filter examples are shown in Table 2.

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SWRS023B − MAY 2004 − REVISED MARCH 2005

loop filter (continued)

C3R3

1 ) sC2R2

F(s) +

(

)

s C1 ) C2 ) sC1C2R2

s )

C3R3

lcp

Vtune

VCO_TUNE

VCO_VCC

CP_OUT

External-Loop Filter

Figure 5. Third-Order Loop Filter and Transfer Function

Table 2. Loop Filter Component Values For Various Data Rates at a Reference Frequency of 409.6 kHz,

0.5-mA Charge Pump Current

Manchester coding

NRZ coding

1.024

2.048

1.024

2.048

4.096

2.048

4.096

8.192

4.096

2.7

8.192

16.384

8.192

0.68

16.384

32.768

16.384

0.18

6.8

19.2

38.4

19.2

0.12

5.1

32.768

65.536

32.768

0.043

1.8

65.536

131.072

65.536

0.01

Bit rate − kbps

Data rate − kHz

Fundamental freq of BB

C1, nF

C2, nF

1800

430

100

1.5

0.47

Loop filter component

(selected to nearest

standard value)

C3, nF

R2, kΩ

R3, kΩ

6.8

0.39

0.1

0.075

6.8

0.027

0.0068

0.39

0.75

1.28

0.75

1.5

5.7

−3−dB bandwidth, kHz (approximate)

2.56

5.12

10.24

20.48

40.96

81.92

VCO

The voltage-controlled oscillator (VCO) produces an RF output signal with a frequency that is dependent upon

the dc-tuning voltage at terminal 12. The tank circuit is passive and has integrated varactor diodes and

inductors. The open-loop VCO gain is approximately 100 MHz/V.

A <1:0> is used to set the output divider ratio for operation within the 315-MHz, 433-MHz, 868-MHz, or 915-MHz

bands.

When the STDBY terminal is high, the reference, PLL, VCO, and dividers are powered up. When STDBY is low,

these blocks are powered down.

power amplifier

The power amplifier has three programmable attenuation states as determined by A<7:6> and B<7:6>: full

power (0-dB attenuation), 10-dB attenuation, and 20-dB attenuation. This adjustment feature allows the user

to fine-tune the device for optimal output power. The power amplifier can be enabled/disabled during transmit

by bit B<3>, PAED. During ASK or OOK operation, the TX_DATA signal turns the output stage of the power

amplifier on and off according to the transmit data incident at terminal 1.

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ꢊ

ꢋ

ꢍ

ꢎꢏ

ꢈ

ꢐ

ꢑ

ꢒ

ꢋꢀ

ꢈ

ꢓ

ꢔ

ꢉ

ꢕ

ꢁ

ꢂ

ꢀ

ꢁ

ꢔ

ꢉ

ꢇꢑ

ꢈ

ꢀ

ꢌ

ꢁ

SWRS023B − MAY 2004 − REVISED MARCH 2005

power amplifier (continued)

↑1

CH1 S22

0.5

CAL

OFS

0.2

0.5

CPL

−5

FIL

−0.5

−2

−1

START 300 MHz

STOP 1000 MHz

Figure 6. Typical PA Output Impedance (S22) at Device Terminal PA_OUT

brownout detector

The brownout detector provides an output voltage to indicate a low supply voltage. This may be used to signal

the need to change transmit power to conserve battery life, or for system power down. The brownout detector

threshold is set with the B word. Four different thresholds are available.

serial control interface

The TRF4903 is controlled through a serial interface; there are five 24-bit control words (A, B, C, D, E) which

set the device state. The A and B words are almost identical, and provide configuration settings for two modes,

designated 0 and 1, which are commonly used to configure the transmit states. Two transmit states can then

be rapidly selected using MODE (terminal 2). The C word sets the reference dividers, the power amplifier bias,

and contains various reset bits. The E word contains the bit-rate select, data clock control bits, and the power

amplifier bias control registers. The D word is used to trim the external crystal frequency and tune the

demodulator.

The register address is the composite of bits 23, 22, 1, and 0 of the 24 bits written to the serial interface. For

some words, certain bits of the address are don’t cares and are noted as XX. This flexible addressing scheme

allows compatibility with the TRF6901/TRF6903 and because of this flexibility, the data length of each register

varies from 15 bits to 22 bits.

Normal (write) operation of the serial interface is to clock in 24 bits through the CLOCK and DATA terminals.

DATA values are clocked into the 24-bit serial interface shift register on the rising edge of CLOCK. The 24-bit

value is decoded and written into the appropriate data register on the rising edge of STROBE.

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SWRS023B − MAY 2004 − REVISED MARCH 2005

PRINCIPLES OF OPERATION

ꢀ ꢁ ꢀ ꢀ ꢀ ꢂ

ꢊꢋ ꢌꢍ ꢎ ꢍ ꢍꢌꢏ ꢐ ꢐ

ꢀ ꢃ

ꢂ ꢄ

ꢂ ꢅ

ꢂ ꢆ

ꢂ ꢇ

ꢂ ꢈ

ꢂꢉ

ꢂꢁ

ꢂꢀ

ꢂꢂ

ꢂꢃ

ꢄ

ꢅ

ꢆ

ꢇ

ꢈ

ꢉ

ꢌ

ꢁ

ꢀ

ꢂ

ꢃ

ꢎꢍ ꢍ ꢌꢏ ꢐꢐ

ꢑ ꢒ ꢓꢔ ꢎꢕꢖ ꢓꢗꢓ ꢍ ꢏ ꢌ ꢘꢋ ꢏ ꢙꢙꢓ ꢚꢓ ꢏ ꢔ ꢛ

ꢜꢑ ꢋ ꢍꢏ ꢃ ꢝ

ꢎ

ꢞ

ꢃ

ꢂ

ꢑ ꢒꢓ ꢔ ꢞ ꢕꢖꢓ ꢗꢓ ꢍꢏ ꢌ ꢘ ꢋꢏꢙꢙ ꢓ ꢚꢓꢏ ꢔꢛ ꢜꢑ ꢋꢍ ꢏ ꢃꢝ

ꢑ ꢒꢓ ꢔ ꢞ ꢕꢖꢓ ꢗꢓ ꢍꢏ ꢌ ꢘ ꢋꢏꢙꢙ ꢓ ꢚꢓꢏ ꢔꢛ ꢜꢑ ꢋꢍ ꢏ ꢂꢝ

ꢟ ꢎ ꢃ

ꢟ ꢎ ꢂ

ꢂ

ꢘ ꢟ ꢎ ꢚꢚꢠ

ꢞꢡ ꢖ

ꢑ ꢒ ꢓꢔ ꢎꢕꢖ ꢓꢗꢓ ꢍ ꢏ ꢌ ꢘꢋ ꢏ ꢙꢙꢓ ꢚꢓ ꢏ ꢔ ꢛ

ꢜꢑ ꢋ ꢍꢏ ꢂ ꢝ

ꢢꢣ ꢤ ꢥ

ꢦ ꢦ ꢤ

ꢖꢏ ꢛ ꢏ ꢚꢛ ꢋꢌ ꢖꢏ ꢛ ꢠ

ꢨ ꢩꢌ ꢏ ꢐꢩꢋ ꢪ ꢍ ꢧꢔ ꢒ ꢫ ꢪꢏ

ꢟꢎ ꢧꢖ

ꢘ

ꢧ

ꢂ

ꢃ

ꢬꢏ ꢙ ꢏꢌ ꢏꢔ ꢚ ꢏ ꢖꢓ ꢗꢓ ꢍ ꢏ ꢌ ꢘꢋ ꢏ ꢙꢙꢓ ꢚꢓ ꢏ ꢔ ꢛ

ꢬ ꢏꢐꢏ ꢌꢗꢏꢍ

ꢌ

ꢃ

ꢂ

ꢞꢬ ꢎ

ꢞꢬꢞ

ꢞꢬ ꢘ ꢨ ꢭꢑ

ꢃ

ꢂ

ꢃ

ꢂ

ꢑ ꢮꢭ

ꢌ

ꢟꢢ ꢖ

ꢌꢏ ꢐꢏ ꢛ

ꢂ

ꢌ

ꢦ ꢦ ꢤꢭꢣ

ꢌ

ꢭꢨꢎꢯ ꢰꢨꢱꢔ ꢏ

ꢌ

ꢃ

ꢖ

NOTE: r = reserved. All reserved bits should be set low (0) during normal operation.

NOTE: All bits indicated as 1 should be set high (1) during normal operation.

NOTE: All bits indicated as 0 should be set low (0) during normal operation.

ADDRESS LOCATION NO. OF

BITS

DESCRIPTION

Main A divider coefficient (Mode 0)

DEFAULT VALUE

00xx

01xx

1000

1001

11x0

21:17

16:8

7:6

00000

Main B divider coefficient (Mode 0)

Controls the PA attenuation (Mode 0)

Enables transmit path (Mode 0); set to 1

Controls charge pump peak current

Output divider coefficient; band select

Main A divider coefficient (Mode 1)

Main B divider coefficient (Mode 1)

Controls the PA attenuation (Mode 1)

Enables transmit path (Mode 1); set to 1

Controls modulation scheme (FSK or OOK)

Enables or disables the power amplifier

Sets threshold for the brownout detector

Enables brownout detector

001110000

3:2

1:0

21:17

16:8

7:6

00000

001110000

2:1

21:14

21:20

19:17

Reference divider coefficient

01000000

Bit-rate divider D1

010

Bit-rate divider D2

Bit-rate divider D3

Transmit capture mode select

12:11

Determines the function of terminal 16, DET_LD_DCLK

Controls the position of the XTAL switch during OOK operation

Tunes the XTAL frequency by using an internal capacitor bank

PFD reset

18:16

000

NOTE: x = don’t care

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SWRS023B − MAY 2004 − REVISED MARCH 2005

PRINCIPLES OF OPERATION

At power on/startup, all of the TRF4903 register contents are as per the default values.

Address 00XX (A-Word)

Word A is a 22-bit data register comprising five fields. The main A-divider coefficient (mode 0), A<21:17>, is

the 5-bit divider ratio of the A counter when the MODE terminal is low. The main B-divider coefficient (mode

0), A<16:8>, is the 9-bit value of the B counter when the MODE terminal is low. A <21:17> and A <16:8> are

unsigned binary values. PA0, A<7:6>, is the 2-bit PA attenuation setting when the MODE terminal is low. CP

Acc., A<3:2>, sets the charge pump current. BND, A<1:0>, sets the output divider, which in turn determines

the band of operation.

Terminal 2 (MODE) selects bits A<21:5> if low, or B<21:5> if high.

Main divider A<21:17>: 5-bit value for divider ratio of the A counter

Main divider A<16:8>: 9-bit value for divider ratio of the B counter

PA attenuation A<7:6>: 2 bits for setting the PA attenuation

A<7:6>

PA ATTENUATION

0 dB

10 dB

20 dB

Not defined

A<5>: 1-bit; set high

A<3:2>: 2 bits for setting the charge pump current

A<3:2>

CP CURRENT

0.5 mA

1 mA

0.25 mA

Not defined

A<1:0>: 2-bit value to set the output divider and thus select the band of operation.

A<1:0>

OUTPUT DIVIDER

RATIO, P

BAND OF

OPERATION

315 MHz

433 MHz

868 MHz or 915 MHz

Bit A<4> is reserved and should be set to 0.

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SWRS023B − MAY 2004 − REVISED MARCH 2005

PRINCIPLES OF OPERATION

Address 01XX (B-Word)

Word B is a 22-bit data register comprising seven fields. The main A-divider coefficient (mode 1), B<21:17>,

is the 5-bit divider ratio of the A counter when the MODE terminal is high. The main B-divider coefficient

(mode 1), B<16:8>, is the 9-bit value of the B counter when the MODE terminal is high. B<21:17> and

B<16:8> are unsigned binary values. PA1, B<7:6>, is the 2-bit PA attenuation setting when the MODE

terminal is high. FSK/OOK, B<4>, sets the modulation scheme for TX. Bit B<3> enables/disables the power

amplifier while in transmit mode. The detector threshold, B<2:1>, is the 2-bit setting for the threshold voltage

of the brownout detector. Det. Enable, B<0>, is the brownout detector enable flag.

Terminal 21 (MODE) selects bits A<21:5> if low, or B<21:5> if high.

Main divider B<21:17>: 5-bit value for divider ratio of the A-counter

Main divider B<16:8>: 9-bit value for divider ratio of the B-counter

PA attenuation B<7:6>: 2 bits for setting the PA attenuation

B<7:6>

PA ATTENUATION

0 dB

10 dB

20 dB

Not defined

B<5>: 1-bit; set high

B<4> 1-bit modulation select

B<4>

TX MODULATION

OOK

FSK

B<3>: 1-bit PA enable/disable

B<3>

PA ENABLE/DISABLE

PA disabled

PA enabled

B<2:1>: 2-bit value to set the threshold voltage for the brownout detector

B<2:1>

THRESHOLD VOLTAGE

2.2 V

2.4 V

2.6 V

2.8 V

B<0>: 1 bit to enable brownout detector

B<0>

BROWNOUT DETECTOR

Off

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SWRS023B − MAY 2004 − REVISED MARCH 2005

PRINCIPLES OF OPERATION

Address 1000 (C-Word)

Word C is a 20-bit data register comprising four fields. The reference divider coefficient, C<21:14>, is the

8-bit divider ratio of the reference divider. The allowable reference divider range is 2 (C <21:14> =

00000010) through 255 (C <21:14> = 11111111).

Reference divider C <21:14>: 8-bit value for divider ratio of reference divider. C<21:14> is an unsigned

binary value.

Bits C<13> through C<2> are reserved and should be set to 0.

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SWRS023B − MAY 2004 − REVISED MARCH 2005

PRINCIPLES OF OPERATION

Address 1001 (E-Word)

Word E is a 20-bit data register comprising five fields. The bit rate or bit frequency, used by the transmit

synchronous mode is controlled by the BRA, E<21:20>, BRB, E<19:17>, and BRC, E<16>, fields. These

three fields control a sequence of dividers, D1 through D3, that divide the reference (crystal) frequency, F .

E<21:20>: 2 bits to set D1 divider setting

E<21:20>

E<19:17>: 3 bits to set D2 divider setting

E<19:17>

000

001

010

011

100

101

110

111

128

E<16>: 1 bit to set D3 divider setting

E<16>

TXM, E<15>, sets the transmit capture mode. If TXM is low, the TX_DATA terminal controls the transmit

function asynchronously. If TXM is high and the bit-rate clock enabled, the bit-rate clock, DCLK, is output at

the DET_LD_DCLK terminal and the transmit data at the TX_DATA terminal is latched on the rising edge of

DCLK.

E<12:11>: 2 bits to determine the function of terminal 16

E<12:11>

TERMINAL 16, DET_LD_DCLK, FUNCTION

PLL lock detect output (default)

Data clock output

Brownout detect output

Not used

Bits E<14>, E<13> and E<10> through E<2> are reserved and should be set to 0.

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SWRS023B − MAY 2004 − REVISED MARCH 2005

PRINCIPLES OF OPERATION

Address 11X0 (D-Word)

Word D is a 21-bit data register comprising two fields. Bit D<20> controls the position of the XTAL switch

during OOK operation. XTAL_Tune, D<18:16>, is used to fine tune the crystal frequency by using an internal

capacitor bank. PFD reset, D<15>, selects the source of the PFD reset signal.

D<20>: 1-bit value to control the position of the XTAL switch during OOK operation, when B<4>=0.

D<20>

XTAL SWITCH DURING

OOK OPERATION

TERMINAL 20

Unconnected (open)

Connected (closed)

High-Z

Shorted to ground externally

It is recommended that D<20> be set to 0 during OOK operation.

D<18:16>: 3-bit value to fine-tune the XTAL frequency by using an internal capacitor bank

D<18:16>

000

TYPICAL LOAD CAPACITANCE

13.23 pF

22.57 pF

17.9 pF

001

010

011

27.24 pF

15.56 pF

24.9 pF

100

101

110

20.23 pF

29.57 pF

111

D<15>: 1-bit value to select the reset signal for the PFD

D<15>

RESET SIGNAL

Derived from XTAL

Derived from prescaler

NOTE: The default setting for D<15> is 1.

Bits D<21>, D<19>, and D<12> through D<1> are reserved and should be set to 0.

operating modes

Controlled with terminal 3, STDBY

STDBY

OPERATING MODE

Power down of all blocks—programming mode

Operational mode and programming mode

Controlled with terminal 2, MODE

MODE

OPERATING MODE

Enable A-word

Enable B-word

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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SWRS023B − MAY 2004 − REVISED MARCH 2005

operating modes (continued)

The transmit mode is controlled by the A<5>, B<5>, and B<3> fields and the MODE and STDBY terminals.

A<5>

B<5>

B<3>

MODE

STDBY

OPERATING MODE

Off, programming mode; SPI enabled

Transmit mode 0, PA disabled; reference, PLL, VCO, and dividers enabled

Transmit mode 0, PA enabled; reference, PLL, VCO, and dividers enabled

Transmit mode 1, PA disabled; reference, PLL, VCO, and dividers enabled

Transmit mode 1, PA enabled; reference, PLL, VCO, and dividers enabled

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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ꢇ ꢈꢉ ꢊꢋ ꢌꢍ ꢎꢏ ꢈ ꢐ ꢑ ꢒꢋꢀꢈ ꢓ ꢔꢉ ꢕ ꢁꢂ ꢀꢁ ꢔꢉ ꢇꢑ ꢈꢀ ꢀ ꢌꢁ

SWRS023B − MAY 2004 − REVISED MARCH 2005

APPLICATION INFORMATION

TX_DATA

CLOCK

TRF4903

MODE

DATA

STDBY

STROBE

PA_OUT

TX_OUT

100 W

XTAL_SW

XTAL

Reference

Generator

(See Note B)

PA_VCC2

PA_VCC1

XTAL 1

Brownout

Detector

Crystek

017119

VCO_VCC

DVDD

Bit

Synchronizer

and

MUX

1, 2, 3

Divider

DET_LD_DCLK

Data Clock

0.1 mF

PA_VCC1

VCC

CP_OUT

C11

C10

PA_VCC2

10 mF

0.1 mF

100 pF

PLL

VCO

VCO_VCC

CP_VCC

DVDD

CP_VCC

C15

C13

C14

0.1 mF

C12

VCO_VCC

C16

0.1 mF

Component Selection for Band of Operation

433 MHz 868 MHz

Component Component

315 MHz

915 MHz

Component

Value

390 pF

5.1 pF

390 pF

560 nH

75 nH

Value

270 pF

4.7 pF

270 pF

470 nH

43 nH

Value

43 pF

1.5 pF

39 pF

330 nH

18 nH

Component

Value

43 pF

1.5 pF

33 pF

270 nH

15 nH

TX PA

Matching

Network

C12

C13

C15

5600 pF

120 pF

75 pF

C12

C13

C15

5600 pF

120 pF

75 pF

C12

C13

C15

5600 pF

120 pF

75 pF

C12

C13

C15

5600 pF

120 pF

75 pF

PLL Loop

Filter

15 kΩ

7.5 kΩ

27 pF

20 pF

27 pF

22 pF

XTAL Switch

Capacitors

5.6 pF

9.1 pF

Figure 7. Typical TRF4903 FSK Application Schematic

NOTES: A. Loop filter components selected for 19.2-kbps Manchester or 38.4-kbps NRZ for each band. I

Reference Frequency = 409.6 kHz

= 0.5 mA,

B. R1 = 100 Ω is optional for operation in the 868-MHz and 915-MHz bands.

C. XTAL switch capacitors selected for the frequency deviation of 50 kHz.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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ꢇꢈ ꢉꢊ ꢋ ꢌꢍꢎꢏꢈ ꢐ ꢑ ꢒꢋꢀ ꢈꢓꢔ ꢉꢕ ꢁꢂ ꢀ ꢁꢔꢉꢇ ꢑ ꢈꢀ ꢀꢌ ꢁ

SWRS023B − MAY 2004 − REVISED MARCH 2005

APPLICATION INFORMATION

TX_DATA

CLOCK

TRF4903

MODE

DATA

STDBY

STROBE

PA_OUT

TX_OUT

XTAL_SW

XTAL

27 pF

Reference

Generator

PA_VCC2

PA_VCC1

XTAL 1

Brownout

Detector

Crystek

017119

VCO_VCC

DVDD

Bit

Synchronizer

and

MUX

1, 2, 3

Divider

DET_LD_DCLK

Data Clock

0.1 mF

PA_VCC1

VCC

CP_OUT

C11

10 mF

C10

0.1 mF

PA_VCC2

100 pF

PLL

VCO

VCO_VCC

CP_VCC

DVDD

CP_VCC

C15

C13

C14

0.1 mF

C12

VCO_VCC

C16

0.1 mF

Component Selection for Band of Operation

433 MHz 868 MHz

Component Component

315 MHz

915 MHz

Component

Value

390 pF

5.1 pF

390 pF

560 nH

75 nH

Value

270 pF

4.7 pF

270 pF

470 nH

43 nH

Value

43 pF

1.5 pF

39 pF

330 nH

18 nH

Component

Value

43 pF

1.5 pF

33 pF

270 nH

15 nH

TX PA

Matching

Network

C12

C13

C15

5600 pF

120 pF

75 pF

C12

C13

C15

5600 pF

120 pF

75 pF

C12

C13

C15

5600 pF

120 pF

75 pF

C12

C13

C15

5600 pF

120 pF

75 pF

PLL Loop

Filter

15 kΩ

7.5 kΩ

Figure 8. Typical TRF4903 OOK Application Schematic

NOTE: Loop filter components selected for 19.2 kbps Manchester or 38.4 kbps NRZ for each band. I

Reference Frequency = 409.6 kHz

= 0.5 mA,

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PACKAGE OPTION ADDENDUM

www.ti.com

11-Apr-2013

PACKAGING INFORMATION

Orderable Device

Status Package Type Package Pins Package

Eco Plan Lead/Ball Finish

MSL Peak Temp

Op Temp (°C)

Top-Side Markings

Samples

Drawing

Qty

(1)

(2)

(3)

(4)

TRF4903PW

TRF4903PWG4

TRF4903PWR

TRF4903PWRG4

NRND

TSSOP

TBD

Call TI

-40 to 85

TRF4903

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability

information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that

lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between

the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight

in homogeneous material)

⁽³⁾MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)

Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a

continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1

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TRF4903PWRG4 [TI]

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