TRS202ECDG4 [TI]
5-V DUAL RS-232 LINE DRIVER/RECEIVER WITH ±15-kV ESD PROTECTION; 5 - V双RS - 232线路驱动器/接收器，具有± 15 kV ESD保护
| 型号： | TRS202ECDG4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 5-V DUAL RS-232 LINE DRIVER/RECEIVER WITH ±15-kV ESD PROTECTION |
| 文件： | 总17页 (文件大小：463K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TRS202E
www.ti.com
SLLS847C –JULY 2007–REVISED MAY 2010
5-V DUAL RS-232 LINE DRIVER/RECEIVER WITH ±15-kV ESD PROTECTION
Check for Samples: TRS202E
1
FEATURES
•
IEC61000-4-2 (Level 4) ESD Protection for
RS-232 Bus Pins
APPLICATIONS
•
•
•
•
•
•
Battery-Powered Systems
PDAs
Notebooks
Laptops
Palmtop PCs
Hand-Held Equipment
–
–
–
±8-kV Contact Discharge
±15-k-V Air-Gap Discharge
±15-kV Human-Body Model
•
Meets or Exceeds the Requirements of
TIA/EIA-232-F and ITU v.28 Standards
•
•
•
•
Operates at 5-V VCC Supply
D, DW, N, OR PW PACKAGE
(TOP VIEW)
Operates Up To 120 kbit/s
External Capacitors . . . 4 × 0.1 mF or 4 × 1 mF
1
C1+
V+
VCC
15 GND
16
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
2
3
4
5
6
7
8
14
13
12
11
10
9
C1-
DOUT1
RIN1
C2+
C2-
ROUT1
DIN1
V-
DOUT2
RIN2
DIN2
ROUT2
DESCRIPTION/ORDERING INFORMATION
The TRS202E device consists of two line drivers, two line receivers, and a dual charge-pump circuit. TRS202E
has IEC61000-4-2 (Level 4) ESD protection pin-to-pin (serial-port connection pins, including GND). The device
meets the requirements of TIA/EIA-232-F and provides the electrical interface between an asynchronous
communication controller and the serial-port connector. The charge pump and four small external capacitors
allow operation from a single 5-V supply. The device operates at data signaling rates up to 120 kbit/s and a
maximum of 30-V/ms driver output slew rate.
The TRS202E can work with both 0.1-mF or 1-mF external capacitors.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2007–2010, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
TRS202E
SLLS847C –JULY 2007–REVISED MAY 2010
www.ti.com
ORDERING INFORMATION
TA
PACKAGE(1) (2)
ORDERABLE PART NUMBER
TOP-SIDE MARKING
TRS202ECN
PDIP – N
SOIC – D
Tube of 25
Tube of 40
Reel of 2500
Tube of 40
Reel of 2000
Tube of 90
Reel of 2000
Tube of 25
Tube of 40
Reel of 2500
Tube of 40
Reel of 2000
Tube of 90
Reel of 2000
TRS202ECN
TRS202ECD
TRS202ECDR
TRS202ECDW
TRS202ECDWR
TRS202EPW
TRS202EPWR
TRS202EIN
TRS202EC
TRS202EC
0°C to 70°C
SOIC – DW
TSSOP – PW
PDIP – N
RU02EC
TRS202EIN
TRS202EI
TRS202EID
SOIC – D
TRS202EIDR
TRS202EIDW
TRS202EIDWR
TRS202EIPW
TRS202EIPWR
–40°C to 85°C
SOIC – DW
TRS202EI
RU02EI
TSSOP – PW
(1) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
(2) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
FUNCTION TABLES
xxx
Each Driver(1)
INPUT
DIN
OUTPUT
DOUT
L
H
L
H
(1) H = high level, L = low level
Each Receiver(1)
INPUT
RIN
OUTPUT
ROUT
L
H
H
L
Open
H
(1) H = high level, L = low level, Open
= input disconnected or connected
driver off
LOGIC DIAGRAM (POSITIVE LOGIC)
11
10
12
9
14
DIN1
DIN2
DOUT1
DOUT2
RIN1
7
13
8
ROUT1
ROUT2
RIN2
2
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Copyright © 2007–2010, Texas Instruments Incorporated
Product Folder Link(s): TRS202E
TRS202E
www.ti.com
SLLS847C –JULY 2007–REVISED MAY 2010
Absolute Maximum Ratings(1) (2)
over operating free-air temperature range (unless otherwise noted)
MIN
–0.3
MAX
6
UNIT
VCC
V+
Supply voltage range(2)
Positive charge pump voltage range(2)
V
V
V
VCC – 0.3
–14
14
V–
Negative charge pump voltage range
0.3
Drivers
–0.3
V+ + 0.3
±30
VI
Input voltage range
Output voltage range
V
V
Receivers
Drivers
V– –0.3
–0.3
V+ + 0.3
VCC + 0.3
Continuous
150
VO
Receivers
DOUT
TJ
Short-circuit duration
Operating virtual junction temperature
Storage temperature range
°C
°C
Tstg
–65
150
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages are with respect to network GND.
Package Thermal Impedance
over operating free-air temperature range (unless otherwise noted)
UNIT
D package
DW package
N package
PW package
73
57
qJA
Package thermal impedance(1) (2)
°C/W
67
108
(1) Maximum power dissipation is a function of TJ(max), qJA, and TA. The maximum allowable power dissipation at any allowable ambient
temperature is PD = (TJ(max) – TA)/qJA. Operating at the absolute maximum TJ of 150°C can affect reliability.
(2) The package thermal impedance is calculated in accordance with JESD 51-7.
Recommended Operating Conditions(1)
(see Figure 4)
MIN
4.5
2
NOM
MAX UNIT
Supply voltage
5
5.5
V
V
V
VIH
VIL
Driver high-level input voltage
Driver low-level input voltage
Driver input voltage
DIN
DIN
DIN
0.8
5.5
30
70
85
0
–30
0
VI
V
Receiver input voltage
TRS202EC
TRS202EI
TA
Operating free-air temperature
°C
–40
(1) Test conditions are C1–C4 = 0.1 mF at VCC = 5 V ±0.5 V.
Electrical Characteristics(1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 4)
PARAMETER
Suppy current
TEST CONDITIONS
No load, VCC = 5 V
MIN
TYP(2)
MAX
UNIT
ICC
8
15
mA
(1) Test conditions are C1–C4 = 0.1 mF at VCC = 5 V + 0.5 V.
(2) All typical values are at VCC = 5 V, and TA = 25°C.
Copyright © 2007–2010, Texas Instruments Incorporated
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TRS202E
SLLS847C –JULY 2007–REVISED MAY 2010
DRIVER SECTION
www.ti.com
Electrical Characteristics(1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 4)
PARAMETER
High-level output voltage
Low-level output voltage
High-level input current
Low-level input current
Short-circuit output current
Output resistance
TEST CONDITIONS
DOUT at RL = 3 kΩ to GND, DIN = GND
DOUT at RL = 3 kΩ to GND, DIN = VCC
VI = VCC
MIN TYP(2)
MAX UNIT
VOH
VOL
IIH
5
9
–9
V
V
–5
15
200
–200
–60
mA
mA
mA
Ω
IIL
VI at 0 V
–15
–10
(3)
IOS
ro
VCC = 5.5 V
VO = 0 V
VCC, V+, and V– = 0 V
VO = ±2 V
300
(1) Test conditions are C1–C4 = 0.1 mF at VCC = 5 V + 0.5 V.
(2) All typical values are at VCC = 5 V, and TA = 25°C.
(3) Short-circuit durations should be controlled to prevent exceeding the device absolute power-dissipation ratings, and not more than one
output should be shorted at a time.
Switching Characteristics(1)
over recommended ranges of suply voltage and operating free-air temperature (unless otherwise noted) (see Figure 4)
PARAMETER
TEST CONDITIONS
MIN TYP(2)
MAX UNIT
CL = 50 to 1000 pF,
One DOUT switching,
RL = 3 kΩ to 7 kΩ,
See Figure 1
Maximum data rate
120
kbit/s
Propagation delay time, low- to
high-level output
CL = 2500 pF,
All drivers loaded,
RL = 3 kΩ,
See Figure 1
tPLH(D)
tPHL(D)
tsk(p)
2
2
ms
ms
ns
Propagation delay time, high- to
low-level output
CL = 2500 pF,
All drivers loaded,
RL = 3 kΩ,
See Figure 1
RL = 3 kΩ to 7 kΩ,
See Figure 2
Pulse skew(3)
CL = 150 to 2500 pF,
300
Slew rate, transition region
(see Figure 1)
CL = 50 to 1000 pF,
VCC = 5 V
SR(tr)
RL = 3 kΩ to 7 kΩ,
3
6
30
V/ms
(1) Test conditions are C1–C4 = 0.1 mF at VCC = 5 V + 0.5 V.
(2) All typical values are at VCC = 5 V, and TA = 25°C.
(3) Pulse skew is defined as |tPLH – tPHL| of each channel of the same device.
ESD Protection
PIN
TEST CONDITIONS
TYP
UNIT
Human-Body Model
Contact Discharge
Air-gap Discharge
±15
±8
DOUT, RIN
kV
±15
4
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Copyright © 2007–2010, Texas Instruments Incorporated
Product Folder Link(s): TRS202E
TRS202E
www.ti.com
SLLS847C –JULY 2007–REVISED MAY 2010
RECEIVER SECTION
Electrical Characteristics(1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 4)
PARAMETER
TEST CONDITIONS
IOH = –1 mA
MIN
3.5 VCC – 0.4
TYP(2)
MAX UNIT
VOH
VOL
VIT+
VIT–
Vhys
ri
High-level output voltage
V
Low-level output voltage
IOL = 1.6 mA
VCC = 5 V,
VCC = 5 V,
0.4
2.4
V
V
Positive-going input threshold voltage
Negative-going input threshold voltage
TA = 25°C
TA = 25°C
1.7
0.8
0.2
3
1.2
0.5
5
V
Input hysteresis (VIT+ – VIT–
Input resistance
)
1
7
V
VI = ±3 V to ±25 V
kΩ
(1) Test conditions are C1–C4 = 0.1 mF at VCC = 5 V + 0.5 V.
(2) All typical values are at VCC = 5 V, and TA = 25°C.
Switching Characteristics(1)
over recommended ranges of suply voltage and operating free-air temperature (unless otherwise noted) (see Figure 3)
PARAMETER
TEST CONDITIONS
CL = 150 pF
MIN
TYP(2)
MAX
10
UNIT
ms
tPLH(R)
tPHL(R)
tsk(p)
Propagation delay time, low- to high-level output
Propagation delay time, high- to low-level output
Pulse skew(3)
0.5
CL = 150 pF
0.5
10
ms
300
ns
(1) Test conditions are C1–C4 = 0.1 mF at VCC = 5 V + 0.5 V.
(2) All typical values are at VCC = 5 V, and TA = 25°C.
(3) Pulse skew is defined as |tPLH – tPHL| of each channel of the same device.
Copyright © 2007–2010, Texas Instruments Incorporated
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TRS202E
SLLS847C –JULY 2007–REVISED MAY 2010
www.ti.com
PARAMETER MEASUREMENT INFORMATION
3 V
0 V
Input
1.5 V
1.5 V
RS-232
Output
Generator
50 W
(see Note B)
tTHL (D)
tTLH (D)
VOH
VOL
CL
RL
(see Note A)
3 V
–3 V
3 V
–3 V
Output
TEST CIRCUIT
VOLTAGE WAVEFORMS
6 V
tTHL(D) or tTLH(D)
SR(t ) =
f
NOTES: A. CL includes probe and jig capacitance.
B. The pulse generator has the following characteristics: PRR = 120 kbit/s, ZO = 50 W, 50% duty cycle, tr £ 10 ns, tf £ 10 ns.
Figure 1. Driver Slew Rate
3 V
RS-232
Output
1.5 V
1.5 V
Input
0 V
tPLH (D)
Generator
50 W
(see Note B)
CL
(see Note A)
tPHL (D)
RL
VOH
VOL
50%
50%
Output
TEST CIRCUIT
NOTES: A. CL includes probe and jig capacitance.
VOLTAGE WAVEFORMS
B. The pulse generator has the following characteristics: PRR = 120 kbit/s, ZO = 50 W, 50% duty cycle, tr £ 10 ns, tf £ 10 ns.
Figure 2. Driver Pulse Skew
3 V
Input
1.5 V
1.5 V
-3 V
Output
Generator
50 W
(see Note B)
tPHL (R)
tPLH (R)
CL
(see Note A)
VOH
VOL
50%
50%
Output
TEST CIRCUIT
VOLTAGE WAVEFORMS
NOTES: A. CL includes probe and jig capacitance.
B. The pulse generator has the following characteristics: ZO = 50 W, 50% duty cycle, tr £ 10 ns, tf £ 10 ns.
Figure 3. Receiver Propagation Delay Times
6
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Product Folder Link(s): TRS202E
TRS202E
www.ti.com
SLLS847C –JULY 2007–REVISED MAY 2010
APPLICATION INFORMATION
1
2
3
4
16
VCC
C1+
V+
+
CBYPASS
= 0.1 mF,
–
C1
0.1 mF,
6.3 V
+
15
C3†
0.1 mF
16 V
GND
+
–
–
14
13
C1–
C2+
C2–
DOUT1
RIN1
5 kW
C2
+
0.1 mF,
–
16 V
5
6
7
12
11
ROUT1
DIN1
V–
C4
–
0.1 mF,
16 V
+
10
9
DOUT2
DIN2
8
RIN2
ROUT2
5 kW
†
C3 can be connected to VCC or GND.
NOTES: A . Resistor values shown are nominal.
B . Nonpolarized ceramic capacitors are acceptable. If polarized tantalum or electrolytic capacitors are used, they should be
connected as shown.
Figure 4. Typical Operating Circuit and Capacitor Values
Capacitor Selection
The capacitor type used for C1-C4 is not critical for proper operation. The TRS202E requires 0.1-mF capacitors,
although capacitors up to 10 mF can be used without harm. Ceramic dielectrics are suggested for the 0.1-mF
capacitors. When using the minimum recommended capacitor values, make sure the capacitance value does not
degrade excessively as the operating temperature varies. If in doubt, use capacitors with a larger (e.g., 2×)
nominal value. The capacitors' effective series resistance (ESR), which usually rises at low temperatures,
influences the amount of ripple on V+ and V–.
Use larger capacitors (up to 10 mF) to reduce the output impedance at V+ and V–.
Bypass VCC to ground with at least 0.1 mF. In applications sensitive to power-supply noise generated by the
charge pumps, decouple VCC to ground with a capacitor the same size as (or larger than) the charge-pump
capacitors (C1–C4).
Copyright © 2007–2010, Texas Instruments Incorporated
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Product Folder Link(s): TRS202E
TRS202E
SLLS847C –JULY 2007–REVISED MAY 2010
www.ti.com
ESD Protection
TI TRS202E devices have standard ESD protection structures incorporated on the pins to protect against
electrostatic discharges encountered during assembly and handling. In addition, the RS232 bus pins (driver
outputs and receiver inputs) of these devices have an extra level of ESD protection. Advanced ESD structures
were designed to successfully protect these bus pins against ESD discharge of ±15-kV when powered down.
ESD Test Conditions
Stringent ESD testing is performed by TI, based on various conditions and procedures. Please contact TI for a
reliability report that documents test setup, methodology, and results.
Human-Body Model (HBM)
The HBM of ESD testing is shown in Figure 5. Figure 6 shows the current waveform that is generated during a
discharge into a low impedance. The model consists of a 100-pF capacitor, charged to the ESD voltage of
concern, and subsequently discharged into the device under test (DUT) through a 1.5-kΩ resistor.
RD
1.5 kW
CS
+
–
DUT
VHBM
100 pF
Figure 5. HBM ESD Test Circuit
1.5
VHBM = 2 kV
DUT = 10-V, 1-W Zener Diode
|
1.0
0.5
0.0
0
50
100
150
200
Time (ns)
Figure 6. Typical HBM Current Waveform
8
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Product Folder Link(s): TRS202E
TRS202E
www.ti.com
SLLS847C –JULY 2007–REVISED MAY 2010
Machine Model (MM)
The MM ESD test applies to all pins using a 200-pF capacitor with no discharge resistance. The purpose of the
MM test is to simulate possible ESD conditions that can occur during the handling and assembly processes of
manufacturing. In this case, ESD protection is required for all pins, not just RS-232 pins. However, after PC
board assembly, the MM test no longer is as pertinent to the RS-232 pins.
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Product Folder Link(s): TRS202E
PACKAGE OPTION ADDENDUM
www.ti.com
21-Apr-2010
PACKAGING INFORMATION
Orderable Device
TRS202ECD
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
SOIC
D
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TRS202ECDG4
TRS202ECDR
TRS202ECDRG4
TRS202ECDW
TRS202ECDWG4
TRS202ECDWR
TRS202ECDWRG4
TRS202ECN
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
PDIP
D
D
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
DW
DW
DW
DW
N
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
25
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
TRS202ECNE4
TRS202ECPW
TRS202ECPWG4
TRS202ECPWR
TRS202ECPWRG4
TRS202EID
PDIP
N
25
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
TSSOP
TSSOP
TSSOP
TSSOP
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
PDIP
PW
PW
PW
PW
D
90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TRS202EIDG4
TRS202EIDR
D
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TRS202EIDRG4
TRS202EIDW
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
DW
DW
DW
DW
N
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TRS202EIDWG4
TRS202EIDWR
TRS202EIDWRG4
TRS202EIN
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
25
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
TRS202EINE4
TRS202EIPW
PDIP
N
25
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
TSSOP
PW
90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
21-Apr-2010
Orderable Device
Status (1)
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
TRS202EIPWG4
TRS202EIPWR
TSSOP
PW
16
16
16
90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TSSOP
TSSOP
PW
PW
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TRS202EIPWRG4
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
30-Jul-2010
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TRS202ECDR
TRS202ECDWR
TRS202ECPWR
TRS202EIDR
SOIC
SOIC
D
16
16
16
16
16
16
2500
2000
2000
2500
2000
2000
330.0
330.0
330.0
330.0
330.0
330.0
16.4
16.4
12.4
16.4
16.4
12.4
6.5
10.3
2.1
2.7
1.6
2.1
2.7
1.6
8.0
12.0
8.0
16.0
16.0
12.0
16.0
16.0
12.0
Q1
Q1
Q1
Q1
Q1
Q1
DW
PW
D
10.75 10.7
TSSOP
SOIC
6.9
6.5
5.6
10.3
8.0
TRS202EIDWR
TRS202EIPWR
SOIC
DW
PW
10.75 10.7
6.9 5.6
12.0
8.0
TSSOP
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
30-Jul-2010
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TRS202ECDR
TRS202ECDWR
TRS202ECPWR
TRS202EIDR
SOIC
SOIC
D
16
16
16
16
16
16
2500
2000
2000
2500
2000
2000
346.0
346.0
346.0
346.0
346.0
346.0
346.0
346.0
346.0
346.0
346.0
346.0
33.0
33.0
29.0
33.0
33.0
29.0
DW
PW
D
TSSOP
SOIC
TRS202EIDWR
TRS202EIPWR
SOIC
DW
PW
TSSOP
Pack Materials-Page 2
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
M
0,10
0,65
14
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
8
14
16
20
24
28
DIM
3,10
2,90
5,10
4,90
5,10
4,90
6,60
6,40
7,90
9,80
9,60
A MAX
A MIN
7,70
4040064/F 01/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
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