TS12A44513DR [TI]
LOW ON-STATE RESISTANCE QUAD SPST CMOS ANALOG SWITCHES; 低导通电阻四路SPST CMOS模拟开关
| 型号： | TS12A44513DR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | LOW ON-STATE RESISTANCE QUAD SPST CMOS ANALOG SWITCHES |
| 文件： | 总16页 (文件大小：458K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TS12A44513, TS12A44514, TS12A44515
www.ti.com ............................................................................................................................................................................................. SCDS247–OCTOBER 2008
LOW ON-STATE RESISTANCE
QUAD SPST CMOS ANALOG SWITCHES
1
FEATURES
•
2-V to 12-V Single-Supply Operation
•
•
Specified Low OFF-Leakage Currents:
•
Specified ON-State Resistance:
–
–
1 nA at 25°C
10 nA at 85°C
–
–
–
15 Ω Max With 12-V Supply
20 Ω Max With 5-V Supply
50 Ω Max With 3.3-V Supply
Specified Low ON-Leakage Currents:
–
–
1 nA at 25°C
10 nA at 85°C
•
RDSON Matching
–
–
–
2.5 Ω (Max) at 12 V
3 Ω (Max) at 5 V
•
•
Low Charge Injection: 11.5 pC (12-V Supply)
Fast Switching Speed:
tON = 80 ns, tOFF = 50 ns (12-V Supply)
3.5 Ω (Max) at 3.3 V
•
•
•
Break-Before-Make Operation (tON > tOFF)
TTL/CMOS-Logic Compatible With 5-V Supply
Available in TSSOP-14 Package, SOIC-14
D OR PW PACKAGE...TS12A44513
(TOP VIEW)
D OR PW PACKAGE...TS12A44514
(TOP VIEW)
D OR PW PACKAGE...TS12A44515
(TOP VIEW)
V
V
V
+
1
2
3
4
5
6
7
14
13
12
1
2
3
4
5
6
7
14
13
12
1
2
3
4
5
6
7
14
13
12
NO1
NO1
COM1
NO2
NC1
COM1
NC2
+
+
COM1
NC2
IN1
IN4
IN1
IN4
IN1
IN4
11 NC4
11 NO4
11 NC4
COM2
IN2
COM2
IN2
COM2
IN2
10
9
10
9
10
9
COM4
COM3
NO3
COM4
COM3
NO3
COM4
COM3
NC3
IN3
IN3
IN3
8
8
8
GND
GND
GND
DESCRIPTION/ORDERING INFORMATION
The TS12A44513/TS12A44514/TS12A44515 are quad single pole/single throw (SPST), low-voltage / wide range,
single-supply CMOS analog switches, with very low switch ON-state resistance. The TS12A44513 has two
switches normally closed (NC) and two switches normally open (NO), the TS12A44514 switches are normally
open (NO), the TS12A44515 switches are normally closed (NC).
These CMOS switches can operate continuously with a single supply between 2 V and 12 V. Each switch can
handle rail-to-rail analog signals. The OFF-leakage current maximum is only 1 nA at 25°C or 10 nA at 85°C.
All digital inputs have 0.8-V to 2.4-V logic thresholds, ensuring TTL/CMOS-logic compatibility when using a 5-V
supply.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2008, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
TS12A44513, TS12A44514, TS12A44515
SCDS247–OCTOBER 2008 ............................................................................................................................................................................................. www.ti.com
ORDERING INFORMATION
TA
PACKAGE(1)(2)
ORDERABLE PART NUMBER
TS12A44513DR
TOP-SIDE MARKING
TS12A44513
Reel of 2500
SOIC – D
Reel of 2500
Reel of 2500
Reel of 2000
Reel of 2000
Reel of 2000
TS12A44514DR
TS12A44515DR
TS12A44513PWR
TS12A44514PWR
TS12A44515PWR
TS12A44514
TS12A44515
YD4513
–40°C to 85°C
TSSOP – PW
YD4514
YD4515
(1) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
(2) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
Web site at www.ti.com.
ABSOLUTE MINIMUM AND MAXIMUM RATINGS(1)(2)
voltages referenced to GND
MIN
MAX UNIT
V+
Supply voltage range
–0.3
13
V
VNC
VNO Analog voltage range(3)
VCOM
–0.3 V+ + 0.3
V
INC
INO
Analog Current range
-20
20
mA
ICOM
Continuous current into any terminal
Peak current, NO or COM (pulsed at 1 ms, 10% duty cycle)
ESD per method 3015.7
±20
±30
2000
85
mA
mA
V
TA
Operating temperature range
–40
–65
°C
D package
1.15
0.88
150
300
Mounted on JEDEC 4-layer board (JESD
51-7), No airflow, TA = 25°C, TJ = 125°C
PD
Tstg
Power dissipation
W
PW package
Storage temperature range
°C
°C
Lead temperature (soldering, 10 s)
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The algebraic convention, whereby the most negative value is a minimum and the most positive value is a maximum
(3) Voltages exceeding V+ or GND on any signal terminal are clamped by internal diodes. Limit forward-diode current to maximum current
rating.
THERMAL IMPEDANCE
UNIT
D package
PW package
D package
PW package
133
167
86
Mounted on JEDEC 1-layer board (JESD 51-3),
No airflow
Thermal impedance,
junction to free air
θJA
°C/W
Mounted on JEDEC 4-layer board (JESD 51-7),
No airflow
112
2
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Product Folder Link(s): TS12A44513 TS12A44514 TS12A44515
TS12A44513, TS12A44514, TS12A44515
www.ti.com ............................................................................................................................................................................................. SCDS247–OCTOBER 2008
ELECTRICAL CHARACTERISTICS FOR 5-V SUPPLY(1)
V+ = 4.5 V to 5.5 V, VINH = 2.4 V, VINL = 0.8 V, TA = –40°C to 85°C (unless otherwise noted)
PARAMETER
Analog Switch
SYMBOL
TEST CONDITIONS
TA
MIN TYP(2)
MAX UNIT
Analog signal range
VCOM, VNO, VNC
ron
0
V+
20
30
3
V
25°C
Full
12
V+ = 4.5 V, VCOM = 3.5 V,
ICOM = 1 mA
ON-state resistance
Ω
25°C
Full
1
ON-state resistance
flatness
VCOM = 1 V, 2 V, 3 V,
ICOM = 1 mA
ron(flat)
Ω
Ω
4
ON-state resistance
matching between
channels(3)
25°C
3
V+ = 4.5 V, ICOM = 5 mA,
VNO or VNC = 3 V
Δron
TMIN to TMAX
4
25°C
Full
1
10
1
NO, NC
INO(OFF),
INC(OFF)
V+ = 5.5 V, VCOM = 1 V,
VNO or VNC = 4.5 V
nA
nA
nA
OFF leakage current(4)
25°C
Full
COM
V+ = 5.5 V, VCOM = 1 V,
VNO or VNC = 4.5 V
ICOM(OFF)
OFF leakage current(4)
10
1
25°C
Full
COM
V+ = 5.5 V, VCOM = 4.5 V,
VNO or VNC = 4.5 V
ICOM(ON)
ON leakage current(4)
10
Digital Control Input (IN)
Input logic high
VIH
VIL
Full
Full
Full
2.4
0
V+
0.8
V
V
Input logic low
Input leakage current
Dynamic
IIH, IIL
VIN = V+, 0 V
0.01
µA
25°C
Full
45
35
100
125
50
Turn-on time
tON
see Figure 6
see Figure 6
ns
ns
25°C
Full
Turn-off time
tOFF
QC
CNO(OFF)
70
CL = 1 nF, VNO = 0 V,
RS = 0 Ω, See Figure 5
Charge injection(5)
25°C
25°C
25°C
–1.5
8
pC
pF
pF
NO, NC
OFF capacitance
,
f = 1 MHz, See Figure 8
f = 1 MHz, See Figure 8
CNC(OFF)
COM
OFF capacitance
CCOM(OFF)
8
COM
ON capacitance
CCOM(ON)
CI
f = 1 MHz, See Figure 8
VIN = V+, 0 V
25°C
25°C
25°C
19
2
pF
pF
Digital input capacitance
RL = 50 Ω, CL = 15 pF,
VNO = 1 VRMS, f = 100 kHz
Bandwidth
BW
530
MHz
RL = 50 Ω, CL = 15 pF,
VNO = 1 VRMS, f = 100 kHz
OFF isolation
OISO
THD
25°C
25°C
–94
dB
%
RL = 50 Ω, CL = 15 pF,
VNO = 1 VRMS, f = 100 kHz
Total harmonic distortion
0.09
Supply
25°C
Full
0.05
0.1
V+ supply current
I+
VIN = 0 V or V+
µA
(1) The algebraic convention, whereby the most negative value is a minimum and the most positive value is a maximum.
(2) Typical values are at TA = 25°C.
(3) ΔrON = rON(MAX) – rON(MIN)
(4) Leakage parameters are 100% tested at maximum-rated hot operating temperature, and are ensured by correlation at 25°C.
(5) Specified by design, not production tested
Copyright © 2008, Texas Instruments Incorporated
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SCDS247–OCTOBER 2008 ............................................................................................................................................................................................. www.ti.com
ELECTRICAL CHARACTERISTICS FOR 12-V SUPPLY(1)
V+ = 11.4 V to 12.6 V, VINH = 5 V, VINL = 0.8 V, TA = –40°C to 85°C (unless otherwise noted)
PARAMETER
Analog Switch
SYMBOL
TEST CONDITIONS
TA
MIN TYP(2)
MAX UNIT
Analog signal range
VCOM, VNO, VNC
ron
0
V+
10
15
3
V
25°C
Full
6.5
V+ = 11.4 V, VCOM = 10 V,
ICOM = 1 mA
ON-state resistance
Ω
V+ = 11.4 V,
VCOM = 2 V, 5 V, 10 V,
ICOM = 1 mA
25°C
1.5
ON-state resistance
flatness
ron(flat)
Ω
Ω
Full
25°C
4
2.5
3
ON-state resistance
matching between
channels(3)
V+ = 11.4 V, ICOM = 5 mA,
VNO or VNC = 10 V
Δron
TMIN to TMAX
25°C
Full
1
10
1
NO, NC
INO(OFF),
INC(OFF)
V+ = 12.6 V, VCOM = 1 V,
VNO or VNC = 10 V
nA
nA
nA
OFF leakage current(4)
25°C
Full
COM
V+ = 12.6 V, VCOM = 1 V,
VNO or VNC = 10 V
ICOM(OFF)
OFF leakage current(4)
10
1
25°C
Full
COM
V+ = 12.6 V, VCOM = 10 V,
VNO or VNC = 10 V
ICOM(ON)
ON leakage current(4)
10
Digital Control Input (IN)
Input logic high
VIH
VIL
Full
Full
Full
5
0
V+
0.8
V
V
Input logic low
Input leakage current
Dynamic
IIH, IIL
VIN = V+, 0 V
0.001
µA
25°C
Full
25
20
75
80
45
50
Turn-on time
tON
See Figure 6
See Figure 6
ns
ns
25°C
Full
Turn-off time
tOFF
QC
CNO(OFF)
CL = 1 nF, VNO = 0 V,
RS = 0 Ω, See Figure 5
Charge injection(5)
25°C
25°C
25°C
–10.5
pC
pF
pF
NO, NC
OFF capacitance
,
f = 1 MHz, See Figure 8
f = 1 MHz, See Figure 8
8
8
CNC(OFF)
COM
OFF capacitance
CCOM(OFF)
COM
ON capacitance
CCOM(ON)
CI
f = 1 MHz, See Figure 8
VIN = V+, 0 V
25°C
25°C
25°C
21.5
2
pF
pF
Digital input capacitance
RL = 50 Ω, CL = 15 pF,
VNO = 1 VRMS, f = 100 kHz
Bandwidth
BW
530
MHz
RL = 50 Ω, CL = 15 pF,
VNO = 1 VRMS, f = 100 kHz
OFF isolation
OISO
THD
25°C
25°C
–95
dB
%
RL = 50 Ω, CL = 15 pF,
VNO = 1 VRMS, f = 100 kHz
Total harmonic distortion
0.07
Supply
25°C
Full
0.05
0.2
V+ supply current
I+
VIN = 0 V or V+
µA
(1) The algebraic convention, whereby the most negative value is a minimum and the most positive value is a maximum.
(2) Typical values are at TA = 25°C.
(3) ΔrON = rON(MAX) – rON(MIN)
(4) Leakage parameters are 100% tested at maximum-rated hot operating temperature, and are ensured by correlation at 25°C.
(5) Specified by design, not production tested
4
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Product Folder Link(s): TS12A44513 TS12A44514 TS12A44515
TS12A44513, TS12A44514, TS12A44515
www.ti.com ............................................................................................................................................................................................. SCDS247–OCTOBER 2008
ELECTRICAL CHARACTERISTICS FOR 3-V SUPPLY(1)
V+ = 3 V to 3.6 V, TA = –40°C to 85°C (unless otherwise noted)
PARAMETER
Analog Switch
SYMBOL
TEST CONDITIONS
TA
MIN TYP(2)
MAX UNIT
Analog signal range
VCOM, VNO, VNC
ron
0
V+
40
50
3
V
25°C
Full
20
V+ = 3 V, VCOM = 1.5 V,
INO = 1 mA,
ON-state resistance
Ω
V+ = 3 V,
VCOM = 1 V, 1.5 V, 2 V,
ICOM = 1 mA
25°C
1
ON-state resistance
flatness
ron(flat)
Ω
Ω
Full
25°C
4
3.5
4.5
ON-state resistance
matching between
channels(3)
V+ = 2.7 V, ICOM = 5 mA,
VNO or VNC = 1.5 V
Δron
TMIN to TMAX
25°C
Full
1
10
1
NO, NC
INO(OFF),
INC(OFF)
V+ = 3.6 V, VCOM = 1 V,
VNO or VNC = 3 V
nA
nA
nA
OFF leakage current(4)
25°C
Full
COM
V+ = 3.6 V, VCOM = 1 V,
VNO or VNC = 3 V
ICOM(OFF)
OFF leakage current(4)
10
1
25°C
Full
COM
V+ = 3.6 V, VCOM = 3 V,
VNO or VNC = 3 V
ICOM(ON)
ON leakage current(4)
10
Digital Control Input (IN)
Input logic high
VIH
VIL
Full
Full
Full
2.4
0
V+
0.8
V
V
Input logic low
Input leakage current
Dynamic
IIH, IIL
VIN = V+, 0 V
0.01
µA
25°C
Full
70
50
120
175
80
Turn-on time(5)
tON
See Figure 6
See Figure 6
ns
ns
25°C
Full
Turn-off time(5)
tOFF
120
Charge injection(5)
QC
CNO(OFF)
CNC(OFF)
CL = 1 nF, See Figure 5
f = 1 MHz, See Figure 8
25°C
–0.5
8
pC
pF
NO, NC
OFF capacitance
,
25°C
25°C
COM
OFF capacitance
CCOM(OFF)
f = 1 MHz, See Figure 8
8
pF
COM
ON capacitance
CCOM(ON)
CI
f = 1 MHz, See Figure 8
VIN = V+, 0 V
25°C
25°C
25°C
17
2
pF
pF
Digital input capacitance
RL = 50 Ω, CL = 15 pF,
VNO = 1 VRMS, f = 100 kHz
Bandwidth
BW
510
MHz
RL = 50 Ω, CL = 15 pF,
VNO = 1 VRMS, f = 100 kHz
OFF isolation
OISO
THD
25°C
25°C
–94
dB
%
RL = 50 Ω, CL = 15 pF,
VNO = 1 VRMS, f = 100 kHz
Total harmonic distortion
0.27
Supply
25°C
Full
0.03
0.05
V+ supply current
I+
VIN = 0 V or V+
µA
(1) The algebraic convention, whereby the most negative value is a minimum and the most positive value is a maximum.
(2) Typical values are at TA = 25°C.
(3) ΔrON = rON(MAX) – rON(MIN)
(4) Leakage parameters are 100% tested at maximum-rated hot operating temperature, and are ensured by correlation at 25°C.
(5) Specified by design, not production tested
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TYPICAL PERFORMANCE
25
20
15
10
5
30
25
20
15
10
5
V
= 3 V
T
= 85°C
= 25°C
+
A
T
A
A
T
= –40°C
V
= 4.5 V
+
V
= 11.4 V
+
0
0
0
1
2
3
4
5
6
7
8
9
10 11 12
0
1
2
3
4
Analog Signal, V
(V)
Analog Signal, V
(V)
COM
COM
Figure 2. rON vs VCOM (V+ = 3 V)
Figure 1. rON vs VCOM (TA = 25°C)
25
20
15
10
5
25
20
15
10
5
T
T
= 85°C
= 25°C
A
T
T
= 85°C
= 25°C
A
A
A
T
= –40°C
A
T
= –40°C
A
V
= 5.5 V
DD
4
0
0
0
1
2
3
4
5
6
7
8
9
10 11 12
0
1
2
3
5
Analog Signal, V
(V)
Analog Signal, V
(V)
COM
COM
Figure 3. rON vs VCOM (V+ = 4.5 V)
Figure 4. rON vs VCOM (V+ = 11.4 V)
6
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TS12A44513, TS12A44514, TS12A44515
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PIN DESCRIPTION(1)
PIN NO.
TS12A44513
TS12A44514
TSSOP-14
2, 4, 9, 10
14
TS12A44515
NAME
DESCRIPTION
2, 4, 9, 10
2, 4, 9, 10
COM
V+
Common
14
5, 6, 12, 13
7
14
Power supply
5, 6, 12, 13
7
5, 6, 12, 13
IN
Digital control to connect COM to NO or NC
Digital ground
7
–
GND
NO
NC
1, 8
1, 3, 8, 11
–
Normally open
3, 11
1, 3, 8, 11
Normally closed
(1) NO, NC, and COM pins are identical and interchangeable. Any may be considered as an input or an output; signals pass in both
directions.
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APPLICATION INFORMATION
Power-Supply Considerations
The TS12A44513/TS12A44514/TS12A44515 construction is typical of most CMOS analog switches, except that
they have only two supply pins: V+ and GND. V+ and GND drive the internal CMOS switches and set their analog
voltage limits. Reverse ESD-protection diodes connected in series are internally connected between each
analog-signal pin and both V+ and GND. If an analog signal exceeds V+ or GND, one of the diodes will be
forward biased, but the other will be reverse biased preventing current flow.
Virtually all the analog leakage current comes from the ESD diodes to V+ or GND. Although the ESD diodes on a
given signal pin are identical and, therefore, fairly well balanced, they are reverse biased differently. Each is
biased by either V+ or GND and the analog signal. This means their leakages will vary as the signal varies. The
difference in the two diode leakages to the V+ and GND pins constitutes the analog-signal-path leakage current.
All analog leakage current flows between each pin and one of the supply terminals, not to the other switch
terminal. This is why both sides of a given switch can show leakage currents of the same or opposite polarity.
There is no connection between the analog-signal paths and V+ or GND.
V+ and GND also power the internal logic and logic-level translators. The logic-level translators convert the logic
levels to switched V+ and GND signals to drive the analog signal gates.
Logic-Level Thresholds
The logic-level thresholds are CMOS/TTL compatible when V+ is 5 V. As V+ is raised, the level threshold
increases slightly. When V+ reaches 12 V, the level threshold is about 3 V – above the TTL-specified high-level
minimum of 2.8 V, but still compatible with CMOS outputs.
CAUTION:
Do not connect the TS12A44513/TS12A44514/MAS4515 V+ to 3 V and then
connect the logic-level pins to logic-level signals that operate from 5-V supply.
Output levels can exceed 3 V and violate the absolute maximum ratings,
damaging the part and/or external circuits.
High-Frequency Performance
In 50-Ω systems, signal response is reasonably flat up to 250 MHz (see Typical Operating Characteristics).
Above 20 MHz, the on response has several minor peaks that are highly layout dependent. The problem is not in
turning the switch on; it is turning it off. The OFF-state switch acts like a capacitor and passes higher frequencies
with less attenuation. At 10 MHz, OFF isolation is about –45 dB in 50-Ω systems, decreasing (approximately 20
dB per decade) as frequency increases. Higher circuit impedances also make OFF isolation decrease. OFF
isolation is about 3 dB above that of a bare IC socket, and is due entirely to capacitive coupling.
Test Circuits/Timing Diagrams
V
+
V
V
+
+
NO
V
or V = 0 V
NC
NO
V
IN
TS12A44513
TS12A44514
TS12A44515
0 V
TS12A44515
TS12A44514
V
IN
IN
COM
V
OUT
V
OUT
GND
∆V
OUT
C
L
50 Ω
1000 pF
∆V is the measured voltage due to charge
OUT
transfer error Q when the channel turns off.
Q = V x C
OUT
L
Figure 5. Charge Injection
8
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TS12A44513, TS12A44514, TS12A44515
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V
+
V
+
50%
V
IN
V
+
0 V
NO
V
NO
TS12A44513
TS12A44514
V
PEAK
NO
V
90%
90%
IN
IN
COM
V
OUT
V
OUT
GND
35 pF
50 Ω
300 Ω
0 V
t
t
OFF
ON
V
+
V
+
50%
V
IN
V
+
0 V
V
NC
NO
TS12A44513
TS12A44515
V
PEAK
NO
V
IN
90%
90%
COM
IN
V
OUT
V
GND
OUT
35 pF
50 Ω
300 Ω
0 V
t
t
ON
OFF
Figure 6. Switching Times
V
10 nF
+
V
IN
50 Ω
50 Ω
V
+
NO
TS12A44513/14/15
V
V
OUT
+
MEAS
REF
COM
IN
GND
50 Ω 50 Ω
Measurements are standardized against short at socket
terminals. OFF isolation is measured between COM and OFF
terminals on each switch. ON loss is measured between COM
and ON terminals on each switch. Signal direction through
switch is reversed; worst values are recorded.
V
OUT
OFF Isolation = 20log
ON Loss = 20log
V
IN
V
OUT
V
IN
Figure 7. OFF Isolation and ON Loss
V
V
+
+
NO
or
NC
TS12A44513/14/15
IN
1-MHz
Capacitance
As
Required
COM
Analyzer
GND
Figure 8. NO, NC, and COM Capacitance
Copyright © 2008, Texas Instruments Incorporated
Submit Documentation Feedback
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Product Folder Link(s): TS12A44513 TS12A44514 TS12A44515
PACKAGE OPTION ADDENDUM
www.ti.com
23-Jun-2008
PACKAGING INFORMATION
Orderable Device
TS12A44513DR
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
SOIC
D
14
14
14
14
14
14
14
14
14
14
14
14
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TS12A44513DRG4
TS12A44513PWR
TS12A44513PWRG4
TS12A44514DR
SOIC
TSSOP
TSSOP
SOIC
D
PW
PW
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TS12A44514DRG4
TS12A44514PWR
TS12A44514PWRG4
TS12A44515DR
SOIC
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TSSOP
TSSOP
SOIC
PW
PW
D
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TS12A44515DRG4
TS12A44515PWR
TS12A44515PWRG4
SOIC
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TSSOP
TSSOP
PW
PW
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
23-Jun-2008
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
30-Jul-2010
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TS12A44513DR
TS12A44513PWR
TS12A44514DR
TS12A44514PWR
TS12A44515DR
TS12A44515PWR
SOIC
TSSOP
SOIC
D
PW
D
14
14
14
14
14
14
2500
2000
2500
2000
2500
2000
330.0
330.0
330.0
330.0
330.0
330.0
16.4
12.4
16.4
12.4
16.4
12.4
6.5
6.9
6.5
6.9
6.5
6.9
9.0
5.6
9.0
5.6
9.0
5.6
2.1
1.6
2.1
1.6
2.1
1.6
8.0
8.0
8.0
8.0
8.0
8.0
16.0
12.0
16.0
12.0
16.0
12.0
Q1
Q1
Q1
Q1
Q1
Q1
TSSOP
SOIC
PW
D
TSSOP
PW
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
30-Jul-2010
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TS12A44513DR
TS12A44513PWR
TS12A44514DR
TS12A44514PWR
TS12A44515DR
TS12A44515PWR
SOIC
TSSOP
SOIC
D
PW
D
14
14
14
14
14
14
2500
2000
2500
2000
2500
2000
346.0
346.0
346.0
346.0
346.0
346.0
346.0
346.0
346.0
346.0
346.0
346.0
33.0
29.0
33.0
29.0
33.0
29.0
TSSOP
SOIC
PW
D
TSSOP
PW
Pack Materials-Page 2
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
M
0,10
0,65
14
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
8
14
16
20
24
28
DIM
3,10
2,90
5,10
4,90
5,10
4,90
6,60
6,40
7,90
9,80
9,60
A MAX
A MIN
7,70
4040064/F 01/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
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