TS12A4516_14 [TI]
DUAL SUPPLY, LOW ON-STATE RESISTANCE SPST CMOS ANALOG SWITCHES;
| 型号： | TS12A4516_14 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | DUAL SUPPLY, LOW ON-STATE RESISTANCE SPST CMOS ANALOG SWITCHES |
| 文件： | 总14页 (文件大小：460K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TS12A4516, TS12A4517
www.ti.com ................................................................................................................................................. SCDS236B–DECEMBER 2006–REVISED APRIL 2009
DUAL SUPPLY, LOW ON-STATE RESISTANCE SPST CMOS ANALOG SWITCHES
1
FEATURES
•
±1-V to ±6-V Dual-Supply Operation
•
Specified Low ON-Leakage Currents:
•
Specified ON-State Resistance:
–
–
5 nA at 25°C
10 nA at 85°C
–
–
–
25 Ω Max With ±5-V Supply
35 Ω Max With ±3.3-V Supply
47 Ω Max With ±1.8-V Supply
•
•
Low Charge Injection: 13 pC (±5-V Supply)
Fast Switching Speed:
tON = 85 ns, tOFF = 50 ns (±5-V Supply)
•
Specified Low OFF-Leakage Currents:
•
•
Break-Before-Make Operation (tON > tOFF)
–
–
5 nA at 25°C
10 nA at 85°C
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
•
ESD Performance Tested Per JESD 22
–
–
–
2500-V Human-Body Model (A114-F)
1000-V Charged-Device Model (C101-C)
250-V Machine Model (A115-A)
DESCRIPTION/ORDERING INFORMATION
The TS12A4516/TS12A4517 are single pole/single throw (SPST), low-voltage, dual-supply CMOS analog
switches, with very low switch ON-state resistance. The TS12A4516 is normally open (NO). The TS12A4517 is
normally closed (NC).
These CMOS switches can operate continuously with a dual supplies between ±1 V and ±6 V [(2 V < (V+ – V–) <
12 V]. Each switch can handle rail-to-rail analog signals. The OFF-leakage current maximum is only 5 nA at 25°C
or 10 nA at 85°C.
For pin-compatible parts for use with single supply, see the TS12A4514/TS12A4515.
ORDERING INFORMATION
TA
PACKAGE(1)(2)
ORDERABLE PART NUMBER
TS12A4516D
TOP-SIDE MARKING
YD516
Reel of 1500
SOIC – D
Reel of 2500
Reel of 3000
Reel of 1500
Reel of 2500
Reel of 3000
TS12A4516DR
TS12A4516DBVR
TS12A4517D
SOP (SOT-23) – DBV
SOIC – D
9CL_
–40°C to 85°C
YD517
9CM_
TS12A4517DR
TS12A4517DBVR
SOP (SOT-23) – DBV
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
(2) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2006–2009, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
TS12A4516, TS12A4517
SCDS236B–DECEMBER 2006–REVISED APRIL 2009................................................................................................................................................. www.ti.com
PIN CONFIGURATIONS
TS12A4516
D PACKAGE
(TOP VIEW)
TS12A4517
D PACKAGE
(TOP VIEW)
TS12A4516
DBV PACKAGE
(TOP VIEW)
TS12A4517
DBV PACKAGE
(TOP VIEW)
1
2
3
5
COM
NC
V+
NO
V–
NC
V–
1
5
COM
N.C.
N.C.
V+
COM
N.C.
N.C.
V+
COM
NO
V–
V+
1
2
3
4
8
7
6
5
1
2
3
4
8
7
6
5
2
3
IN
IN
4
V–
IN
N.C.
N.C.
4
IN
SWITCH STATE
INPUT
TS12A4516
OFF
TS12A4517
ON
N.C. = Not internally connected
NC = Normally closed
NO = Normally open
LOW
HIGH
ON
OFF
Absolute Minimum and Maximum Ratings(1)(2)
voltages referenced to 0 V
MIN
MAX
UNIT
V+
Supply voltage range
–0.3
13
V
VNC
VNO
Analog voltage range(3)
V– –0.3
V– –0.3
V+ + 0.3
V
VCOM
VIN
Logic input range
V+ + 0.3
±20
V
mA
mA
V
Continuous current into any terminal
Peak current, NO or COM (pulsed at 1 ms, 10% duty cycle)
ESD per method 3015.7
±30
>2000
471
8-pin SOIC (derate 5.88 mW/°C above 70°C)
5-pin SOT23-5 (derate 7.1 mW/°C above 70°C)
Continuous power dissipation (TA = 70°C)
mW
571
TA
Operating temperature range
Storage temperature range
–40
–65
85
°C
°C
°C
Tstg
150
Lead temperature (soldering, 10 s)
300
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The algebraic convention, whereby the most negative value is a minimum and the most positive value is a maximum
(3) Voltages exceeding V+ or GND on any signal terminal are clamped by internal diodes. Limit forward-diode current to maximum current
rating.
2
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Copyright © 2006–2009, Texas Instruments Incorporated
Product Folder Link(s): TS12A4516 TS12A4517
TS12A4516, TS12A4517
www.ti.com ................................................................................................................................................. SCDS236B–DECEMBER 2006–REVISED APRIL 2009
Electrical Characteristics for ±5-V Supply(1)
V+ = 4.5 V to 5.5 V, V– = –4.5 V to –5.5 V, TA = –40°C to 85°C (unless otherwise noted)
PARAMETER
Analog Switch
SYMBOL
TEST CONDITIONS
TA
MIN TYP(2)
MAX
UNIT
Analog signal range
VCOM, VNO, VNC
ron
V–
V+
20
V
V+ = 4.5 V, V– = –4.5 V,
VCOM = 3.5 V,
ICOM = 20 mA
25°C
Full
12
ON-state resistance
Ω
25
2.5
3
V+ = 4.5 V, V– = –4.5 V,
VCOM = –3.5 V, 0 V, 3.5 V,
ICOM = 20 mA
25°C
Full
1.2
ON-state resistance
flatness
ron(flat)
Ω
V+ = 5.5 V, V– = –5.5 V,
VCOM = 4.5 V,
VNO or VNC = –4.5 V
25°C
Full
5
NO, NC
INO(OFF),
INC(OFF)
nA
nA
nA
OFF leakage current(3)
10
5
V+ = 5.5 V, V– = –5.5 V,
VCOM = –4.5 V,
VNO or VNC = 4.5 V
25°C
Full
COM
ICOM(OFF)
OFF leakage current(3)
10
5
V+ = 5.5 V, V– = –5.5 V,
VCOM = 5.5 V,
VNO or VNC = open
25°C
Full
COM
ICOM(ON)
ON leakage current(3)
10
Digital Control Input (IN)
Input logic high
VIH
VIL
Full
Full
Full
V+ – 1.5
V
V
Input logic low
V–
V+ – 3.5
0.010
Input leakage current
Dynamic
IIH, IIL
VIN = V+, 0 V
µA
25°C
Full
58
28
75
85
45
50
Turn-on time
tON
See Figure 2
See Figure 2
ns
ns
25°C
Full
Turn-off time
tOFF
QC
CNO(OFF)
CL = 1 nF, VNO = 0 V,
RS = 0 Ω, See Figure 1
Charge injection(4)
25°C
25°C
25°C
–13
5.5
5.5
pC
pF
pF
NO, NC
OFF capacitance
,
f = 1 MHz, See Figure 4
f = 1 MHz, See Figure 4
CNC(OFF)
COM
OFF capacitance
CCOM(OFF)
COM
ON capacitance
CCOM(ON)
CI
f = 1 MHz, See Figure 4
VIN = V+, 0 V
25°C
25°C
25°C
16
1.5
pF
pF
Digital input capacitance
RL = 50 Ω, CL = 15 pF,
VNO = 1 VRMS, f = 100 kHz
Bandwidth
BW
464
MHz
RL = 50 Ω, CL = 15 pF,
VNO = 1 VRMS, f = 1 MHz
OFF isolation
OISO
THD
25°C
25°C
–83
dB
%
RL = 600 Ω, CL = 15 pF,
VNO = 1 VRMS, f = 20 kHz
Total harmonic distortion
0.07
Supply
25°C
Full
70
80
V+ supply current
V– supply current
I+
VIN = 0 V or V+
VIN = 0 V or V+
µA
µA
25°C
Full
–70
–80
I–
(1) The algebraic convention, whereby the most negative value is a minimum and the most positive value is a maximum.
(2) Typical values are at TA = 25°C.
(3) Leakage parameters are 100% tested at maximum-rated hot operating temperature, and are ensured by correlation at 25°C.
(4) Specified by design, not production tested
Copyright © 2006–2009, Texas Instruments Incorporated
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TS12A4516, TS12A4517
SCDS236B–DECEMBER 2006–REVISED APRIL 2009................................................................................................................................................. www.ti.com
Electrical Characteristics for ±3.3-V Supply(1)
V+ = 3.0 V to 3.6 V, V– = –3.0 V to –3.6, TA = –40°C to 85°C (unless otherwise noted)
PARAMETER
Analog Switch
SYMBOL
TEST CONDITIONS
TA
MIN
TYP(2)
MAX
UNIT
Analog signal range
VCOM, VNO, VNC
ron
V–
V+
25
V
V+ = 3.0 V, V– = –3.0 V,
VCOM = 3 V,
ICOM = 20 mA
25°C
Full
17
ON-state resistance
Ω
35
25°C
Full
1.5
3
4
5
ON-state resistance
flatness
VCOM = –2 V, 0 V, 2 V,
ICOM = 20 mA
ron(flat)
Ω
V+ = 3.6 V, V– = –3.6 V,
VCOM = 3 V,
VNO or VNC = –3 V
25°C
NO, NC
INO(OFF),
INC(OFF)
nA
OFF leakage current(3)
Full
25°C
Full
10
5
V+ = 3.6 V, V– = –3.6 V,
VCOM = –3 V,
VNO or VNC = 3 V
COM
ICOM(OFF)
nA
nA
OFF leakage current(3)
10
5
V+ = 3.6 V, V– = –3.6 V,
VCOM = 3.6 V,
VNO or VNC = open
25°C
Full
COM
ICOM(ON)
ON leakage current(3)
10
Digital Control Input (IN)
Input logic high
VIH
VIL
Full
Full
Full
V+ – 1.5
V–
V
V
Input logic low
V+ – 3.5
0.01
Input leakage current
Dynamic
IIH, IIL
VIN = V+, 0 V
µA
25°C
Full
65
37
85
95
60
70
Turn-on time
tON
see Figure 2
see Figure 2
ns
ns
25°C
Full
Turn-off time
tOFF
QC
CL = 1 nF, VNO = 0 V,
RS = 0 Ω, See Figure 1
Charge injection(4)
25°C
25°C
25°C
–7.5
5.5
pC
pF
pF
NO, NC
OFF capacitance
CNO(OFF)
CNC(OFF)
f = 1 MHz, See Figure 4
f = 1 MHz, See Figure 4
COM
OFF capacitance
CCOM(OFF)
5.5
COM
ON capacitance
CCOM(ON)
CI
f = 1 MHz, See Figure 4
VIN = V+, 0 V
25°C
25°C
25°C
16
1.5
pF
pF
Digital input capacitance
RL = 50 Ω, CL = 15 pF,
VNO = 1 VRMS, f = 100 kHz
Bandwidth
BW
464
MHz
RL = 50 Ω, CL = 15 pF,
VNO = 1 VRMS, f = 100 kHz
OFF isolation
OISO
THD
25°C
25°C
–83
dB
%
RL = 600 Ω, CL = 15 pF,
VNO = 1 VRMS, f = 20 kHz
Total harmonic distortion
0.10
Supply
25°C
Full
40
45
V+ supply current
V– supply current
I+
VIN = 0 V or V+
VIN = 0 V or V+
µA
µA
25°C
Full
–40
45
I–
(1) The algebraic convention, whereby the most negative value is a minimum and the most positive value is a maximum.
(2) Typical values are at TA = 25°C.
(3) Leakage parameters are 100% tested at maximum-rated hot operating temperature, and are ensured by correlation at 25°C.
(4) Specified by design, not production tested
4
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Copyright © 2006–2009, Texas Instruments Incorporated
Product Folder Link(s): TS12A4516 TS12A4517
TS12A4516, TS12A4517
www.ti.com ................................................................................................................................................. SCDS236B–DECEMBER 2006–REVISED APRIL 2009
Electrical Characteristics for ±1.8-V Supply(1)
V+ = 1.65 V to 1.95 V, V– = –1.65 V to –1.95 V, TA = –40°C to 85°C (unless otherwise noted)
PARAMETER
Analog Switch
SYMBOL
TEST CONDITIONS
TA
MIN
TYP(2)
MAX
UNIT
Analog signal range
VCOM, VNO, VNC
ron
V–
V+
40
V
V+ = 1.65 V, V– = –1.65 V,
VCOM = 0 V,
ICOM = 20 mA
25°C
Full
28
9
ON-state resistance
Ω
47
13
15
5
V+ = 1.65 V, V– = –1.65 V,
VCOM = –1.8 V, 0 V, 1.5 V,
ICOM = 20 mA
25°C
Full
ON-state resistance
flatness
ron(flat)
Ω
V+ = 1.95 V, V– = –1.95 V,
VCOM = 1.65 V,
VNO or VNC = –1.65 V
25°C
Full
NO, NC
INO(OFF),
INC(OFF)
nA
nA
nA
OFF leakage current(3)
10
5
V+ = 1.95 V, V– = –1.95 V,
VCOM = –1.65 V,
VNO or VNC = 1.65 V
25°C
Full
COM
ICOM(OFF)
OFF leakage current(3)
10
5
V+ = 1.95 V, V– = –1.95 V,
VCOM = 1.95 V,
VNO or VNC = open
25°C
Full
COM
ICOM(ON)
ON leakage current(3)
10
Digital Control Input (IN)
Input logic high
VIH
VIL
Full
Full
Full
V+ – 1.5
V–
V
V
Input logic low
V+ – 3.5
0.01
Input leakage current
Dynamic
IIH, IIL
VIN = V+, 0 V
µA
25°C
Full
90
95
120
150
150
200
Turn-on time(4)
tON
See Figure 2
See Figure 2
ns
ns
25°C
Full
Turn-off time(4)
tOFF
Charge injection(4)
QC
CNO(OFF)
CNC(OFF)
CL = 1 nF, See Figure 1
f = 1 MHz, See Figure 4
25°C
–3.5
6
pC
pF
NO, NC
OFF capacitance
,
25°C
25°C
COM
OFF capacitance
CCOM(OFF)
f = 1 MHz, See Figure 4
6
pF
COM
ON capacitance
CCOM(ON)
CI
f = 1 MHz, See Figure 4
VIN = V+, 0 V
25°C
25°C
25°C
14.5
1.5
pF
pF
Digital input capacitance
RL = 50 Ω, CL = 15 pF,
VNO = 1 VRMS, f = 100 kHz
Bandwidth
BW
464
MHz
RL = 50 Ω, CL = 15 pF,
VNO = 1 VRMS, f = 1 MHz
OFF isolation
OISO
THD
25°C
25°C
–83
dB
%
RL = 600 Ω, CL = 50 pF,
VNO = 1 VRMS, f = 20 kHz
Total harmonic distortion
0.37
Supply
25°C
Full
20
30
V+ supply current
V– supply current
I+
VIN = 0 V or V+
VIN = 0 V or V+
µA
µA
25°C
Full
–20
–30
I–
(1) The algebraic convention, whereby the most negative value is a minimum and the most positive value is a maximum.
(2) Typical values are at TA = 25°C.
(3) Leakage parameters are 100% tested at maximum-rated hot operating temperature, and are ensured by correlation at 25°C.
(4) Specified by design, not production tested
Copyright © 2006–2009, Texas Instruments Incorporated
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Product Folder Link(s): TS12A4516 TS12A4517
TS12A4516, TS12A4517
SCDS236B–DECEMBER 2006–REVISED APRIL 2009................................................................................................................................................. www.ti.com
PIN DESCRIPTION(1)
PIN NO.
TS12A4516
TS12A4517
SOT23-5
NAME
DESCRIPTION
D, P
SOT23-5
D, P
1
1
–
5
4
3
2
–
1
1
–
COM
N.C.
V+
Common
2, 3, 5
2, 3, 5
No connect (not internally connected)
Positive power supply
4
6
7
8
–
4
6
7
–
8
5
4
3
–
2
IN
Digital control to connect COM to NO or NC
Negative power supply
V–
NO
NC
Normally open
Normally closed
(1) NO, NC, and COM pins are identical and interchangeable. Any may be considered as an input or an output; signals pass in both
directions.
6
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Product Folder Link(s): TS12A4516 TS12A4517
TS12A4516, TS12A4517
www.ti.com ................................................................................................................................................. SCDS236B–DECEMBER 2006–REVISED APRIL 2009
APPLICATION INFORMATION
Power-Supply Considerations
The TS12A4516 and TS12A4517 operate with power-supply voltages from ±1 V to ±6 V [(2 V < (V+ – V–) < 12 V],
but are tested and specified at ±5V, ±3.3V, and ±1.8V supplies. The pin-compatible TS12A4514 and TS12A4515
are recommended for use when only a single supply is desirable.
The TS12A4516 and TS12A4517 construction is typical of most CMOS analog switches, except that they have
only two supply pins: V+ and V–. V+ and V– drive the internal CMOS switches and set their analog voltage limits.
Reverse ESD-protection diodes are internally connected between each analog-signal pin and both V+ and V–.
One of these diodes conducts if any analog signal exceeds V+ or V–.
Virtually all the analog leakage current comes from the ESD diodes to V+ or V–. Although the ESD diodes on a
given signal pin are identical and, therefore, fairly well balanced, they are reverse biased differently. Each is
biased by either V+ or V– and the analog signal. This means their leakages will vary as the signal varies. The
difference in the two diode leakages to the V+ and V– pins constitutes the analog-signal-path leakage current. All
analog leakage current flows between each pin and one of the supply terminals, not to the other switch terminal.
This is why both sides of a given switch can show leakage currents of the same or opposite polarity.
V+ and V– also power the internal logic and logic-level translators. The logic-level translators convert the logic
levels to switched V+ and V– signals to drive the analog signal gates.
Logic-Level Thresholds
Since these parts have no ground pin, the logic-level threshold is referenced to V+. The threshold limits are V+
–1.5 V and V+ –3.5 V for V+ levels between 6 V and 3 V. When V+ = 2 V, the logic threshold is approximately 0.6
V.
CAUTION:
Do not connect the TS12A4516/TS12A4517 V+ to 3 V and then connect the
logic-level pins to logic-level signals that operate from 5-V supply. TTL levels
can exceed 3 V and violate the absolute maximum ratings, damaging the part
and/or external circuits.
Test Circuits/Timing Diagrams
NO
or NC
Figure 1. Charge Injection
Copyright © 2006–2009, Texas Instruments Incorporated
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Product Folder Link(s): TS12A4516 TS12A4517
TS12A4516, TS12A4517
SCDS236B–DECEMBER 2006–REVISED APRIL 2009................................................................................................................................................. www.ti.com
V
+
V
+
50%
V
IN
V
+
0 V
NO
V
NO
TS12A4516
COM
V
PEAK
NO
V
90%
90%
IN
IN
V
OUT
V
OUT
V
–
35 pF
50 Ω
300 Ω
0 V
t
t
OFF
ON
V
+
V
+
50%
90%
V
IN
V
+
0 V
V
NC
NO
TS12A4517
COM
V
PEAK
NO
V
IN
90%
IN
V
OUT
V
V
–
OUT
35 pF
50 Ω
300 Ω
0 V
t
t
ON
OFF
Figure 2. Switching Times
V
10 nF
+
V
IN
50 Ω
50 Ω
V
+
NO
or NC
TS12A4516
TS12A4517
V
V
OUT
+
MEAS
REF
IN
COM
V
–
50 Ω 50 Ω
V
V
OUT
OFF Isolation = 20log
ON Loss = 20log
Measurements are standardized against short at socket
terminals. OFF isolation is measured between COM and OFF
terminals on each switch. ON loss is measured between COM
and ON terminals on each switch. Signal direction through
switch is reversed; worst values are recorded.
IN
V
OUT
V
IN
Figure 3. OFF Isolation and ON Loss
V
V
+
+
NO
or
NC
TS12A4516
TS12A4517
1-MHz
As
Required
IN
COM
Capacitance
Analyzer
V
–
Figure 4. NO, NC, and COM Capacitance
8
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Copyright © 2006–2009, Texas Instruments Incorporated
Product Folder Link(s): TS12A4516 TS12A4517
PACKAGE OPTION ADDENDUM
www.ti.com
21-Apr-2009
PACKAGING INFORMATION
Orderable Device
TS12A4516D
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
SOIC
D
8
5
8
8
8
8
5
8
8
8
75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TS12A4516DBVR
TS12A4516DG4
TS12A4516DR
TS12A4516DRG4
TS12A4517D
SOT-23
SOIC
SOIC
SOIC
SOIC
SOT-23
SOIC
SOIC
SOIC
DBV
D
3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
D
75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TS12A4517DBVR
TS12A4517DG4
TS12A4517DR
TS12A4517DRG4
DBV
D
3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
15-Apr-2009
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0 (mm)
B0 (mm)
K0 (mm)
P1
W
Pin1
Diameter Width
(mm) W1 (mm)
(mm) (mm) Quadrant
TS12A4516DBVR
TS12A4516DR
TS12A4517DR
SOT-23
SOIC
DBV
D
5
8
8
3000
2500
2500
180.0
330.0
330.0
9.2
3.23
6.4
3.17
5.2
1.37
2.1
4.0
8.0
8.0
8.0
Q3
Q1
Q1
12.4
12.4
12.0
12.0
SOIC
D
6.4
5.2
2.1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
15-Apr-2009
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TS12A4516DBVR
TS12A4516DR
TS12A4517DR
SOT-23
SOIC
DBV
D
5
8
8
3000
2500
2500
202.0
346.0
346.0
201.0
346.0
346.0
28.0
29.0
29.0
SOIC
D
Pack Materials-Page 2
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