TS3DDR4000 [TI]
3.3V、2:1 (SPDT)、12 通道 DDR2、DDR3 和 DDR4 开关;
| 型号： | TS3DDR4000 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 3.3V、2:1 (SPDT)、12 通道 DDR2、DDR3 和 DDR4 开关 开关 双倍数据速率 光电二极管 |
| 文件： | 总24页 (文件大小：1050K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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TS3DDR4000
ZHCSDL6C –NOVEMBER 2014–REVISED MARCH 2019
TS3DDR4000 12 位 1:2 高速 DDR2/DDR3/DDR4 开关/多路复用器
1 特性
3 说明
1
•
宽 VDD 范围：2.375V 至 3.6V
TS3DDR4000 是一款 1:2 或 2:1 高速
DDR2/DDR3/DDR4 开关，可实现 12 位宽总线切换。
该器件可针对所有位同时将 A 端口切换为 B 或 C 端
口。TS3DDR4000 设计用于 DDR2、DDR3 和 DDR4
存储器总线系统，并且采用一种专有架构，可提供高带
宽（单端 5.6GHz 下的带宽为 -3dB）、低频下的低插
入损耗以及超低传播延迟等诸多优势。TS3DDR4000
兼容 1.8V 逻辑，并且所有开关均为双向开关，提高了
设计灵活性。此外，TS3DDR4000 还具有低功耗模
式。在此模式下，所有通道均呈高阻态且器件功耗最
低。
•
高带宽：5.6GHz（单端典型值）；6.0GHz（差分
典型值）
•
•
低开关导通电阻 (RON)：8Ω（典型值）
低位间偏差：3ps（典型值）；所有通道的最大值
为 6ps
•
•
•
•
•
低串扰：1067MHz 下的典型值为 –34dB
低工作电流：40μA（典型值）
具有低功耗模式，电流消耗极低：2µA（典型值）
IOFF保护防止断电状态 (VCC = 0V) 下的电流泄漏
支持 POD_12、SSTL_12、SSTL_15 和 SSTL_18
信令
器件信息(1)
•
静电放电 (ESD) 性能:
器件型号
封装
封装尺寸（标称值）
–
–
3kV 人体放电模式（A114B，II 类）
1kV 组件充电模式 (C101)
TS3DDR4000
NFBGA (48)
8.00mm x 3.00mm
(1) 如需了解所有可用封装，请见产品说明书末尾的可订购产品附
录。
•
8mm x 3mm 48 焊球 0.65mm 间距 ZBA 封装
2 应用
•
•
•
•
•
NVDIMM 模块
企业级数据系统和服务器
笔记本／台式机
通用 DDR3/DDR4 信号切换
通用高速信号切换
应用图
NVDIMM Module
Memory
Controller
Register
& PLL
DRAM
Battery/
Supercapacitor
NVDIMM
controller
NAND
Flash
1
本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。 有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确
性和有效性。 在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SCDS356
TS3DDR4000
ZHCSDL6C –NOVEMBER 2014–REVISED MARCH 2019
www.ti.com.cn
目录
8.3 Feature Description................................................. 12
8.4 Device Functional Modes........................................ 12
Application and Implementation ........................ 13
9.1 Application Information............................................ 13
9.2 Typical Application ................................................. 13
1
2
3
4
5
6
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings.............................................................. 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information.................................................. 4
6.5 Static Electrical Characteristics................................. 5
6.6 Dynamic Electrical Characteristics............................ 6
6.7 Typical Characteristics.............................................. 7
Parameter Measurement Information .................. 9
Detailed Description ............................................ 11
8.1 Overview ................................................................. 11
8.2 Functional Block Diagram ....................................... 11
9
10 Power Supply Recommendations ..................... 14
11 Layout................................................................... 15
11.1 Layout Guidelines ................................................. 15
11.2 Layout Example .................................................... 16
12 器件和文档支持 ..................................................... 17
12.1 接收文档更新通知 ................................................. 17
12.2 社区资源................................................................ 17
12.3 商标....................................................................... 17
12.4 静电放电警告......................................................... 17
12.5 术语表 ................................................................... 17
13 机械、封装和可订购信息....................................... 17
7
8
4 修订历史记录
Changes from Revision B (May 2017) to Revision C
Page
•
•
Changed the Pin Configuration image.................................................................................................................................... 3
Changed VIH From: SEL1m and SEL2 To: SEL0 and SEL1 with a MIN value of 1 V in the Recommended Operating
Conditions............................................................................................................................................................................... 4
•
•
Changed SEL1 To: SEL0 and SLE2 To: SEL1 in 图 18 ...................................................................................................... 11
Changed text 'Standard layout technique for 0.5 mm pitch BGA package" To: "Standard layout technique for 0.65
mm pitch BGA package..." in the Layout Guidelines............................................................................................................ 15
Changes from Revision A (March 2015) to Revision B
Page
•
•
Changed VDD Max value From: 5.5 V toTo: 4.8 V in the Absolute Maximum Ratings........................................................... 4
Added the Note to the Application and Implementation section........................................................................................... 13
Changes from Original (November 2014) to Revision A
Page
•
已将文档更新为完整版。 ........................................................................................................................................................ 1
2
Copyright © 2014–2019, Texas Instruments Incorporated
TS3DDR4000
www.ti.com.cn
ZHCSDL6C –NOVEMBER 2014–REVISED MARCH 2019
5 Pin Configuration and Functions
ZBA Package
48-Balls (NFBGA)
Top View
1
2
3
4
A0
SEL0
B0
C0
A
B
C
D
E
F
A1
A2
GND
VDD
GND
GND
GND
VDD
EN
B1
B2
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
A3
B3
A4
B4
A5
B5
A6
B6
G
H
J
A7
B7
A8
GND
VDD
GND
SEL1
B8
A9
B9
K
L
A10
A11
B10
B11
M
Not to scale
Pin Functions
PINS
TYPE
DESCRIPTION
NAME
VDD
NO.
C2, G2, K2
Power
Power supply
Ground
GND
B2, D2, E2, F2, J2, L2
Ground
A0-A11
B0-B11
C0-C11
SEL0
SEL1
EN
A1-M1
A3-M3
A4-M4
A2
I/O
Port A, signal 0-11
Port B, signal 0-11
Port C, signal 0-11
Select control 0
Select control 1
Enable
I/O
I/O
I
I
I
M2
H2
Copyright © 2014–2019, Texas Instruments Incorporated
3
TS3DDR4000
ZHCSDL6C –NOVEMBER 2014–REVISED MARCH 2019
www.ti.com.cn
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
(1)
MIN
-0.3
-0.3
-0.3
-40
MAX
4.8
UNIT
V
VDD
VIN
VI/O
TA
Voltage range on VDD
Control input voltage range: SEL0, SEL1, and /EN
Analog voltage range: A0-A11, B0-B11, and C0-C11
Operating ambient temperature range
Storage temperature range
5.5
V
3.6
V
85
°C
°C
Tstg
-65
125
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE UNIT
Charge device model (CDM)(1)
Human body model (HBM) on all pins(2)
±1000
±3000
V
V
Electrostatic
discharge
V(ESD)
(1) Tested in accordance with JEDEC Standard 22, Test Method C101
(2) Tested in accordance with JEDEC Standard 22, Test Method A114
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
2.375
0
MAX
UNIT
V
VDD Voltage range on VDD
3.6
3.3
VDD
VDD
0.5
85
VI/O
Analog voltage range: A0-A11, B0-B11, and C0-C11
High-level control input voltage threshold (EN)
V
1.4
1
V
VIH
High-level control input voltage threshold (SEL0 and SEL1)
Low-level control input voltage threshold (EN, SEL0 and SEL1)
Operating ambient temperature range
V
VIL
TA
0
V
-40
°C
6.4 Thermal Information
TS3DDR4000
BGA (48)
92.6
THERMAL METRIC(1)
UNIT
RθJA
RθJC(top)
RθJB
ψJT
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
33.4
56.2
°C/W
Junction-to-top characterization parameter
Junction-to-board characterization parameter
1.3
ψJB
54.9
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report .
4
Copyright © 2014–2019, Texas Instruments Incorporated
TS3DDR4000
www.ti.com.cn
ZHCSDL6C –NOVEMBER 2014–REVISED MARCH 2019
6.5 Static Electrical Characteristics
Unless otherwise noted the specification applies over the VDD range and operation junction temp of –40°C ≤ TJ ≤ 85°C.
Typical values are for VDD = 3.3 V and TJ = 25°C.
PARAMETER
TEST CONDITION
VDD = 2.375 V, VI/O = 1.2 V,
MIN
–
TYP
8.3
8.3
0.6
0.6
0.2
0.2
–
MAX
11.2
11.2
–
UNIT
Ω
Port A to B
Port A to C
Port A to B
Port A to C
Port A to B
Port A to C
RON
On-state resistance
II/O = 10 mA
–
Ω
–
Ω
RON
On-state resistance flatness for all
I/Os
VDD = 2.375 V, VI/O = 1.2 V, II/O = 10 mA
(FLAT)
–
–
Ω
–
1.0
1.0
±1
Ω
On-state resistance match between
channels
∆RON
VDD = 2.375 V, VI/O = 1.2 V, II/O = 10 mA
–
Ω
VDD = 3.6 V, V/EN = 1.4 V
–
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
EN
VDD = 2.375 V, V/EN = 3.3 V
–
–
±1
VDD = 3.6 V, VSEL1 = 1.4 V
–
–
±1
IIH
Control input high leakage current
Control input low leakage current
SEL1
SEL2
VDD = 2.375 V, VSEL1 = 3.3 V
–
–
±1
VDD = 3.6 V, VSEL2 = 1.4 V
–
–
±1
VDD = 2.375 V, VSEL2 = 3.3 V
–
–
±1
EN
VDD = 3.6 V, V/EN = 0 V
–
–
±0.5
±0.5
±0.5
±5
IIL
SEL1
SEL2
VDD = 3.6 V, VSEL1 = 0 V
–
–
VDD = 3.6 V, VSEL2 = 0 V
–
–
VDD = 0 V, V/EN = 0 V, VI/O = 0 V to 3.3 V
VDD = 0 V, V//EN = 3.6 V, VI/O = 0 V to 3.3 V
VDD = 0 V, VSEL1 = 0 V, VI/O = 0 V to 3.3 V
VDD = 0 V, VSEL1 = 3.6 V, VI/O = 0 V to 3.3 V
VDD = 0 V, VSEL2 = 0 V, VI/O = 0 V to 3.3 V
VDD = 0 V, VSEL2 = 3.6 V, VI/O = 0 V to 3.3 V
–
–
EN
–
–
±5
–
–
±5
Leakage under power off condition for
all I/Os
IOFF
SEL1
SEL2
–
–
±5
–
–
±5
–
–
±5
VDD = 3.6 V, II/O = 0 A, /EN = 0 V, VSEL1 = VSEL2= 0
V
–
–
–
28
40
40
35
48
44
µA
µA
µA
VDD = 3.6 V, II/O = 0 A, /EN = 0 V, VSEL1 = VSEL2
=
1.8 V
IDD
VDD supply current
VDD = 3.6 V, II/O = 0 A, /EN = 0 V, VSEL1 = 0 V,
VSEL2= 1.8 V
VDD = 3.6 V,II/O = 0 A, /EN = 0 V, VSEL1 = 1.8 V,
VSEL2= 0 V
–
–
40
2
44
5
µA
µA
IDD, PD
VDD supply current in power-down mode
VDD = 3.6 V, II/O = 0 A, /EN = 1.8 V
Copyright © 2014–2019, Texas Instruments Incorporated
5
TS3DDR4000
ZHCSDL6C –NOVEMBER 2014–REVISED MARCH 2019
www.ti.com.cn
MAX UNIT
6.6 Dynamic Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITION
MIN
TYP
VDD = 2.375 V, RL = 50 Ω, VAn = 3.3 V, V/EN
= 1.8 V→ 0 V, VSEL1 = VSEL2 = 0 V
(See 图 12)
EN to B
EN to C
SEL to B
SEL to C
–
–
–
–
65
65
65
50
140
µs
µs
ns
ns
tON
Switch turn-on time
VDD = 2.375 V, RL = 50 Ω, VAn = 3.3 V, V/EN
= 1.8 V→ 0 V, VSEL1 = VSEL2 = 1.8 V
(See 图 12)
140
–
VDD = 2.375 V, V/EN = 0 V, RL = 50 Ω, VAn
3.3 V,
(See 图 13)
=
=
Switching time between channels for
all I/Os
tSWITCH
VDD = 2.375 V, V/EN = 0 V, RL = 50 Ω, VAn
3.3 V,
–
(See 图 13)
VDD = 2.375 V,
(See 图 14)
Port A to B
Port A to C
–
–
85
85
–
–
ps
ps
tPD
Propagation delay
VDD = 2.375 V,
(See 图 14)
B0 to B11
C0 to C11
EN
–
–
–
–
–
3
3
6
6
6
8
6
–
–
–
ps
ps
pF
pF
pF
VDD = 2.375 V, from any output to any other
output
(1)
tSKEW
CIN
Singe-ended skew between channels
Control input capacitance
f = 1 MHz, VIN= 0 V
f = 1 MHz, VIN= 0 V
f = 1 MHz, VIN= 0 V
SEL1
SEL2
f = 1067 MHz, VI/O = 0 V, VSEL1 = VSEL2
1.8V
=
COFF
Switch off capacitance
Switch on capacitance
Crosstalk between channels
Port A to B
Port A to C
Port A to B
Port A to C
B0 to B11
C0 to C11
Port A to B
Port A to C
–
–
–
–
–
–
–
–
0.5
0.5
1.0
1.0
-34
-31
-21
-21
–
–
–
–
–
–
–
–
pF
pF
pF
pF
dB
dB
dB
dB
f = 1067 MHz, VI/O = 0 V, VSEL1 = VSEL2 = 0
V
f = 1067 MHz, VI/O = 1.2 V, VSEL1 = VSEL2
0V
=
CON
f = 1067 MHz, VI/O= 1.2 V, VSEL1 = VSEL2
1.8V
=
f = 1067 MHz, VSEL1 = VSEL2 = 0 V, RL = 50
Ω
XTALK
f = 1067 MHz, VSEL1 = VSEL2 = 1.8 V, RL = 50
Ω
f = 1067 MHz, VSEL1 = VSEL2 = 1.8 V, RL = 50
Ω
OISO
Off-isolation
f = 1067 MHz, VSEL1 = VSEL2 = 0 V, RL = 50
Ω
IL
Insertion loss (channel on)
Port A to B
Port A to C
Port A to B
Port A to C
Port A to B
Port A to C
f = DC, RL = 50 Ω
f = DC, RL = 50 Ω
–
–
–
–
–
–
-0.75
-0.75
5.6
5.6
6
-1
-1
–
dB
dB
BWSE
-3 dB bandwidth (Single-ended)
-3 dB bandwidth (Differential)
RL = 50 Ω
GHz
GHz
–
–
BWDIFF
RL = 100 Ω
6
–
(1) Verified by design.
6
版权 © 2014–2019, Texas Instruments Incorporated
TS3DDR4000
www.ti.com.cn
ZHCSDL6C –NOVEMBER 2014–REVISED MARCH 2019
6.7 Typical Characteristics
0
-1
0
-1
-2
-2
-3
-3
-4
-4
-5
-5
-6
-6
-7
-7
-8
-8
-9
-9
-10
-10
1M
10M
100M
1G
10G
1M
10M
100M
1G
10G
Frequency (Hz)
Frequency (Hz)
D001
D002
图 1. Single-Ended S21 vs Frequency for Port B
图 2. Single-Ended S21 vs Frequency for Port C
0
-1
0
-1
-2
-2
-3
-3
-4
-4
-5
-5
-6
-6
-7
-7
-8
-8
-9
-9
-10
-10
1M
10M
100M
1G
10G
1M
10M
100M
1G
10G
Frequency (Hz)
Frequency (Hz)
D003
D004
图 3. Differential S21 vs Frequence for Port B
图 4. Differential S21 vs Frequence for Port C
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
1M
10M
100M
1G
10G
1M
10M
100M
1G
10G
Frequency (Hz)
Frequency (Hz)
D005
D006
图 5. Crosstalk vs Frequency for Port B
图 6. Crosstalk vs Frequency for Port C
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TS3DDR4000
ZHCSDL6C –NOVEMBER 2014–REVISED MARCH 2019
www.ti.com.cn
Typical Characteristics (接下页)
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
1M
10M
100M
1G
10G
1M
10M
100M
1G
10G
Frequency (Hz)
Frequency (Hz)
D007
D008
图 7. Off-Isolation vs Frequency for Port B
图 8. Off-Isolation vs Frequency for Port C
图 9. Eye Diagram (6 Gbps Data Rate): Through Path
图 10. Eye Diagram (6 Gbps Data Rate): Port A to Port B
Without Device
Through TS3DDR4000
图 11. Eye Diagram (6 Gbps Data Rate): Port A to Port C Through TS3DDR4000
8
版权 © 2014–2019, Texas Instruments Incorporated
TS3DDR4000
www.ti.com.cn
ZHCSDL6C –NOVEMBER 2014–REVISED MARCH 2019
7 Parameter Measurement Information
VDD
VDD
Port B
Port B
Port A
Port A
CL
RL
CL
RL
RL
Port C
Port C
CL
+
+
SEL1/
SEL2
/EN
CL
RL
Control
Input
Control
Input
VDD
0
VDD
0
RL= 50Ω
VPORTA= VDD
SEL1/
SEL2
RL= 50Ω
VPORTA= VDD
/EN
50%
50%
tON
tON
VOH
VOL
VOH
VOL
Switch
Output
Switch
Output
50%
50%
图 12. Switch Turn-on Time (tON) Measurement
图 13. Switch Switching Time (tSWITCH)
Measurement
VDD
3V
0
Network Analyzer
Input 50%
50%
R
S
RT
V
S
RT
tPLH
tPLH
V
OUT
VOH
VOL
NC
Output
50%
50%
RT
SEL
GND
RT
tPD= (tPLH+tPLH)/2
Control
Input
Channel ON
SEL = H or L
RS=RT=50Ω
VS= -10dBm (200mV at 50Ω Load)
VDC_BIAS = 0.6V
图 14. Propagation Delay (tPD) Measurement
图 15. Crosstalk Measurement
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9
TS3DDR4000
ZHCSDL6C –NOVEMBER 2014–REVISED MARCH 2019
www.ti.com.cn
Parameter Measurement Information (接下页)
VDD
VDD
Network Analyzer
Network Analyzer
VOUT+
RS
RS
R
T
V
OUT
VS
V
S
R
T
SEL
SEL
GND
GND
RT
R
T
Control
Input
Control
Input
Channel OFF
SEL = H or L
RS=RT=50Ω
Channel ON
SEL = H or L
RS=RT=50Ω
VS= -10dBm (200mV at 50Ω Load)
VS= -10dBm (200mV at 50Ω Load)
VDC_BIAS = 0.6V
VDC_BIAS = 0.6V
图 16. Off Isolation Measurement
图 17. Bandwidth Measurement
10
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TS3DDR4000
www.ti.com.cn
ZHCSDL6C –NOVEMBER 2014–REVISED MARCH 2019
8 Detailed Description
8.1 Overview
The TS3DDR4000 is 1:2 or 2:1 high speed DDR2/DDR3/DDR4 switch that offers 12-bit wide bus switching. The
A port can be routed to the B or C port for all bits simultaneously. Designed for operation in DDR2, DDR3 and
DDR4 memory bus systems that support POD_12, SSTL_12, SSTL_135, SSTL_15, or SSTL_18 signaling, the
TS3DDR4000 uses a proprietary architecture that delivers high bandwidth (differential -3dB bandwidth of up to 6
GHz), and very low propagation delay and skew across all channels. The TS3DDR4000 is 1.8 V logic
compatible, and all switches are bi-directional for added design flexibility. The TS3DDR4000 also offers a low-
power mode, in which all channels become high-Z and the device operates with minimal power.
8.2 Functional Block Diagram
The following diagram (图 18) represents the switch function block diagram of the TS3DDR4000. Port A (A0-A11)
can be routed to either port B (B0-B11) or port C (C0-C11) by configuring the SEL0 and SEL1 pins. The EN pin
can be toggled high to put the device into the low-power mode with minimal power consumption.
A0
B0
A1
A2
A3
A4
A5
A6
A7
B1
B2
B3
B4
B5
B6
B7
B8
B9
A8
A9
B10
B11
A10
A11
C0
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
SEL0
SEL1
EN
Control Logic
图 18. TS3DDR4000 Switch Function Block Diagram
版权 © 2014–2019, Texas Instruments Incorporated
11
TS3DDR4000
ZHCSDL6C –NOVEMBER 2014–REVISED MARCH 2019
www.ti.com.cn
8.3 Feature Description
•
IOFF Protection: When no power is provided to the device (VCC = 0 V), the TS3DDR4000 prevents any I/O
signals from back-powering the device. The leakage current is tightly controlled under such condition (refer to
the IOFF in the Specifications section) so it does not cause any system issues.
•
Low-power mode: The EN pin can be driven high to make the TS3DDR4000 enter the low-power mode.
When in low power mode, all channels are isolated and the device consumes less than 5 µA of current.
8.4 Device Functional Modes
When EN pin is driven high, the TS3DDR4000 enters into the power-down mode, in which all channels are
isolated and the device consumes less than 5 µA of current. When EN pin is driven low, the A port is routed to
either B port or C port depending on the configuration of SEL0 and SEL1 signals. The B and C port can also be
partially turned on when SEL0 and SEL1 are not both high or both low. Refer to 表 1 for the control logic details.
表 1. Logic Control Table
CONTROL PINS
FUNCTION
EN
SEL0
SEL1
H
X
X
Power –down mode. All channels off (isolated)
Port A to port B ON
L
L
L
Port A to port C OFF (isolated)
A [0,1,4,5,8,9] ↔ B [0,1,4,5,8,9]
A [2,3,6,7,10,11] ↔ C [2,3,6,7,10,11]
All other channels OFF (isolated)
A [2,3,6,7,10,11] ↔ B [2,3,6,7,10,11]
A [0,1,4,5,8,9] ↔ C [0,1,4,5,8,9]
All other channels OFF (isolated)
Port A to port B OFF (isolated)
Port A to port C ON
L
L
H
L
L
H
H
L
H
12
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TS3DDR4000
www.ti.com.cn
ZHCSDL6C –NOVEMBER 2014–REVISED MARCH 2019
9 Application and Implementation
注
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The TS3DDR4000 is a high-speed switch targeted for DDR memory applications that require 1:2 or 2:1
switching. The following sections describe two application scenarios that are widely used. In addition to memory
applications, the TS3DDR4000 can also be used for generic high-speed switching that requires high bandwidth
and minimal signal degradation.
9.2 Typical Application
9.2.1 Non-Volatile Dual In-line Memory Module (NVDIMM) application
NVDIMM Module
Power-good signal
Battery/
Supercapacitor
DDR bus
Termination
Resistor
Memory
Controller
Register
& PLL
DRAM
Control
DDR bus
during power
failure
NVDIMM Controller
NAND Flash
图 19. TS3DDR4000 Used In NVDIMM Application
9.2.1.1 Design Requirements
The TS3DDR4000 can be used in the NVDIMM application to provide server systems reliable data backups
when the system encounters power-failure conditions. 图 19 depicts a typical NVDIMM design utilizing the
TS3DDR4000.
In normal system operation, the TS3DDR4000 routes the DDR signals between the system and the DRAM for
normal data access. When the system encounters power failure, the charge stored in the battery or the super
capacitor is used to power the NVDIMM controller, which configures the TS3DDR4000 to save the data from
DRAM into the NAND Flash. The NAND Flash is non-volatile in nature, so the data stored internally stays intact
even when the power goes away eventually. When the system power comes back on, the NVDIMM controller
can re-route the data from the NAND Flash through the TS3DDR4000 back into the DRAM and can
subsequently re-start the normal system operation.
版权 © 2014–2019, Texas Instruments Incorporated
13
TS3DDR4000
ZHCSDL6C –NOVEMBER 2014–REVISED MARCH 2019
www.ti.com.cn
Typical Application (接下页)
9.2.1.2 Detailed Design Procedure
The battery or the super capacitor needs to be designed to have enough capacity to maintain the power long
enough for the backup procedure to be completed. At a backup speed of 128 MB/sec, it takes about 10 seconds
per 1 GB to either backup or restore the data. Typically a super capacitor is preferred for its longer life of
operation. The super capacitor is usually a separate module and is connected to the NVDIMM via a cable.
NVDIMMs require support from the system motherboard. When plugged in, the BIOS must recognize the
NVDIMMs. Manufacturers who control the BIOS and MRC (memory reference code) can make the necessary
code changes to implement NVDIMMs into their servers.
9.2.2 Load Isolation Application
SSD Controller
Control
SSTL
signaling
Processor
SSTL
Flash Memory
signaling
Flash
Controller
Bank #1
PCIe, Fiber
Channel, or iSCSI
SSTL
signaling
Flash Memory
Bank #2
Buffer
图 20. TS3DDR4000 Used In Load Isolation Application
9.2.2.1 Design Requirements
In recent years, the size of Solid-State-Drives (SSDs) has increased rapidly, making it necessary to increase the
number of flash memory devices in each drive. The flash memory devices sometimes share the same control
and data channel to communicate with the controller. This causes increased loading to each communication
channel as the number of flash memory devices increases. To meet the performance requirement of an SSD, the
ability to isolate the loading becomes necessary.
9.2.2.2 Detailed Design Procedure
As depicted in 图 20, the TS3DDR4000 can be used for load isolation purpose. Flash memory bank #1 and #2
can share the same communication channel to the flash controller without increasing the loading to each other.
While the TS3DDR4000 is enabled for one channel, the other channel is fully isolated. The off-isolation
specification is about –21 dB at 1067 MHz, as described in the Specifications section.
10 Power Supply Recommendations
VDD should be in the range of 2.375 V to 3.6 V. A 0.1 µF or higher decoupling capacitors placed as closed to the
BGA pad as possible is recommended. There are no power sequence requirements for the TS3DDR4000.
14
版权 © 2014–2019, Texas Instruments Incorporated
TS3DDR4000
www.ti.com.cn
ZHCSDL6C –NOVEMBER 2014–REVISED MARCH 2019
11 Layout
11.1 Layout Guidelines
Standard layout technique for 0.65 mm pitch BGA package shall be employed. The following commonly-used
printed-circuit-board (PCB) layout guidelines are recommended:
•
Use Non-Solder-Mask-Defined (NSMD), rather than Solder-Mask-Defined (SMD) pads for the BGA solder
balls to adhere if possible. For most applications, the NSMD pads provide more flexibility, fewer stress.
Solder mask
Solder mask
Copper pad
PCB
PCB
Solder Mask Defined
(SMD) Pads
Non-Solder Mask Defined
(NSMD) Pads
图 21. Solder-Mask-Defined (SMD) and Non-Solder-Mask-Defined (NSMD) Pads
•
•
One trace can generally be routed between two solder pads of a 0.65 mm pitch BGA. This allows the outer
two rows of solder pads to be routed on the same top/bottom layer. The TS3DDR4000 has 4 rows, and thus
no VIAs is generally required to route all the inner balls out.
Generally high-speed signal layout guidelines:
–
To minimize the effects of crosstalk on adjacent traces, keep the traces at least two times the trace width
apart.
–
–
–
Separate high-speed signals from low-speed signals and digital from analog signals.
Avoid right-angle bends in a trace and try to route them at least with two 45° corners.
The high-speed differential signal traces should be routed parallel to each other as much as possible. The
traces are recommended to be symmetrical.
–
A solid ground plane should be placed next to the high-speed signal layer. This also provides an excellent
low-inductance path for the return current flow.
版权 © 2014–2019, Texas Instruments Incorporated
15
TS3DDR4000
ZHCSDL6C –NOVEMBER 2014–REVISED MARCH 2019
www.ti.com.cn
11.2 Layout Example
To GND Plane
To VDD Plane
Decoupling
capacitor
Port C
SEL0
A0
B0
C0
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
GND
A1
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
VDD
A2
GND
A3
GND
A4
GND
A5
Port A
VDD
A6
EN
GND
VDD
GND
SEL1
A7
A8
A9
Top Layer
Bottom Layer
A10
A11
Decoupling
capacitor
Port B
To VDD Plane
To GND Plane
Controller
图 22. TS3DDR4000 Layout Example
16
版权 © 2014–2019, Texas Instruments Incorporated
TS3DDR4000
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ZHCSDL6C –NOVEMBER 2014–REVISED MARCH 2019
12 器件和文档支持
12.1 接收文档更新通知
要接收文档更新通知，请导航至 TI.com.cn 上的器件产品文件夹。单击右上角的通知我 进行注册，即可每周接收产
品信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
12.2 社区资源
下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，
并且不一定反映 TI 的观点；请参阅 TI 的 《使用条款》。
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.3 商标
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.4 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损
伤。
12.5 术语表
SLYZ022 — TI 术语表。
这份术语表列出并解释术语、缩写和定义。
13 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且
不会对此文档进行修订。如需获取此产品说明书书的浏览器版本，请查阅左侧的导航栏。
版权 © 2014–2019, Texas Instruments Incorporated
17
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TS3DDR4000ZBAR
ACTIVE
NFBGA
ZBA
48
3000 RoHS & Green
SNAGCU
Level-3-260C-168 HR
-40 to 85
DDR4000
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
8-Jun-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TS3DDR4000ZBAR
NFBGA
ZBA
48
3000
330.0
16.4
3.4
8.4
1.65
8.0
16.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
8-Jun-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
NFBGA ZBA 48
SPQ
Length (mm) Width (mm) Height (mm)
336.6 336.6 31.8
TS3DDR4000ZBAR
3000
Pack Materials-Page 2
PACKAGE OUTLINE
ZBA0048A
NFBGA - 1.2 mm max height
SCALE 2.200
BALL GRID ARRAY
1.95 TYP
0.65 TYP
3.1
2.9
B
A
0.65 TYP
4
2
1
3
A
B
C
D
E
F
BALL A1
CORNER
SYMM
8.1
7.9
7.15
TYP
G
H
J
K
L
M
SYMM
48X
(0.43) TYP
(0.53) TYP
0.4
0.3
1.2 MAX
0.15
0.08
C A
B
NOTE 4
C
C
NOTE 3
SEATING PLANE
0.24
TYP
0.19
0.1
BALL TYP
4221524/A 07/2014
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Dimension is measured at the maximum solder ball diameter, parallel to primary datum C.
4. Primary datum C and seating plane are defined by the spherical crowns of the solder balls.
www.ti.com
EXAMPLE BOARD LAYOUT
ZBA0048A
NFBGA - 1.2 mm max height
BALL GRID ARRAY
(0.65) TYP
48X ( 0.35)
(0.65) TYP
4
3
1
2
A
B
C
D
E
F
SYMM
G
H
J
K
L
M
SYMM
LAND PATTERN EXAMPLE
SCALE:10X
0.05 MAX
0.05 MIN
METAL
UNDER MASK
(
0.35)
METAL
(
0.35)
SOLDER MASK
OPENING
SOLDER MASK
OPENING
NON-SOLDER MASK
SOLDER MASK
DEFINED
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
NOT TO SCALE
4221524/A 07/2014
NOTES: (continued)
5. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.
For more information, see Texas Instruments Literature number SPRAA99 (www.ti.com/lit/spraa99).
www.ti.com
EXAMPLE STENCIL DESIGN
ZBA0048A
NFBGA - 1.2 mm max height
BALL GRID ARRAY
(0.65) TYP
48X ( 0.35)
3
1
2
4
A
(0.65)
TYP
B
C
D
E
F
SYMM
G
H
J
K
L
M
SYMM
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
4221524/A 07/2014
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.
www.ti.com
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