TS3DV642-Q1 [TI]
TS3DV642-Q1 8 Gbps 12-Channel differential 1-to-2 and 2-to-1 mux;
| 型号： | TS3DV642-Q1 |
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TEXAS INSTRUMENTS |
| 描述： | TS3DV642-Q1 8 Gbps 12-Channel differential 1-to-2 and 2-to-1 mux |
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TS3DV642-Q1
SCDS430 – DECEMBER 2020
TS3DV642-Q1 8 Gbps 12-Channel differential 1-to-2 and 2-to-1 mux
1 Features
3 Description
•
•
•
Automotive Q100 qualified
The TS3DV642-Q1 is an analog high-speed
bidirectional passive switch in mux or demux
configurations that works for many high-speed
differential interfaces with data rates up to 8.1 Gbps. It
is suited for many applications including HDMI 1.4 /
2.0, DisplayPort 1.4 and Mipi DPHY/CPHY DSI /
CSI-2. The TS3DV642-Q1 supports both differential
and single-ended signaling - virtually compatible to
most standard and non standard interfaces. The
dynamic characteristics of the TS3DV642-Q1 allows
high-speed switching with minimal attenuation to the
signal eye diagram, and with very little added jitter.
The device's silicon design is optimized for excellent
frequency response at higher frequency spectrum of
the signals. The device supports differential signaling
with common mode voltage range (CMV) of 0 to 3.6 V
and 0 - 5.5 V CMOS signals.
Temperature range of -40 to 105 °C (grade 2)
Support 6 differential or 12 single-ended signals or
other differential/single ended combinations
Supports HDMI 1.4b / 2.0, DisplayPort 1.4 HBR3,
Mipi DPHY / CPHY DSI / CSI-2
Bidirectional analog mux - handles most electrical
signals within 0 to 5 V and DC to 8.1 Gbps range
–3-dB differential BW of 6.5 GHz
Excellent dynamic characteristics
– Insertion loss: –1.5 dB at 3.0 GHz
– Return loss: –14 dB at 3.0 GHz
Support 1.8 V, 3.3 V or 5.0 V control logic
Single supply voltage of 3.3 V
Low active (45 μA) and standby power (6 μA)
IOFF protection that prevents current leakage when
supply rail collapsed (VCC = 0 V)
•
•
•
•
•
•
•
•
The TS3DV642-Q1 consumes very low active power
of 45 μA. The device also offers a power-down mode,
in which all channels become Hi-Z and the device
operates with minimal power.
•
•
ESD Performance of 2 kV HBM and 1 kV CDM
42-pin, 3.5 x 9 mm, 0.5 mm pitch WQFN package
with wettable flank
Device Information (1)
2 Applications
PART NUMBER
PACKAGE
BODY SIZE (NOM)
•
•
•
•
•
Advanced driver assistance systems (ADAS)
Automotive infotainment & cluster
Rear seat entertainment
Automotive head unit
Aerospace & defense
TS3DV642-Q1
WQFN (42)
3.50 mm x 9.00 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
Simplified Use Cases
T0A
T1A
T2A
AUXA/DDCA
D0A
D1A
D2A
D3A/CKA
D0A
D1A
D2A
D3A
CKA
AUX/DDC
T0
T1
T2
D0
D1
D2
D3
CK
D0
D1
D2
HPDA
CECA
D3/CK
HPD
CEC
AUXB/DDCB
D0B
D1B
D2B
D3B/CKB
T0B
T1B
T2B
D0B
D1B
D2B
D3B
CKB
HPDB
CECB
Mipi DPHY CSI-2/DSI
DisplayPort/HDMI
Mipi CPHY CSI-2
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. ADVANCE INFORMATION for preproduction products; subject to change
without notice.
TS3DV642-Q1
SCDS430 – DECEMBER 2020
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Table of Contents
1 Features............................................................................1
2 Applications.....................................................................1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
Pin Functions.................................................................... 3
6 Specifications.................................................................. 5
6.1 Absolute Maximum Ratings ....................................... 5
6.2 ESD Ratings .............................................................. 5
6.3 Recommended Operating Conditions ........................5
6.4 Thermal Information ...................................................5
6.5 Electrical Characteristics ............................................6
6.6 High-Speed Performances .........................................6
6.7 Switching Characteristics ...........................................7
6.8 Typical Characteristics................................................8
7 Parameter Measurement Information............................9
8 Detailed Description......................................................11
8.1 Overview................................................................... 11
8.2 Functional Block Diagram......................................... 11
8.3 Feature Description...................................................11
8.4 Device Functional Modes..........................................12
9 Application and Implementation..................................13
9.1 Application Information............................................. 13
9.2 Typical Application - Switching HDMI Source...........13
10 Power Supply Recommendations..............................17
11 Layout...........................................................................18
11.1 Layout Guidelines................................................... 18
11.2 Layout Example...................................................... 19
12 Device and Documentation Support..........................20
12.1 Receiving Notification of Documentation Updates..20
12.2 Support Resources................................................. 20
12.3 Trademarks.............................................................20
12.4 Electrostatic Discharge Caution..............................20
12.5 Glossary..................................................................20
13 Mechanical, Packaging, and Orderable
Information.................................................................... 20
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Date
Revision
Notes
December 2020
*
Initial Release
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5 Pin Configuration and Functions
VCC
EN
1
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
D0+A
D0œA
D1+A
D1-A
D2+A
D2œA
D3+A
D3œA
NC
2
SCL
SDA
D0+
D0œ
D1+
D1œ
NC
3
4
5
6
7
8
Thermal
Pad
9
D2+
D2œ
D3+
D3œ
HPD
CEC
SEL1
SEL2
10
11
12
13
14
15
16
17
D0+B
D0œB
D1+B
D1œB
D2+B
D2œB
D3+B
D3œB
Not to scale
Figure 5-1. 42 Pin WQFN RUA Package with exposed thermal pad - top view - not to scale
Pin Functions
PIN
TYPE
DESCRIPTION
NAME
VCC
NO.
1
Power
I
Supply Voltage
SEL1
SEL2
EN
16
17
2
Select Input 1
I
Select Input 2
I
Device Enable
D0+A
D0–A
D1+A
D1-A
38
37
36
35
34
33
32
31
42
41
19
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Port A, Channel 0, +ve signal
Port A, Channel 0, –ve signal
Port A, Channel 1, +ve signal
Port A, Channel 1, –ve signal
Port A, Channel 2, +ve signal
Port A, Channel 2,–ve signal
Port A, Channel 3, +ve signal
Port A, Channel 3, –ve signal
Port A, DDC Clock
D2+A
D2–A
D3+A
D3–A
SCL_A
SDA_A
HPD_A
Port A, DDC Data
Port A, Hot Plug Detects
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PIN
TYPE
DESCRIPTION
Port A, Consumer Electronics Control
NAME
CEC_A
D0+B
D0–B
D1+B
D1–B
D2+B
D2–B
D3+B
D3–B
SCL_B
SDA_B
HPD_B
CEC_B
D0+
NO.
18
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
NC
GND
29
Port B, Channel 0, +ve signal
Port B, Channel 0, –ve signal
Port B, Channel 1, +ve signal
Port B, Channel 1, –ve signal
Port B, Channel 2, +ve signal
Port B, Channel 2,–ve signal
Port B, Channel 3, +ve signal
Port B, Channel 3, –ve signal
Port B, DDC Clock
28
27
26
25
24
23
22
40
39
Port B, DDC Data
21
Port B, Hot Plug Detects
20
Port B, Consumer Electronics Control
Common Port, Channel 0, +ve signal
Common Port, Channel 0, –ve signal
Common Port, Channel 1, +ve signal
Common Port, Channel 1, –ve signal
Common Port, Channel 2, +ve signal
Common Port, Channel 2, –ve signal
Common Port, Channel 3, +ve signal
Common Port, Channel 3,–ve signal
Common Port, DDC Clock
5
D0–
6
D1+
7
D1–
8
D2+
10
D2–
11
D3+
12
D3–
13
SCL
3
SDA
4
14
Common Port, DDC Data
HPD
Common Port, Hot Plug Detects
Common Port, Consumer Electronics Control
No Connect
CEC
15
NC
9, 30
PowerPad
GND
Ground
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
UNIT
VCCABS
Supply voltage range
–0.5
5.5
V
MAX
VI/O-
Analog voltage range(2) (3) (4)
Digital input voltage range(2) (3)
All I/O (data pins)
SEL1, SEL2, EN
–0.5
–0.5
5.5
5.5
V
V
ABSMAX
VIN-
ABSMAX
Tjmax
Tstg
Maximum junction temperature
Storage temperature range
–40
–65
125
150
°C
°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Theseare stress ratings
only, which do not imply functional operation of the device at these or anyother conditions beyond those indicated under
Recommended OperatingConditions. Exposure to absolute-maximum-rated conditions for extended periods mayaffect device
reliability.
(2) All voltages are with respect to ground, unless otherwisespecified.
(3) The input and output voltage ratings may be exceeded if theinput and output clamp-current ratings are observed.
(4) VI and VO areused to denote specific conditions for VI/O
.
6.2 ESD Ratings
VALUE
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, (1)
±2000
V(ESD)
Electrostatic discharge
V
Charged device model (CDM), per JEDEC specification JESD22-C101,
±1000
(2)
(1) JEDEC document JEP155 states that 500-V HBM allows safemanufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safemanufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
3.6
UNIT
V
VCC
Supply voltage
3.0
0
VI/O,CM Input/Output common mode voltage (data pins)
3.6
V
VI/O
VIN
DR
TA
Input/Output voltage (data pins)
Digital input voltage (control pins)
Data rate for differential signals
Operating ambient temperature
Operating junction temperature
0
5.5
V
0
5.5
V
8.1
Gbps
°C
°C
–40
–40
105
110
TJ
(1) All unused control inputs of the device must be held at VDD orGND to ensure proper device operation. Refer to the TI application
report,Implications of Slow or Floating CMOS Inputs, literature numberSCBA004.
6.4 Thermal Information
TS3DV642-Q1
THERMAL METRIC(1)
RUA
42 PINS
28.7
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
Junction-to-top characterization parameter
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
16.7
9.7
ψJT
0.3
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UNIT
TS3DV642-Q1
RUA
THERMAL METRIC(1)
42 PINS
9.7
ψJB
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
°C/W
°C/W
RθJC(bot)
2.9
(1) For more information about traditional and new thermalmetrics, see the Semiconductor and ICPackage Thermal Metrics application
report.
6.5 Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS(1)
MIN TYP(2)
MAX UNIT
DC Characteristics
RON
ON-state resistance
All data pins
All data pins
VI/O = 0 V, II/O = –10 mA
7
12
Ω
Ω
RON,FLAT
ON-state resistance
flatness
RON at VI/O = 1.5 V minus RON at VI/O
= 0 V, II/O = –10 mA
0.6
(3)
Leakage under power off
(failsafe current)
All data and control
pins
IOFF
VCC = 0 V, VI/O or VIN = 0 V to 5.5 V
±10
µA
Control Inputs (SEL1, SEL2, EN)
High-level input voltage for
control pins
VIH
SEL1, SEL2, EN
SEL1, SEL2, EN
SEL1, SEL2, EN
SEL1, SEL2, EN
1.4
V
V
Low-level input voltage for
control pins
VIL
0.5
±10
±10
Input high leakage current
for control pins
IIH
VCC = 3.6 V, VIN = 5.5 V
VCC = 3.6 V, VIN = GND
µA
µA
Input low leakage current
for control pins
IIL
Power Supply
ICC
VCC supply current in active mode
VCC supply current in power-down mode
EN = H
EN = L
45
6
µA
µA
ICC_PD
(1) VI, VO,II, and IO refer to data I/O pins,VIN refers to the control inputs.
(2) All typical values are at VDD = 3.3 V (unless otherwise noted), TA = 25°C.
(3) RON,FLAT is the difference of RON in a given channel at specified voltages.
6.6 High-Speed Performances
Over recommended operation free-air temperature range, VDD =3.3V ± 0.3V (unless otherwise noted). For all data pins. RL =
50 Ω where applicable.
PARAMETER
TEST CONDITIONS
MIN TYP(1)
MAX
UNIT
Differential Bandwidth (–3 dB from
DC)
BW
IL
6.5
GHz
DC
–0.6
–0.9
–1.3
-1.5
–1.9
–24
–22
–16
–14
–11
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
1.7 GHz
2.7 GHz
3.0 GHz
4.05 GHz
DC
Differential insertion loss
1.7 Ghz
2.7Ghz
3.0 Ghz
4.05 Ghz
Differential return loss for Port A and
B (DA, DB)
RLDAB
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Over recommended operation free-air temperature range, VDD =3.3V ± 0.3V (unless otherwise noted). For all data pins. RL =
50 Ω where applicable.
PARAMETER
TEST CONDITIONS
MIN TYP(1)
MAX
UNIT
DC
-80
dB
1.7 GHz
2.7 GHz
3.0 GHz
4.05 GHz
DC
–40
Xtalk
Differential crosstalk
–30
dB
dB
–27
-
–22
–80
1.7 GHz
2.7 GHz
3.0 GHz
4.05 GHz
–21
OISO Differential off isolation
–16
–16
–15
(1) All Typical Values are at VDD = 3.3 V(unless otherwise noted), TA = 25°C.
6.7 Switching Characteristics
over recommended operation free-air temperature range, VDD =3.3 V± 0.3 V (unless otherwise noted). For all data pins.
PARAMETER
TEST CONDITIONS
MIN TYP(1)
MAX UNIT
tpd
Propagation Delay
All I/O
All I/O
All I/O
66
ps
(2)
tON
Switch turn-on time
100
µs
µs
(3)
tSWITCH
Switching time between channels
20
(1) All typical values are at VDD = 3.3 V(unless otherwise noted), TA = 25°C.
(2) tON is the time it takes the output to recover within 95% of final value after enabling switches
(3) tSWITCH is the time it takes for theoutput to recover within 95% of final value after the state is changed
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6.8 Typical Characteristics
Figure 6-1 shows typical s-parameter plots for TS3DV642-Q1 - top differential forward gain (S21/S12) and
bottom differential return loss (S11/S22) in TI evaluation board with measurement parasitics calibrated out.
Figure 6-1. Differential gain (S21/S12) and return loss (S11/S22) vs frequency of TS3DV642-Q1
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7 Parameter Measurement Information
VCC
RL
CL
4 pF
VCOM
VCC
50 Ω
*CL includes probe, cable, and board
capacitance
Port A
VCOM
2.6 V
CL
RL
EN
50%
Port B
CL
+
0
EN
RL
tON
VOH
Switch
Output
50%
Control
Input
VOL
Figure 7-1. Switch Turn-On Time (tON
)
VCC
RL
CL
4 pF
VCOM
VCC
50 Ω
*CL includes probe, cable, and board
capacitance
Port A
VCOM
CL
RL
Port B
CL
2.6 V
+
50%
SEL1/SEL2
tON
0
SEL1/SEL2
RL
VOH
Switch
Output
Control
Input
50%
VOL
Figure 7-2. Switching Time Between Channels (tSWITCH
)
3 V
Input
50%
50%
0
tpd = (tPLH + tPLH) / 2
tPLH
tPLH
VOH
VOL
Output
50%
50%
Figure 7-3. Propagation Delay (tpd)
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VDD
Network Analyzer
TS3DV642
RS
RT
VS
Channel ON
RT
VOUT
NC
SEL = H or L
RS = RT = 50Ω
VS
RT
VS = -10dBm (200mV at 50Ω Load)
VDC_BIAS = 1 V
SEL
GND
RT
Control
Input
Figure 7-4. Crosstalk (Xtalk)
VCC
TS3DV642
Network Analyzer
RS
VOUT+
RT
VS
Channel OFF
RS
SEL = H or L
RS = RT = 50Ω
RT
VS
SEL
GND
VS = -10dBm (200mV at 50Ω Load)
VDC_BIAS = 1 V
VOUT-
RT
RT
Control
Input
Figure 7-5. Differential Off-Isolation (OISO)
VDD
Network Analyzer
TS3DV642
VOUT+
RS
VS
Channel ON
RT
VOUT-
RS
SEL = H or L
RS = RT = 50Ω
VS
RT
VS = -10dBm (200mV at 50Ω Load)
VDC_BIAS = 1 V
GND
RT
RT
Control
Input
Figure 7-6. Differential Bandwidth (BW)
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8 Detailed Description
8.1 Overview
The TS3DV642-Q1 is a 6 differential channel or 12 single ended channel bidirectional multiplexer/demultiplexer.
It offers low on-state resistance as well as low I/O capacitance which allows it to achieve a high bandwidth. The
TS3DV642-Q1 is a passive mux that is recommended for data rates up to 8.1 Gbps, however the device can be
used for interfaces with higher data rates if overall electrical link loss permits. The device provides the high
bandwidth necessary for many interfaces to handle differential and as well as single ended signals. The device
supports differential signaling with common mode voltage range (CMV) of 0 to 3.6 V and 0 - 5.5 V CMOS
signals.
The TS3DV642-Q1 has total 6 differential channels. All these channels are functionaly equivalent and provides
almost identical electrical performance. The channels can be used in an arbitrary fashion for differental and
single ended signals in any order.
8.2 Functional Block Diagram
TS3DV642-Q1
SEL1,
SEL2,
EN
D0+
D0+A
D0+B
CEC
CEC_A
CEC_B
8.3 Feature Description
The TS3DV642-Q1 is based on proprietary TI technology which uses FET switches driven by a high-voltage
generated from an integrated charge-pump to achieve a low on-state resistance. TS3DV642-Q1 has 6
differential channel or 12 single ended channel bidirectional switches with a high bandwidth. TS3DV642-Q1 uses
an extremely low power technology and uses only 45 µA ICC in active mode. The device has integrated ESD that
can support up to 2-kV Human-Body Model (HBM) and 1-kV Charge Device Model (CDM). TS3DV642-Q1 is
offered in a 42-pin QFN package (9 mm x 3.5 mm) with 0.5 mm pitch. The device can support analog I/O signal
in 0 to 5.5 V range. TS3DV642-Q1 also has a special feature that prevents the device from back-powering when
the VCC supply is not available and an analog signal is applied on the I/O pin. In this situation this special feature
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prevents leakage current in the device. The TS3DV642-Q1 is not designed for passing signals with negative
swings.
8.4 Device Functional Modes
D0+
D0+A
D0-
D1+
D1-
D2+
D2-
D3+
D3-
D0-A
D1+A
D1-A
D2+A
D2-A
D3+A
D3-A
D0+B
D0-B
D1+B
D1-B
D2+B
D2-B
D3+B
D3-B
SCL
SCL_A
SDA_A
HPD_A
CEC_A
SDA
HPD
CEC
SCL_B
SDA_B
HPD_B
CEC_B
SEL1
SEL2
EN
Control Logic
Figure 8-1. Logic Diagram
Table 8-1 lists the device functions for the TS3DV642-Q1 device.
Table 8-1. Functional Table
EN
SEL1
SEL2
FUNCTION
L
X
X
Switch disabled. All channels are Hi-Z.
Channel D0+/D0– to D0+A/D0–A is ON. All the other channels (D1+/D1-, D2+/
D2-, D3+/D3-, SCL, SDA, HPD, CEC) are Hi-Z.
H
H
L
L
L
Channel D0+/D0– to D0+B/D0–B is ON. All the other channels (D1+/D1-, D2+/
D2-, D3+/D3-, SCL, SDA, HPD, CEC) are Hi-Z.
H
H
H
H
H
L
All A channels are enabled. All B channels are Hi-Z.
All B channels are enabled. All A channels are Hi-Z.
H
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9 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes. Customers should validate and test their design
implementation to confirm system functionality.
9.1 Application Information
The TS3DV642-Q1 is an analog differential passive mux or demux that works for many high-speed differential
interfaces with data rates up to 8.1 Gbps. The device also works for single ended signals. The TS3DV642-Q1
supports differential signaling with common mode voltage range (CMV) of 0 to 3.6 V and with differential
amplitude up to 1800 mVpp, and single ended CMOS signaling with swing limited to 0 to 5.5 V. TS3DV642-Q1
can be used as mux or demux switch for:
•
•
•
•
•
HDMI 1.4 and HDMI 2.0 - up to 6 Gbps per channel
DisplayPort (DP) for RBR, HBR, and HBR-3 data rates - up to 8.1 Gbps per lane
Mipi DPHY interfaces such as DSI and CSI-2 - up to 4.5 Gbps per lane
Mipi CPHY based CSI-2
LVDS
6 Channels of the TS3DV642-Q1 are functionaly equivalent and can be used in an arbitrary fashion for
differential and single ended signals in any order. For example in Mipi DPHY applications any of the 6 differential
channels can be used for clock signals. For Mipi CPHY applications the data pins can be grouped any order to
form trio signals. For HDMI application, while TS3DV642-Q1 data signal pins are marked for specific HDMI use,
the main-link data, main-link clock, DDC, HPD, CEC can be assigned in any order if required.
9.2 Typical Application - Switching HDMI Source
The TS3DV642-Q1 can be used to switch HDMI signals. Figure 9-1 shows use case where TS3DV642-Q1
switches HDMI signals either from an external connector or from an SOC. This is a multiplexing use case. The
device can also be used as a demultiplexer where a graphics processor can be switched into one of the two
HDMI connectors. This section provides detailed design implemenation for a HDMI application where
TS3DV642-Q1 provides 2:1 multiplexing function.
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VCC
TMDS0+A
TMDS0-A
5V
D0+A
D0-A
HDMI
user
input
47kO
47kO
TMDS1+A
TMDS1-A
D1+A
D1-A
TMDS2+A
TMDS2-A
D2+A
D2-A
TMDS0+
TMDS0-
D0+
D0-
TMDS3+A
TMDS3-A
D3+A
D3-A
TMDS1+
TMDS1-
D1+
D1-
DDC_CLKA
DDC_DATA
SCL_A
SDA_A
TMDS2+
TMDS2-
D2+
D2-
5V
HPDA
HDMI
Sink
(Display)
HPD_A
2kO
2kO
TS3DV642-Q1
TMDS0+B
TMDS0-B
TMDS3+
TMDS3-
D0+B
D3+
D0-B
D3-
TMDS1+B
TMDS1-B
DDC_CLK
DDC_DAT
D1+B
D1-B
SCL
SDA
HPD
TMDS2+B
TMDS2-B
HPD
D2+B
D2-B
SOC/
HDMI
Source
TMDS3+B
TMDS3-B
D3+B
D3-B
DDC_CLKB
DDC_DATB
VCC
SCL_B
SDA_B
0.1ꢀF
HPDB
HPD_B
VCC
100kO
10kO
SEL
Figure 9-1. Switching HDMI application schematic
9.2.1 Design Requirements
Table 9-1. Design Parameters for HDMI Application
Design parameter
Example value
VCC
3.0 V to 3.6 V
0.1 µF
VCC decoupling capacitor
DDC Pull-up resistors on sink side
DDC Pull-up resistors on source side
HPD pulldown resistor on source side
Pull-up / Pull-down resistors for SEL1 / SEL2 pins
47 kΩ to 5 V
2 kΩ to 5 V
100 kΩ to GND
10 kΩ
9.2.2 Detailed Design Procedure
The TS3DV642-Q1 is designed to operate with 3.0 V to 3.6 V power supply. Decoupling capacitors may be used
to reduce noise and improve power supply integrity. Pull-up resistors to 5 V must be placed on the sinke side
DDC clock and data lines according to the HDMI standard.
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9.2.3 Systems Examples
9.2.3.1 DisplayPort 2:1 mulitplexing
ML0A+
ML0A-
D0+A
D0-A
ML1A+
ML1A-
D1+A
D1-A
ML2A+
ML2A-
D2+A
D2-A
ML0+
ML0-
D0+
D0-
ML3A+
ML3A-
D3+A
D3-A
ML1+
ML1-
D1+
D1-
AUXA+
AUXA-
SCL_A
SDA_A
ML2+
ML2-
D2+
D2-
HPDA
HPD_A
TS3DV642-Q1
ML0B+
ML0B-
ML3+
ML3-
D0+B
D3+
D0-B
D3-
ML1B+
ML1B-
AUX+
AUX-
D1+B
D1-B
SCL
SDA
ML2B+
ML2B-
HPD
D2+B
D2-B
HPD
ML3B+
ML3B-
D3+B
D3-B
AUXB+
AUXB-
SCL_B
SDA_B
HPDB
HPD_B
Figure 9-2. DisplayPort 2:1 switching
9.2.3.2 Mipi DPHY based CSI-2 switching
DATA_A4+
D0+A
D0-A
DATA_A4-
DATA_A3+
DATA_A3-
D1+A
D1-A
DATA_A2+
DATA_A2-
DATA4+
DATA4-
D2+A
D2-A
D0+
D0-
DATA_A1+
DATA_A1-
DATA3+
DATA3-
D3+A
D3-A
D1+
D1-
CLOCK_A+
CLOCK_A-
DATA2+
DATA2-
HPD_A
CEC_A
D2+
D2-
TS3DV642-Q1
DATA_B4+
DATA_B4-
DATA1+
DATA1-
D0+B
D0-B
D3+
D3-
DATA_B3+
DATA_B3-
D1+B
D1-B
CLOCK+
CLOCK-
HPD
CEC
DATA_B2+
DATA_B2-
D2+B
D2-B
DATA_B1+
DATA_B1-
D3+B
D3-B
CLOCK_B+
CLOCK_B-
HPD_B
CEC_B
Figure 9-3. Mipi DPHY based CSI-2 switching
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9.2.3.3 Mipi CPHY based CSI-2 switching
T0A_A
T0A_B
T0A_C
D0+A
D0-A
D1+A
T1A_A
T1A_B
T1A_C
D1-A
D2+A
D2-A
T0_A
T0_B
T0_C
D0+
D0-
D1+
T2A_A
T2A_B
D3+A
D3-A
T1_A
T1_B
T1_C
D1-
T2A_C
HPD_A
D2+
D2-
TS3DV642-Q1
T0A_A
T0A_B
T0A_C
T2_A
T2_B
T2_C
D0+B
D0-B
D1+B
D3+
D3-
HPD
T1A_A
T1A_B
T1A_C
D1-B
D2+B
D2-B
T2A_A
T2A_B
T2A_C
D3+B
D3-B
HPD_B
Figure 9-4. Mipi CPHY based CSI-2 switching
9.2.3.4 Mipi DPHY based DSI switching
DATA_A4+
DATA_A4-
D0+A
D0-A
DATA_A3+
DATA_A3-
D1+A
D1-A
DATA4+
DATA4-
D0+
D0-
DATA_A2+
DATA_A2-
D2+A
D2-A
DATA3+
DATA3-
D1+
D1-
DATA_A1+
DATA_A1-
D3+A
D3-A
DATA2+
DATA2-
CLOCK_A+
CLOCK_A-
D2+
D2-
HPD_A
CEC_A
TS3DV642-Q1
DATA1+
DATA1-
DATA_B4+
DATA_B4-
D3+
D3-
D0+B
D0-B
CLOCK+
CLOCK-
DATA_B3+
DATA_B3-
HPD
CEC
D1+B
D1-B
DATA_B2+
DATA_B2-
D2+B
D2-B
DATA_B1+
DATA_B1-
D3+B
D3-B
CLOCK_B+
CLOCK_B-
HPD_B
CEC_B
Figure 9-5. Mipi DPHY based DSI2 switching
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10 Power Supply Recommendations
VCC should be in the range of 3.0 V to 3.6 V. Voltage levels above those listed in the Absolute Ratings table
should not be used. Decoupling capacitors may be used to reduce noise and improve power supply integrity.
There are no power sequence requirements for the TS3DV642-Q1.
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11 Layout
11.1 Layout Guidelines
To ensure reliability of the device, the following commonly used printed-circuit board layout guidelines are
recommended:
•
Decoupling capacitors should be used between power supply pin and ground pin to ensure low impedance to
reduce noise To achieve a low impedance over a wide frequency range use capacitors with a high self-
resonance frequency.
•
•
•
ESD and EMI protection devices (if used) should be placed as close as possible to the connector.
Short trace lengths should be used to avoid excessive loading.
To minimize the effects of crosstalk on adjacent traces, keep the traces at least two times the trace width
apart.
•
•
•
Separate high-speed signals from low-speed signals and digital from analog signals
Avoid right-angle bends in a trace and try to route them at least with two 45° corners.
The high-speed differential signal traces should be routed parallel to each other as much as possible. The
traces are recommended to be symmetrical.
•
A solid ground plane should be placed next to the high-speed signal layer. This also provides an excellent
low-inductance path for the return current flow.
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11.2 Layout Example
TS3DV642-Q1 application with a single controller interfacing with two HDMI connectors.
1
2
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
3
HDMI
controller
SCL
SDA
D0+
D0-
4
5
6
7
D1+
D1-
HDMI Connector A
8
9
D2+
D2-
10
11
12
13
14
15
16
17
D3+
D3-
HPD
CEC
MCU
GPIOA
GPIOB
GPIOC
: VIA to GND
: VIA to signal plane
HDMI Connector B
Figure 11-1. Layout Example
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12 Device and Documentation Support
12.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
12.2 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.3 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
12.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.5 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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30-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TS3DV642RUARQ1
TS3DV642RUATQ1
XTS3DV642RUAQ1
PREVIEW
WQFN
WQFN
WQFN
RUA
42
42
42
3000 RoHS (In work)
& Non-Green
Call TI
Call TI
Call TI
Call TI
-40 to 105
-40 to 105
-40 to 105
PREVIEW
ACTIVE
RUA
250
RoHS (In work)
& Non-Green
Call TI
Call TI
RUA
3000 RoHS (In work)
& Non-Green
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
30-Dec-2020
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TS3DV642-Q1 :
Catalog: TS3DV642
•
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
•
Addendum-Page 2
PACKAGE OUTLINE
RUA0042A
WQFN - 0.8 mm max height
S
C
A
L
E
1
.
8
0
0
PLASTIC QUAD FLATPACK - NO LEAD
3.6
3.4
A
B
PIN 1 INDEX AREA
9.1
8.9
0.8
0.6
C
SEATING PLANE
0.08 C
0.05
0.00
2.05 0.1
2X 1.5
SYMM
(0.1) TYP
EXPOSED
THERMAL PAD
21
18
17
22
SYMM
43
2X 8
7.55 0.1
0.3
0.2
1
38
42X
42
39
38X 0.5
0.1
C A B
0.5
0.3
42X
PIN 1 ID
0.05
4219139/A 03/2020
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
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EXAMPLE BOARD LAYOUT
RUA0042A
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(2.05)
SYMM
SEE SOLDER MASK
DETAIL
42X (0.6)
42X (0.25)
42
39
1
38X (0.5)
38
(3.525) TYP
(R0.05) TYP
(
0.2) TYP
VIA
1.17 TYP
SYMM
43
(7.55) (8.8)
17
22
18
21
(0.775)
TYP
(3.3)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 10X
0.05 MIN
ALL AROUND
0.05 MAX
ALL AROUND
METAL UNDER
SOLDER MASK
METAL EDGE
EXPOSED
METAL
SOLDER MASK
OPENING
EXPOSED
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4219139/A 03/2020
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
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EXAMPLE STENCIL DESIGN
RUA0042A
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(0.56) TYP
42X (0.6)
42X (0.25)
42
39
1
38X (0.5)
38
(R0.05) TYP
(0.585)
TYP
43
SYMM
(8.8)
12X (0.97)
22
17
21
18
12X (0.92)
SYMM
(3.3)
SOLDER PASTE EXAMPLE
BASED ON 0.125 MM THICK STENCIL
SCALE: 12X
EXPOSED PAD 43
69% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
4219139/A 03/2020
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
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