TS3L500 [TI]
16-BIT TO 8-BIT SPDT GIGABIT LAN SWITCH WITH LED SWITCH; 16位到8位SPDT千兆网卡，带LED开关开关
| 型号： | TS3L500 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 16-BIT TO 8-BIT SPDT GIGABIT LAN SWITCH WITH LED SWITCH |
| 文件： | 总15页 (文件大小：330K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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ꢒ ꢊꢀ ꢔ ꢃ ꢕꢎ ꢁ ꢒꢊ ꢀꢓ ꢔ
SCDS212B − SEPTEMBER 2005 − REVISED APRIL 2006
D
D
D
D
Wide Bandwidth (BW > 1100 MHz Typ)
Low Crosstalk (X = −37 dB Typ)
TQFN PACKAGE
(TOP VIEW)
TALK
Low Bit-to-Bit Skew (t
= 100 ps Max)
sk(o)
Low and Flat ON-State Resistance
(r = 4 ꢀ Typ, r = 0.5 ꢀ Typ)
on
on(flat)
1
2
48
0B
GND
D
D
Low Input/Output Capacitance
(C = 8 pF Typ)
1
1
2
47 1B
46
A
0
A
1
ON
3
0B
45 1B
Rail-to-Rail Switching on Data I/O Ports
(0 to 5 V)
4
V
CC
2
5
44
43
GND
NC
D
V
Operating Range From 3 V to 3.6 V
CC
6
2B
1
GND
D
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
7
42 3B
A
2
A
3
1
2
2
8
41
2B
D
D
ESD Performance Tested Per JESD 22
− 2000-V Human-Body Model
(A114-B, Class II)
9
40 3B
GND
GND
10
11
12
13
14
15
39
V
CC
38 V
A
4
A
5
CC
− 1000-V Charged-Device Model (C101)
37 4B
1
1
2
2
Applications
5B
36
GND
− 10/100/1000 Base-T Signal Switching
− Differential (LVDS, LVPECL) Signal
Switching
− Audio/Video Switching
− Hub and Router Signal Switching
35 4B
A
6
A
7
5B
34
33
32
31
30
29
GND
GND 16
6B
1
7B
1
6B
2
7B
2
SEL 17
18
V
CC
LED 19
0
20
LED
1
description/ordering information
The TS3L500 is a 16-bit to 8-bit multiplexer/
demultiplexer LAN switch with a single select
(SEL) input. SEL controls the data path of the
multiplexer/demultiplexer. The device provides
additional I/Os for switching status indicating LED
signals.
The device provides a low and flat ON-state resistance (r ) and an excellent ON-state resistance match. Low
on
input/output capacitance, high bandwidth, low skew, and low crosstalk among channels make this device
suitable for various LAN applications, such as 10/100/1000 Base-T.
This device can be used to replace mechanical relays in LAN applications. It also can be used to route signals
from a 10/100 Base-T ethernet transceiver to the RJ-45 LAN connectors in laptops or in docking stations.
ORDERING INFORMATION
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
†
T
A
PACKAGE
−40°C to 85°C
TQFN
Tape and reel
TS3L500RHUR
TK500
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines
are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
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Copyright 2006, Texas Instruments Incorporated
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1
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ꢒꢊ ꢀ ꢔ ꢃ ꢕꢎ ꢁꢒ ꢊ ꢀ ꢓꢔ
SCDS212B − SEPTEMBER 2005 − REVISED APRIL 2006
FUNCTION TABLE
INPUT/OUTPUT
INPUT
SEL
FUNCTION
A
n
L
nB
A
A
= nB , LED = XLED
1
2
n
1
x
1
2
H
nB
= nB , LED = XLED
2 x
n
PIN DESCRIPTION
DESCRIPTION
Data I/O
NAME
A
n
nB
m
Data I/O
SEL
LED
Select input
LED I/O port
LED I/O port
x
XLED
m
2
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ꢒ ꢊꢀ ꢔ ꢃ ꢕꢎ ꢁ ꢒꢊ ꢀꢓ ꢔ
SCDS212B − SEPTEMBER 2005 − REVISED APRIL 2006
logic diagram (positive logic)
2
3
48
0B
1B
0B
1B
A
A
1
1
2
2
0
1
47
46
45
7
8
43
42
41
40
2B
3B
2B
3B
A
A
1
1
2
2
2
3
11
37
36
35
34
4B
5B
4B
5B
A
A
1
1
2
2
4
5
12
14
15
32
31
30
29
6B
7B
6B
7B
A
A
1
1
2
2
6
7
19
20
22
25
0LED
0LED
1LED
1LED
2LED
2LED
LED
LED
LED
1
2
1
2
1
2
0
1
2
23
26
52
51
54
17
SEL
3
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ꢒꢊ ꢀ ꢔ ꢃ ꢕꢎ ꢁꢒ ꢊ ꢀ ꢓꢔ
SCDS212B − SEPTEMBER 2005 − REVISED APRIL 2006
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4.6 V
CC
Control input voltage range, V (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Switch I/O voltage range, V (see Notes 1, 2, and 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Control input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
IN
I/O
IK IN
I/O port clamp current, I
(V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
I/OK I/O
ON-state switch current, I (see Note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA
Continuous current through V
I/O
or GND terminals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA
CC
Package thermal impedance, θ (see Note 5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31.8°C/W
JA
stg
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltages are with respect to ground, unless otherwise specified.
2. The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
3. V and V are used to denote specific conditions for V
I/O
.
I
O
4. I and I are used to denote specific conditions for I .
I
O
I/O
5. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 6)
MIN
3
MAX
3.6
5.5
0.8
5.5
85
UNIT
V
V
V
V
V
Supply voltage
CC
High-level control input voltage (SEL)
Low-level control input voltage (SEL)
Input/output voltage
2
V
IH
0
V
IL
0
V
I/O
T
A
Operating free-air temperature
−40
°C
NOTE 6: All unused control inputs of the device must be held at V
or GND to ensure proper device operation. Refer to the TI application report,
CC
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
4
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ꢒ ꢊꢀ ꢔ ꢃ ꢕꢎ ꢁ ꢒꢊ ꢀꢓ ꢔ
SCDS212B − SEPTEMBER 2005 − REVISED APRIL 2006
electrical characteristics for 1000 Base-T ethernet switching over recommended operating free-air
†
temperature range, V
= 3.3 V + 0.3 V (unless otherwise noted)
CC
‡
PARAMETER
TEST CONDITIONS
MIN TYP
MAX
−1.2
1
UNIT
V
V
SEL
SEL
SEL
V
V
V
V
= 3.6 V,
= 3.6 V,
= 3.6 V,
= 3.6 V,
I = −18 mA
IN
−0.7
IK
CC
CC
CC
CC
I
I
I
V
V
= V
CC
µA
µA
µA
pF
pF
pF
IH
IN
IN
= GND
= 0,
1
IL
I
Switch ON or OFF
250
2
500
2.5
4
CC
I/O
C
C
C
SEL
f = 1 MHz,
V = 0,
V
IN
= 0
IN
B port
f = 1 MHz,
f = 1 MHz,
Outputs open,
Outputs open,
Switch OFF
Switch ON
2.5
8
OFF
ON
I
V = 0,
I
9
V
CC
V
CC
V
CC
= 3 V,
1.5 V ≤ V ≤ V
,
I
O
I
O
I
O
= −40 mA
= −40 mA
= −40 mA
4
0.5
0.4
6
1
Ω
Ω
Ω
r
I
CC
on
§
= 3 V,
= 3 V,
V = 1.5 V and V
I
,
r
CC
on(flat)
¶
1.5 V ≤ V ≤ V
,
∆r
I
CC
on
†
‡
§
¶
V , V , I , and I refer to I/O pins. V refers to the control inputs.
IN
I
O
I
O
All typical values are at V
= 3.3 V (unless otherwise noted), T = 25°C.
CC
A
r
is the difference of r in a given channel at specified voltages.
on
on(flat)
∆r is the difference of r from center (A , A ) ports to any other port.
on on
4
5
electrical characteristics for 10/100 Base-T ethernet switching over recommended operating
†
free-air temperature range, V
= 3.3 V + 0.3 V (unless otherwise noted)
CC
‡
PARAMETER
TEST CONDITIONS
MIN TYP
MAX
−1.2
1
UNIT
V
V
SEL
SEL
SEL
V
V
V
V
= 3.6 V,
= 3.6 V,
= 3.6 V,
= 3.6 V,
I = −18 mA
IN
−0.7
IK
CC
CC
CC
CC
I
I
I
V
V
= V
CC
µA
µA
µA
pF
IH
IN
IN
= GND
= 0,
1
IL
I
Switch ON or OFF
250
2
500
2.5
4
CC
I/O
C
C
SEL
f = 1 MHz,
V = 0,
V
IN
= 0
IN
B port
f = 1 MHz,
f = 1 MHz,
Outputs open,
Outputs open,
Switch OFF
Switch ON
2.5
pF
OFF
I
C
r
V = 0,
I
8
4
pF
Ω
ON
V
CC
V
CC
V
CC
= 3 V,
1.25 V ≤ V ≤ V
,
I
O
I
O
I
O
= −10 mA to −30 mA
6
1
I
CC
on
§
= 3 V,
= 3 V,
V = 1.25 V and V
I
,
= −10 mA to −30 mA
= −10 mA to −30 mA
0.5
0.4
Ω
r
CC
on(flat)
¶
1.25 V ≤ V ≤ V
,
Ω
∆r
I
CC
on
†
‡
§
¶
V , V , I , and I refer to I/O pins. V refers to the control inputs.
IN
I
O
I
O
All typical values are at V
= 3.3 V (unless otherwise noted), T = 25°C.
CC
A
r
is the difference of r in a given channel at specified voltages.
on
on(flat)
∆r is the difference of r from center (A , A ) ports to any other port.
on on
4
5
5
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SCDS212B − SEPTEMBER 2005 − REVISED APRIL 2006
switching characteristics over recommended operating free-air temperature range,
V
= 3.3 V + 0.3 V, R = 200 Ω, C = 10 pF (unless otherwise noted) (see Figures 4 and 5)
CC
L
L
FROM
(INPUT)
TO
(OUTPUT)
†
PARAMETER
MIN TYP
MAX
UNIT
‡
t
t
t
t
t
B or A
A or B
A or B
B or A
0.25
ns
ns
ns
ps
ps
A or B
SEL
pd
, t
0.5
0.9
15
9
PZH PZL
, t
SEL
PHZ PLZ
§
50
50
100
150
A or B
sk(o)
¶
sk(p)
†
‡
All typical values are at V
CC
= 3.3 V (unless otherwise noted), T = 25°C.
A
The propagation delay is the calculated RC time constant of the typical ON-state resistance of the switch and the specified load capacitance when
driven by an ideal voltage source (zero output impedance).
§
¶
Output skew between center port (A to A ) to any other port
Skew between opposite transitions of the same output in a given device |t |
4
5
− t
PHL PLH
dynamic characteristics over recommended operating free-air temperature range,
V
= 3.3 V + 0.3 V (unless otherwise noted)
CC
†
PARAMETER
TEST CONDITIONS
See Figure 8
TYP
UNIT
dB
X
TALK
R
R
R
= 100 Ω,
= 100 Ω,
= 100 Ω,
f = 250 MHz,
f = 250 MHz,
See Figure 7
−37
−37
L
L
L
O
IRR
BW
See Figure 9
dB
1100
MHz
†
All typical values are at V
CC
= 3.3 V (unless otherwise noted), T = 25°C.
A
6
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SCDS212B − SEPTEMBER 2005 − REVISED APRIL 2006
OPERATING CHARACTERISTICS
0
−2
0
−20
−4
−40
−6
−60
−8
−80
−10
−12
−100
0.1
1
10
100
1000
10,000
1000
10,000
1
0.1
10
100
Frequency (MHz)
Frequency (MHz)
Figure 1. Gain vs Frequency
Figure 2. OFF Isolation vs Frequency
0
6
5
4
3
2
1
0
−20
−40
−60
−80
−100
1000
10,000
0
1
2
3
4
5
6
1
0.1
10
100
V
COM
(V)
Frequency (MHz)
Figure 3. Crosstalk vs Frequency
Figure 4. r
(ꢀ) vs V
(V)
on
com
7
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SCDS212B − SEPTEMBER 2005 − REVISED APRIL 2006
PARAMETER MEASUREMENT INFORMATION
Enable and Disable Times
V
CC
Input Generator
V
IN
50 Ω
50 Ω
V
G1
TEST CIRCUIT
DUT
2 × V
CC
Open
Input Generator
50 Ω
S1
R
V
V
O
L
I
GND
C
L
50 Ω
V
G2
R
L
(see Note A)
S1
V
C
V
R
V
TEST
/t
in
L
∆
L
CC
t
3.3 V 0.3 V
3.3 V 0.3 V
2 × V
200 Ω
200 Ω
GND
10 pF
10 pF
0.3 V
0.3 V
PLZ PZL
CC
t
/t
GND
V
CC
PHZ PZH
2.5 V
0 V
Output Control
1.25 V
1.25 V
(V
IN
)
V
I
t
t
PLZ
PZL
Output
V
OH
Waveform 1
V
/2
CC
V
O
S1 at 2 y V
(see Note B)
V
V
+ 0.3 V
CC
OL
V
OL
t
t
PZH
PHZ
Output
Waveform 2
S1 at GND
V
OH
− 0.3 V
OH
V
O
V
CC
/2
V
OL
(see Note B)
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A.
C includes probe and jig capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2.5 ns, t ≤ 2.5 ns.
O
r
f
D. The outputs are measured one at a time, with one transition per measurement.
E.
F.
t
t
and t
and t
are the same as t
.
.
PLZ
PZL
PHZ
PZH
dis
are the same as t
en
Figure 5. Test Circuit and Voltage Waveforms
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀꢁ ꢂꢃ ꢄꢅ ꢅ
ꢆ ꢇ ꢈꢉꢊ ꢀ ꢀ ꢋ ꢌ ꢈꢉꢊ ꢀ ꢁꢍ ꢎꢀ ꢏ ꢊꢏ ꢐꢉꢊ ꢀ ꢃ ꢐꢑ ꢁ ꢒꢊ ꢀꢓ ꢔ
ꢒ ꢊꢀ ꢔ ꢃ ꢕꢎ ꢁ ꢒꢊ ꢀꢓ ꢔ
SCDS212B − SEPTEMBER 2005 − REVISED APRIL 2006
PARAMETER MEASUREMENT INFORMATION
Skew
V
CC
Input Generator
V
IN
50 Ω
50 Ω
V
G1
TEST CIRCUIT
DUT
2 × V
CC
Open
Input Generator
50 Ω
S1
R
V
V
O
L
I
GND
C
L
50 Ω
V
G2
R
L
(see Note A)
S1
V
in
C
R
L
V
CC
TEST
L
t
3.3 V 0.3 V
3.3 V 0.3 V
Open
200 Ω
200 Ω
V
V
or GND
or GND
10 pF
10 pF
sk(o)
CC
t
Open
sk(p)
CC
3.5 V
Data In at
Ax or Ay
V
I
2.5 V
1.5 V
t
t
PHLx
PLHx
V
(V
OH
OH
Data Out at
XB or XB
V
O
+ V )/2
OL
3.5 V
2.5 V
1.5 V
1
2
V
OL
Input
t
t
sk(o)
sk(o)
V
(V
V
O
OH
OH
t
t
PHL
Data Out at
YB or YB
PLH
+ V )/2
OL
1
2
V
OH
+ V )/2
V
OL
Output
(V
OH
OL
OL
t
t
PHLy
PLHy
V
t
= ꢁt
− t
PHL PLH
ꢁ
sk(p)
t
= ꢁt
− t
ꢁ or ꢁt
− t
ꢁ
sk(o)
PLHy PLHx
PHLy PHLx
VOLTAGE WAVEFORMS
OUTPUT SKEW (t
VOLTAGE WAVEFORMS
PULSE SKEW [t
)
]
sk(p)
sk(o)
NOTES: A.
C includes probe and jig capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2.5 ns, t ≤ 2.5 ns.
O
r
f
D. The outputs are measured one at a time, with one transition per measurement.
Figure 6. Test Circuit and Voltage Waveforms
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁ ꢂꢃ ꢄ ꢅꢅ
ꢆꢇ ꢈꢉꢊ ꢀ ꢀꢋ ꢌ ꢈꢉ ꢊ ꢀ ꢁ ꢍꢎ ꢀ ꢏ ꢊꢏ ꢐꢉ ꢊ ꢀ ꢃꢐ ꢑ ꢁ ꢒꢊ ꢀꢓ ꢔ
ꢒꢊ ꢀ ꢔ ꢃ ꢕꢎ ꢁꢒ ꢊ ꢀ ꢓꢔ
SCDS212B − SEPTEMBER 2005 − REVISED APRIL 2006
PARAMETER MEASUREMENT INFORMATION
EXT TRIGGER
BIAS
Network Analyzer
(HP8753ES)
V
BIAS
P1
P2
V
CC
A
0B
1
0
C
= 10 pF
L
(see Note A)
DUT
SEL
V
SEL
NOTE A: C includes probe and jig capacitance.
L
Figure 7. Test Circuit for Frequency Response (BW)
Frequency response is measured at the output of the ON channel. For example, when V
= 0 and A is the input,
0
SEL
the output is measured at 0B . All unused analog I/O ports are left open.
1
HP8753ES setup
Average = 4
RBW = 3 kHz
V
= 0.35 V
BIAS
ST = 2 s
P1 = 0 dBM
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀꢁ ꢂꢃ ꢄꢅ ꢅ
ꢆ ꢇ ꢈꢉꢊ ꢀ ꢀ ꢋ ꢌ ꢈꢉꢊ ꢀ ꢁꢍ ꢎꢀ ꢏ ꢊꢏ ꢐꢉꢊ ꢀ ꢃ ꢐꢑ ꢁ ꢒꢊ ꢀꢓ ꢔ
ꢒ ꢊꢀ ꢔ ꢃ ꢕꢎ ꢁ ꢒꢊ ꢀꢓ ꢔ
SCDS212B − SEPTEMBER 2005 − REVISED APRIL 2006
PARAMETER MEASUREMENT INFORMATION
EXT TRIGGER
BIAS
Network Analyzer
(HP8753ES)
V
BIAS
P1
P2
V
CC
A
A
0B
0
1
1
R
= 100 Ω
L
1B
0B
1
2
1B
2B
2
DUT
A
A
2
3
1
R
= 100 Ω
L
3B
1
2B
3B
2
2
SEL
V
SEL
NOTES: A.
C includes probe and jig capacitance.
L
B. A 50-Ω termination resistor is needed to match the loading of the network analyzer.
Figure 8. Test Circuit for Crosstalk (X
)
TALK
Crosstalk is measured at the output of the nonadjacent ON channel. For example, when V
= 0
SEL
and A is the input, the output is measured at 1B . All unused analog input (A) ports are connected to GND, and output
0
1
(B) ports are connected to GND through 50-Ω pulldown resistors.
HP8753ES setup
Average = 4
RBW = 3 kHz
V
= 0.35 V
BIAS
ST = 2 s
P1 = 0 dBM
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁ ꢂꢃ ꢄ ꢅꢅ
ꢆꢇ ꢈꢉꢊ ꢀ ꢀꢋ ꢌ ꢈꢉ ꢊ ꢀ ꢁ ꢍꢎ ꢀ ꢏ ꢊꢏ ꢐꢉ ꢊ ꢀ ꢃꢐ ꢑ ꢁ ꢒꢊ ꢀꢓ ꢔ
ꢒꢊ ꢀ ꢔ ꢃ ꢕꢎ ꢁꢒ ꢊ ꢀ ꢓꢔ
SCDS212B − SEPTEMBER 2005 − REVISED APRIL 2006
PARAMETER MEASUREMENT INFORMATION
EXT TRIGGER
BIAS
Network Analyzer
(HP8753ES)
V
BIAS
P1
P2
V
CC
A
A
0B
1B
0
1
1
R
= 100 Ω
L
1
DUT
0B
1B
2
2
SEL
V
SEL
NOTES: A.
C includes probe and jig capacitance.
L
B. A 50-Ω termination resistor is needed to match the loading of the network analyzer.
Figure 9. Test Circuit for OFF Isolation (O
)
IRR
OFF isolation is measured at the output of the OFF channel. For example, when V
= V
and A is the input, the
SEL
CC 0
output is measured at 0B . All unused analog input (A) ports are left open, and output (B) ports are connected to GND
2
through 50-Ω pulldown resistors.
HP8753ES setup
Average = 4
RBW = 3 kHz
V
= 0.35 V
BIAS
ST = 2 s
P1 = 0 dBM
12
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
5-Feb-2007
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
TS3L500RHUR
ACTIVE
QFN
RHU
56
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
IMPORTANT NOTICE
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