TS3USBCA420IRSVT [TI]
USB Type-C SBU 多路复用器 | RSV | 16 | -40 to 85;型号: | TS3USBCA420IRSVT |
厂家: | TEXAS INSTRUMENTS |
描述: | USB Type-C SBU 多路复用器 | RSV | 16 | -40 to 85 商用集成电路 复用器 |
文件: | 总44页 (文件大小:1348K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
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TS3USBCA4
ZHCSHL5C –FEBRUARY 2018–REVISED SEPTEMBER 2019
TS3USBCA4 USB Type-C SBU 多路复用器
1 特性
3 说明
1
•
USB Type-C™用于模拟音频 MIC/AGND、
TS3USBCA4 是无源 4:1 (TS3USBCA420) 和 3:1
DisplayPort AUX 和其他信号的 4:1
(TS3USBCA420) 和 3:1 (TS3USBCA410) 多路复
用器 (MUX)
(TS3USBCA410) 多路复用器,支持将 USB Type-C
连接器端接到不同接口的 SBU1/SBU2 端子上的各种
类型的差分或单端信号。这些信号可以是差分
DisplayPort 辅助 (AUX)、模拟音频 MIC 和 AGND、
PCIe 差分时钟或任何其他受支持的通用差分或单端信
号。
•
•
适用于 0 至 3.6V 差分或单端信号的通用多路复用
器
用于 AGND 连接的 60mΩ 超低电阻 RON,可实现
低串扰性能
•
•
•
•
低总谐波失真 (THD)
音频路径 具有 超低导通状态电阻 (RON)、低串扰和出
色的总谐波失真 (THD) 性能。先断后通功能防止在信
号从一个通道传输到另一个通道时产生信号失真。高速
路径支持的带宽高达 500MHz,为 DisplayPort AUX、
PCIe 时钟和其他类似信号提供充分支持。这些 特性
再加上低功耗性能,使得这款器件适合于便携式音频
应用。
高达 500MHz 的高带宽通道
支持引脚和 I2C 配置
支持在 3.3V ±10% 稳压电源或 2.4V 至 5.5V 电池
电压下工作
•
•
•
工业温度范围:-40°C 至 85ºC TS3USBCA420I 和
TS3USBCA410I
商业温度范围:0ºC 至 70ºC TS3USBCA420 和
TS3USBCA410
TS3USBCA4 具有 2.4V 至 5.5V 宽电源电压范围,用
户可以灵活地选择使用单节电池、3.3V 稳压器或
VBUS 供电。它还提供面向商业和工业温度范围的选
项。
1.8mm x 2.6mm、16 引脚、0.4mm 间距 QFN 封
装
2 应用
器件信息(1)
•
•
•
•
•
•
•
平板电脑
器件型号
封装
封装尺寸(标称值)
笔记本电脑
台式机
TS3USBCA4
UQFN (16)
1.80mm × 2.60mm
(1) 如需了解所有可用封装,请参阅数据表末尾的可订购产品附
录。
游戏控制台
VR 模块
智能手机
显示器
简化原理图
USB Host
USB 2.0
L/R
TS5USBA224
DP/DM
MIC/GND
Audio Codec
DP
SBU
TS3USBCA420
AUX
CK
PCIe
CC
Debug
SEL0,1, OEn
uP
Type-C/PD
Controller
1
本文档旨在为方便起见,提供有关 TI 产品中文版本的信息,以确认产品的概要。 有关适用的官方英文版本的最新信息,请访问 www.ti.com,其内容始终优先。 TI 不保证翻译的准确
性和有效性。 在实际设计之前,请务必参考最新版本的英文版本。
English Data Sheet: SLLSF73
TS3USBCA4
ZHCSHL5C –FEBRUARY 2018–REVISED SEPTEMBER 2019
www.ti.com.cn
目录
8.2 Functional Block Diagram ....................................... 24
8.3 Feature Description................................................. 25
8.4 Device Functional Modes........................................ 26
8.5 Programming........................................................... 28
8.6 Register Maps ........................................................ 29
Application and Implementation ........................ 31
9.1 Application Information............................................ 31
9.2 Typical Application ................................................. 31
1
2
3
4
5
6
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings.............................................................. 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information.................................................. 5
6.5 Electrical Characteristics (3 V ≤ VCC ≤ 3.6 V)........... 5
6.6 Electrical Characteristics (2.4 V ≤ VCC ≤ 5.5 V)........ 7
6.7 Switching Characteristics (2.4 V ≤ VCC ≤ 5.5 V) ....... 9
6.8 Timing Requirements (3 V ≤ VCC ≤ 3.6 V) .............. 10
6.9 Timing Requirements (2.4 V ≤ VCC ≤ 5.5 V) ........... 10
6.10 Timing Diagrams................................................... 12
6.11 Typical Characteristics.......................................... 13
Parameter Measurement Information ................ 14
Detailed Description ............................................ 24
8.1 Overview ................................................................. 24
9
10 Power Supply Recommendations ..................... 34
11 Layout................................................................... 35
11.1 Layout Guidelines ................................................. 35
11.2 Layout Example .................................................... 35
12 器件和文档支持 ..................................................... 36
12.1 接收文档更新通知 ................................................. 36
12.2 支持资源................................................................ 36
12.3 商标....................................................................... 36
12.4 静电放电警告......................................................... 36
12.5 Glossary................................................................ 36
13 机械、封装和可订购信息....................................... 36
7
8
4 修订历史记录
注:之前版本的页码可能与当前版本有所不同。
Changes from Revision B (January 2019) to Revision C
Page
•
Changed description for LaAp pin From: "as a negative polarity" To "as a positive polarity". .............................................. 4
Changes from Revision A (August 2018) to Revision B
Page
•
Changed the I2C_EN pin Description From: This pin has an internal weak pull-up. To: This pin has an internal weak
pull-down. .............................................................................................................................................................................. 3
Changes from Original (February 2018) to Revision A
Page
•
将器件从预告信息 更改成了生产数据 ..................................................................................................................................... 1
2
Copyright © 2018–2019, Texas Instruments Incorporated
TS3USBCA4
www.ti.com.cn
ZHCSHL5C –FEBRUARY 2018–REVISED SEPTEMBER 2019
5 Pin Configuration and Functions
UQFN Package for TS3USBCA420
16-Pin (RSV)
UQFN Package for TS3USBCA410
16-Pin (RSV)
Top View
Top View
VCC
MIC_GND1/Ln1
MIC_GND2/Ln2
OEn
1
12
11
10
9
I2C_EN
SBU1
SBU2
GND
VCC
MIC_GND1/Ln1
MIC_GND2/Ln2
OEn
1
12
11
10
9
I2C_EN
SBU1
SBU2
GND
2
3
4
2
3
4
Not to scale
Not to scale
Pin Functions
PIN
I/O
DESCRIPTION
NAME
TS3USBCA420
TS3USBCA410
VCC
1
1
P
Power supply. External decoupling capacitors are required close to this pin.
Analog audio MIC/AGND signal connection to audio codec. This pin can also function as a general
purpose I/O.
MIC_GND1/Ln1
MIC_GND2/Ln2
2
3
2
3
I/O, CMOS
Analog audio MIC/AGND signal connection to audio codec. This pin can also function as a general
purpose I/O.
I/O, CMOS
2 Level I
Output Enable:
L: Normal Operation
H: Standby Mode, I2C registers reset (Default)
This pin has an internal weak pull-up.
OEn
4
5
6
4
5
6
In Pin Configuration Mode (I2C_EN = L), this pin functions as SEL1 which is used along with SEL0
pin to select switch configurations (Refer to 表 2). This pin has an internal weak pull-down.
In I2C Mode (I2C_EN = M or H), this pin functions as SCL pin for I2C clock. When used for I2C
clock, pull it up to VI2C with a resistor between 0.62 kΩ and 2.2 kΩ.
2 Level I
(Failsafe)
SEL1/SCL
SEL0/SDA
In Pin Configuration Mode (I2C_EN = L), this pin functions as SEL0 which is used along with SEL1
pin to select switch configurations (Refer to 表 2). This pin has an internal weak pull-down.
In I2C Mode (I2C_EN = M or H), this pin functions as SDA pin for I2C data. When used for I2C
2 Level I/O
(Failsafe)
data, pull it up to VI2C with a resistor between 0.62 kΩ and 2.2 kΩ.
This pin can be used in single-ended format or as a positive polarity differential pair partner to pin
LnBn. It can be used for connection to any generic I/O signals such as for DisplayPort AUX, PCI
Express clock, I2C, UART, and debug interfaces.
LnBp
LnBn
7
8
7
8
I/O, CMOS
This pin can be used in single-ended format or as a negative polarity differential pair partner to pin
LnBp. It can be used for connection to any generic I/O signals such as for DisplayPort AUX, PCI
Express clock, I2C, UART, and debug interfaces.
I/O, CMOS
G
GND
9
9
Primary ground connection for the TS3USBCA4. Must be connected to system ground.
I/O, CMOS
(Failsafe)
This pin should be DC coupled to the SBU2 pin of the Type-C receptacle. This pin has an internal
nominally 1.6-MΩ pull-down resistor.
SBU2
10
10
I/O, CMOS
(Failsafe)
This pin should be DC coupled to the SBU1 pin of the Type-C receptacle. This pin has an internal
nominally 1.6-MΩ pull-down resistor.
SBU1
11
12
11
12
This pin enables I2C Mode and sets I2C mode addresses (Refer to 表 5) depending on the pin
level defined in 表 1.
L: Pin Configuration Mode
M: I2C Mode enabled with I2C address ADDR0
I2C_EN
3 Level I
H: I2C Mode enabled with I2C address ADDR1
This pin has an internal weak pull-down.
Copyright © 2018–2019, Texas Instruments Incorporated
3
TS3USBCA4
ZHCSHL5C –FEBRUARY 2018–REVISED SEPTEMBER 2019
www.ti.com.cn
Pin Functions (continued)
PIN
I/O
DESCRIPTION
NAME
TS3USBCA420
TS3USBCA410
This pin can be used in single-ended format or as a negative polarity differential pair partner to pin
LnCp. It can be used for connection to any generic I/O signals such as for DisplayPort AUX, PCI
Express clock, I2C, UART, and debug interfaces.
LnCn
13
14
I/O, CMOS
This pin can be used in single-ended format or as a positive polarity differential pair partner to pin
LnCn. It can be used for connection to any generic I/O signals such as for DisplayPort AUX, PCI
Express clock, I2C, UART, and debug interfaces.
LnCp
NC
I/O, CMOS
I/O, CMOS
13
14
Not connected.
This pin flips the switches based on type-C plug orientation in pin configuration mode (I2C_EN=L).
L: Normal orientation.
H: Flipped orientation.
FLIP
This pin has an internal weak pull-down.
This pin can be used in single-ended format or as a negative polarity differential pair partner to pin
LnAp. This pin is preferred for connection to DisplayPort AUX. It can also be used for connection
to any generic I/O signals such as for PCI Express clock, I2C, UART, and debug interfaces.
LnAn
LnAp
15
16
15
16
I/O, CMOS
I/O, CMOS
This pin can be used in single-ended format or as a positive polarity differential pair partner to pin
LnAn. This pin is preferred for connection to DisplayPort AUX. It can also be used for connection
to any generic I/O signals such as for PCI Express clock, I2C, UART, and debug interfaces.
6 Specifications
6.1 Absolute Maximum Ratings
Over operating free-air temperature range unless otherwise noted.(1)
MIN
-0.5
-4
MAX
6
UNIT
V
(2)
VCC
Supply Voltage Range
VIN_DIFF
VIN_SE
VIN_CMOS
VIN_SBU
TJ
Differential Voltage at Differential Inputs
4
V
(2)
Input Voltage at Differential Inputs
-0.5
-0.5
-0.5
6
V
(2)
Input Voltage at CMOS Inputs other than SBU1/SBU2 Pins
6
V
(2)
Input Voltage at SBU1/SBU2 Input-output Pins
6
V
Junction Temperature
Storage temperature
105
150
°C
°C
TSTG
-65
(1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to the GND terminal.
6.2 ESD Ratings
PARAMETER
VALUE
UNIT
Human body model (HBM), per
VHBM
VCDM
Electrostatic discharge
Electrostatic discharge
±2000
V
ANSI/ESDA/JEDEC JS-001, all pins(1)
Charged device model (CDM), per JEDEC
specification JESD22-C101, all pins(2)
±500
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
Over operating free-air temperature range unless otherwise noted.
MIN
0
NOM
MAX
70
UNIT
°C
°C
V
TA
Ambient temperature for TS3USBCA410 and TS3USBCA420
Ambient temperature for TS3USBCA410I and TS3USBCA420I
Supply voltage
TA
-40
2.4
1.7
0
85
VCC
5.0
5.5
3.6
1.8
100
VI2C
VI/O_DIFF
VPSN
Supply that external resistors on SDA and SCL are pulled up too
Differential Input-output Voltage
V
V
Power supply noise
mV
4
Copyright © 2018–2019, Texas Instruments Incorporated
TS3USBCA4
www.ti.com.cn
ZHCSHL5C –FEBRUARY 2018–REVISED SEPTEMBER 2019
6.4 Thermal Information
TS3USBCA4
THERMAL METRIC
RSV (R-PUQFN-N16)
UNIT
16 PINS
107.1
41.2
(1)
RθJA
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
(2)
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
(3)
Junction-to-board thermal resistance
43.6
(4)
ΨJT
Junction-to-top characterization parameter
1.1
(5)
(6)
ΨJB
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
43.6
RθJC(bot)
N/A
(1) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
(2) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC standard
test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(3) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
(4) The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7).
(5) The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7).
(6) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
6.5 Electrical Characteristics (3 V ≤ VCC ≤ 3.6 V)
All minimum/maximum specifications are at TA = -40/85°C, VCC = 3.0 V/3.6 V, unless otherwise noted. Typical specifications
are at TA = 25°C, VCC = 3.3 V, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Power
ICC
Supply Current
OEn = L, DEVICE_ENABLE = 1
OEn = L, DEVICE_ENABLE = 0
OEn = 3.6 V
45
17
70
30
μA
μA
μA
μA
IOFF_I2C
Device Shutdown Current
Device Shutdown Current
Device Shutdown Current
0.05
4
3.5
12
IOFF_OEN
OEn = 1.4 V
SEL0, SEL1
VIH
VIL
Input-high voltage
1.4
V
V
Input-low voltage
Input-high current
Input-low current
Pull-down resistor
0.4
2.5
1
IIH
VIN = VCC
VIN = 0 V
µA
µA
MΩ
IIL
RPD
FLIP
VIH
VIL
1.6
1.4
3.0
5.8
Input-high voltage
Input-low voltage
Input-high current
Input-low current
Pull-down resistor
V
V
0.4
2.5
1
IIH
VIN = VCC
VIN = 0 V
µA
µA
MΩ
IIL
RPD
OEn
VIH
VIL
1.6
1.4
3
5.8
Input-high voltage
Input-low voltage
Input-high current
Input-low current
Pull-up resistor
V
V
0.4
0.6
6
IIH
VIN=VCC
VIN=0 V
µA
µA
MΩ
IIL
RPU
I2C_EN
VIH
0.6
1.1
2.5
Input-high voltage
0.85
VCC
Copyright © 2018–2019, Texas Instruments Incorporated
5
TS3USBCA4
ZHCSHL5C –FEBRUARY 2018–REVISED SEPTEMBER 2019
www.ti.com.cn
Electrical Characteristics (3 V ≤ VCC ≤ 3.6 V) (continued)
All minimum/maximum specifications are at TA = -40/85°C, VCC = 3.0 V/3.6 V, unless otherwise noted. Typical specifications
are at TA = 25°C, VCC = 3.3 V, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Upper bound of mid-level input voltage.
Higher input may be intepreted as logic
HIGH.
VIMH
0.6
VCC
Lower bound of mid-level input
voltage. Lower input may be intepreted
as logic LOW.
VIML
0.4
VCC
VIL
IIH
Input-low voltage
Input-high current
Mid-level input current
Input-low current
Pull-down resistor
0.15
2.5
1.2
1
VCC
µA
IIM
IIL
µA
µA
RPD
1.6
3.0
5.8
MΩ
I2C Control Pins SCL, SDA
VIH_I2C
VIL_I2C
VOL_I2C
IOL_I2C
II_I2C
High-level input voltage
I2C mode
I2C mode
I2C mode; IOL_I2C = 3 mA
I2C mode; VOL_I2C = 0.4 V
0.1*VI2C < Input voltage < 3.6 V
1.3
0
VI2C
0.5
V
V
Low-level input voltage
Low-level output voltage
Low-level output current
Input current on SDA pin
Input capacitance
0
0.4
V
6
mA
µA
pF
-5
0.5
5
CI_I2C
10
C(I2C_FM_
BUS)
I2C bus capacitance for FM (400 kHz)
150
pF
R(EXT_I2C External pull up resistors on both SDA
C(I2C_FM_BUS) = 150 pF
620
1500
2200
Ω
and SCL for FM (400 kHz)
_FM)
SBU1, SBU2
Single-ended capacitance at
CSBU_HS
VIN = 0 V, outputs open, high-speed path
enabled
4
8
11
10
13
14
pF
pF
500MHz looking into SBU pin
CSBU_AU Single-ended capacitance at
VIN = 0 V, outputs open, audio path
enabled; TA = 25°C; VCC = 3.3 V
500MHz looking into SBU pin
DIO
Single-ended capacitance at
CSBU_OFF
VIN = 0 V, outputs open, OEn=H; TA
25°C; VCC = 3.3 V
=
11
14
17
pF
500MHz looking into SBU pin
RPD
Pull-down resistor
0.8
1.6
3.3
MΩ
LnA, LnB, LnC: HIGH-SPEED PATH
VI_HS
Single-ended HS input voltage
-0.3
3.6
V
Single-ended capacitance at 500 MHz
looking into HS pins
VIN = 0 V, outputs open, high-speed path
enabled
CHS_ON
8.5
1.7
10.5
pF
CHS_AUDI Single-ended capacitance at 500 MHz
VIN = 0 V, outputs open, audio path
enabled; TA = 25°C; VCC = 3.3 V
2
pF
looking into HS pins
O
Single-ended capacitance at 500 MHz
looking into HS pins
VIN = 0 V, outputs open, OEn=H; TA
25°C; VCC = 3.3 V
=
CHS_OFF
1.7
4.9
2
7.1
0.5
pF
Ω
RON_HS
ON resistance
VIN = 0 V, IO = -40 mA
ON resistance match between pairs of
the same channel
ΔRON_HS
VIN ≤ 0 V, IO = -40 mA
Ω
RON_FLAT ON resistance flatness (RON_HS(MAX)
-
0 V ≤ VIN ≤ 3.6 V, IO = -40 mA
1.35
510
Ω
RON_HS(MIN)
)
_HS
RL = 50 Ω, VIN = 0 V, MIC_GND1 pin
open, MIC_GND1 pin open; TA = 25°C;
VCC = 3.3 V
BWHS
-3-dB bandwidth
460
-0.3
550
3.6
MHz
RL = 50 Ω, 10 kHz to 20 MHz offset, f =
100 MHz; TA = 25°C; VCC = 3.3 V
RJHS
Additive random jitter
0.012
ps-RMS
MIC_GND1, MIC_GND2: AUDIO PATH
VI_MIC MIC input voltage
V
6
Copyright © 2018–2019, Texas Instruments Incorporated
TS3USBCA4
www.ti.com.cn
ZHCSHL5C –FEBRUARY 2018–REVISED SEPTEMBER 2019
Electrical Characteristics (3 V ≤ VCC ≤ 3.6 V) (continued)
All minimum/maximum specifications are at TA = -40/85°C, VCC = 3.0 V/3.6 V, unless otherwise noted. Typical specifications
are at TA = 25°C, VCC = 3.3 V, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
CAUDIO_O Single-ended capacitance at 500MHz
VIN = 0 V, outputs open, audio path
enabled; TA = 25°C; VCC = 3.3 V
9.5
12
pF
looking into the MIC_GND pins
N
CAUDIO_H Single-ended capacitance at 500MHz
VIN = 0 V, outputs open, high-speed path
enabled; TA = 25°C; VCC = 3.3 V
11.5
12.5
50
16
14.5
80
pF
pF
looking into the MIC_GND pins
S
CAUDIO_O Single-ended capacitance at 500MHz
VIN = 0 V, outputs open, OEn=H; TA
25°C; VCC = 3.3 V
=
looking into the MIC_GND pins
FF
RON_AUDI
O
ON resistance for AUDIO path
VIN = 0 V, IO = -75 mA
mΩ
MHz
dB
RL = 50 Ω, VIN = 0 V; TA = 25°C; VCC
=
BWAUDIO -3-dB bandwidth
580
630
-105
-96
700
-100
-92
3.3 V
RL = 50 Ω, VIN = 3.3 V ± 200 mVPP, f =
217 Hz
PSR217
RL = 50 Ω, VIN = 3.3 V ± 200 mVPP, f = 1
kHz
PSR1K
Power supply rejection
dB
RL = 50 Ω, VIN = 3.3 V ± 200 mVPP, f =
20 kHz
PSR20K
-85
-81
dB
RS=600Ω, RL=600Ω,
VIN=1.8V±200mVPP, f=20Hz~20kHz; TA
= 25°C; VCC = 3.3 V
THD200_
MIC
Total harmonic distortion
Total harmonic distortion
0.006
0.003
%
%
RS=600Ω, RL=600Ω,
VIN=1.8V±500mVPP, f=20Hz~20kHz; TA
= 25°C; VCC = 3.3 V
THD500_
MIC
XTALK_MI
CGND
VIN = 200 mVPP, f = 20 Hz – 20 kHz, RL
= 50 Ω; TA = 25°C;
Crosstalk between MIC and AGND
OFF isolation
-110
-73
-90
-67
dB
dB
ISOOFF_
MICGND
VIN = 200 mVPP, f = 20 Hz – 20 kHz, RL
= 50 Ω; TA = 25°C;
6.6 Electrical Characteristics (2.4 V ≤ VCC ≤ 5.5 V)
All minimum/maximum specifications are at TA = -40/85°C, VCC = 2.4 V/5.5 V, unless otherwise noted. Typical specifications
are at TA = 25°C, VCC = 3.3 V, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Power
ICC
Supply Current
OEn = L, DEVICE_ENABLE = 1
OEn = L, DEVICE_ENABLE = 0
OEn = 3.6 V
45
17
75
40
μA
μA
μA
μA
IOFF_I2C
Device Shutdown Current
Device Shutdown Current
Device Shutdown Current
0.05
4
5.5
80
IOFF_OEN
OEn = 1.4 V
SEL0, SEL1
VIH
VIL
IIH
Input-high voltage
1.4
V
V
Input-low voltage
Input-high current
Input-low current
Pull-down resistor
0.4
3.5
1
VIN = VCC
VIN = 0 V
µA
µA
MΩ
IIL
RPD
FLIP
VIH
VIL
IIH
1.6
1.4
3.0
3.0
5.8
Input-high voltage
Input-low voltage
Input-high current
Input-low current
Pull-down resistor
V
V
0.4
3.5
1
VIN = VCC
VIN = 0 V
µA
µA
MΩ
IIL
RPD
OEn
VIH
1.6
1.5
5.8
Input-high voltage
V
Copyright © 2018–2019, Texas Instruments Incorporated
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Electrical Characteristics (2.4 V ≤ VCC ≤ 5.5 V) (continued)
All minimum/maximum specifications are at TA = -40/85°C, VCC = 2.4 V/5.5 V, unless otherwise noted. Typical specifications
are at TA = 25°C, VCC = 3.3 V, unless otherwise noted.
PARAMETER
Input-low voltage
TEST CONDITIONS
MIN
TYP
MAX
0.4
1
UNIT
V
VIL
IIH
Input-high current
Input-low current
Pull-up resistor
VIN=VCC
VIN=0 V
µA
IIL
8
µA
RPU
I2C_EN
VIH
0.6
1.1
2.5
MΩ
Input-high voltage
0.9
VCC
VCC
Upper bound of mid-level input
voltage. Higher input may be intepreted
as logic HIGH.
VIMH
0.58
Lower bound of mid-level input
voltage. Lower input may be intepreted
as logic LOW.
VIML
0.42
VCC
VIL
IIH
Input-low voltage
Input-high current
Mid-level input current
Input-low current
Pull-down resistor
0.14
3.5
1.6
1
VCC
µA
IIM
IIL
µA
µA
RPD
1.6
3.0
5.8
MΩ
I2C Control Pins SCL, SDA
VIH_I2C
VIL_I2C
VOL_I2C
IOL_I2C
II_I2C
High-level input voltage
I2C mode
I2C mode
I2C mode; IOL_I2C = 3 mA
I2C mode; VOL_I2C = 0.4 V
0.1*VI2C < Input voltage < 3.6 V
1.3
0
VI2C
0.5
V
V
Low-level input voltage
Low-level output voltage
Low-level output current
Input current on SDA pin
Input capacitance
0
0.4
V
4
mA
µA
pF
-5
0.5
5
CI_I2C
10
C(I2C_FM_
BUS)
I2C bus capacitance for FM (400 kHz)
150
pF
R(EXT_I2C External pull up resistors on both SDA
C(I2C_FM_BUS) = 150 pF
620
1500
2200
Ω
and SCL for FM (400 kHz)
_FM)
SBU1, SBU2
Single-ended capacitance at
CSBU_HS
VIN = 0 V, outputs open, high-speed path
enabled
4
8
11
10
13
14
pF
pF
500MHz looking into SBU pin
CSBU_AU Single-ended capacitance at
VIN = 0 V, outputs open, audio path
enabled; TA = 25°C; VCC = 3.3 V
500MHz looking into SBU pin
DIO
Single-ended capacitance at
CSBU_OFF
VIN = 0 V, outputs open, OEn=H; TA
25°C; VCC = 3.3 V
=
11
14
17
pF
500MHz looking into SBU pin
RPD
Pull-down resistor
0.8
1.6
3.3
MΩ
LnA, LnB, LnC: HIGH-SPEED PATH
VI_HS
Single-ended HS input voltage
-0.3
3.6
V
Single-ended capacitance at 500 MHz
looking into HS pins
VIN = 0 V, outputs open, high-speed path
enabled
CHS_ON
8.5
1.7
10.5
pF
CHS_AUDI Single-ended capacitance at 500 MHz
VIN = 0 V, outputs open, audio path
enabled; TA = 25°C; VCC = 3.3 V
2
pF
looking into HS pins
O
Single-ended capacitance at 500 MHz
looking into HS pins
VIN = 0 V, outputs open, OEn=H; TA
25°C; VCC = 3.3 V
=
CHS_OFF
1.7
4.9
2
7.5
pF
Ω
RON_HS
ON resistance
VIN = 0 V, IO = -40 mA
ON resistance match between pairs of
the same channel
ΔRON_HS
VIN ≤ 0 V, IO = -40 mA
0.65
Ω
RON_FLAT ON resistance flatness (RON_HS(MAX)
RON_HS(MIN)
-
0 V ≤ VIN ≤ 3.6 V, IO = -40 mA
1.35
Ω
)
_HS
8
Copyright © 2018–2019, Texas Instruments Incorporated
TS3USBCA4
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ZHCSHL5C –FEBRUARY 2018–REVISED SEPTEMBER 2019
Electrical Characteristics (2.4 V ≤ VCC ≤ 5.5 V) (continued)
All minimum/maximum specifications are at TA = -40/85°C, VCC = 2.4 V/5.5 V, unless otherwise noted. Typical specifications
are at TA = 25°C, VCC = 3.3 V, unless otherwise noted.
PARAMETER
-3-dB bandwidth
Additive random jitter
TEST CONDITIONS
MIN
TYP
MAX
UNIT
RL = 50 Ω, VIN = 0 V; TA = 25°C; VCC
=
BWHS
RJHS
450
510
670
MHz
3.3 V
RL = 50 Ω, 10 kHz to 20 MHz offset, f =
100 MHz; TA = 25°C; VCC = 3.3 V
0.012
ps-RMS
MIC_GND1, MIC_GND2: AUDIO PATH
VI_MIC MIC input voltage
-0.3
3.6
12
V
CAUDIO_O Single-ended capacitance at 500MHz
VIN = 0 V, outputs open, audio path
enabled; TA = 25°C; VCC = 3.3 V
9.5
11.5
12.5
50
pF
looking into the MIC_GND pins
N
CAUDIO_H Single-ended capacitance at 500MHz
VIN = 0 V, outputs open, high-speed path
enabled; TA = 25°C; VCC = 3.3 V
16
14.5
80
pF
pF
looking into the MIC_GND pins
S
CAUDIO_O Single-ended capacitance at 500MHz
VIN = 0 V, outputs open, OEn=H; TA
25°C; VCC = 3.3 V
=
looking into the MIC_GND pins
FF
RON_AUDI
O
ON resistance for AUDIO path
VIN = 0 V, IO = -75 mA
mΩ
MHz
dB
RL = 50 Ω, VIN = 0 V; TA = 25°C; VCC
3.3 V
=
BWAUDIO -3-dB bandwidth
580
630
-105
-96
720
-96
-90
-81
RL = 50 Ω, VIN = 3.3 V ± 200 mVPP, f =
217 Hz
PSR217
RL = 50 Ω, VIN = 3.3 V ± 200 mVPP, f = 1
kHz
PSR1K
Power supply rejection
dB
RL = 50 Ω, VIN = 3.3 V ± 200 mVPP, f =
20 kHz
PSR20K
-85
dB
RS=600Ω, RL=600Ω,
VIN=1.8V±200mVPP, f=20HZ~20kHz; TA
= 25°C; VCC = 3.3 V
THD200_
MIC
Total harmonic distortion
Total harmonic distortion
0.006
0.003
%
%
RS=600Ω, RL=600Ω,
VIN=1.8V±500mVPP, f=20Hz~20kHz; TA
= 25°C; VCC = 3.3 V
THD500_
MIC
XTALK_MI
CGND
VIN = 200 mVPP, f = 20 Hz – 20 kHz, RL
= 50 Ω; TA = 25°C;
Crosstalk between MIC and AGND
OFF isolation
-110
-73
-90
-67
dB
dB
ISOOFF_
MICGND
VIN = 200 mVPP, f = 20 Hz – 20 kHz, RL
= 50 Ω; TA = 25°C;
6.7 Switching Characteristics (2.4 V ≤ VCC ≤ 5.5 V)
All minimum/maximum specifications are at TA = -40/85°C, VCC = 2.4 V/5.5 V, unless otherwise noted. Typical specifications
are at TA = 25°C, VCC = 3.3 V, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
I2C
fSCL
I2C clock frequency
400
kHz
µs
Bus free time between START and
STOP conditions
tBUF
1.3
0.6
Hold time after repeated START
condition. After this period, the first clock
pulse is generated
tHDSTA
µs
tLOW
tHIGH
Low period of the I2C clock
High period of the I2C clock
1.3
0.6
µs
µs
Setup time for a repeated START
condition
tSUSTA
0.6
µs
tHDDAT
tSUDAT
tR
Data hold time
0
µs
ns
ns
Data setup time
150
Rise time of both SDA and SCL signals
300
Copyright © 2018–2019, Texas Instruments Incorporated
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Switching Characteristics (2.4 V ≤ VCC ≤ 5.5 V) (continued)
All minimum/maximum specifications are at TA = -40/85°C, VCC = 2.4 V/5.5 V, unless otherwise noted. Typical specifications
are at TA = 25°C, VCC = 3.3 V, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
20 ×
(VI2C/5.5
V)
tF
Fall time of both SDA and SCL signals
Setup time for STOP condition
300
ns
tSUSTO
0.6
µs
6.8 Timing Requirements (3 V ≤ VCC ≤ 3.6 V)
All minimum/maximum specifications are at TA = -40/85°C, VCC = 3.0 V/3.6 V, unless otherwise noted. Typical specifications
are at TA = 25°C, VCC = 3.3 V, unless otherwise noted.
TEST
CONDITIONS
MIN
NOM
MAX
UNIT
VPU=1.8V,
RPU=2100Ω,
CL=50pF
tON_MICG
ND
Switch ON time for MIC/AGND path
Switch OFF time for MIC/AGND path
10
µs
VPU=1.8V,
RPU=2100Ω,
CL=50pF
tOFF_MICG
ND
5
µs
tON_HS
Switch ON time for high-speed path
Switch OFF time for high-speed path
RS=50Ω, RL =50Ω
RS=50Ω, RL =50Ω
1.1
µs
ns
tOFF_HS
725
VPU=1.8V,
tBBM
Break before make off time for MIC/AGND path
RPU=2100Ω,
RL=50Ω, CL=50pF
1300
ns
tFLIP
tDEV_ENA
Response time for the FLIP pin
RS=50Ω, RL=50Ω
1
µs
µs
Device enable time from OEn = L to device ready
OEn=L
350
BLE
tDEV_DISA
BLE
Device disable time from OEn = H to device shutdown
OEn=H
175
250
ns
µs
ns
tD_PG
VCC (MIN) to Internal Power Good asserted high (Refer to 图 1) OEn=L
Debounce time for SEL[1:0] and I2C_EN configuration pins
(Refer to 图 1)
tCFG_DB
OEn=L
150
0.1
tVCC_RAM VCC power supply (0 – 100%) ramp time requirement (Refer to
P
100
ms
图 1)
6.9 Timing Requirements (2.4 V ≤ VCC ≤ 5.5 V)
All minimum/maximum specifications are at TA = -40/85°C, VCC = 2.4 V/5.5 V, unless otherwise noted. Typical specifications
are at TA = 25°C, VCC = 3.3 V, unless otherwise noted.
TEST
CONDITIONS
MIN
NOM
MAX
UNIT
VPU=1.8V,
RPU=2100Ω,
CL=50pF
tON_MICG
ND
Switch ON time for MIC/AGND path
Switch OFF time for MIC/AGND path
12
µs
VPU=1.8V,
RPU=2100Ω,
CL=50pF
tOFF_MICG
ND
6
µs
tON_HS
Switch ON time for high-speed path
Switch OFF time for high-speed path
RS=50Ω, RL =50Ω
RS=50Ω, RL =50Ω
1.2
µs
ns
tOFF_HS
780
VPU=1.8V,
tBBM
tFLIP
Break before make off time for MIC/AGND path
RPU=2100Ω,
RL=50Ω, CL=50pF
1300
ns
Response time for the FLIP pin
RS=50Ω, RL=50Ω
1.1
µs
µs
tDEV_ENA
BLE
Device enable time from OEn = L to device ready
OEn=L
450
10
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TS3USBCA4
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ZHCSHL5C –FEBRUARY 2018–REVISED SEPTEMBER 2019
Timing Requirements (2.4 V ≤ VCC ≤ 5.5 V) (continued)
All minimum/maximum specifications are at TA = -40/85°C, VCC = 2.4 V/5.5 V, unless otherwise noted. Typical specifications
are at TA = 25°C, VCC = 3.3 V, unless otherwise noted.
TEST
CONDITIONS
MIN
NOM
MAX
UNIT
tDEV_DISA
BLE
Device disable time from OEn = H to device shutdown
OEn=H
200
250
ns
µs
ns
tD_PG
VCC (MIN) to Internal Power Good asserted high (Refer to 图 1) OEn=L
Debounce time for SEL[1:0] and I2C_EN configuration pins
(Refer to 图 1)
tCFG_DB
OEn=L
140
0.1
tVCC_RAM VCC power supply (0 – 100%) ramp time requirement (Refer to
P
100
ms
图 1)
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6.10 Timing Diagrams
TVCC_RAMP
TCFG_DB
VCC (MIN)
VCC
TD_PG
OEn pin
50%
Internal
Power
Good
50%
SEL0, SEL1,
I2C_EN Pins
50%
图 1. Power-Up Timing
70%
30%
tBUF
SDA
tR
tF
tHDSTA
tLOW
tHIGH
70%
30%
SCL
P
S
S
P
tHDSTA
tHDDAT
tSUDAT
tSUSTA
tSUSTO
图 2. I2C Timing Diagram Definitions
12
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ZHCSHL5C –FEBRUARY 2018–REVISED SEPTEMBER 2019
6.11 Typical Characteristics
space
-71.5
-72
0.0040
0.0035
0.0030
0.0025
0.0020
0.0015
0.0010
Off Isolation at VCC = 2.4V
Off Isolation at VCC = 3.0V
Off Isolation at VCC = 3.3V
Off Isolation at VCC = 3.6V
Off Isolation at VCC = 5.5V
-72.5
-73
200 mVpp
500 mVpp
-73.5
-74
-74.5
-75
217
4217
8217 12217
Frequency (Hz)
16217
20000
0
4000
8000 12000
Frequency (Hz)
16000
20000
D001
TS3U
图 3. S3PX Total Harmonic Distortion
图 4. Off Isolation
-84
-86
-100
-102
-104
-106
-108
-110
-112
-114
-116
-118
-120
-88
-90
-92
-94
-96
-98
-100
-102
-104
-106
-108
PSR at VCC = 2.4V
Xtalk at VCC = 2.4V
Xtalk at VCC = 3.0V
Xtalk at VCC = 3.3V
Xtalk at VCC = 3.6V
Xtalk at VCC = 5.5V
PSR at VCC = 3.0V
PSR at VCC = 3.3V
PSR at VCC = 3.6V
PSR at VCC = 5.5V
0
4000
8000 12000
Frequency (Hz)
16000
20000
0
4000
8000 12000
Frequency (Hz)
16000
20000
TS3U
TS3U
图 5. Power Supply Rejection
图 6. Crosstalk
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7 Parameter Measurement Information
TS3USBCA420
MIC_GND1/Ln1
SBU1
+
VIN1
IO1
-
MIC_GND2/Ln2
LnAp
SBU2
IO2
+
VIN2
-
RL = 50 ꢀ
3.3 V
LnAn
LnBp
LnBn
I2C_EN
SEL0/SDA
SEL1/SCL
RL = 50 ꢀ
RL = 50 ꢀ
OEn
RL = 50 ꢀ
LnCp
LnCn
3.3 V
RL = 50 ꢀ
VCC
GND
RL = 50 ꢀ
VIN1 = VIN2 = 0 V
IO1 = IO2 = 75 mA
RON_AGND1 = VIN1/IO1
RON_AGND2 = VIN2/IO2
Copyright © 2018, Texas Instruments Incorporated
图 7. ON-State Resistance for the Analog Audio GND (RON_AGND
)
14
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ZHCSHL5C –FEBRUARY 2018–REVISED SEPTEMBER 2019
Parameter Measurement Information (接下页)
VPU
RPU
TS3USBCA420
MIC_GND1/Ln1
SBU1
+
-
CL
VIN1
MIC_GND2/Ln2
LnAp
SBU2
+
-
VIN2
IO1
3.3 V
LnAn
LnBp
LnBn
I2C_EN
IO2
SEL0/SDA
3.3 V
SEL1/SCL
OEn
RL = 50 ꢀ
RL = 50 ꢀ
LnCp
LnCn
3.3 V
VCC
GND
RL = 50 ꢀ
RL = 50 ꢀ
VIN1 = VIN2 = 3.3 V
IO1 = 40 mA
IO2 = -40 mA
VPU = 3.3 V, RPU = 1.5K, CL = 50 pF
RON_HS1 = VIN1/IO1
RON_HS2 = VIN2/IO2
Copyright © 2018, Texas Instruments Incorporated
图 8. ON-State Resistance for High-Speed Data Paths (RON_HS
)
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Parameter Measurement Information (接下页)
Network Analyzer
Port 2
Port 1
50 ꢀ Terminations
TS3USBCA420
MIC_GND1
SBU1
MIC_GND2
LnAp
SBU2
3.3 V
3.3 V
LnAn
LnBp
LnBn
I2C_EN
SEL0/SDA
SEL1/SCL
OEn
RL = 50 ꢀ
RL = 50 ꢀ
LnCp
LnCn
3.3 V
RL = 50 ꢀ
VCC
GND
RL = 50 ꢀ
C = -1/[Œf.Im(Zdiff)]
Zdiff = 100(1+SDD11)/(1-SDD11)
f = 500 MHz
图 9. ON-State and OFF-State Output Capacitance for High-Speed Data Paths (CON_HS, COFF_HS
)
16
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ZHCSHL5C –FEBRUARY 2018–REVISED SEPTEMBER 2019
Parameter Measurement Information (接下页)
TS3USBCA420
Spectrum Analyzer
MIC_GND1Ln1
SBU1
VO
RL = 50 ꢀ
MIC_GND2/Ln2
LnAp
SBU2
3.3 V
I2C_EN
RL = 50 ꢀ
SEL0/SDA
LnAn
LnBp
LnBn
DC Power
Supply Source
SEL1/SCL
OEn
RL = 50 ꢀ
R
RL = 50 ꢀ
3.3 V 200 mVpp
VCC
RL = 50 ꢀ
LnCp
LnCn
AWG
VN = 400 mVpp
RL = 50 ꢀ
f = 217, 1 K, 20 K
GND
RL = 50 ꢀ
PSR (dB) = 20*log(VO/VN)
Copyright © 2018, Texas Instruments Incorporated
图 10. Power Supply Rejection (PSR)
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Parameter Measurement Information (接下页)
Audio Analyzer
RS = 600 ꢀ
TS3USBCA420
MIC_GND1/Ln1
SBU1
MIC_GND2/Ln2
LnAp
SBU2
3.3 V
I2C_EN
RL = 50 ꢀ
SEL0/SDA
LnAn
LnBp
LnBn
SEL1/SCL
OEn
RL = 50 ꢀ
3.3 V
RL = 50 ꢀ
VCC
RL = 50 ꢀ
LnCp
LnCn
RL = 50 ꢀ
GND
RL = 50 ꢀ
Copyright © 2018, Texas Instruments Incorporated
图 11. Total Harmonic Distortion (THD)
18
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ZHCSHL5C –FEBRUARY 2018–REVISED SEPTEMBER 2019
Parameter Measurement Information (接下页)
XTALK_MICGND = S43
Network Analyzer
Port 2
Port 4
Port 1
50ꢀ Terminations
Port 3
TS3USBCA420
MIC_GND1/Ln1
SBU1
MIC_GND2/Ln2
LnAp
SBU2
RL = 50 ꢀ
3.3 V
LnAn
LnBp
LnBn
I2C_EN
SEL0/SDA
RL = 50 ꢀ
SEL1/SCL
OEn
RL = 50 ꢀ
RL = 50 ꢀ
LnCp
LnCn
3.3 V
RL = 50 ꢀ
VCC
GND
RL = 50 ꢀ
Copyright © 2018, Texas Instruments Incorporated
图 12. Crosstalk Between MIC and AGND (XTALKMICGND
)
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Parameter Measurement Information (接下页)
ISOOFF_MICGND1 = S31
ISOOFF_MICGND2 = S42
Network Analyzer
Port 2
Port 4
Port 1
50ꢀ Terminations
Port 3
TS3USBCA420
MIC_GND1/Ln1
SBU1
MIC_GND2/Ln2
LnAp
SBU2
RL = 50 ꢀ
LnAn
LnBp
LnBn
I2C_EN
SEL0/SDA
RL = 50 ꢀ
SEL1/SCL
OEn
RL = 50 ꢀ
RL = 50 ꢀ
LnCp
LnCn
3.3 V
RL = 50 ꢀ
VCC
GND
RL = 50 ꢀ
Copyright © 2018, Texas Instruments Incorporated
图 13. OFF Isolation (ISOOFF_MICGND
)
20
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Parameter Measurement Information (接下页)
VPU
VPU = 1.8 V, RPU = 2.1 K, CL = 50 pF
RPU
TS3USBCA420
MIC_GND1/Ln1
SBU1
VO
+
-
CL
VS1
MIC_GND2/Ln2
LnAp
SBU2
+
-
VS2
RL = 50 ꢀ
LnAn
LnBp
LnBn
I2C_EN
SEL0/SDA
RL = 50 ꢀ
SEL1/SCL
OEn
RL = 50 ꢀ
RL = 50 ꢀ
LnCp
LnCn
3.3 V
VCC
GND
RL = 50 ꢀ
RL = 50 ꢀ
3.3 V
SEL[1:0]
3.3 V
SEL[1:0]
50%
50%
0 V
VS1 = 3.3 V
VS2 = 0 V
0 V
VS1 = 3.3 V
VS2 = 0 V
VO
90%
10%
VO
tON_MICGND
tOFF_MICGND
Copyright © 2018, Texas Instruments Incorporated
图 14. Turn-ON time (tON) and Turn-OFF time (tOFF) for MIC and AGND
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Parameter Measurement Information (接下页)
VPU
VPU = 1.8 V, RPU = 2.1K, CL = 50 pF
RPU
TS3USBCA420
ZS = 50 ꢀ
VS1
MIC_GND1/Ln1
SBU1
CL
VS2
ZS = 50 ꢀ
MIC_GND2/Ln2
LnAp
SBU2
RL = 50 ꢀ
LnAn
LnBp
LnBn
I2C_EN
SEL0/SDA
RL = 50 ꢀ
VO1
SEL1/SCL
OEn
RL = 50 ꢀ
VO2
RL = 50 ꢀ
LnCp
LnCn
3.3 V
VCC
GND
RL = 50 ꢀ
RL = 50 ꢀ
50%
50%
SEL[1:0]
SEL[1:0]
VS1 = 3.3 V
VS2 = 0 V
VS1 = 3.3 V
VS2 = 0 V
VO1
90%
10%
VO1
tON_HS
tOFF_HS
Copyright © 2018, Texas Instruments Incorporated
图 15. Turn-ON time (tON) and Turn-OFF time (tOFF) for High-Speed Data Paths
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Parameter Measurement Information (接下页)
VPU
VPU = 1.8 V, RPU = 2.1K, CL = 50 pF
RPU
TS3USBCA420
MIC_GND1/Ln1
SBU1
VO
+
-
CL
VS1
MIC_GND2/Ln2
LnAp
SBU2
+
-
VS2
RL = 50 ꢀ
LnAn
LnBp
LnBn
I2C_EN
SEL0/SDA
RL = 50 ꢀ
VO1
SEL1/SCL
OEn
RL = 50 ꢀ
VO2
RL = 50 ꢀ
LnCp
LnCn
3.3 V
VCC
GND
RL = 50 ꢀ
RL = 50 ꢀ
3.3 V
SEL[1:0]
0 V
VS1 = 3.3 V
VS2 = 0 V
VO1
10%
10%
tBBM
VO
Copyright © 2018, Texas Instruments Incorporated
图 16. Break-Before-Make Time (tBBM
)
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8 Detailed Description
8.1 Overview
The TS3USBCA4 is a passive 4:1 (TS3USBCA420) and 3:1 (TS3USBCA410) MUX. It supports differential or
single-ended signals on the SBU1/SBU2 terminals of a USB Type-C connected to different interfaces. The
signals can be DisplayPort auxiliary (AUX), analog audio MIC and AGND, PCIe differential clock, or any other
supported generic differential or single-ended signals.
The audio path features ultra-low ON-state resistance (RON), low crosstalk and excellent total harmonic distortion
(THD). The break-before-make feature prevents signal distortion during signal transfer from one channel to
another. The high-speed paths support bandwidth as high as 500 MHz to provide adequate support for
DisplayPort AUX, PCIe clock, and other similar signals. Together with low power consumption, these features
make this device suitable for portable audio applications.
The TS3USBCA4 supports operation from a wide VCC range between 2.4 V and 5.5 V, which gives the system
designer the flexibility of powering the device from various sources, such as a regulator, a single-cell battery, or
VBUS. The TS3USBCA4 provides options for both commercial and industrial temperature ranges.
8.2 Functional Block Diagram
TS3USBCA420
VBUS
VBUS
SBU1
MIC_GND1/Ln1
SBU1
D-
D+
D-
Audio Codec,
UART, I2C
D+
MIC_GND2/Ln2
LnAp
SBU2
SBU2
VBUS
VBUS
DP AUX, Debug,
PCIe CK, UART,
I2C
USB Type-C
LnAn
LnBp
LnBn
I2C_EN
DP AUX, Debug,
PCIe CK, UART,
I2C
Logic
Control
SEL0/SDA
SEL1/SCL
LnCp
LnCn
OEn
DP AUX, Debug,
PCIe CK, UART,
I2C
VCC
GND
Copyright © 2018, Texas Instruments Incorporated
图 17. Functional Block Diagram
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8.3 Feature Description
8.3.1 Analog Audio Path
The TS3USBCA4 supports analog audio switching between the SBU1 and SBU2 pins on one side of the switch.
It supports the MIC_GND1 and MIC_GND2 pins on the other side of the switch. This audio path has an ultra-low
ON resistance and low total harmonic distortion for better audio performance.
The MIC and AGND paths are identical by design, with both providing ultra-low RON. The audio path does not
support flipping MIC and AGND. The audio codec should provide this function.
8.3.2 High-Speed Paths
The TS3USBCA4 supports three (TS3USBCA420) or two (TS3USBCA410) high-speed paths between the SBU1
and SBU2 pins on one side of the switch. The LnAp/LnAn, LnBp/LnBn or LnCp/LnCn pins on the other side of
the switch. The high-speed paths are identical by design. All high-speed paths have a 500-MHz bandwidth, a low
ON-state resistance, and low additive random jitter for signal integrity. For different USB Type-C plug
orientations, the polarity of each high-speed lane can be flipped through the I2C interface in TS3USBCA420, or
though either the I2C interface or pin control in TS3USBCA410.
8.3.3 3-level Input
The 3-level input pin I2C_EN is used to enable the I2C interface and to choose between two I2C slave addresses
to avoid address conflict. The settings for the three levels are shown in 表 1.
表 1. 3-Level Control Pin Settings
Level
I2C_EN Pin Settings
Tied directly to GND or left floating
Tied directly to VCC/2
Configuration Mode
L
M
H
Pin-configuration mode
I2C-configuration mode with ADDR0
I2C-configuration mode with ADDR1
Tied directly to VCC
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8.4 Device Functional Modes
Switch selection and flipping can be controlled either through the I2C interface in I2C-configuration mode or
through the control pins (SEL0, SEL1, and FLIP when applicable) in pin-configuration mode, according to 表 1.
表 2 and 表 3 show the configuration truth table for TS3USBCA420 and TS3USBCA410, respectively. Note in
TS3USBCA420 the flipping capability is available only in I2C-configuration mode.
表 2. TS3USBCA420 Switch Configuration Truth Table(1)
{SWSEL[1:0], FLIPSEL}
(I2C-Configuration Mode)
{SEL1, SEL0}
(Pin-Configuration Mode)
Input Pin
Output Pin
SBU1
SBU2
SBU1
SBU2
SBU1
SBU2
SBU1
SBU2
SBU1
SBU2
SBU1
SBU2
SBU1
SBU2
SBU1
SBU2
LnBp
LnBn
000
001
010
011
100
101
110
111
LL
LH
HL
HH
LnBn
LnBp
MIC_GND1/Ln1
MIC_GND2/Ln2
MIC_GND1/Ln1
MIC_GND2/Ln2
LnCp
LnCn
LnCp
LnCn
LnAp
LnAn
LnAn
LnAp
(1) For normal operation, drive OEn low (and in I2C mode set DEVICE_ENABLE = 1’b1). Driving the OEn pin high (or in I2C mode setting
DEVICE_ENABLE = 1’b0) disables the switch. Note: The ports which are not selected by the control lines are in high impedance state
表 3. TS3USBCA410 Switch Configuration Truth Table(1)
{SWSEL[1:0], FLIPSEL}
(I2C-Configuration Mode)
{SEL1, SEL0, FLIP}
(Pin-Configuration Mode)
Input Pin
Output Pin
SBU1
SBU2
SBU1
SBU2
SBU1
SBU2
SBU1
SBU2
SBU1
SBU2
SBU1
SBU2
SBU1
SBU2
SBU1
SBU2
LnBp
LnBn
000
001
010
011
100
101
110
111
LLL
LLH
LHL
LHH
HLL
HLH
HHL
HHH
LnBn
LnBp
MIC_GND1/Ln1
MIC_GND2/Ln2
MIC_GND1/Ln1
MIC_GND2/Ln2
LnAp
LnAn
LnAn
LnAp
(1) For normal operation, drive OEn low (and in I2C mode set DEVICE_ENABLE = 1’b1). Driving the OEn pin high (or in I2C mode setting
DEVICE_ENABLE = 1’b0) disables the switch. Note: The ports which are not selected by the control lines are in high impedance state
26
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In addition to switch control, the I2C-configuration mode also allows enabling and disabling the device through
the DEVICE_ENABLE register. 表 4 shows the details.
表 4. TS3USBCA4 Enable/Disable Truth Table
OEn
L
DEVICE_ENABLE
Device Behavior
Device is shut down with IOFF_I2C
.
On-chip bandgap and IO buffers are still on.
I2C is functional.
0
1
X
L
Normal operation.
Device is under reset with IOFF_OEN
.
H
On-chip bandgap and IO buffers are off.
I2C is not functional.
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8.5 Programming
The TS3USBCA4 can be controlled using I2C. The SCL and SDA terminals are used for I2C clock and I2C data
respectively.
表 5. TS3USBCA4 I2C Slave Address
ADDR
ADDR0
ADDR1
Bit 7 (MSB)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0 (W/R)
1
1
0
0
1
1
1
1
1
1
0
0
0
1
0/1
0/1
The following procedure should be followed to write to TS3USBCA4 I2C registers:
1. The master initiates a write operation by generating a start condition (S), followed by the TS3USBCA4 7-bit
address and a zero-value “W/R” bit to indicate a write cycle
2. The TS3USBCA4 acknowledges the address cycle.
3. The master presents the sub-address (I2C register within TS3USBCA4) to be written, consisting of one byte
of data, MSB-first.
4. The TS3USBCA4 acknowledges the sub-address cycle.
5. The master presents the first byte of data to be written to the I2C register.
6. The TS3USBCA4 acknowledges the byte transfer.
7. The master may continue presenting additional bytes of data to be written, with each byte transfer completing
with an acknowledge from the TS3USBCA4.
8. The master terminates the write operation by generating a stop condition (P).
The following procedure should be followed to read the TS3USBCA4 I2C registers:
1. The master initiates a read operation by generating a start condition (S), followed by the TS3USBCA4 7-bit
address and a one-value “W/R” bit to indicate a read cycle
2. The TS3USBCA4 acknowledges the address cycle.
3. The TS3USBCA4 transmit the contents of the memory registers MSB-first starting at register 00h or last read
sub-address+1. If a write to the I2C.register occurred prior to the read, then the TS3USBCA4 shall start at the
sub-address specified in the write.
4. The TS3USBCA4 shall wait for either an acknowledge (ACK) or a not-acknowledge (NACK) from the master
after each byte transfer; the I2C master acknowledges reception of each data byte transfer.
5. If an ACK is received, the TS3USBCA4 transmits the next byte of data.
6. The master terminates the read operation by generating a stop condition (P).
The following procedure should be followed for setting a starting sub-address for I2C reads:
1. The master initiates a write operation by generating a start condition (S), followed by the TS3USBCA4 7-bit
address and a zero-value “W/R” bit to indicate a write cycle.
2. The TS3USBCA4 acknowledges the address cycle.
3. The master presents the sub-address (I2C register within TS3USBCA4) to be written, consisting of one byte
of data, MSB-first.
4. The TS3USBCA4 acknowledges the sub-address cycle.
5. The master terminates the write operation by generating a stop condition (P).
注
Upon reset, the TS3USBCA4 sub-address is always set to 0x00. The TS3USBCA4
increments the sub-address by one after each successful read or write transaction, so that
the next read transaction that does not explicitly specify the sub-address will start from the
next register.
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8.6 Register Maps
8.6.1 TS3USBCA4 Registers
Table 6 lists the memory-mapped registers for the TS3USBCA4 registers. All register offset addresses not listed
in Table 6 should be considered as reserved locations and the register contents should not be modified.
Table 6. TS3USBCA4 Registers
Offset
9h
Acronym
Revision_ID
General_1
General_2
Register Name
Section
Go
Revsion ID
Ah
Enable and FLIPSEL control
SWSEL control
Go
Bh
Go
Complex bit access types are encoded to fit into small table cells. Table 7 shows the codes that are used for
access types in this section.
Table 7. TS3USBCA4 Access Type Codes
Access Type
Read Type
R
Code
Description
R
Read
Write Type
W
W
Write
Reset or Default Value
-n
Value after reset or the default
value
8.6.1.1 Revision_ID Register (Offset = 9h) [reset = 0h]
Revision_ID is shown in Figure 18 and described in Table 8.
Return to Summary Table.
Figure 18. Revision_ID Register
7
6
5
4
3
2
1
0
RESERVED
R-0h
REVISION_ID
R-0h
Table 8. Revision_ID Register Field Descriptions
Bit
Field
Type
Reset
Description
Reserved
7-4
3-0
RESERVED
R
0h
REVISION_ID
R
0h
Silicon revision.
8.6.1.2 General_1 Register (Offset = Ah) [reset = 0h]
General_1 is shown in Figure 19 and described in Table 9.
Return to Summary Table.
Figure 19. General_1 Register
7
6
5
4
3
2
1
0
RESERVED
R-0h
DEVICE_ENAB
LE
FLIPSEL
R/W-0h
R/W-0h
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Table 9. General_1 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-2
RESERVED
R
0h
Reserved
1
DEVICE_ENABLE
R/W
R/W
0h
0h
Controls the switch enable.
0h = Disabled
1h = Enabled
0
FLIPSEL
Controls the USB-C orientation.
0h = Normal Orientation
1h = Flip orientation.
8.6.1.3 General_2 Register (Offset = Bh) [reset = 0h]
General_2 is shown in Figure 20 and described in Table 10.
Return to Summary Table.
Figure 20. General_2 Register
7
6
5
4
3
2
1
0
RESERVED
R-0h
SWSEL
R/W-0h
Table 10. General_2 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-2
1-0
RESERVED
SWSEL
R
0h
Reserved
R/W
0h
This field along with FLIPSEL controls the SBU switch connections.
0h = SBU to LnB
1h = SBU to MICGND
2h = SBU to LnC
3h = SBU to LnA
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9 Application and Implementation
注
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The SBU1 and SBU2 pins of a USB type-C connector can be re-purposed in different applications. Examples
include DisplayPort AUX, analog audio MIC and AGND, and debug signals. The TS3USBCA4 is controlled by a
micro-processor (that is, an application processor in a smartphone) that routes SBU1 and SBU2 to the desired
destination, such as a DisplayPort source or sink, an audio codec, or a processor. The TS3USBCA4 provides
cross-switch capability for different USB type-C plug orientations.
9.2 Typical Application
图 21 shows the typical application of TS3USBCA420 in I2C-configuration mode from a 3.3-V supply. The I2C
slave address is set to ADDR1. VIO_uP is the supply for the micro-processor IOs.
USB 2.0
USB Host
DP/DM
TS5USBA224
L/R
3.3V
Audio Codec
VCC
MIC_GND1/Ln1
I2C_EN
MIC_GND2/Ln2
MIC/AGND
TS3USBCA420
LnAp
LnAn
AUX
CK
DP
SBU1
SBU2
LnBp
LnBn
SBU1/SBU2
PCIe
LnCp
LnCn
OEn
Debug
SDA
SCL
I2C
GND
µP
VI2C
VIO_µP
SDA
SCL
INT_N
CC1/CC2
TUSB320
Copyright © 2018, Texas Instruments Incorporated
图 21. Application of TS3USBCA420 in I2C-Configuration Mode
图 22 shows the typical application of TS3USBCA420 in pin-configuration mode from VBUS. VIO_uP is the supply
for the micro-processor IOs.
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Typical Application (接下页)
USB 2.0
L/R
USB Host
DP/DM
VBUS
TS5USBA224
Audio Codec
VCC
MIC_GND1
MIC/AGND
I2C_EN
MIC_GND2
TS3USBCA420
LnAp
LnAn
AUX
CK
DP
SBU1
SBU2
LnBp
LnBn
SBU1/SBU2
PCIe
LnCp
LnCn
OEn
Debug
SEL0
SEL1
GND
µP
VIO_µP
ID
CC1/CC2
DIR TUSB322I
OUT3
图 22. Application of TS3USBCA420 in Pin-Configuration Mode
图 21 shows the typical application of TS3USBCA410 in I2C-configuration mode from VBAT. The I2C slave
address is set to ADDR0. VIO_uP is the supply for the micro-processor IOs.
USB 2.0
USB Host
DP/DM
TS5USBA224
L/R
VBAT
Audio Codec
VCC
MIC_GND1/Ln1
MIC/AGND
AUX
I2C_EN
MIC_GND2/Ln2
TS3USBCA410
LnAp
DP
LnAn
SBU1
SBU2
SBU1/SBU2
FLIP
LnBp
LnBn
OEn
Debug
SDA
SCL
I2C
µP
GND
VI2C VIO_µP
SDA
SCL
INT_N
CC1/CC2
TUSB320
Copyright © 2018, Texas Instruments Incorporated
图 23. Application of TS3USBCA410 in I2C-Configuration Mode
图 22 shows the typical application of TS3USBCA410 in pin-configuration mode from VBUS. VIO_uP is the supply
for the micro-processor IOs.
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Typical Application (接下页)
USB 2.0
L/R
USB Host
DP/DM
TS5USBA224
VBUS
Audio Codec
VCC
MIC_GND1
MIC/AGND
AUX
I2C_EN
MIC_GND2
TS3USBCA410
LnAp
LnAn
DP
SBU1
SBU2
SBU1/SBU2
FLIP
LnBp
LnBn
OEn
Debug
SEL0
SEL1
µP
GND
VIO_µP
ID
DIR
CC1/CC2
TUSB322I
OUT3
图 24. Application of TS3USBCA410 in Pin-Configuration Mode
9.2.1 Design Requirements
Design requirements of USB type-C and other relevant standards (DisplayPort, analog audio, etc.) must be
followed.
9.2.2 Detailed Design Procedure
The design procedure starts with the choice of supply. TS3USBCA4 wide supply range from 2.4 V to 5.5 V gives
the designer flexibility when selecting a supply. Examples include, but are not limited to, a single-cell battery, a
3.3-V regulator, or VBUS. The designer must account for the parametric variation of TS3USBCA4 with supply
range, the supply range of other components in the system, the IO voltage levels of companion devices, and
cost. For example, a regulated 3.3-V VCC has the advantage of smaller variation of TS3USBCA4 performance
compared to a single-cell batter between 2.7 V and 4.3 V. This regulator may add to the system cost and board
area.
The next step in the design procedure is to choose between I2C- and pin-configuration mode. The I2C-
configuration mode is preferred because it reduces the number of IOs needed from the micro-processor. Note
that in TS3USBCA420 the flip functionality is only available in the I2C-configuration mode. The designer can
choose from two I2C slave addresses through pin-strapping of I2C_EN to avoid address conflict. The IOs of
TS3USBCA4 have well-controlled VIH and VIL and are supposed to work with a wide range of IO voltage levels of
the micro-processor. However, the designer needs to check the compatibility of the IOs between the micro-
processor and TS3USBCA4, and insert level translators when necessary.
In I2C-configuration mode, when it is necessary to set I2C_EN to the middle level to avoid slave address conflict,
it is desirable to use as high a resistor value as possible for the resistor divider to minimize the static current
through the resistor divider. However, the designer needs to take into account the resistor tolerance and the
effect of the on-chip pull-down resistor to ensure a satisfactory voltage margin for VIM of the I2C_EN pin.
It should be noted that the bandwidth of the high-speed lanes is defined with the audio channel open. Due to the
low RON of the audio channel, big parasitic capacitance exists between the audio output port and the SBU port.
The load (capacitive and/or resistive) at the audio output port may significantly impact the bandwidth of the high-
speed lanes. If bandwidth is importance, the audio channel is preferred. If certain high-speed signals have to go
through the high-speed lanes, care should be taken to minimize the load at the audio output port, including the
traces.
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Typical Application (接下页)
9.2.3 Application Curves
300
250
200
150
100
50
0
20
30
40
50
60
70
80
90
100
Contact Resistance (mW)
D001
图 25. Max Current vs Contact Resistance
10 Power Supply Recommendations
The TS3USBCA4 is designed to operate from a VCC range between 2.4 V and 5.5 V. The supply is
recommended to be decoupled to ground via two de-coupling capacitors of 0.1 µF and 1 µF placed as close as
possible to the TS3USBCA4. To ensure a POR trip during a power-down and power-on event the power supply
should follow the minimum and maximum VCC rise and fall times specified in the electrical specifications section.
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11 Layout
11.1 Layout Guidelines
•
•
•
The VCC pin must have de-coupling capacitors placed as closely to the device as possible. Typically
recommended capacitors are a 0.1-µF and a 1-µF capacitor.
The total resistance from SBU1 and SBU2 pins of the type-C connector to the MIC_GND1 and MIC_GND2
pins of the audio codec should be kept low to avoid degrading the crosstalk performance.
Route the I2C and digital signals away from the audio signals to prevent coupling onto the audio lines.
11.2 Layout Example
图 26 shows a layout example of TS3USBCA420.
1
2
3
4
12
11
10
9
I2C_EN
SBU1
SBU2
GND
Via to VCC plane
Via to GND plane
图 26. Layout Example
版权 © 2018–2019, Texas Instruments Incorporated
35
TS3USBCA4
ZHCSHL5C –FEBRUARY 2018–REVISED SEPTEMBER 2019
www.ti.com.cn
12 器件和文档支持
12.1 接收文档更新通知
要接收文档更新通知,请导航至 ti.com. 上的器件产品文件夹。单击右上角的通知我进行注册,即可每周接收产品
信息更改摘要。有关更改的详细信息,请查看任何已修订文档中包含的修订历史记录。
12.2 支持资源
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.3 商标
E2E is a trademark of Texas Instruments.
USB Type-C is a trademark of USB Implementers Forum.
12.4 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
12.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更,恕不另行通知,且
不会对此文档进行修订。如需获取此数据表的浏览器版本,请查阅左侧的导航栏。
36
版权 © 2018–2019, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TS3USBCA410IRSVR
TS3USBCA410IRSVT
TS3USBCA410RSVR
TS3USBCA410RSVT
TS3USBCA420IRSVR
TS3USBCA420IRSVT
TS3USBCA420RSVR
TS3USBCA420RSVT
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
UQFN
UQFN
UQFN
UQFN
UQFN
UQFN
UQFN
UQFN
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
16
16
16
16
16
16
16
16
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
NIPDAUAG
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 85
-40 to 85
0 to 70
410
410
410
410
420
420
420
420
NIPDAUAG
NIPDAUAG
NIPDAUAG
NIPDAUAG
NIPDAUAG
NIPDAUAG
NIPDAUAG
0 to 70
-40 to 85
-40 to 85
0 to 70
0 to 70
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
16-Jun-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TS3USBCA410IRSVR
TS3USBCA410IRSVT
TS3USBCA410RSVR
TS3USBCA410RSVT
TS3USBCA420IRSVR
TS3USBCA420IRSVT
TS3USBCA420RSVR
TS3USBCA420RSVT
UQFN
UQFN
UQFN
UQFN
UQFN
UQFN
UQFN
UQFN
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
16
16
16
16
16
16
16
16
3000
250
178.0
178.0
178.0
178.0
178.0
178.0
178.0
178.0
13.5
13.5
13.5
13.5
13.5
13.5
13.5
13.5
2.1
2.1
2.1
2.1
2.1
2.1
2.1
2.1
2.9
2.9
2.9
2.9
2.9
2.9
2.9
2.9
0.75
0.75
0.75
0.75
0.75
0.75
0.75
0.75
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
3000
250
3000
250
3000
250
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
16-Jun-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TS3USBCA410IRSVR
TS3USBCA410IRSVT
TS3USBCA410RSVR
TS3USBCA410RSVT
TS3USBCA420IRSVR
TS3USBCA420IRSVT
TS3USBCA420RSVR
TS3USBCA420RSVT
UQFN
UQFN
UQFN
UQFN
UQFN
UQFN
UQFN
UQFN
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
16
16
16
16
16
16
16
16
3000
250
189.0
189.0
189.0
189.0
189.0
189.0
189.0
189.0
185.0
185.0
185.0
185.0
185.0
185.0
185.0
185.0
36.0
36.0
36.0
36.0
36.0
36.0
36.0
36.0
3000
250
3000
250
3000
250
Pack Materials-Page 2
PACKAGE OUTLINE
RSV0016A
UQFN - 0.55 mm max height
S
C
A
L
E
5
.
0
0
0
ULTRA THIN QUAD FLATPACK - NO LEAD
1.85
1.75
A
B
PIN 1 INDEX AREA
2.65
2.55
C
0.55
0.45
SEATING PLANE
0.05 C
0.05
0.00
2X 1.2
SYMM
℄
(0.13) TYP
5
8
0.45
0.35
15X
4
9
SYMM
℄
2X 1.2
12X 0.4
1
0.25
16X
12
0.15
0.07
0.05
C A B
13
16
0.55
0.45
PIN 1 ID
(45° X 0.1)
4220314/C 02/2020
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
www.ti.com
EXAMPLE BOARD LAYOUT
RSV0016A
UQFN - 0.55 mm max height
ULTRA THIN QUAD FLATPACK - NO LEAD
SYMM
℄
(0.7)
16
SEE SOLDER MASK
DETAIL
13
12
16X (0.2)
1
SYMM
℄
12X (0.4)
(2.4)
(R0.05) TYP
9
4
15X (0.6)
5
8
(1.6)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 25X
0.05 MIN
ALL AROUND
0.05 MAX
ALL AROUND
METAL UNDER
SOLDER MASK
METAL EDGE
EXPOSED METAL
SOLDER MASK
OPENING
EXPOSED
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4220314/C 02/2020
NOTES: (continued)
3. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271).
www.ti.com
EXAMPLE STENCIL DESIGN
RSV0016A
UQFN - 0.55 mm max height
ULTRA THIN QUAD FLATPACK - NO LEAD
(0.7)
16
13
16X (0.2)
1
12
SYMM
℄
12X (0.4)
(2.4)
(R0.05) TYP
4
9
15X (0.6)
5
8
SYMM
℄
(1.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 MM THICK STENCIL
SCALE: 25X
4220314/C 02/2020
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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