TS3V340PWR [TI]
QUAD SPDT HIGH-BANDWIDTH VIDEO SWITCH WITH LOW AND FLAT ON-STATE RESISTANCE; QUAD SPDT高带宽视频低收入和FLAT开关导通电阻
| 型号： | TS3V340PWR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | QUAD SPDT HIGH-BANDWIDTH VIDEO SWITCH WITH LOW AND FLAT ON-STATE RESISTANCE |
| 文件： | 总23页 (文件大小：511K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ꢀꢁ ꢂꢃ ꢂ ꢄꢅ
ꢆ ꢇꢈꢉ ꢁꢊ ꢉꢀ ꢋꢌ ꢍꢋ ꢎꢏꢈꢐꢉꢑ ꢌ ꢉꢀ ꢋ ꢃꢌ ꢉꢒꢓ ꢁ ꢑꢌ ꢀꢔ ꢋ
ꢑ ꢌꢀ ꢋ ꢕ ꢓꢑ ꢈꢐꢉ ꢖ ꢕꢈꢀ ꢓ ꢐꢎꢁꢀꢈꢀ ꢒ ꢗꢒꢁ ꢌ ꢁꢀꢈ ꢐꢔ ꢒ
SCDS172A - JULY 2004 − REVISED DECEMBER 2004
D, DBQ, DGV, OR PW PACKAGE
(TOP VIEW)
D
Low Differential Gain and Phase
(D = 0.2%, D = 0.1° Typ)
G
P
D
D
D
D
Wide Bandwidth (B = 500 MHz Typ)
W
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
EN
S1
S2
D
S1
S2
D
IN
CC
Low Crosstalk (X
= −80 dB Typ)
TALK
S1
S2
D
S1
S2
D
A
A
A
B
B
B
Bidirectional Data Flow, With Near-Zero
Propagation Delay
D
D
Low and Flat ON-State Resistance
D
(r = 3 Ω Typ, r
= 1 Ω Typ)
C
on
on(flat)
C
D
V Operating Range From 3 V to 3.6 V
CC
GND
C
D
I
Supports Partial-Power-Down Mode
off
Operation
D
D
D
Data and Control Inputs Provide
Undershoot Clamp Diode
RGY PACKAGE
(TOP VIEW)
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
1
16
ESD Performance Tested Per JESD 22
− 2000-V Human-Body Model
(A114-B, Class II)
15
14
13
12
11
10
S1
S2
D
2
EN
S1
A
3
A
D
4
S2
− 1000-V Charged-Device Model (C101)
A
D
S1
S2
D
5
D
B
D
D
Suitable for Both RGB and Composite
Video Switching
6
S1
B
C
7
S2
B
C
8
9
description/ordering information
The TI video switch TS3V340 is a 4-bit 1-of-2
multiplexer/demultiplexer
with
a
single
switch-enable (EN) input. When EN is low, the switch is enabled, and the D port is connected to the S port. When
EN is high, the switch is disabled, and the high-impedance state exists between the D and S ports. The select
(IN) input controls the data path of the multiplexer/demultiplexer.
Low differential gain and phase makes this switch ideal for composite and RGB video applications. The device
has a wide bandwidth and low crosstalk, making it suitable for high-frequency applications as well.
ORDERING INFORMATION
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
†
T
A
PACKAGE
QFN − RGY
SOIC − D
Tape and reel
Tube
TS3V340RGYR
TS3V340D
TF340
TS3V340
TF340
Tape and reel
TS3V340DR
TS3V340DBQR
TS3V340PW
TS3V340PWR
SSOP (QSOP) − DBQ Tape and reel
−40°C to 85°C
Tube
TSSOP − PW
TF340
Tape and reel
TVSOP − DGV
Tape and reel
TS3V340DGVR
TF340
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines
are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
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Copyright 2004, Texas Instruments Incorporated
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁ ꢂꢃꢂ ꢄ ꢅ
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ꢑꢌ ꢀ ꢋ ꢕ ꢓꢑ ꢈ ꢐꢉ ꢖꢕ ꢈꢀ ꢓ ꢐꢎꢁ ꢀꢈꢀ ꢒ ꢗꢒ ꢁ ꢌ ꢁ ꢀꢈꢐꢔ ꢒ
SCDS172A - JULY 2004 − REVISED DECEMBER 2004
description/ordering information (continued)
This device is fully specified for partial-power-down applications using I . The I feature ensures that
off
off
damaging current will not backflow through the device when it is powered down. This switch maintains isolation
during power off.
To ensure the high-impedance state during power up or power down, EN should be tied to V
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
through a pullup
CC
FUNCTION TABLE
INPUTS
INPUT/OUTPUT
D
FUNCTION
EN
IN
L
L
L
S1
S2
Z
D port = S1 port
D port = S2 port
Disconnect
H
X
H
PIN DESCRIPTION
PIN NAME
DESCRIPTION
Analog video I/Os
Analog video I/Os
Select input
S1, S2
D
IN
EN
Switch-enable input
2
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ꢑ ꢌꢀ ꢋ ꢕ ꢓꢑ ꢈꢐꢉ ꢖ ꢕꢈꢀ ꢓ ꢐꢎꢁꢀꢈꢀ ꢒ ꢗꢒꢁ ꢌ ꢁꢀꢈ ꢐꢔ ꢒ
SCDS172A - JULY 2004 − REVISED DECEMBER 2004
PARAMETER DEFINITIONS
DESCRIPTION
Resistance between the D and S ports, with the switch in the ON state
PARAMETER
R
ON
OZ
OS
I
Output leakage current measured at the D and S ports, with the switch in the OFF state
Short-circuit current measured at the I/O pins
I
V
IN
Voltage at IN
V
EN
Voltage at EN
C
Capacitance at the control (EN, IN) inputs
IN
C
Capacitance at the analog I/O port when the switch is OFF
Capacitance at the analog I/O port when the switch is ON
Minimum input voltage for logic high for the control (EN, IN) inputs
Maximum input voltage for logic low for the control (EN, IN) inputs
I/O and control (EN, IN) inputs diode clamp voltage
Voltage applied to the D or S pins when D or S is the switch input
Voltage applied to the D or S pins when D or S is the switch output
Input high leakage current of the control (EN, IN) inputs
Input low leakage current of the control (EN, IN) inputs
Current into the D or S pins when D or S is the switch input
Current into the D or S pins when D or S is the switch output
OFF
C
ON
V
IH
V
IL
V
IK
V
I
V
O
I
IH
I
IL
I
I
I
O
I
Output leakage current measured at the D or S ports, with V
= 0
Propagation delay measured between S1 and S2 under the specified conditions, measured from 50% of the digital
off
CC
x
x
t
pds
input to 90% of the analog output
B
W
Frequency response of the switch in the ON state, measured at −3 dB
Unwanted signal coupled from channel to channel. Measured in −dB. X
crosstalk.
= 20 log V /V . This is a nonadjacent
O I
TALK
X
TALK
O
OFF isolation is the resistance (measured in −dB) between the input and output with the switch OFF.
IRR
Magnitude variation between analog input and output pins when the switch is ON and the DC offset of composite video
signal varies at the analog input pin. In NTSC standard, the frequency of the video signal is 3.58 MHz, and DC offset is
from 0 to 0.714 V.
D
G
Phase variation between analog input and output pins when the switch is ON and the DC offset of composite video
signal varies at the analog input pin. In NTSC standard, the frequency of the video signal is 3.58 MHz, and DC offset is
from 0 to 0.714 V.
D
P
I
Static power-supply current
CC
I
Variation of I for a change in frequency in the control (EN, IN) inputs
CC
CCD
∆I
Increase in supply current for each control input that is at the specified voltage level, rather than V
or GND
CC
CC
3
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ꢑꢌ ꢀ ꢋ ꢕ ꢓꢑ ꢈ ꢐꢉ ꢖꢕ ꢈꢀ ꢓ ꢐꢎꢁ ꢀꢈꢀ ꢒ ꢗꢒ ꢁ ꢌ ꢁ ꢀꢈꢐꢔ ꢒ
SCDS172A - JULY 2004 − REVISED DECEMBER 2004
functional diagram (positive logic)
4
2
3
S1
S2
D
A
A
A
7
5
6
D
B
S1
S2
B
B
9
11
10
S1
S2
D
C
C
C
12
14
13
D
D
S1
S2
D
D
1
IN
Control
Logic
15
EN
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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ꢑ ꢌꢀ ꢋ ꢕ ꢓꢑ ꢈꢐꢉ ꢖ ꢕꢈꢀ ꢓ ꢐꢎꢁꢀꢈꢀ ꢒ ꢗꢒꢁ ꢌ ꢁꢀꢈ ꢐꢔ ꢒ
SCDS172A - JULY 2004 − REVISED DECEMBER 2004
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4.6 V
CC
Control input voltage range, V (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Switch I/O voltage range, V (see Notes 1, 2, and 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Control input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
IN
I/O
IK IN
I/O port clamp current, I
(V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
I/OK I/O
ON-state switch current, I (see Note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA
Continuous current through V
I/O
or GND terminals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA
CC
Package thermal impedance, θ (see Note 5): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73°C/W
JA
(see Note 5): DBQ package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90°C/W
(see Note 5): DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120°C/W
(see Note 5): PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108°C/W
(see Note 6): RGY package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39°C/W
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltages are with respect to ground, unless otherwise specified.
2. The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
3. V and V are used to denote specific conditions for V
I/O
.
I
O
4. I and I are used to denote specific conditions for I .
I
O
I/O
5. The package thermal impedance is calculated in accordance with JESD 51-7.
6. The package thermal impedance is calculated in accordance with JESD 51-5.
recommended operating conditions (see Note 7)
MIN
3
MAX
3.6
5.5
0.8
5.5
85
UNIT
V
V
V
V
V
Supply voltage
CC
IH
IL
High-level control input voltage (EN, IN)
Low-level control input voltage (EN, IN)
Analog I/O voltage
2
V
0
V
0
V
O
T
A
Operating free-air temperature
−40
°C
NOTE 7: All unused control inputs of the device must be held at V
or GND to ensure proper device operation. Refer to the TI application report,
CC
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
5
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SCDS172A - JULY 2004 − REVISED DECEMBER 2004
electrical characteristics over recommended operating free-air temperature range,
†
V
= 3.3 V ꢀ 0.3 V (unless otherwise noted)
CC
‡
PARAMETER
TEST CONDITIONS
= −18 mA
MIN TYP
MAX
−1.8
1
UNIT
V
V
EN, IN
EN, IN
EN, IN
V
V
V
V
V
V
V
V
V
= 3 V,
I
IN
IK
CC
CC
CC
CC
CC
CC
CC
CC
CC
I
I
I
I
I
I
= 3.6 V,
= 3.6 V,
= 3.6 V,
= 3.6 V,
= 0,
V
V
V
V
V
and V
and V
= 5.5 V
= GND
µA
µA
µA
mA
µA
mA
µA
IH
IN
IN
O
EN
1
IL
EN
§
¶
= 0 to 5.5 V,
= 0.5 V
V = 0,
I
Switch OFF
Switch ON
1
OZ
,
V = 0,
I
50
OS
off
O
CC
= 0 to 5.5 V,
= 0,
V = 0
I
1
1.5
30
O
= 3.6 V,
= 3.6 V,
= 3.6 V,
I
Switch ON or OFF
0.7
CC
I/O
∆I
CC
EN, IN
One input at 3 V,
Other inputs at V
CC
or GND
V
V
= GND,
mA/
MHz
EN
input switching 50% duty cycle
I
0.35
CCD
D and S ports open,
IN
C
C
C
r
EN, IN
D port
S port
V
or V = 5.5 V,
3.3 V or 0,
f = 1 MHz
2.5
5.5
3.5
3.5
7
pF
pF
pF
Ω
IN
IN
EN
V = 5.5 V, 3.3 V, or 0, f = 1 MHz,
I
Outputs open,
Switch OFF
Switch ON
OFF
5
V = 5.5 V, 3.3 V, or 0, f = 1 MHz,
I
Outputs open,
10.5
3
14
6
ON
#
V = 1 V,
I
I
I
= 13 mA
= 26 mA
O
V
CC
= 3 V
on
V = 2 V,
I
3
6
O
||
V
CC
= 3.3 V,
V = 0 to V
I
,
I
O
= 26 mA
1
Ω
r
CC
on(flat)
†
‡
§
¶
#
V , V , I , and I refer to I/O pins.
I
O
I
O
All typical values are at V
= 3.3 V (unless otherwise noted), T = 25°C.
OZ
CC
A
For I/O ports, the parameter I
includes the input leakage current.
test is applicable to only one ON channel at a time. The duration of this test is less than 1 s.
The I
OS
Measured by the voltage drop between the D and S terminals at the indicated current through the switch. ON-state resistance is determined by
the lower of the voltages of the two (D or S) terminals.
||
r
is the difference of r in a given channel at specified voltages.
on
on(flat)
switching characteristics over recommended operating free-air temperature range,
V
= 3.3 V ꢀ 0.3 V, R = 75 Ω, C = 20 pF (unless otherwise noted) (see Figures 6 and 7)
CC
L
L
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
MIN
TYP
MAX
UNIT
t
D
S
S
2
4
2
5
7
7
ns
ns
ns
IN
pd(s)
t
IN or EN
IN or EN
ON
t
OFF
dynamic characteristics over recommended operating free-air temperature range,
= 3.3 V ꢀ 0.3 V (unless otherwise noted)
V
CC
‡
PARAMETER
TEST CONDITIONS
See Figure 7
TYP
UNIT
%
k
D
D
R
R
R
R
R
= 150 Ω,
= 150 Ω,
= 150 Ω,
= 150 Ω,
= 150 Ω,
f = 3.58 MHz,
f = 3.58 MHz,
See Figure 8
f = 10 MHz,
f = 10 MHz,
0.2
0.1
G
L
L
L
L
L
k
See Figure 7
°
P
B
X
500
−80
−60
MHz
dB
W
R
= 10 Ω,
See Figure 9
TALK
IN
See Figure 10
O
dB
IRR
‡
k
All typical values are at V
= 3.3 V (unless otherwise noted), T = 25°C.
A
CC
D
and D are expressed in absolute magnitude.
G
P
6
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ꢑ ꢌꢀ ꢋ ꢕ ꢓꢑ ꢈꢐꢉ ꢖ ꢕꢈꢀ ꢓ ꢐꢎꢁꢀꢈꢀ ꢒ ꢗꢒꢁ ꢌ ꢁꢀꢈ ꢐꢔ ꢒ
SCDS172A - JULY 2004 − REVISED DECEMBER 2004
0
0
Phase
−10
−20
−30
−1
Gain
−2
−3
−4
−5
−6
−40
Y
J
−50
−60
700
1
10
100
Frequency (MHz)
Y
Gain −3 dB at 627 MHz
Phase at −3-dB Frequency, −47 Deg
J
Figure 1. Gain/Phase vs Frequency
0
0.09
0.08
0.07
−0.02
Differental Gain
−0.04
−0.06
0.06
0.05
−0.08
J
Differental Phase
0.04
0.03
0.02
0.01
−0.1
−0.12
−0.14
−0.16
Y
0
−0.18
−0.2
−0.01
0
0.1
0.2
0.3
0.4
0.5
(V)
0.6
0.7
0.8
0.9
1
V
BIAS
Y
J
Differential Gain at 0.714 V, −0.11%
Differential Phase at 0.714 V, 0.0466 Deg
Figure 2. Differential Gain/Phase vs V
BIAS
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁ ꢂꢃꢂ ꢄ ꢅ
ꢆꢇ ꢈ ꢉ ꢁꢊ ꢉꢀ ꢋ ꢌ ꢍꢋ ꢎꢏꢈꢐ ꢉꢑ ꢌ ꢉꢀ ꢋ ꢃ ꢌ ꢉꢒ ꢓ ꢁꢑ ꢌ ꢀꢔ ꢋ
ꢑꢌ ꢀ ꢋ ꢕ ꢓꢑ ꢈ ꢐꢉ ꢖꢕ ꢈꢀ ꢓ ꢐꢎꢁ ꢀꢈꢀ ꢒ ꢗꢒ ꢁ ꢌ ꢁ ꢀꢈꢐꢔ ꢒ
SCDS172A - JULY 2004 − REVISED DECEMBER 2004
0
160
140
120
100
80
−10
−20
−30
Phase
J
−40
−50
−60
60
Y
40
OFF Isolation
20
−70
−80
0
700
1
10
100
Frequency (MHz)
Y
J
OFF Isolation at 10 MHz, −56 dB
Phase at 10 MHz, 90 Deg
Figure 3. OFF Isolation vs Frequency
180
160
140
120
100
80
0
−10
−20
−30
−40
−50
Phase
J
Y
60
−60
Crosstalk
40
−70
−80
20
−90
0
1
10
100
Frequency (MHz)
700
Y
J
Crosstalk at 10 MHz, −63 dB
Phase at 10 MHz, 90 Deg
Figure 4. Crosstalk vs Frequency
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀꢁ ꢂꢃ ꢂ ꢄꢅ
ꢆ ꢇꢈꢉ ꢁꢊ ꢉꢀ ꢋꢌ ꢍꢋ ꢎꢏꢈꢐꢉꢑ ꢌ ꢉꢀ ꢋ ꢃꢌ ꢉꢒꢓ ꢁ ꢑꢌ ꢀꢔ ꢋ
ꢑ ꢌꢀ ꢋ ꢕ ꢓꢑ ꢈꢐꢉ ꢖ ꢕꢈꢀ ꢓ ꢐꢎꢁꢀꢈꢀ ꢒ ꢗꢒꢁ ꢌ ꢁꢀꢈ ꢐꢔ ꢒ
SCDS172A - JULY 2004 − REVISED DECEMBER 2004
5
4
3
2
1
0
20
16
12
8
V
O
r
ON
4
0
5
0
1
2
3
4
Input Voltage (V)
Figure 5. Output Voltage/ON-State Resistance vs Input Voltage
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁ ꢂꢃꢂ ꢄ ꢅ
ꢆꢇ ꢈ ꢉ ꢁꢊ ꢉꢀ ꢋ ꢌ ꢍꢋ ꢎꢏꢈꢐ ꢉꢑ ꢌ ꢉꢀ ꢋ ꢃ ꢌ ꢉꢒ ꢓ ꢁꢑ ꢌ ꢀꢔ ꢋ
ꢑꢌ ꢀ ꢋ ꢕ ꢓꢑ ꢈ ꢐꢉ ꢖꢕ ꢈꢀ ꢓ ꢐꢎꢁ ꢀꢈꢀ ꢒ ꢗꢒ ꢁ ꢌ ꢁ ꢀꢈꢐꢔ ꢒ
SCDS172A - JULY 2004 − REVISED DECEMBER 2004
PARAMETER MEASUREMENT INFORMATION
V
CC
Input Generator
V
IN
IN
50 Ω
50 Ω
V
G1
TEST CIRCUIT
S1
x
DUT
V
V
V
S1
O
D
x
S2
x
EN
C
R
L
L
(see Note A)
S2
R
V
V
S2
C
V
TEST
L
S1
GND
L
CC
3.3 V 0.3 V
3.3 V 0.3 V
75
75
20 pF
20 pF
V
CC
GND
t
pds
V
CC
Output
Control
(V
V
CC
50%
50%
)
IN
0 V
Analog Output
Waveform
V
OH
90%
90%
(V
O
)
0 V
VOLTAGE WAVEFORMS
TIMES
t
pd(s)
NOTES: A.
C includes probe and jig capacitance.
L
B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2.5 ns, t ≤ 2.5 ns.
O
r
f
C. The outputs are measured one at a time, with one transition per measurement.
Figure 6. Test Circuit and Voltage Waveforms
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀꢁ ꢂꢃ ꢂ ꢄꢅ
ꢆ ꢇꢈꢉ ꢁꢊ ꢉꢀ ꢋꢌ ꢍꢋ ꢎꢏꢈꢐꢉꢑ ꢌ ꢉꢀ ꢋ ꢃꢌ ꢉꢒꢓ ꢁ ꢑꢌ ꢀꢔ ꢋ
ꢑ ꢌꢀ ꢋ ꢕ ꢓꢑ ꢈꢐꢉ ꢖ ꢕꢈꢀ ꢓ ꢐꢎꢁꢀꢈꢀ ꢒ ꢗꢒꢁ ꢌ ꢁꢀꢈ ꢐꢔ ꢒ
SCDS172A - JULY 2004 − REVISED DECEMBER 2004
PARAMETER MEASUREMENT INFORMATION
V
CC
Input Generator
TEST CIRCUIT
V
IN
IN
or
EN
S1
X
X
50 Ω
50 Ω
V
G1
C
R
R
L
L
L
(see Note A)
DUT
V
O
D
S2
X
V
I
C
L
(see Note A)
R
L
75 W
V
I
C
V
TEST
L
CC
t
/t
3.3 V 0.3 V
20 pF
V
CC
ON OFF
Output
Control
(V
V
CC
50%
50%
)
IN
0 V
t
t
OFF
ON
Analog Output
Waveform
V
OH
90%
90%
(V
O
)
0 V
VOLTAGE WAVEFORMS
AND t TIMES
t
ON
OFF
NOTES: A.
C includes probe and jig capacitance.
L
B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2.5 ns, t ≤ 2.5 ns.
O
r
f
C. The outputs are measured one at a time, with one transition per measurement.
Figure 7. Test Circuit and Voltage Waveforms
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁ ꢂꢃꢂ ꢄ ꢅ
ꢆꢇ ꢈ ꢉ ꢁꢊ ꢉꢀ ꢋ ꢌ ꢍꢋ ꢎꢏꢈꢐ ꢉꢑ ꢌ ꢉꢀ ꢋ ꢃ ꢌ ꢉꢒ ꢓ ꢁꢑ ꢌ ꢀꢔ ꢋ
ꢑꢌ ꢀ ꢋ ꢕ ꢓꢑ ꢈ ꢐꢉ ꢖꢕ ꢈꢀ ꢓ ꢐꢎꢁ ꢀꢈꢀ ꢒ ꢗꢒ ꢁ ꢌ ꢁ ꢀꢈꢐꢔ ꢒ
SCDS172A - JULY 2004 − REVISED DECEMBER 2004
PARAMETER MEASUREMENT INFORMATION
EXT TRIGGER
V
BIAS
BIAS
Network Analyzer
(HP8753ES)
Sawtooth
Waveform
Generator
P1
P2
V
CC
S1
A
D
A
R
= 150 Ω
L
IN
DUT
V
IN
EN
V
EN
NOTE: For additional information on measurement method, refer to the TI application report, Measuring Differential Gain and Phase,
literature number SLOA040.
Figure 8. Test Circuit for Differential Gain/Phase Measurement
Differential gain and phase is measured at the output of the ON channel. For example, when V = 0,
IN
V
= 0, and D is the input, the output is measured at S1 .
EN
A
A
HP8753ES setup
Average = 20
RBW = 300 Hz
ST = 1.381 s
P1 = −7 dBM
CW frequency = 3.58 MHz
sawtooth waveform generator setup
V
= 0 to 1 V
BIAS
Frequency = 0.905 Hz
12
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀꢁ ꢂꢃ ꢂ ꢄꢅ
ꢆ ꢇꢈꢉ ꢁꢊ ꢉꢀ ꢋꢌ ꢍꢋ ꢎꢏꢈꢐꢉꢑ ꢌ ꢉꢀ ꢋ ꢃꢌ ꢉꢒꢓ ꢁ ꢑꢌ ꢀꢔ ꢋ
ꢑ ꢌꢀ ꢋ ꢕ ꢓꢑ ꢈꢐꢉ ꢖ ꢕꢈꢀ ꢓ ꢐꢎꢁꢀꢈꢀ ꢒ ꢗꢒꢁ ꢌ ꢁꢀꢈ ꢐꢔ ꢒ
SCDS172A - JULY 2004 − REVISED DECEMBER 2004
PARAMETER MEASUREMENT INFORMATION
EXT TRIGGER
BIAS
Network Analyzer
(HP8753ES)
V
BIAS
P1
P2
V
CC
D
S1
A
A
R
= 150 Ω
L
IN
DUT
V
IN
EN
V
EN
Figure 9. Test Circuit for Frequency Response (B )
W
The frequency response is measured at the output of the ON channel. For example, when V = 0, V
= 0, and
IN
EN
D is the input, the output is measured at S1 . All unused analog I/O ports are left open.
A
A
HP8753ES setup
Average = 4
RBW = 3 kHz
V
= 0.35 V
BIAS
ST = 2 s
P1 = 0 dBM
13
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁ ꢂꢃꢂ ꢄ ꢅ
ꢆꢇ ꢈ ꢉ ꢁꢊ ꢉꢀ ꢋ ꢌ ꢍꢋ ꢎꢏꢈꢐ ꢉꢑ ꢌ ꢉꢀ ꢋ ꢃ ꢌ ꢉꢒ ꢓ ꢁꢑ ꢌ ꢀꢔ ꢋ
ꢑꢌ ꢀ ꢋ ꢕ ꢓꢑ ꢈ ꢐꢉ ꢖꢕ ꢈꢀ ꢓ ꢐꢎꢁ ꢀꢈꢀ ꢒ ꢗꢒ ꢁ ꢌ ꢁ ꢀꢈꢐꢔ ꢒ
SCDS172A - JULY 2004 − REVISED DECEMBER 2004
PARAMETER MEASUREMENT INFORMATION
EXT TRIGGER
BIAS
Network Analyzer
V
BIAS
(HP8753ES)
P1
P2
V
CC
D
S1
A
A
†
50 Ω
IN
R
= 150 Ω
L
V
IN
DUT
EN
V
EN
D
S1
B
B
R
= 10 Ω
R = 150 Ω
L
IN
†
A 50-Ω termination resistor is needed for the network analyzer.
Figure 10. Test Circuit for Crosstalk (X
)
TALK
The crosstalk is measured at the output of the nonadjacent ON channel. For example, when V
= 0,
IN
V
= 0, and D is the input, the output is measured at S1 . All unused analog input (D) ports and output (S) ports
EN
A B
are connected to GND through 10-Ω and 50-Ω pulldown resistors, respectively.
HP8753ES setup
Average = 4
RBW = 3 kHz
V
= 0.35 V
BIAS
ST = 2 s
P1 = 0 dBM
14
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀꢁ ꢂꢃ ꢂ ꢄꢅ
ꢆ ꢇꢈꢉ ꢁꢊ ꢉꢀ ꢋꢌ ꢍꢋ ꢎꢏꢈꢐꢉꢑ ꢌ ꢉꢀ ꢋ ꢃꢌ ꢉꢒꢓ ꢁ ꢑꢌ ꢀꢔ ꢋ
ꢑ ꢌꢀ ꢋ ꢕ ꢓꢑ ꢈꢐꢉ ꢖ ꢕꢈꢀ ꢓ ꢐꢎꢁꢀꢈꢀ ꢒ ꢗꢒꢁ ꢌ ꢁꢀꢈ ꢐꢔ ꢒ
SCDS172A - JULY 2004 − REVISED DECEMBER 2004
PARAMETER MEASUREMENT INFORMATION
EXT TRIGGER
BIAS
Network Analyzer
(HP8753ES)
V
BIAS
P1
P2
V
CC
D
S1
A
A
R
R
= 150 Ω
= 150 Ω
L
IN
DUT
V
IN
S2
A
EN
†
50 Ω
L
V
EN
†
A 50-Ω termination resistor is needed for the network analyzer.
Figure 11. Test Circuit for OFF Isolation (O
)
IRR
The OFF isolation is measured at the output of the OFF channel. For example, when V = V , V
= 0, and
IN
CC EN
D is the input, the output is measured at S1 . All unused analog input (D) ports are left open, and output (S) ports
A
A
are connected to GND through 50-Ω pulldown resistors.
HP8753ES setup
Average = 4
RBW = 3 kHz
V
= 0.35 V
BIAS
ST = 2 s
P1 = 0 dBM
15
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
30-Aug-2005
PACKAGING INFORMATION
Orderable Device
TS3V340D
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
SOIC
D
16
16
16
16
16
16
16
16
16
16
16
16
16
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TS3V340DBQR
TS3V340DBQRE4
TS3V340DE4
SSOP/
QSOP
DBQ
DBQ
D
2500 Green (RoHS & CU NIPDAU Level-2-260C-1YEAR
no Sb/Br)
SSOP/
QSOP
2500 Green (RoHS & CU NIPDAU Level-2-260C-1YEAR
no Sb/Br)
SOIC
TVSOP
TVSOP
SOIC
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TS3V340DGVR
TS3V340DGVRE4
TS3V340DR
DGV
DGV
D
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TS3V340DRE4
TS3V340PW
SOIC
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TSSOP
TSSOP
TSSOP
TSSOP
QFN
PW
PW
PW
PW
RGY
90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TS3V340PWE4
TS3V340PWR
TS3V340PWRE4
TS3V340RGYR
90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
1000 Green (RoHS & CU NIPDAU Level-2-260C-1YEAR
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan
-
The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS
&
no Sb/Br)
-
please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
30-Aug-2005
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
MECHANICAL DATA
MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000
DGV (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
24 PINS SHOWN
0,23
0,13
M
0,07
0,40
24
13
0,16 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
0°–ā8°
0,75
1
12
0,50
A
Seating Plane
0,08
0,15
0,05
1,20 MAX
PINS **
14
16
20
24
38
48
56
DIM
A MAX
A MIN
3,70
3,50
3,70
3,50
5,10
4,90
5,10
4,90
7,90
7,70
9,80
9,60
11,40
11,20
4073251/E 08/00
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.
D. Falls within JEDEC: 24/48 Pins – MO-153
14/16/20/56 Pins – MO-194
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
M
0,10
0,65
14
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
8
14
16
20
24
28
DIM
3,10
2,90
5,10
4,90
5,10
4,90
6,60
6,40
7,90
9,80
9,60
A MAX
A MIN
7,70
4040064/F 01/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,
enhancements, improvements, and other changes to its products and services at any time and to discontinue
any product or service without notice. Customers should obtain the latest relevant information before placing
orders and should verify that such information is current and complete. All products are sold subject to TI’s terms
and conditions of sale supplied at the time of order acknowledgment.
TI warrants performance of its hardware products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI
deems necessary to support this warranty. Except where mandated by government requirements, testing of all
parameters of each product is not necessarily performed.
TI assumes no liability for applications assistance or customer product design. Customers are responsible for
their products and applications using TI components. To minimize the risks associated with customer products
and applications, customers should provide adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right,
copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process
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does not constitute a license from TI to use such products or services or a warranty or endorsement thereof.
Use of such information may require a license from a third party under the patents or other intellectual property
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Reproduction of information in TI data books or data sheets is permissible only if reproduction is without
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is an unfair and deceptive business practice. TI is not responsible or liable for any such statements.
Following are URLs where you can obtain information on other Texas Instruments products and application
solutions:
Products
Applications
Audio
Amplifiers
amplifier.ti.com
www.ti.com/audio
Data Converters
dataconverter.ti.com
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www.ti.com/automotive
DSP
dsp.ti.com
Broadband
Digital Control
Military
www.ti.com/broadband
www.ti.com/digitalcontrol
www.ti.com/military
Interface
Logic
interface.ti.com
logic.ti.com
Power Mgmt
Microcontrollers
power.ti.com
Optical Networking
Security
www.ti.com/opticalnetwork
www.ti.com/security
www.ti.com/telephony
www.ti.com/video
microcontroller.ti.com
Telephony
Video & Imaging
Wireless
www.ti.com/wireless
Mailing Address:
Texas Instruments
Post Office Box 655303 Dallas, Texas 75265
Copyright 2005, Texas Instruments Incorporated
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TI
TS3V340_101
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TS3V3702
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TS3V3702I
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TS3V3702IDT
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TS3V3702IN
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