TS5MP645YFPR [TI]
具有断电保护和 1.8V 逻辑的 1.5pF、5V、2:1 (SPDT)、10 通道 MIPI 模拟开关 | YFP | 36 | -40 to 85;
| 型号： | TS5MP645YFPR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有断电保护和 1.8V 逻辑的 1.5pF、5V、2:1 (SPDT)、10 通道 MIPI 模拟开关 | YFP | 36 | -40 to 85 开关 光电二极管 |
| 文件： | 总35页 (文件大小：1233K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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TS5MP645
ZHCSHH3B –JANUARY 2018–REVISED JULY 2018
TS5MP645 4 数据通道 2:1 MIPI 开关（10 通道，2:1 模拟开关）
1 特性
3 说明
1
•
电源电压范围 1.65V 至 5.5V
10 通道 2:1 开关
TS5MP645 是一款四数据通道 MIPI 开关。此器件是一
款经优化的 10 通道（包含 5 个差动通道）单极双投开
关，适用于高速 应用。TS5MP645 可方便地将多个符
合 MIPI 标准的器件与单个 CSI/DSI、C-PHY/D-PHY
模块相连接。
•
•
关断保护
VDD = 0V 时，I/O 类型为 Hi-Z
•
•
•
•
•
•
•
低 RON，典型值 2.45Ω
低 CON，为 1.5pF
此器件具有出色的带宽、几乎不会造成信号恶化的低通
道间偏斜以及可补偿布局损失的宽裕量。其低电流消耗
可满足低功率 应用供电。
1.5GHz 最小带宽
-40dB 超低串扰
低功耗禁用模式
器件信息(1)
1.8V 兼容型逻辑输入
ESD 保护性能超出 JESD 22 标准
器件编号
TS5MP645
封装
封装尺寸（标称值）
DSBGA (YFP)
2.42mm x 2.42mm
–
2000V 人体放电模型 (HBM)
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
2 应用
•
•
•
•
•
移动电话
平板电脑
台式机/笔记本电脑
虚拟现实
扩增实境
简化原理图
1.65 V œ 5.5 V
100 nF
2.2 µF
VDD
CLK
Data[1:4]
CLK
MIPI Module 1
Data[1:4]
TS5MP645
4-Data Lane
MIPI Switch
Processor
CLK
Data[1:4]
MIPI Module 2
SEL
/OE
Copyright © 2018, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SCDS385
TS5MP645
ZHCSHH3B –JANUARY 2018–REVISED JULY 2018
www.ti.com.cn
目录
8.4 Device Functional Modes........................................ 19
Application and Implementation ........................ 20
9.1 Application Information............................................ 20
9.2 Typical Application ................................................. 20
1
2
3
4
5
6
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 5
6.1 Absolute Maximum Ratings ...................................... 5
6.2 ESD Ratings.............................................................. 5
6.3 Recommended Operating Conditions....................... 5
6.4 Thermal Information.................................................. 5
6.5 Electrical Characteristics........................................... 6
6.6 Typical Characteristics.............................................. 9
Parameter Measurement Information ................ 10
Detailed Description ............................................ 16
8.1 Overview ................................................................. 16
8.2 Functional Block Diagram ....................................... 16
8.3 Feature Description................................................. 17
9
10 Power Supply Recommendations ..................... 21
11 Layout................................................................... 22
11.1 Layout Guidelines ................................................. 22
11.2 Layout Example .................................................... 22
12 器件和文档支持 ..................................................... 23
12.1 文档支持 ............................................................... 23
12.2 接收文档更新通知 ................................................. 23
12.3 社区资源................................................................ 23
12.4 商标....................................................................... 23
12.5 静电放电警告......................................................... 23
12.6 术语表 ................................................................... 23
13 机械、封装和可订购信息....................................... 24
7
8
4 修订历史记录
注：之前版本的页码可能与当前版本有所不同。
Changes from Revision A (March 2018) to Revision B
Page
•
Changed the IOFF Test conditions From: VDD = 1.65 V to 5.5 V To: VDD = 0 V, 1.65 V to 5.5 V in the Electrical
Characteristics table .............................................................................................................................................................. 6
Changes from Original (January 2018) to Revision A
Page
•
将“器件信息”表中的“封装尺寸（标称值）”从 2.459 x 2.459 更改成了 2.42 x 2.42................................................................. 1
2
Copyright © 2018, Texas Instruments Incorporated
TS5MP645
www.ti.com.cn
ZHCSHH3B –JANUARY 2018–REVISED JULY 2018
5 Pin Configuration and Functions
DSBGA Package
36 Pin (YFP)
Top View
1
2
3
4
5
6
A
B
C
D
E
F
VDD
GND
DA4N
DA4P
OE
SEL
DB4N
DB3N
DB2N
DB1N
CLKBN
DB4P
DB3P
DB2P
DB1P
CLKBP
DA3N
NC
DA3P
NC
D4N
D3N
D4P
D3P
D2P
D1P
DA2N
DA1N
CLKAN
DA2P
DA1P
CLKAP
D2N
D1N
CLKN
CLKP
Not to scale
Pin Functions
PIN
I/O
DESCRIPTION
NAME
VDD
GND
DA4N
DA4P
OE
NO.
A1
A2
A3
A4
A5
A6
B1
B2
B3
B4
B5
B6
C1
C2
C3
C4
C5
C6
D1
D2
D3
PWR
GND
I/O
I/O
I
Power supply input
Device Ground
Differential I/O
Differential I/O
Output enable (Active Low)
Channel Select
Differential I/O
Differential I/O
Differential I/O
Differential I/O
Differential I/O
Differential I/O
Differential I/O
Differential I/O
No connect
SEL
I
DB4N
DB4P
DA3N
DA3P
D4N
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
-
D4P
DB3N
DB3P
NC
NC
-
No connect
D3N
I/O
I/O
I/O
I/O
I/O
Differential I/O
Differential I/O
Differential I/O
Differential I/O
Differential I/O
D3P
DB2N
DB2P
DA2N
Copyright © 2018, Texas Instruments Incorporated
3
TS5MP645
ZHCSHH3B –JANUARY 2018–REVISED JULY 2018
www.ti.com.cn
Pin Functions (continued)
PIN
I/O
DESCRIPTION
NAME
DA2P
D2N
NO.
D4
D5
D6
E1
E2
E3
E4
E5
E6
F1
F2
F3
F4
F5
F6
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Differential I/O
Differential I/O
Differential I/O
Differential I/O
Differential I/O
Differential I/O
Differential I/O
Differential I/O
Differential I/O
Differential I/O
Differential I/O
Differential I/O
Differential I/O
Differential I/O
Differential I/O
D2P
DB1N
DB1P
DA1N
DA1P
D1N
D1P
CLKBN
CLKBP
CLKAN
CLKAP
CLKN
CLKP
4
Copyright © 2018, Texas Instruments Incorporated
TS5MP645
www.ti.com.cn
ZHCSHH3B –JANUARY 2018–REVISED JULY 2018
6 Specifications
6.1 Absolute Maximum Ratings
Over operating free-air temperature range (unless otherwise noted)(1)
(2)
MIN
MAX
UNIT
VDD
VI/O
Supply Voltage
-0.5
6
V
Analog voltage range (DxN, CLKN, DxP, CLKP, DAxN, CLKAN, DAxP, CLKAP, DBxN,
CLKBN, DBxP, CLKBP)
-0.5
4
V
VSEL , VOE Digital Input Voltage (SEL, OE)
-0.5
-65
-65
6
V
TJ
Junction temperature
Storage temperature
150
150
°C
°C
Tstg
(1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage are with respect to ground, unless otherwise specified
6.2 ESD Ratings
VALUE
UNIT
Human body model (HBM), per
±2000
ANSI/ESDA/JEDEC JS-001, all pins(1)
V(ESD)
Electrostatic discharge
V
Charged device model (CDM), per JEDEC
specification JESD22-C101, all pins(2)
±250
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
Over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
VDD
VI/O
Supply Voltage
1.65
5.5
V
Analog voltage range (DxN, CLKN, DxP, CLKP, DAxN, CLKAN, DAxP,
CLKAP, DBxN, CLKBN, DBxP, CLKBP)
0
3.6
V
VSEL, VOE Digital Input Voltage (SEL, OE)
0
-35
-40
-65
5.5
35
V
II/O
TA
TJ
Continuous I/O current
mA
°C
°C
Operating ambient temperature
Junction temperature
85
150
6.4 Thermal Information
TS5MP645
THERMAL METRIC(1)
YFP
36
UNIT
RθJA
RθJC(top)
RθJB
ΨJT
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
57.6
0.3
°C/W
°C/W
°C/W
°C/W
°C/W
12.6
0.2
Junction-to-top characterization parameter
Junction-to-board characterization parameter
ΨJB
12.7
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
版权 © 2018, Texas Instruments Incorporated
5
TS5MP645
ZHCSHH3B –JANUARY 2018–REVISED JULY 2018
www.ti.com.cn
6.5 Electrical Characteristics
Over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
0
TYP
30
MAX
60
UNIT
µA
POWER SUPPLY
VDD = 1.65 V to 5.5 V
OE = 0 V
SEL = 0 V to 5.5 V
Dn, CLKn = 0 V
IDD
Active Supply Current
VDD = 1.65 V to 5.5 V
OE = VDD
SEL = 0 V to 5.5 V
Dn, CLKn = 0 V
IDD_PD
Power-down Supply current
Power-down Supply current
0
0.1
0.1
1
µA
VDD = 1.65 V to 5.5 V
OE = 1.8 V
SEL = 0 V to 5.5 V
Dn, CLKn = 0 V
IDD_PD_1.8
0
10
µA
DC CHARACTERISTICS
VDD = 1.65 V to 5.5 V
OE = 0 V
Dn,CLKn = -8 mA, 0.2V
RON_HS
On-state resistance
2.45
2.65
0.1
5.5
6.5
Ω
Ω
Ω
Ω
Ω
Ω
DAn, DBn, CLKAn, CLKBn = 0.2 V, -8 mA
VDD = 1.65 V to 5.5 V
OE = 0 V
Dn, CLKn = -8 mA, 1.2V
RON_LP
On-state resistance
DAn, DBn, CLKAn, CLKBn = 1.2 V, -8 mA
VDD = 1.65 V to 5.5 V
OE = 0 V
Dn, CLKn = -8 mA, 0 V to 0.3 V
RON_flat_HS
RON_flat_LP
ΔRON_HS
ΔRON_LP
On-state resistance flatness
On-state resistance flatness
DAn, DBn, CLKAn, CLKBn = 0 V to 0.3 V,-8 mA
VDD = 1.65 V to 5.5 V
OE = 0 V
Dn, CLKn = -8 mA, 0 V to 1.3 V
0.9
DAn, DBn, CLKAn, CLKBn = 0 V to 1.3 V, -8 mA
VDD = 1.65 V to 5.5 V
OE = 0 V
Dn, CLKn = -8 mA, 0.2 V
On-state resistance match between+and -
paths
0.1
DAn, DBn, CLKAn, CLKBn = 0.2 V, -8 mA
VDD = 1.65 V to 5.5 V
OE = 0 V
Dn, CLKn = -8 mA, 1.2 V
On-state resistance match between+and -
paths
0.1
DAn, DBn, CLKAn, CLKBn = 1.2 V, -8 mA
VDD = 0 V, 1.65 V to 5.5 V
OE = 0 V to 5.5 V
SEL= 0 V to 5.5 V
Dn, CLKn = 0 V to 1.3 V
DAn, DBn, CLKAn, CLKBn = 0 V to 1.3 V
IOFF
Switch off leakage current
Switch on leakage current
-0.5
-0.5
0.5
0.5
µA
µA
VDD = 1.65 V to 5.5 V
OE = 0 V
SEL= 0 V to 5.5 V
ION
Dn, CLKn = 0 V to 1.3 V
DAn, DBn, CLKAn, CLKBn = 0 V to 1.3 V
DYNAMIC CHARACTERISTICS
VDD = 1.65 V to 5.5 V
OE = 0 V
Dn, CLKn = 0.6 V
tSWITCH
Switching time between channels
1.5
µs
DAn, DBn, CLKAn, CLKBn: RL=50 Ω, CL = 5 pF
fSEL_MAX
Maximum toggling frequency for the SEL
line
VDD = 1.65 V to 5.5 V
Dn, CLKn = 0.6 V
100
kHz
DAn, DBn, CLKAn, CLKBn: RL= 50 Ω, CL=1 pF
VDD = 1.65 V to 5.5 V
tON_OE
Device enable time OE to switch on
Device enable time VDD to switch on
Dn, CLKn = 0.6 V
DAn, DBn, CLKAn, CLKBn: RL= 50 Ω, CL= 1 pF
50
50
300
300
µs
µs
tON_VDD
VDD = 0 V to 1.65 V
Dn, CLKn = 0.6 V
DAn, DBn, CLKAn, CLKBn: RL= 50 Ω, CL= 1 pF
6
Copyright © 2018, Texas Instruments Incorporated
TS5MP645
www.ti.com.cn
ZHCSHH3B –JANUARY 2018–REVISED JULY 2018
Electrical Characteristics (continued)
Over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VDD = 1.65 V to 5.5 V
tOFF_OE
Device disable time OE to switch off
Dn, CLKn = 0.6 V
0.5
1
µs
DAn, DBn, CLKAn, CLKBn: RL= 50 Ω, CL= 1 pF
VDD = 5 V to 0 V
VDD ramp rate = 250 µs
Dn, CLKn = 0.6 V
DAn, DBn, CLKAn, CLKBn: RL = 50 Ω, CL = 1pF
tOFF_VDD
Device disable time VDD to switch off
Minimum pulse width for OE
0.5
1
ms
ns
tMIN_OE
VDD = 1.65 V to 5.5 V
Dn, CLKn = 0.6 V
DAn, DBn, CLKAn, CLKBn: RL = 50 Ω, CL = 1 pF
500
50
VDD = 1.65 V to 5.5 V
OE = 0 V
Dn, CLKn = RL = 50 Ω, CL = 1 pF
tBBM
Break before make time
Intrapair skew
ns
ps
ps
DAn, DBn, CLKAn, CLKBn: 0.6 V
VDD = 1.65 V to 5.5 V
OE = 0 V
Dn, CLKn = 0.3 V
tSKEW
1
4
DAn, DBn, CLKAn, CLKBn: RL = 50 Ω, CL = 1 pF
VDD = 1.65 V to 5.5 V
OE = 0 V
Dn, CLKn = 0.3 V
tSKEW
Interpair Skew
DAn, DBn, CLKAn, CLKBn: RL = 50 Ω, CL = 1 pF
VDD = 1.65 V to 5.5 V
OE = 0 V
Dn, CLKn = 0.6 V
tPD
Propagation delay with 100 ps rise time
40
ps
DAn, DBn, CLKAn, CLKBn: RL = 50 Ω, CL = 1 pF
tRISE = 100 ps
VDD = 1.65 V
OE = 0 V, VDD
SEL = 0 V, VDD
OISO
Differential off isolation
Dn, CLKn, DAn, DBn, CLKAn, CLKBn: RS = 50 Ω,
RL = 50 Ω, CL = 1 pF
-20
dB
VI/O = 200 mV + 200 mVPP (differential)
f = 1250 MHz
VDD = 1.65 V to 5.5 V
OE = 0 V, VDD
SEL = 0 V, VDD
XTALK
Differential channel to channel crosstalk
Dn, CLKn, DAn, DBn, CLKAn, CLKBn: RS = 50 Ω,
RL = 50 Ω, CL = 1 pF
VI/O = 200 mV + 200 mVPP (differential)
f = 1250 MHz
-40
dB
GHz
dB
VDD = 1.65 V to 5.5 V
OE = 0 V
SEL = 0 V, VDD
Dn, CLKn, DAn, DBn, CLKAn, CLKBn: RS = 50 Ω,
RL = 50 Ω, CL = 1 pF
VI/O = 200 mV + 200 mVPP (differential)
BW
Differential Bandwidth
1.5
2
VDD = 1.65 V to 5.5 V
OE = 0 V
SEL = 0 V, VDD
Dn, CLKn, DAn, DBn, CLKAn, CLKBn: RS = 50 Ω,
RL = 50 Ω, CL = 1 pF
ILOSS
Insertion Loss
-0.4
VI/O = 200 mV + 200 mVPP (differential)
f = 100 kHz
VDD = 1.65 V to 5.5 V
OE = 0 V, VDD
SEL = 0 V, VDD
Dn, CLKn, DAn, DBn, CLKAn, CLKBn = 0 V , 0.2 V
f = 1250 MHz
COFF
Off capacitance
On capacitance
1.5
1.5
pF
pF
VDD = 1.65 V to 5.5 V
OE = VDD
SEL = 0 V, VDD
CON
Dn, CLKn, DAn, DBn, CLKAn, CLKBn = 0 V , 0.2 V
f = 1250 MHz
Copyright © 2018, Texas Instruments Incorporated
7
TS5MP645
ZHCSHH3B –JANUARY 2018–REVISED JULY 2018
www.ti.com.cn
Electrical Characteristics (continued)
Over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DIGITAL CHARACTERISTICS
VIH
VIL
IIH
Input logic high (SEL, OE)
VI/O = 0.6 V, RL = 50 Ω, CL = 5 pF
VI/O = 0.6 V, RL = 50 Ω, CL = 5 pF
VI/O = 0.6 V, RL = 50 Ω, CL = 5 pF
VI/O = 0.6 V, RL = 50 Ω,CL = 5 pF
1.425
0
5.5
0.5
5
V
V
Input logic low (SEL, OE)
Input high leakage current (SEL, OE)
Input low leakage current (SEL, OE)
-5
µA
µA
IIL
-5
5
Internal pull-down resistance on digital
input pins
RPD
VI/O = 0.6 V, RL = 50 Ω, CL = 5 pF
6
5
MΩ
CSEL, COE
Digital Input capacitance (SEL, OE)
f = 1 MHz
pF
8
版权 © 2018, Texas Instruments Incorporated
TS5MP645
www.ti.com.cn
ZHCSHH3B –JANUARY 2018–REVISED JULY 2018
6.6 Typical Characteristics
4.5
4
4.5
4
RON (-40°C)
RON (25°C)
RON (85°C)
RON (-40°C)
RON (25°C)
RON (85°C)
3.5
3
3.5
3
2.5
2
2.5
2
1.5
1.5
0
0.2
0.4
0.6
0.8
1
1.2
1.4
0
0.2
0.4
0.6
0.8
1
1.2
1.4
Input Voltage (V)
Input Voltage (V)
D003
D002
图 1. RON vs Input Voltage. VDD = 1.65 V
图 2. RON vs Input Voltage. VDD = 3.3 V
4.5
4
0
-1
RON (-40°C)
RON (25°C)
RON (85°C)
-2
-3
-4
3.5
3
-5
-6
-7
-8
-9
2.5
2
-10
-11
-12
-13
-14
Bandwidth
1.5
0
0.2
0.4
0.6
0.8
1
1.2
1.4
300000
1E+7
1E+8
1E+9
1E+10
Input Voltage (V)
Frequency (Hz)
D004
D001
图 3. RON vs Input Voltage. VDD = 5.5 V
图 4. Differential Bandwidth
0
0
-20
-20
-40
-40
-60
-60
-80
-80
-100
-120
-100
Off Isolation
Crosstalk
-120
100000
1000000
1E+7
1E+8
1E+9
1E+10
200000 1000000
1E+7
1E+8
1E+9
1E+10
Frequency (Hz)
Frequency (Hz)
D002
D003
图 5. Off Isolation
图 6. Differential Crosstalk
版权 © 2018, Texas Instruments Incorporated
9
TS5MP645
ZHCSHH3B –JANUARY 2018–REVISED JULY 2018
www.ti.com.cn
7 Parameter Measurement Information
Channel ON
RON = V/ION
V
VI/O
ION
Switch
Copyright © 2018, Texas Instruments Incorporated
图 7. On Resistance
VI/O
VI/O
A
A
Switch
图 8. Off Leakage
VI/O
A
Switch
图 9. On Leakage
VI/OA
VI/OB
VI/O
CL
RL
RL
SEL
CL
VSEL
1.8 V
0 V
1.8 V
0 V
VSEL
tSWITCH
VI/OA
VIL
VIH
VSEL
tSWITCH
VI/OB
VIH
VIL
tSWITCH
tSWITCH
20 %
VI/O
VI/O
80
%
80 %
20 %
0 V
0 V
Copyright © 2018, Texas Instruments Incorporated
(1) All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω , tr = 3 ns,
tf = 3 ns.
(2) CL includes probe and jig capacitance.
图 10. tSWITCH timing
10
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TS5MP645
www.ti.com.cn
ZHCSHH3B –JANUARY 2018–REVISED JULY 2018
Parameter Measurement Information (接下页)
1.65 V
VDD
VI/O
/OE
VI/O
1.8 V
0 V
VIL
VIH
V/OE
CL
RL
tON
tOFF
VI/O
90 %
10 %
VI/O
V/OE
0 V
Copyright © 2018, Texas Instruments Incorporated
(1) All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω , tr = 3 ns,
tf = 3 ns.
(2) CL includes probe and jig capacitance.
图 11. tON and tOFF Timing for OE
Network Analyzer
Switch
50 ꢀ
DXP
DXN
50 ꢀ
Source
Signal
50 ꢀ
50 ꢀ
Source
Signal
50 ꢀ
50 ꢀ
Copyright © 2018, Texas Instruments Incorporated
图 12. Off Isolation
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11
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ZHCSHH3B –JANUARY 2018–REVISED JULY 2018
www.ti.com.cn
Parameter Measurement Information (接下页)
Network Analyzer
Switch
50 ꢀ
DXP
50 ꢀ
50 ꢀ
Source
Signal
50 ꢀ
50 ꢀ
DXN
Source
Signal
50 ꢀ
DXP
DXN
50 ꢀ
50 ꢀ
50 ꢀ
50 ꢀ
50 ꢀ
50 ꢀ
Copyright © 2018, Texas Instruments Incorporated
图 13. Crosstalk
Network Analyzer
Switch
50 ꢀ
DXN
DXP
50 ꢀ
Source
Signal
50 ꢀ
50 ꢀ
Source
Signal
50 ꢀ
50 ꢀ
Copyright © 2017, Texas Instruments Incorporated
图 14. BW and Insertion Loss
12
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TS5MP645
www.ti.com.cn
ZHCSHH3B –JANUARY 2018–REVISED JULY 2018
Parameter Measurement Information (接下页)
Generator
Switch
50 ꢀ
D1P
D1N
D2P
D2N
DX1P
50 ꢀ
50 ꢀ
50 ꢀ
50 ꢀ
50 ꢀ
50 ꢀ
50 ꢀ
50 ꢀ
50 ꢀ
50 ꢀ
Source
Signal
50 ꢀ
50 ꢀ
50 ꢀ
50 ꢀ
50 ꢀ
50 ꢀ
DX1N
Source
Signal
50 ꢀ
50 ꢀ
50 ꢀ
DX2P
Source
Signal
DX2N
Source
Signal
50 ꢀ
50 ꢀ
50 ꢀ
D3P
D3N
DX3P
Source
Signal
DX3N
Source
Signal
50 ꢀ
50 ꢀ
50 ꢀ
D4P
DX4P
Source
Signal
D4N
DX4N
Source
Signal
50 ꢀ
50 ꢀ
50 ꢀ
CLKP
CLKN
CLKXP
Source
Signal
CLKXN
Source
Signal
50 ꢀ
Copyright © 2017, Texas Instruments Incorporated
图 15. tPD, tSKEW(INTRA) and tSKEW Setup
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13
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www.ti.com.cn
Parameter Measurement Information (接下页)
DXX/CLKX
50%
50%
tPD
tPD
DXXX/CLKXX
50%
50%
(1) All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω , tr = 100
ps, tf = 100 ps.
(2) CL includes probe and jig capacitance.
图 16. tPD
DXX/CLKX
50%
50%
tSKEW
tSKEW
50%
DXXX/CLKXX
50%
(1) All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω , tr = 100
ps, tf = 100 ps.
(2) CL includes probe and jig capacitance.
图 17. tSKEW
14
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TS5MP645
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ZHCSHH3B –JANUARY 2018–REVISED JULY 2018
Parameter Measurement Information (接下页)
tSKEW
DX/CLKX
tSKEW
tSKEW
DX1
50%
50%
50%
50%
50%
DX2
50%
DX3
50%
DX4
50%
CLK
50%
50%
(1) All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω , tr = 100
ps, tf = 100 ps.
(2) CL includes probe and jig capacitance.
(3) tSK(INTER) is the max skew between all channels. Diagram exaggerates tSK(INTER) to show measurement technique
图 18. tSKEW
0.6 V
VI/O
VSEL
CL
RL
SEL
0.6 V
tBBM
80 %
VI/O
VSEL
tBBM
Copyright © 2017, Texas Instruments Incorporated
(1) All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω , tr = 3 ns,
tf = 3 ns.
(2) CL includes probe and jig capacitance.
图 19. tBBM
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15
TS5MP645
ZHCSHH3B –JANUARY 2018–REVISED JULY 2018
www.ti.com.cn
8 Detailed Description
8.1 Overview
The TS5MP645 is a high-speed 4 Data lane 2:1 MIPI Switch. The device includes 10 channels (5 differential)
with 4 differential data lanes and 1 differential clock lane for D-PHY, CSI or DSI. The switch allows a single MIPI
port to interface between two MIPI modules, expanding the number of potential MIPI devices that can be used
within a system that is MIPI port limited.
8.2 Functional Block Diagram
VDD
SEL
6 MO
6 MO
Control
Logic
/OE
CLKAP
CLKBP
CLKP
CLKN
D1P
D1N
D2P
D2N
D3P
D3N
D4P
D4N
CLKAN
CLKBN
DA1P
DB1P
DA1N
DB1N
DA2P
DB2P
DA2N
DB2N
DA3P
DB3P
DA3N
DB3N
DA4P
DB4P
DA4N
DB4N
GND
Copyright © 2018, Texas Instruments Incorporated
16
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TS5MP645
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ZHCSHH3B –JANUARY 2018–REVISED JULY 2018
8.3 Feature Description
8.3.1 Powered-Off Protection
When the TS5MP645 is powered off (VDD = 0 V) the I/Os and digital logic pins of the device will remain in a high
impedance state. The crosstalk, off-isolation, and leakage remains within the electrical specifications. This
prevents errant voltages from reaching the rest of the system and maintains isolation when the system is
powering up.
图 20 shows an example system containing a switch without powered-off protection with the following system
level scenario
1. Subsystem A powers up and starts sending information to Subsystem B that remains unpowered.
2. The I/O voltage back powers the supply rail in Subsystem B.
3. The digital logic is back powered and turns on the switch. The signal is transmitted to Subsystem B before it
is powered and damages it.
Unpowered
Powered
LDO
2
VDD
1
ESD
Subsystem A
Subsystem B
SEL
3
Switch
图 20. System Without Powered-Off Protection
With powered-off protection, the switch prevents back powering the supply and the switch remains high-
impedance. Subsystem B remains protected.
Unpowered
Powered
LDO
VDD
Protection
ESD
Subsystem A
Subsystem B
SEL
Hi-Z
Switch
图 21. System With Powered-Off Protection
This features has the following system level benefits.
•
•
•
Protects the system from damage.
Prevents data from being transmitted unintentionally
Eliminates the need for power sequencing solutions reducing BOM count and cost, simplifying system design
and improving reliability.
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TS5MP645
ZHCSHH3B –JANUARY 2018–REVISED JULY 2018
www.ti.com.cn
Feature Description (接下页)
8.3.2 1.8 V Logic Compatible Inputs
The TS5MP645 has 1.8 V logic compatible digital inputs for switch control. Regardless of the VDD voltage the
digital input thresholds remained fixed, allowing a 1.8 V processor GPIO to control the TS5MP645 without the
need for an external translator. This saves both space and BOM cost.
An example setup for a system without a 1.8 V logic compatible input is shown in 图 22. Here the supply
mismatch between the process and its GPIO output and the supply to the switch require a translator.
3.3 V
1.8 V
Processor
VDD
SEL
1.8 V
GPIO
Switch
图 22. System Without 1.8 V Logic Compatible Inputs
With the 1.8 V logic compatibility in the TS5MP645, the translator is built in to the device so that the external
components are no longer needed, simplifying the system design and overall cost.
3.3 V
1.8 V
VDD
Processor
1.8 V
GPIO
SEL
Switch
图 23. System With 1.8 V Logic Compatible Inputs
8.3.3 Low Power Disable Mode
The TS5MP645 has a low power mode that places all the signal paths in a high impedance state and lowers the
current consumption while the device is not in use. To put the device in low power mode and disable the switch,
the output enable pin OE must be supplied with a logic high signal.
18
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TS5MP645
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ZHCSHH3B –JANUARY 2018–REVISED JULY 2018
8.4 Device Functional Modes
8.4.1 Pin Functions
SEL and OE have weak 6-MΩ pulldown resistors to prevent floating input logic.
表 1. Function Table
OE
SEL
Function
I/O pins High-Impedance
CLK(P/N) = CLKA(P/N)
Dn(P/N) = DAn(P/N)
H
X
L
L
L
CLK(P/N) = CLKB(P/N)
Dn(P/N) = DBn(P/N)
H
8.4.2 Low Power Mode
While the output enable pin OE is supplied with a logic high the device remains in low power state. This reduces
the current consumption substantially and the switches are be high impedance. The SEL pin is ignored while the
OE remains high. Upon exiting low power mode, the switch status reflects the SEL pin as seen in 表 1.
8.4.3 Switch Enabled Mode
While the output enable pin OE is supplied with a logic low the device will remain in switch enabled mode.
版权 © 2018, Texas Instruments Incorporated
19
TS5MP645
ZHCSHH3B –JANUARY 2018–REVISED JULY 2018
www.ti.com.cn
9 Application and Implementation
注
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
9.2 Typical Application
图 24 represents a typical application of the TS5MP645 MIPI switch. The TS5MP645 is used to switch signals
between multiple MIPI modules and a single MIPI port on a processor. This expands the capabilities of a single
port to handle multiple MIPI modules.
1.65 V œ 5.5 V
100 nF
2.2 µF
VDD
CLK
Data[1:4]
CLK
MIPI Module 1
MIPI Module 2
Data[1:4]
TS5MP645
4-Data Lane
MIPI Switch
Processor
CLK
Data[1:4]
SEL
/OE
图 24. Typical TS5MP645 Application
9.2.1 Design Requirements
Design requirements of the MIPI standard being used must be followed. Supply pin decoupling capacitors of 2.2
µF and 100 nF are recommended for best performance. The TS5MP645 has internal 6-MΩ pulldown resistors on
SEL and OE. The pulldown on these pins ensure that the digital remains in a non-floating state during system
power-up to prevent shoot through current spikes and an unknown switch status. By default the switch will power
up enabled and with the A path selected until driven externally by the processor.
9.2.2 Detailed Design Procedure
The TS5MP645 can be properly operated without any external components. However, TI recommends that
unused I/O signal pins be connected to ground through a 50 Ω resistor to prevent signal reflections and maintain
device performance. The NC pins of the device do not require any external connections or terminations and have
no connection to the rest of the device internally.
The clock and data lanes can be interchanged as necessary to facilitate the best layout possible for the
application. For example the clock can be placed on the D1 channel and a data lane can be used on the CLK
channel if this improves the layout. In addition the signal lines of the TS5MP645 are routed single ended on the
chip die. This makes the device suitable for both differential and single-ended high-speed systems.
20
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TS5MP645
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ZHCSHH3B –JANUARY 2018–REVISED JULY 2018
Typical Application (接下页)
9.2.3 Application Curves
0
-1
-2
-3
-4
-5
-6
-7
-8
-9
-10
-11
-12
-13
Bandwidth
-14
300000
1E+7
1E+8
1E+9
1E+10
Frequency (Hz)
D001
图 25. Differential Bandwidth
10 Power Supply Recommendations
When the TS5MP645 is powered off (VDD = 0 V), the I/Os of the device remains in a high-Z state. The crosstalk,
off-isolation, and leakage remain within the electrical Specifications. Power to the device is supplied through the
VDD pin. Decoupling capacitors of 100 nF and 2.2 µF are recommended on the supply.
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www.ti.com.cn
11 Layout
11.1 Layout Guidelines
Place the supply de-coupling capacitors as close to the VDD and GND pin as possible. The spacing between the
power traces, supply and ground, and the signal I/O lines, clock and data, should be a minimum of three times
the race width of the signal I/O lines to maintain signal integrity.
The characteristic impedance of the trace(s) must match that of the receiver and transmitter to maintain signal
integrity. Route the high-speed traces using a minimum amount of vias and corners. This will reduce the amount
of impedance changes.
When it becomes necessary to make the traces turn 90°, use two 45° turns or an arc instead of making a single
90° turn.
Do not route high-speed traces near crystals, oscillators, external clock signals, switching regulators, mounting
holes or magnetic devices.
Avoid stubs on the signal lines.
All I/O signal traces should be routed over a continuous ground plane with no interruptions. The minimum width
from the edge of the trace to any break in the ground plane must be 3 times the trace width. When routing on
PCB inner signal layers, the high speed traces should be between two ground planes and maintain characteristic
impedance.
High speed signal traces must be length matched as much as possible to minimize skew between data and clock
lines.
11.2 Layout Example
VIA to
power plane
VIA to
ground plane
C
C
To Control
Logic
DA4
DA4
P
VDD
GND
N
/OE
D4N
D3N
D2N
D1N
SEL
D4P
D3P
D2P
D1P
DB4
N
DB4
P
DA3
N
DA3
P
DB3
N
DB3
P
To MIPI
Modules
NC
NC
To MIPI Port
DB2
N
DB2
P
DA2
N
DA2
P
DB1
N
DB1
P
DA1
N
DA1
P
CLK
BN
CLK
BP
CLK
AN
CLK
AP
CLK
N
CLK
P
图 26. Layout Example
22
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TS5MP645
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ZHCSHH3B –JANUARY 2018–REVISED JULY 2018
12 器件和文档支持
12.1 文档支持
12.2 接收文档更新通知
要接收文档更新通知，请导航至 TI.com.cn 上的器件产品文件夹。单击右上角的通知我 进行注册，即可每周接收产
品信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
12.3 社区资源
下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，
并且不一定反映 TI 的观点；请参阅 TI 的 《使用条款》。
TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在
e2e.ti.com 中，您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。
设计支持
TI 参考设计支持 可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。
12.4 商标
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.5 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
12.6 术语表
SLYZ022 — TI 术语表。
这份术语表列出并解释术语、缩写和定义。
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TS5MP645
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13 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且
不会对此文档进行修订。如需获取此产品说明书的浏览器版本，请查阅左侧的导航栏。
24
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TS5MP645
www.ti.com.cn
ZHCSHH3B –JANUARY 2018–REVISED JULY 2018
PACKAGE OUTLINE
YFP0036
DSBGA - 0.5 mm max height
S
C
A
L
E
4
.
7
0
0
DIE SIZE BALL GRID ARRAY
B
E
A
BALL A1
CORNER
D: Max = 2.45 mm, Min = 2.39 mm
E: Max = 2.45 mm, Min = 2.39 mm
D
C
0.5 MAX
SEATING PLANE
0.05 C
BALL TYP
0.19
0.13
2 TYP
SYMM
F
E
D
C
SYMM
2
TYP
B
A
0.25
0.21
36X
0.015
C A
B
0.4 TYP
1
2
3
4
5
6
0.4 TYP
4222013/A 04/2015
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
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版权 © 2018, Texas Instruments Incorporated
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TS5MP645
ZHCSHH3B –JANUARY 2018–REVISED JULY 2018
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EXAMPLE BOARD LAYOUT
YFP0036
DSBGA - 0.5 mm max height
DIE SIZE BALL GRID ARRAY
(0.4) TYP
3
36
0.23)
1
2
4
5
6
A
(0.4) TYP
B
C
SYMM
D
E
F
SYMM
LAND PATTERN EXAMPLE
SCALE:25X
0.05 MAX
0.05 MIN
METAL UNDER
SOLDER MASK
( 0.23)
METAL
(
0.23)
SOLDER MASK
OPENING
SOLDER MASK
OPENING
NON-SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
NOT TO SCALE
4222013/A 04/2015
NOTES: (continued)
3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.
For more information, see Texas Instruments literature number SNVA009 (www.ti.com/lit/snva009).
www.ti.com
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TS5MP645
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ZHCSHH3B –JANUARY 2018–REVISED JULY 2018
EXAMPLE STENCIL DESIGN
YFP0036
DSBGA - 0.5 mm max height
DIE SIZE BALL GRID ARRAY
(0.4) TYP
36X ( 0.25)
(R0.05) TYP
4
1
2
3
5
6
A
B
(0.4) TYP
METAL
TYP
C
D
E
F
SYMM
SYMM
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
SCALE:30X
4222013/A 04/2015
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.
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版权 © 2018, Texas Instruments Incorporated
27
PACKAGE OPTION ADDENDUM
www.ti.com
7-Jan-2023
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TS5MP645NYFPR
TS5MP645YFPR
ACTIVE
ACTIVE
DSBGA
DSBGA
YFP
YFP
36
36
3000 RoHS & Green
3000 RoHS & Green
SNAGCU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 85
-40 to 85
TS5MP645
TS5MP645
Samples
Samples
SNAGCU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
7-Jan-2023
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
8-Jan-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TS5MP645NYFPR
TS5MP645YFPR
DSBGA
DSBGA
YFP
YFP
36
36
3000
3000
180.0
330.0
8.4
2.58
2.58
2.58
2.58
0.62
0.62
4.0
8.0
8.0
Q1
Q1
12.4
12.0
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
8-Jan-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TS5MP645NYFPR
TS5MP645YFPR
DSBGA
DSBGA
YFP
YFP
36
36
3000
3000
182.0
335.0
182.0
335.0
20.0
25.0
Pack Materials-Page 2
PACKAGE OUTLINE
YFP0036
DSBGA - 0.5 mm max height
S
C
A
L
E
4
.
7
0
0
DIE SIZE BALL GRID ARRAY
A
B
E
BALL A1
CORNER
D
C
0.5 MAX
SEATING PLANE
0.05 C
BALL TYP
0.19
0.13
2 TYP
SYMM
F
E
D: Max = 2.45 mm, Min = 2.39 mm
E: Max = 2.45 mm, Min = 2.39 mm
D
C
SYMM
2
TYP
B
A
0.25
0.21
0.015
36X
C A
B
0.4 TYP
1
2
3
4
5
6
0.4 TYP
4222013/A 04/2015
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
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EXAMPLE BOARD LAYOUT
YFP0036
DSBGA - 0.5 mm max height
DIE SIZE BALL GRID ARRAY
(0.4) TYP
3
36X ( 0.23)
(0.4) TYP
1
4
5
6
2
A
B
C
SYMM
D
E
F
SYMM
LAND PATTERN EXAMPLE
SCALE:25X
0.05 MAX
0.05 MIN
METAL UNDER
SOLDER MASK
(
0.23)
METAL
(
0.23)
SOLDER MASK
OPENING
SOLDER MASK
OPENING
NON-SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
NOT TO SCALE
4222013/A 04/2015
NOTES: (continued)
3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.
For more information, see Texas Instruments literature number SNVA009 (www.ti.com/lit/snva009).
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EXAMPLE STENCIL DESIGN
YFP0036
DSBGA - 0.5 mm max height
DIE SIZE BALL GRID ARRAY
(0.4) TYP
36X ( 0.25)
(R0.05) TYP
4
1
2
3
5
6
A
B
(0.4) TYP
METAL
TYP
C
D
E
F
SYMM
SYMM
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
SCALE:30X
4222013/A 04/2015
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.
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