TSB12LV23PZR [TI]
PCI BUS CONTROLLER, PQFP100, PLASTIC, QFP-100;
| 型号： | TSB12LV23PZR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | PCI BUS CONTROLLER, PQFP100, PLASTIC, QFP-100 时钟 数据传输 PC 驱动 外围集成电路 驱动器 |
| 文件： | 总84页 (文件大小：411K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Contents
Section
Title
Page
1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−1
1.1
1.2
1.3
1.4
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−1
Related Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−2
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−2
2
3
Terminal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−1
TSB12LV23 Controller Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . 3−1
3.1
3.2
3.3
3.4
3.5
3.6
3.7
3.8
3.9
PCI/CardBus Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . 3−3
Vendor ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−3
Device ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−4
PCI Command Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−4
PCI Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−5
Class Code and Revision ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . 3−6
Latency Timer and Class Cache Line Size Register . . . . . . . . . . . . . . 3−6
Header Type and BIST Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−7
OHCI Base Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−7
3.10 TI Extension Base Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−8
3.11 CIS Base Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−8
3.12 CardBus CIS Pointer Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−9
3.13 PCI Subsystem Identification Register . . . . . . . . . . . . . . . . . . . . . . . . . . 3−9
3.14 PCI Power Management Capabilities Pointer Register . . . . . . . . . . . . 3−10
3.15 Interrupt Line and Pin Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−10
3.16 MIN_GNT and MAX_LAT Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−11
3.17 PCI OHCI Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−11
3.18 Capability ID and Next Item Pointer Registers . . . . . . . . . . . . . . . . . . . 3−12
3.19 Power Management Capabilities Register . . . . . . . . . . . . . . . . . . . . . . 3−13
3.20 Power Management Control and Status Register . . . . . . . . . . . . . . . . 3−14
3.21 Power Management Extension Registers . . . . . . . . . . . . . . . . . . . . . . . 3−14
3.22 PCI Miscellaneous Configuration Register . . . . . . . . . . . . . . . . . . . . . . 3−15
3.23 Link Enhancement Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−16
3.24 Subsystem Access Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−17
3.25 GPIO Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−18
OHCI Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−1
4
4.1
4.2
4.3
4.4
OHCI Version Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−4
GUID ROM Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−5
Asynchronous Transmit Retries Register . . . . . . . . . . . . . . . . . . . . . . . 4−6
CSR Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−6
iii
4.5
4.6
4.7
4.8
4.9
CSR Compare Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−7
CSR Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−7
Configuration ROM Header Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−8
Bus Identification Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−8
Bus Options Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−9
4.10 GUID High Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−10
4.11 GUID Low Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−10
4.12 Configuration ROM Mapping Register . . . . . . . . . . . . . . . . . . . . . . . . . . 4−11
4.13 Posted Write Address Low Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−11
4.14 Posted Write Address High Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−12
4.15 Vendor ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−12
4.16 Host Controller Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−13
4.17 Self ID Buffer Pointer Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−14
4.18 Self ID Count Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−14
4.19 Isochronous Receive Channel Mask High Register . . . . . . . . . . . . . . 4−15
4.20 Isochronous Receive Channel Mask Low Register . . . . . . . . . . . . . . . 4−16
4.21 Interrupt Event Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−18
4.22 Interrupt Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−20
4.23 Isochronous Transmit Interrupt Event Register . . . . . . . . . . . . . . . . . . 4−21
4.24 Isochronous Transmit Interrupt Mask Register . . . . . . . . . . . . . . . . . . . 4−22
4.25 Isochronous Receive Interrupt Event Register . . . . . . . . . . . . . . . . . . . 4−22
4.26 Isochronous Receive Interrupt Mask Register . . . . . . . . . . . . . . . . . . . 4−23
4.27 Fairness Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−23
4.28 Link Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−24
4.29 Node Identification Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−25
4.30 PHY Layer Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−26
4.31 Isochronous Cycle Timer Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−27
4.32 Asynchronous Request Filter High Register . . . . . . . . . . . . . . . . . . . . . 4−28
4.33 Asynchronous Request Filter Low Register . . . . . . . . . . . . . . . . . . . . . 4−30
4.34 Physical Request Filter High Register . . . . . . . . . . . . . . . . . . . . . . . . . . 4−32
4.35 Physical Request Filter Low Register . . . . . . . . . . . . . . . . . . . . . . . . . . 4−34
4.36 Physical Upper Bound Register (Optional Register) . . . . . . . . . . . . . . 4−36
4.37 Asynchronous Context Control Register . . . . . . . . . . . . . . . . . . . . . . . . 4−37
4.38 Asynchronous Context Command Pointer Register . . . . . . . . . . . . . . 4−38
4.39 Isochronous Transmit Context Control Register . . . . . . . . . . . . . . . . . . 4−39
4.40 Isochronous Transmit Context Command Pointer Register . . . . . . . . 4−40
4.41 Isochronous Receive Context Control Register . . . . . . . . . . . . . . . . . . 4−40
4.42 Isochronous Receive Context Command Pointer Register . . . . . . . . 4−41
4.43 Isochronous Receive Context Match Register . . . . . . . . . . . . . . . . . . . 4−42
GPIO Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5−1
Serial EEPROM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6−1
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7−1
5
6
7
7.1
Absolute Maximum Ratings Over Operating
Temperature Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7−1
iv
7.2
7.3
Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 7−2
Electrical Characteristics Over Recommended
Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7−3
7.4
7.5
Switching Characteristics for PCI Interface . . . . . . . . . . . . . . . . . . . . . . 7−3
Switching Characteristics for PHY-Link Interface . . . . . . . . . . . . . . . . . 7−3
8
Mechanical Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8−1
List of Illustrations
Figure
Title
Page
2−1 Terminal Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−1
3−1 TSB12LV23 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−2
5−1 GPIO2 and GPIO3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5−1
List of Tables
Table
Title
Page
2−1 Signals Sorted by Pin Number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−2
2−2 Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−2
2−3 PCI System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−3
2−4 PCI Address and Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−3
2−5 PCI Interface Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−4
2−6 IEEE1394 PHY/Link . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−4
2−7 Miscellaneous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−5
3−1 Bit Field Access Tag Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−1
3−2 PCI Configuration Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−3
3−3 PCI Command Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−4
3−4 PCI Status Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−5
3−5 Class Code and Revision ID Register Description . . . . . . . . . . . . . . . . . . . . . 3−6
3−6 Latency Timer and Class Cache Line Size Register Description . . . . . . . . . 3−6
3−7 Header Type and BIST Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . 3−7
3−8 OHCI Base Address Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−7
3−9 CIS Base Address Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−8
3−10 CardBus CIS Pointer Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . 3−9
3−11 PCI Subsystem Identification Register Description . . . . . . . . . . . . . . . . . . . . 3−9
3−12 Interrupt Line and Pin Registers Description . . . . . . . . . . . . . . . . . . . . . . . . . 3−10
3−13 MIN_GNT and MAX_LAT Register Description . . . . . . . . . . . . . . . . . . . . . . . 3−11
3−14 PCI OHCI Control Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−11
3−15 Capability ID and Next Item Pointer Registers Description . . . . . . . . . . . . . 3−12
3−16 Power Management Capabilities Register Description . . . . . . . . . . . . . . . . 3−13
3−17 Power Management Control and Status Register Description . . . . . . . . . . 3−14
3−18 Power Management Extension Registers Description . . . . . . . . . . . . . . . . . 3−14
v
3−19 PCI Miscellaneous Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . 3−15
3−20 Link Enhancement Control Register Description . . . . . . . . . . . . . . . . . . . . . 3−16
3−21 Subsystem Access Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−17
3−22 General-Purpose Input/Output Control Register Description . . . . . . . . . . . 3−18
4−1 OHCI Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−1
4−2 OHCI Version Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−4
4−3 GUID ROM Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−5
4−4 Asynchronous Transmit Retries Register Description . . . . . . . . . . . . . . . . . . 4−6
4−5 CSR Control Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−7
4−6 Configuration ROM Header Register Description . . . . . . . . . . . . . . . . . . . . . . 4−8
4−7 Bus Options Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−9
4−8 Configuration ROM Mapping Register Description . . . . . . . . . . . . . . . . . . . . . 4−11
4−9 Posted Write Address Low Register Description . . . . . . . . . . . . . . . . . . . . . . . 4−11
4−10 Posted Write Address High Register Description . . . . . . . . . . . . . . . . . . . . . 4−12
4−11 Host Controller Control Register Description . . . . . . . . . . . . . . . . . . . . . . . . . 4−13
4−12 Self ID Count Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−14
4−13 Isochronous Receive Channel Mask High Register Description . . . . . . . . 4−15
4−14 Isochronous Receive Channel Mask Low Register Description . . . . . . . . . 4−16
4−15 Interrupt Event Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−18
4−16 Interrupt Mask Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−20
4−17 Isochronous Transmit Interrupt Event Register Description . . . . . . . . . . . . 4−21
4−18 Isochronous Receive Interrupt Event Register Description . . . . . . . . . . . . . 4−22
4−19 Fairness Control Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−23
4−20 Link Control Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−24
4−21 Node Identification Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−25
4−22 PHY Control Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−26
4−23 Isochronous Cycle Timer Register Description . . . . . . . . . . . . . . . . . . . . . . . 4−27
4−24 Asynchronous Request Filter High Register Description . . . . . . . . . . . . . . . 4−28
4−25 Asynchronous Request Filter Low Register Description . . . . . . . . . . . . . . . 4−30
4−26 Physical Request Filter High Register Description . . . . . . . . . . . . . . . . . . . . 4−32
4−27 Physical Request Filter Low Register Description . . . . . . . . . . . . . . . . . . . . 4−34
4−28 Asynchronous Context Control Register Description . . . . . . . . . . . . . . . . . . 4−37
4−29 Asynchronous Context Command Pointer Register Description . . . . . . . . 4−38
4−30 Isochronous Transmit Context Control Register Description . . . . . . . . . . . 4−39
4−31 Isochronous Receive Context Control Register Description . . . . . . . . . . . . 4−40
4−32 Isochronous Receive Context Match Register Description . . . . . . . . . . . . . 4−42
6−1 Registers and Bits Loadable through Serial EEPROM . . . . . . . . . . . . . . . . . 6−1
6−2 Serial EEPROM Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6−2
vi
1 Introduction
1.1 Description
The Texas Instruments TSB12LV23 is a PCI-to-1394 host controller compatible with the latest PCI Local Bus, PCI
Bus Power Management Interface, IEEE 1394-1995, and 1394 Open Host Controller Interface Specifications. The
chip provides the IEEE 1394 link function, and is compatible with serial bus data rates of 100 Mbits/s, 200 Mbits/s,
and 400 Mbits/s.
As required by the 1394 Open Host Controller Interface (OHCI) and IEEE 1394A Specifications, internal control
registers are memory mapped and non-prefetchable. The PCI configuration header is accessed through
configuration cycles specified by PCI, and provides Plug-and-Play (PnP) compatibility. Furthermore, the TSB12LV23
is compliant with the PCI Bus Power Management Interface Specification, per the PC 98 requirements. TSB12LV23
supports the D0, D2, and D3 power states.
The TSB12LV23 design provides PCI bus master bursting, and is capable of transferring a cacheline of data at 132
Mbytes/s after connection to the memory controller. Since PCI latency can be large even on a PCI Revision 2.1
system, deep FIFOs are provided to buffer 1394 data.
The TSB12LV23 provides physical write posting buffers and a highly tuned physical data path for SBP-2 performance.
The TSB12LV23 also provides multiple isochronous contexts, multiple cacheline burst transfers, advanced internal
arbitration, and bus holding buffers on the PHY/Link interface, thus, making the TSB12LV23 the best-in-class 1394
OHCI solution.
An advanced CMOS process is used to achieve low power consumption while operating at PCI clock rates up to
33 MHz.
1.2 Features
The TSB12LV23 supports the following features:
•
•
•
•
•
•
•
•
•
•
•
•
•
3.3-V core logic with universal PCI interfaces compatible with 3.3-V and 5-V PCI signaling environments
Supports serial bus data rates of 100, 200, and 400 Mbits/s
Provides bus-hold buffers on physical interface for low-cost single capacitor isolation
Supports physical write posting of up to three outstanding transactions
Serial ROM interface supports 2-wire devices
Supports external cycle timer control for customized synchronization
Implements PCI burst transfers and deep FIFOs to tolerate large host latency
Provides two general-purpose I/Os
Fabricated in advanced low-power CMOS process
Packaged in 100 LQFP (PZ)
Supports CLKRUN
Drop-in replacement for the TSB12LV22
Supports PCI and CardBus applications
1−1
1.3 Related Documents
•
•
•
•
•
1394 Open Host Controller Interface Specification
IEEE 1394-1995 and Compatible with Proposal 1394A
PC 98
PCI Bus Power Management Interface Specification (Revision 1.1)
PCI Local Bus Specification (Revision 2.2)
1.4 Ordering Information
ORDERING NUMBER
NAME
OHCI-Lynx PCI-Based IEEE 1394 Host Controller
VOLTAGE
PACKAGE
TSB12LV23
3.3 V, 5-V Tolerant I/Os
100-pin LQFP
1−2
2 Terminal Descriptions
This section provides the terminal descriptions for the TSB12LV23.
PZ PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
GND
GPIO2
GND
PCI_AD0
PCI_AD1
PCI_AD2
PCI_AD3
3.3 VCC
PCI_AD4
PCI_AD5
PCI_AD6
PCI_AD7
PCI_C/BE0
PCI_AD8
VCCP
PCI_AD9
PCI_AD10
GND
PCI_AD11
PCI_AD12
PCI_AD13
PCI_AD14
GPIO3
SCL
SDA
VCCP
CLKRUN
PCI_INTA/CINT
3.3 VCC
G_RST
GND
PCI_CLK
3.3 VCC
PCI_GNT
PCI_REQ
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
VCCP
PCI_PME/CSTSCHG
PCI_AD31
PCI_AD30
3.3 VCC
PCI_AD29
PCI_AD28
PCI_AD27
GND
3.3 VCC
PCI_AD15
PCI_C/BE1
PCI_PAR
PCI_AD26
PCI_SERR
Figure 2−1. Terminal Assignments
2−1
Table 2−1. Signals Sorted by Pin Number
NO.
1
TERMINAL NAME
NO.
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
TERMINAL NAME
PCI_AD25
PCI_AD24
PCI_C/BE3
PCI_IDSEL
GND
NO.
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
TERMINAL NAME
PCI_SERR
PCI_PAR
NO.
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
TERMINAL NAME
RST
GND
GPIO2
GPIO3
SCL
2
CARDBUS/CYCLEOUT
CYCLEIN
3
PCI_C/BE1
PCI_AD15
4
ISOLATED
5
SDA
3.3 V
3.3 V
CC
CC
6
V
CCP
PCI_AD23
PCI_AD22
PCI_AD21
PCI_AD20
PCI_AD14
PCI_AD13
PCI_AD12
PCI_AD11
GND
PHY_DATA7
PHY_DATA6
GND
7
CLKRUN
8
PCI_INTA/CINT
9
3.3 V
PHY_DATA5
PHY_DATA4
PHY_DATA3
CC
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
G_RST
GND
3.3 V
CC
PCI_AD19
PCI_AD18
PCI_AD17
PCI_AD10
PCI_AD9
PCI_CLK
V
CCP
3.3 V
V
CCP
PHY_DATA2
PHY_DATA1
PHY_DATA0
CC
PCI_GNT
PCI_REQ
V
CCP
PCI_AD8
PCI_C/BE0
PCI_AD7
PCI_AD6
PCI_AD5
PCI_AD4
PCI_AD16
PCI_C/BE2
GND
V
CCP
3.3 V
CC
PCI_PME/CSTSCHG
PCI_AD31
PHY_CTL1
PHY_CTL0
GND
PCI_FRAME
PCI_IRDY
PCI_TRDY
PCI_AD30
3.3 V
3.3 V
PHY_SCLK
CC
CC
PCI_AD29
PCI_AD28
PCI_AD27
GND
3.3 V
PCI_AD3
PCI_AD2
PCI_AD1
PCI_AD0
GND
3.3 V
CC
CC
PCI_DEVSEL
PCI_STOP
PCI_PERR
GND
PHY_LREQ
PHY_LINKON
PHY_LPS
GND
PCI_AD26
The terminals are grouped in tables by functionality, such as PCI system function, power supply function, etc. The
terminal numbers are also listed for convenient reference.
Table 2−2. Power Supply
TERMINAL
I/O
DESCRIPTION
NAME
NO.
1, 11, 24, 30,
42, 50, 60, 75,
83, 94, 100
GND
I
Device ground terminals
9, 13, 20, 35,
46, 55, 70, 80,
91, 96
3.3 V
I
I
3.3-V power supply terminals
CC
6, 16, 39, 63,
87
V
CCP
PCI signaling clamp voltage power input. PCI signals are clamped per the PCI Local Bus Specification.
2−2
Table 2−3. PCI System
TERMINAL
NAME
I/O
DESCRIPTION
NO.
PCI bus clock. Provides timing for all transactions on the PCI bus. All PCI signals are sampled at rising edge
of PCLK.
PCI_CLK
12
I
Global power reset. This reset brings all of the TSB12LV23 internal registers to their default states, including
those registers not reset by RST. When asserted, the device is completely nonfunctional.
When implementing wake capabilities from the 1394 host controller, it is necessary to implement two resets
to the TSB12LV23. G_RST should be a one-time power-on reset, and RST should be connected to the PCI
bus RST. If wake capabilities are not required, G_RST may be connected to the PCI bus RST (see RST,
terminal 76).
G_RST
10
8
I
O
I
Interrupt signal. This output indicates interrupts from the TSB12LV23 to the host.
This terminal is implemented as open-drain.
PCI_INTA/CINT
RST
PCI reset. When this bus reset is asserted, the TSB12LV23 places all output buffers in a high impedance state
and resets all internal registers except device power management context- and vendor-specific bits initialized
by host power-on software. When asserted, the device is completely nonfunctional.
76
If this terminal is implemented, then it should be connected to the PCI bus RST signal. Otherwise, it should
be pulled high to the link V
terminal 10).
through a 4.7-kΩ resistor, or strapped to the G_RST terminal (see G_RST,
CC
Table 2−4. PCI Address and Data
TERMINAL
I/O
DESCRIPTION
NAME
NO.
PCI_AD31
PCI_AD30
PCI_AD29
PCI_AD28
PCI_AD27
PCI_AD26
PCI_AD25
PCI_AD24
PCI_AD23
PCI_AD22
PCI_AD21
PCI_AD20
PCI_AD19
PCI_AD18
PCI_AD17
PCI_AD16
PCI_AD15
PCI_AD14
PCI_AD13
PCI_AD12
PCI_AD11
PCI_AD10
PCI_AD9
PCI_AD8
PCI_AD7
PCI_AD6
PCI_AD5
PCI_AD4
PCI_AD3
PCI_AD2
PCI_AD
18
19
21
22
23
25
26
27
31
32
33
34
36
37
38
40
54
56
57
58
59
61
62
64
66
67
68
69
71
72
73
74
PCI address/data bus. These signals make up the multiplexed PCI address and data bus on the PCI interface
during the address phase of a PCI cycle, AD31−AD0 contain a 32-bit address or other destination information.
During the data phase, AD31−AD0 contain data.
I/O
PCI_AD0
2−3
PCI_C/BE0
PCI_C/BE1
PCI_C/BE2
PCI_C/BE3
65
53
41
28
PCI bus commands and byte enables. The command and byte enable signals are multiplexed on the same PCI
terminals. During the address phase of a bus cycle C/BE3−C/BE0 defines the bus command. During the data
phase, this 4-bit bus is used as byte enables.
I/O
I/O
PCI parity. In all PCI bus read and write cycles, the TSB12LV23 calculates even parity across the AD and C/BE
buses. As an initiator during PCI cycles, the TSB12LV23 outputs this parity indicator with a one PCLK delay. As
a target during PCI cycles, the calculated parity is compared to the initiator’s parity indicator; a miscompare can
result in a parity error assertion (PERR).
PCI_PAR
52
2−4
Table 2−5. PCI Interface Control
TERMINAL
NAME
I/O
DESCRIPTION
NO.
PCI device select. The TSB12LV23 asserts this signal to claim a PCI cycle as the target device. As a PCI
PCI_DEVSEL
PCI_FRAME
47
I/O initiator, the TSB12LV23 monitors this signal until a target responds. If no target responds before time-out
occurs, then the TSB12LV23 terminates the cycle with an initiator abort.
PCI cycle frame. This signal is driven by the initiator of a PCI bus cycle. FRAME is asserted to indicate that a
I/O bus transaction is beginning, and data transfers continue until while this signal is asserted. When FRAME is
deasserted, the PCI bus transaction is in the final data phase.
43
PCI bus grant. This signal is driven by the PCI bus arbiter to grant the TSB12LV23 access to the PCI bus after
PCI_GNT
PCI_IDSEL
PCI_IRDY
14
29
44
I
I
the current data transaction has completed. This signal may or may not follow a PCI bus request depending
upon the PCI bus parking algorithm.
Initialization device select. IDSEL selects the TSB12LV23 during configuration space accesses. IDSEL can be
connected to 1 of the upper 24 PCI address lines on the PCI bus.
PCI initiator ready. IRDY indicates the PCI bus initiator’s ability to complete the current data phase of the
I/O transaction. A data phase is completed upon a rising edge of PCLK where both IRDY and TRDY are asserted;
until which wait states are inserted.
PCI cycle stop signal. This signal is driven by a PCI target to request the initiator to stop the current PCI bus
I/O transaction. This signal is used for target disconnects, and is commonly asserted by target devices which do
not support burst data transfers.
PCI_STOP
48
7
Clock run. This terminal provides clock control through the CLKRUN protocol. An internal pulldown resistor is
I/O implemented on this terminal.
CLKRUN
This terminal is implemented as open-drain.
PCI parity error indicator. This signal is driven by a PCI device to indicate that calculated parity does not match
PAR when enabled through the command register.
PCI_PERR
49
17
15
I/O
PCI_PME/
CSTSCHG
PME or card status change. This terminal indicates wake events to the host. When in a CardBus configuration,
per the CARDBUS sample, the CSTSCHG output is an active high.
O
PCI bus request. Asserted by the TSB12LV23 to request access to the bus as an initiator. The host arbiter
asserts the GNT signal when the TSB12LV23 has been granted access to the bus.
PCI_REQ
O
PCI system error. Output pulsed from the TSB12LV23 when enabled indicating an address parity error has
PCI_SERR
51
45
O
occurred. The TSB12LV23 needs not be the target of the PCI cycle to assert this signal.
This terminal is implemented as open-drain.
PCI target ready. TRDY indicates the PCI bus target’s ability to complete the current data phase of the
I/O transaction. A data phase is completed upon a rising edge of PCLK where both IRDY and TRDY are asserted;
until which wait states are inserted.
PCI_TRDY
Table 2−6. IEEE1394 PHY/Link
TERMINAL
NAME
I/O
DESCRIPTION
NO.
Phy-link interface control. These bidirectional signals control passage of information between the two devices.
I/O The TSB12LV23 can only drive these terminals after the PHY has granted permission following a link request
(LREQ).
PHY_CTL1
PHY_CTL0
92
93
PHY_DATA7
PHY_DATA6
PHY_DATA5
PHY_DATA4
PHY_DATA3
PHY_DATA2
PHY_DATA1
PHY_DATA0
81
82
84
85
86
88
89
90
Phy-link interface data. These bidirectional signals pass data between the TSB12LV23 and the PHY device.
These terminals are driven by the TSB12LV23 on transmissions and are driven by the PHY on reception. Only
DATA1−DATA0 are valid for 100-Mbit speeds, DATA3−DATA0 are valid for 200-Mbit speeds, and
DATA7−DATA0 are valid for 400-Mbit speeds.
I/O
PHY_SCLK
PHY_LREQ
PHY_LINKON
PHY_LPS
95
97
98
99
I
System clock. This input from the PHY provides a 49.152 MHz clock signal for data synchronization.
Link request. This signal is driven by the TSB12LV23 to initiate a request for the PHY to perform some service.
O
I/O LinkOn wake indication. Used and defined by 1394A and 3.3-V signaling is required.
I/O Link power status. Used and defined by 1394A and 3.3-V signaling is required.
2−5
Table 2−7. Miscellaneous
TERMINAL
NAME
I/O
DESCRIPTION
NO.
Serial data. The TSB12LV23 determines whether a two-wire serial ROM, or no serial ROM is implemented at
reset. If a two-wire serial ROM is detected, then this terminal provides the SDA serial data signaling. This
terminal must be wired low to indicate no serial ROM is present.
SDA
5
I/O
This terminal is implemented as open-drain, and for normal operation (an EEPROM is implemented in the
design), this terminal should be pulled high to the EEPROM V with a 2.7-kΩ resistor. Otherwise, it should
CC
be pulled low to ground with a 220-Ω resistor.
Serial clock. The TSB12LV23 determines whether a two-wire, or no serial ROM is implemented at reset. If a
two-wire serial ROM is implemented, then this terminal provides the SCL serial clock signaling.
SCL
4
I/O
This terminal is implemented as open-drain, and for normal operation (an EEPROM is implemented in the
design), this terminal should be pulled high to the EEPROM V with a 2.7-kΩ resistor. Otherwise, it should
CC
be pulled low to ground with a 220-Ω resistor.
For isolated designs, the bus holders are implemented by pulling this terminal low to ground with a 220-Ω
ISOLATED
CYCLEIN
79
78
I
resistor. If this terminal is not emplemented, it should be pulled high to the link V with a 4.7-kΩ resistor.
CC
The CYCLEIN terminal allows an external 8-kHz clock to be used as a cycle timer for synchronization with other
system devices.
I/O
If this terminal is not implemented, then it should be pulled high to the link V through a 4.7-kΩ resistor.
CC
This terminal is sampled when G_RST is asserted, and it selects between PCI buffers and CardBus buffers.
I/O After reset, this terminal may also function as CYCLEOUT which provides an 8 kHz cycle timer synchronization
signal.
CARDBUS/
CYCLEOUT
77
General-purpose I/O [3]. This terminal defaults as an input and if it is not implemented, then it is recommended
that it be pulled low to ground with a 220-Ω resistor.
GPIO3
GPIO2
3
2
I/O
General-purpose I/O [2]. This terminal defaults as an input and if it is not implemented, then it is recommended
that it be pulled low to ground with a 220-Ω resistor.
I/O
2−6
2−7
3 TSB12LV23 Controller Programming Model
This section describes the internal registers used to program the TSB12LV23, including both PCI configuration
registers and OHCI registers (see Section 4). All registers are detailed in the same format: a brief description for each
register, followed by the register offset and a bit table describing the reset state for each register.
A bit description table, typically included, indicates bit field names, a detailed field description, and field access tags.
Table 3−1 describes the field access tags.
Table 3−1. Bit Field Access Tag Descriptions
ACCESS TAG
NAME
Read
Write
Set
MEANING
Field may be read by software.
R
W
S
Field may be written by software to any value.
Field may be set by a write of 1. Writes of 0 have no effect.
Field may be cleared by a write of 1. Writes of 0 have no effect.
Field may be autonomously updated by the TSB12LV23.
C
U
Clear
Update
A simplified block diagram of the TSB12LV23 is provided in Figure 3−1.
3−1
Serial
ROM
PCI
Target
SM
Internal
Registers
OHCI PCI Power
Mgmt & CLKRUN
GPIOs
MISC
Interface
ISO Transmit
Contexts
Transmit
FIFO
Async Transmit
Contexts
Physical DMA
& Response
Link
Transmit
Resp
Timeout
Receive
Acknowledge
PCI
Host
Bus
Central
Arbiter
&
PCI
Initiator
SM
PHY
Cycle Start
Generator &
Cycle Monitor
Interface
Register
Access
& Status
Monitor
CRC
PHY /
Link
Interface
Synthesized
Bus Reset
Request
Filters
Link
General
Receive
Request Receive
Receive
FIFO
Async Response
Receive
ISO Receive
Contexts
Figure 3−1. TSB12LV23 Block Diagram
3−2
3.1 PCI/CardBus Configuration Registers
The TSB12LV23 is a single-function PCI device that can be configured as either a PCI or CardBus device. The
configuration header is compliant with the PCI Local Bus Specification as a standard header. Table 3−2 illustrates
the PCI configuration header that includes both the predefined portion of the configuration space and the user
definable registers. Most of the registers in this configuration have not changed from the TSB12LV22 design.
Table 3−2. PCI Configuration Register Map
REGISTER NAME
OFFSET
00h
Device ID
Status
Vendor ID
Command
04h
Class code
Header type
Revision ID
08h
BIST
Latency timer
Cache line size
0Ch
10h
OHCI registers base address
TI extension registers base address
CIS base address
Reserved
14h
18h
1Ch
20h
Reserved
Reserved
24h
CardBus CIS pointer
28h
Subsystem ID
Subsystem vendor ID
2Ch
30h
Reserved
Reserved
Capabilities pointer
Interrupt line
34h
Reserved
38h
Maximum latency Minimum grant
PCI OHCI control register
Power management capabilities Next item pointer
PM data PMCSR_BSE
Reserved
Interrupt pin
3Ch
40h
Capability ID
44h
Power management CSR
48h
4C−ECh
F0h
F4h
F8h
FCh
PCI miscellaneous configuration register
Link_Enhancements register
Subsystem ID alias
Subsystem vendor ID alias
Reserved
GPIO3
GPIO2
3.2 Vendor ID Register
The vendor ID register contains a value allocated by the PCI SIG and identifies the manufacturer of the PCI device.
The vendor ID assigned to Texas Instruments is 104Ch.
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Type
Default
Vendor ID
R
0
R
0
R
0
R
1
R
0
R
0
R
0
R
0
R
0
R
1
R
0
R
0
R
1
R
1
R
0
R
0
Register:
Type:
Offset:
Default:
Vendor ID
Read-only
00h
104Ch
3−3
3.3 Device ID Register
The device ID register contains a value assigned to the TSB12LV23 by Texas Instruments. The device identification
for the TSB12LV23 is 8019.
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Type
Default
Device ID
R
1
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
1
R
1
R
0
R
0
R
1
Register:
Type:
Offset:
Default:
Device ID
Read-only
02h
8019h
3.4 PCI Command Register
The command register provides control over the TSB12LV23 interface to the PCI bus. All bit functions adhere to the
definitions in the PCI Local Bus Specification, as seen in the following bit descriptions.
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Type
Default
PCI command
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R/W
0
R
0
R/W
0
R
0
R/W
0
R
0
R/W
0
R/W
0
R
0
Register:
Type:
Offset:
Default:
PCI command
Read/Write
04h
0000h
Table 3−3. PCI Command Register Description
BIT
FIELD NAME
TYPE
DESCRIPTION
15−10 RSVD
R
Reserved. Bits 15−10 return 0s when read.
Fast back-to-back enable. The TSB12LV23 does not generate fast back-to-back transactions, thus
this bit returns 0 when read.
9
8
7
6
5
FBB_ENB
R
R/W
R
SERR enable. When this bit is set, the TSB12LV23 SERR driver is enabled. SERR can be asserted
after detecting an address parity error on the PCI bus.
SERR_ENB
STEP_ENB
PERR_ENB
VGA_ENB
Address/data stepping control. The TSB12LV23 does not support address/data stepping, thus this bit
is hardwired to 0.
Parity error enable. When this bit is set, the TSB12LV23 is enabled to drive PERR response to parity
errors through the PERR signal.
R/W
R
VGA palette snoop enable. The TSB12LV23 does not feature VGA palette snooping. This bit returns 0
when read.
Memory write and invalidate enable. When this bit is set, the TSB12LV23 is enabled to generate MWI
PCI bus commands. If this bit is reset, then the TSB12LV23 generates memory write commands
instead.
4
MWI_ENB
R/W
Special cycle enable. The TSB12LV23 function does not respond to special cycle transactions. This bit
returns 0 when read.
3
2
1
SPECIAL
R
MASTER_ENB
MEMORY_ENB
R/W
R/W
Bus master enable. When this bit is set, the TSB12LV23 is enabled to initiate cycles on the PCI bus.
Memory response enable. Setting this bit enables the TSB12LV23 to respond to memory cycles on the
PCI bus. This bit must be set to access OHCI registers.
I/O space enable. The TSB12LV23 does not implement any I/O mapped functionality; thus, this bit re-
turns 0 when read.
0
IO_ENB
R
3−4
3.5 PCI Status Register
The status register provides status over the TSB12LV23 interface to the PCI bus. All bit functions adhere to the
definitions in the PCI Local Bus Specification, as seen in the following bit descriptions.
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Type
Default
PCI status
RCU RCU RCU RCU RCU
R
0
R
1
RCU
R
0
R
0
R
0
R
1
R
0
R
0
R
0
R
0
0
0
0
0
0
0
Register:
Type:
Offset:
Default:
PCI status
Read/Clear/Update
06h
0210h
Table 3−4. PCI Status Register Description
BIT
FIELD NAME
TYPE
DESCRIPTION
15
PAR_ERR
RCU
Detected parity error. This bit is set when a parity error is detected, either address or data parity errors.
Signaled system error. This bit is set when SERR is enabled and the TSB12LV23 has signaled a
system error to the host.
14
13
SYS_ERR
RCU
RCU
RCU
RCU
R
Received master abort. This bit is set when a cycle initiated by the TSB12LV23 on the PCI bus has been
terminated by a master abort.
MABORT
Received target abort. This bit is set when a cycle initiated by the TSB12LV23 on the PCI bus was
terminated by a target abort.
12
TABORT_REC
TABORT_SIG
PCI_SPEED
Signaled target abort. This bit is set by the TSB12LV23 when it terminates a transaction on the PCI bus
with a target abort.
11
DEVSEL timing. Bits 10−9 encode the timing of DEVSEL and are hardwired to 01b indicating that the
TSB12LV23 asserts this signal at a medium speed on nonconfiguration cycle accesses.
10−9
Data parity error detected. This bit is set when the following conditions have been met:
a. PERR was asserted by any PCI device including the TSB12LV23
8
DATAPAR
RCU
b. The TSB12LV23 was the bus master during the data parity error
c. The parity error response bit is set in the command register (see Section 3.4)
Fast back-to-back capable. The TSB12LV23 cannot accept fast back-to-back transactions; thus, this
bit is hardwired to 0.
7
6
5
FBB_CAP
UDF
R
R
R
User definable features (UDF) supported. The TSB12LV23 does not support the UDF; thus, this bit is
hardwired to 0.
66 MHz capable. The TSB12LV23 operates at a maximum PCLK frequency of 33 MHz; therefore, this
bit is hardwired to 0.
66MHZ
Capabilities list. This bit returns 1 when read, indicating that capabilities additional to standard PCI are
implemented. The linked list of PCI power management capabilities is implemented in this function.
4
CAPLIST
RSVD
R
R
3−0
Reserved. Bits 3−0 return 0s when read.
3−5
3.6 Class Code and Revision ID Register
The class code and revision ID register categorizes the TSB12LV23 as a serial bus controller (0Ch), controlling an
IEEE1394 bus (00h), with an OHCI programming model (10h). Furthermore, the TI chip revision is indicated in the
lower byte.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Type
Default
Bit
Class code and revision ID
R
0
R
0
R
0
R
0
R
1
R
1
R
0
9
R
0
8
R
0
7
R
0
6
R
0
5
R
0
4
R
0
3
R
0
2
R
0
1
R
0
0
15
14
13
12
11
10
Name
Type
Default
Class code and revision ID
R
0
R
0
R
0
R
1
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
Register:
Type:
Offset:
Default:
Class code and revision ID
Read-only
08h
0C00 1000h
Table 3−5. Class Code and Revision ID Register Description
BIT
FIELD NAME
TYPE
DESCRIPTION
Base class. This field returns 0Ch when read, which broadly classifies the function as a serial bus
controller.
31−24 BASECLASS
23−16 SUBCLASS
R
Subclass. This field returns 00h when read, which specifically classifies the function as controlling an
IEEE1394 serial bus.
R
Programming interface. This field returns 10h when read, indicating that the programming model is
compliant with the 1394 Open Host Controller Interface Specification.
15−8
7−0
PGMIF
R
R
CHIPREV
Silicon revision. This field returns 00h when read, indicating the silicon revision of the TSB12LV23.
3.7 Latency Timer and Class Cache Line Size Register
The latency timer and class cache line size register is programmed by host BIOS to indicate system cache line size
and the latency timer associated with the TSB12LV23.
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Type
Default
Latency timer and class cache line size
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Register:
Type:
Offset:
Default:
Latency timer and class cache line size
Read/Write
0Ch
0000h
Table 3−6. Latency Timer and Class Cache Line Size Register Description
BIT
FIELD NAME
TYPE
DESCRIPTION
PCI latency timer. The value in this register specifies the latency timer for the TSB12LV23, in units of
PCI clock cycles. When the TSB12LV23 is a PCI bus initiator and asserts FRAME, the latency timer
begins counting from zero. If the latency timer expires before the TSB12LV23 transaction has
terminated, then the TSB12LV23 terminates the transaction when its GNT is deasserted.
15−8
LATENCY_TIMER
R/W
Cache line size. This value is used by the TSB12LV23 during memory write and invalidate, memory
read line, and memory read multiple transactions.
7−0
CACHELINE_SZ
R/W
3−6
3.8 Header Type and BIST Register
The header type and BIST register indicates the TSB12LV23 PCI header type, and indicates no built-in self test.
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Type
Default
Header type and BIST
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
Register:
Type:
Offset:
Default:
Header type and BIST
Read-only
0Eh
0000h
Table 3−7. Header Type and BIST Register Description
BIT
FIELD NAME
TYPE
DESCRIPTION
Built-in self test. The TSB12LV23 does not include a built-in self test; thus, this field returns 00h when
read.
15−8
BIST
HEADER_TYPE
R
R
PCI header type. The TSB12LV23 includes the standard PCI header, and this is communicated by re-
turning 00h when this field is read.
7−0
3.9 OHCI Base Address Register
The OHCI base address register is programmed with a base address referencing the memory-mapped OHCI control.
When BIOS writes all 1s to this register, the value read back is FFFF F800h, indicating that at least 2K bytes of memory
address space are required for the OHCI registers.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Type
Default
Bit
OHCI base address
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Type
Default
OHCI address
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
Register:
Type:
Offset:
Default:
OHCI base address
Read/Write
10h
0000 0000h
Table 3−8. OHCI Base Address Register Description
BIT
FIELD NAME
TYPE
DESCRIPTION
OHCI register pointer. Specifies the upper 21 bits of the 32-bit OHCI base address register.
31−11
OHCIREG_PTR
R/W
OHCI register size. This field returns 0s when read, indicating that the OHCI registers require a
2-Kbyte region of memory.
10−4
3
OHCI_SZ
OHCI_PF
R
OHCI register prefetch. This bit returns 0 when read, indicating that the OHCI registers are
nonprefetchable.
R
R
R
OHCI memory type. This field returns 0s when read, indicating that the OHCI base address register is
32 bits wide and mapping can be done anywhere in the 32-bit memory space.
2−1
0
OHCI_MEMTYPE
OHCI_MEM
OHCI memory indicator. This bit returns 0 when read, indicating that the OHCI registers are mapped
into system memory space.
3−7
3.10 TI Extension Base Address Register
The TI extension base address register is programmed with a base address referencing the memory-mapped TI
extension registers. Refer to the OHCI base address register (see Section 3.9) for bit field details.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Type
Default
Bit
TI extension base address
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Type
Default
TI extension base address
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
Register:
Type:
Offset:
Default:
TI extension base address
Read/Write
14h
0000 0000h
3.11 CIS Base Address Register
If CARDBUS is sampled high on a PCI reset, then this 32-bit register returns 0s when read. If CARDBUS is sampled
low, then this register is to be programmed with a base address referencing the memory mapped CIS. This register
must be programmed with a nonzero value before the CIS may be accessed.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Type
Default
Bit
CIS base address
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Type
Default
CIS base address
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
Register:
Type:
Offset:
Default:
CIS base address
Read/Write
18h
0000 0000h
Table 3−9. CIS Base Address Register Description
BIT
FIELD NAME
TYPE
DESCRIPTION
CIS base address. Specifies the upper 21 bits of the 32-bit CIS base address. If the CARDBUS input is
sampled high on a PCI reset, then this field is read-only, returning 0s when read.
31−11 CIS_BASE
R/W
R
CIS address space size. This field returns 0s when read, indicating that the CIS space requires a
2-Kbyte region of memory.
10−4
CIS_SZ
CIS_PF
CIS prefetch. This bit returns 0 when read, indicating that the CIS is nonprefetchable. Furthermore, the
CIS is a byte-accessible address space, and double-word or 16-bit word access yields indeterminate
results.
3
R
CIS memory type. This field returns 0s when read, indicating that the CIS base address register is
32 bits wide and mapping can be done anywhere in the 32-bit memory space.
2−1
CIS_MEMTYPE
CIS_MEM
R
R
CIS memory indicator. This bit returns 0 when read, indicating that the CIS is mapped into system
memory space.
0
3−8
3.12 CardBus CIS Pointer Register
The CARDBUS input to the TSB12LV23 is sampled at PCI reset to determine the TSB12LV23 application. If
CARDBUS is sampled high, then this register is read-only returning 0s when read. If CARDBUS is sampled low, then
this register is the CardBus card information structure pointer.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Type
Default
Bit
CardBus CIS pointer
R
0
R
0
R
0
R
0
R
0
R
0
R
0
9
R
0
8
R
0
7
R
0
6
R
0
5
R
0
4
R
0
3
R
0
2
R
0
1
R
0
0
15
14
13
12
11
10
Name
Type
Default
CardBus CIS pointer
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
x
R
0
Register:
Type:
Offset:
Default:
CardBus CIS pointer
Read-only
28h
0000 000xh
Table 3−10. CardBus CIS Pointer Register Description
BIT
FIELD NAME
TYPE
DESCRIPTION
Since the CIS is not implemented as a ROM image, this field returns 0s when read.
31−28 ROM_IMAGE
R
This field indicates the offset into the CIS address space where the CIS begins, and bits 7−3 are loaded
from the serial ROM field CIS_Offset (7−3). This implementation allows the TSB12LV23 to produce
serial ROM addresses equal to the lower PCI address byte to acquire data from the serial ROM.
27−3
2−0
CIS_OFFSET
R
This field indicates the address space where the CIS resides and returns 010b if CARDBUS is
sampled asserted during a PCI reset. If CARDBUS is sampled high during a PCI reset, then this field
returns 000b when read. Thus, bit 1 is implemented as the logical inverse of the CARDBUS input.
CIS_INDICATOR
R
3.13 PCI Subsystem Identification Register
The PCI subsystem identification register is used for system and option card identification purposes. This register
can be initialized from the serial EEPROM or programmed via the subsystem ID and subsystem vendor ID alias
registers at offset 0XFC.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Type
Default
Bit
PCI subsystem identification
RU
0
RU
0
RU
0
RU
0
RU
0
RU
0
RU
0
RU
0
RU
0
RU
0
RU
0
RU
0
RU
0
RU
0
RU
0
RU
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Type
Default
PCI subsystem identification
RU
0
RU
0
RU
0
RU
0
RU
0
RU
0
RU
0
RU
0
RU
0
RU
0
RU
0
RU
0
RU
0
RU
0
RU
0
RU
0
Register:
Type:
Offset:
Default:
PCI subsystem identification
Read/Update
2Ch
0000 0000h
Table 3−11. PCI Subsystem Identification Register Description
BIT
FIELD NAME
TYPE
RU
DESCRIPTION
31−16
15−0
OHCI_SSID
Subsystem device ID. This field indicates the subsystem device ID.
Subsystem vendor ID. This field indicates the subsystem vendor ID.
OHCI_SSVID
RU
3−9
3.14 PCI Power Management Capabilities Pointer Register
The PCI power management capabilities pointer register provides a pointer into the PCI configuration header where
the PCI power management register block resides. The TSB12LV23 configuration header double-words at offsets
44h and 48h provide the power management registers. This register is read-only and returns 44h when read.
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
PCI power management capabilities pointer
R
0
R
1
R
0
R
0
R
0
R
1
R
0
R
0
Register:
Type:
Offset:
Default:
PCI power management capabilities pointer
Read-only
34h
44h
3.15 Interrupt Line and Pin Registers
The interrupt line and pin register is used to communicate interrupt line routing information.
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Type
Default
Interrupt line and pin
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
1
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Register:
Type:
Offset:
Default:
Interrupt line and pin
Read/Write
3Ch
0100h
Table 3−12. Interrupt Line and Pin Registers Description
BIT
FIELD NAME
TYPE
DESCRIPTION
Interrupt pin register. This register returns 01h when read, indicating that the TSB12LV23 PCI function
signals interrupts on the INTA pin.
15−8
INTR_PIN
R
Interrupt line register. This register is programmed by the system and indicates to software to which
interrupt line the TSB12LV23 INTA is connected.
7−0
INTR_LINE
R/W
3−10
3.16 MIN_GNT and MAX_LAT Register
The MIN_GNT and MAX_LAT register is used to communicate to the system the desired setting of the latency timer
register (see Section 3.7). If a serial ROM is detected, then the contents of this register are loaded through the serial
ROM interface after a PCI reset. If no serial ROM is detected, then this register returns a default value that
corresponds to the MIN_GNT = 2, MAX_LAT = 4.
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Type
Default
MIN_GNT and MAX_LAT
RU
0
RU
0
RU
0
RU
0
RU
0
RU
0
RU
1
RU
0
RU
0
RU
0
RU
0
RU
0
RU
0
RU
0
RU
1
RU
0
Register:
Type:
Offset:
Default:
MIN_GNT and MAX_LAT
Read/Update
3Eh
0202h
Table 3−13. MIN_GNT and MAX_LAT Register Description
BIT
FIELD NAME
TYPE
DESCRIPTION
Maximum latency. The contents of this register may be used by host BIOS to assign an arbitration
priority-level to the TSB12LV23. The default for this register indicates that the TSB12LV23 may need to
access the PCI bus as often as every 0.25 μs; thus, an extremely high priority level is requested. The
contents of this field may also be loaded through the serial ROM.
15−8
MAX_LAT
RU
RU
Minimum grant. The contents of this register may be used by host BIOS to assign a latency timer register
value to the TSB12LV23. The default for this register indicates that the TSB12LV23 may need to sustain
burst transfers for nearly 64 μs; thus, requesting a large value be programmed in the TSB12LV23 latency
timer register (see Section 3.7).
7−0
MIN_GNT
3.17 PCI OHCI Control Register
The PCI OHCI control register is defined by the 1394 Open Host Controller Interface Specification and provides a
bit for big endian PCI support.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Type
Default
Bit
PCI OHCI control
R
0
R
0
R
0
R
0
R
0
R
0
R
0
9
R
0
8
R
0
7
R
0
6
R
0
5
R
0
4
R
0
3
R
0
2
R
0
1
R
0
0
15
14
13
12
11
10
Name
Type
Default
PCI OHCI control
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R/W
0
Register:
Type:
Offset:
Default:
PCI OHCI control
Read/Write
40h
0000 0000h
Table 3−14. PCI OHCI Control Register Description
BIT
FIELD NAME
TYPE
DESCRIPTION
31−1
RSVD
R
Reserved. Bits 31−1 return 0s when read.
When this bit is set, all quadlets read from and written to the PCI interface are byte swapped (big
endian).
0
GLOBAL_SWAP
R/W
3−11
3.18 Capability ID and Next Item Pointer Registers
The capability ID and next item pointer register identifies the linked list capability item and provides a pointer to the
next capability item.
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Type
Default
Capability ID and next item pointer
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
1
Register:
Type:
Offset:
Default:
Capability ID and next item pointer
Read-only
44h
0001h
Table 3−15. Capability ID and Next Item Pointer Registers Description
BIT
FIELD NAME
TYPE
DESCRIPTION
Next item pointer. The TSB12LV23 supports only one additional capability that is communicated to
the system through the extended capabilities list; thus, this field returns 00h when read.
15−8
NEXT_ITEM
R
Capability identification. This field returns 01h when read, which is the unique ID assigned by the PCI
SIG for PCI power management capability.
7−0
CAPABILITY_ID
R
3−12
3.19 Power Management Capabilities Register
The power management capabilities register indicates the capabilities of the TSB12LV23 related to PCI power
management.
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Type
Default
Power management capabilities
RU
0
RU
1
RU
1
RU
0
RU
0
RU
1
R
0
R
0
R
0
R
0
R
0
R
1
R
0
R
0
R
0
R
1
Register:
Type:
Offset:
Default:
Power management capabilities
Read/Update
46h
6411h
Table 3−16. Power Management Capabilities Register Description
BIT
FIELD NAME
TYPE
DESCRIPTION
PME support from D3
. When this bit is set, the TSB12LV23 generates a PME wake event from
COLD
15
PME_D3COLD
RU
D3
. This bit state is dependent upon the TSB12LV23 V
implementation and may be
COLD
AUX
configured by host software using the PCI miscellaneous configuration register (see Section 3.22).
PME support. This 4-bit field indicates the power states from which the TSB12LV23 may assert PME.
This field returns a value of 1100b by default, indicating that PME may be asserted from the D3
D2 power states. Bit 13 may be modified by host software using the PCI miscellaneous configuration
register (see Section 3.22).
and
HOT
14−11
PME_SUPPORT
RU
D2 support. This bit returns a 1 when read, indicating that the TSB12LV23 does not support the D2
power state.
10
9
D1_SUPPORT
D1_SUPPORT
RU
R
D1 support. This bit returns a 0 when read, indicating that the TSB12LV23 does not support the D1
power state.
Dynamic data support. This bit returns a 0 when read, indicating that the TSB12LV23 does not report
dynamic power consumption data.
8
DYN_DATA
RSVD
R
R
7−6
Reserved. Bits 7−6 return 0s when read.
Device specific initialization. This bit returns 0 when read, indicating that the TSB12LV23 does not
require special initialization beyond the standard PCI configuration header before a generic class
driver is able to use it.
5
DSI
R
Auxiliary power source. Since the TSB12LV23 does not support PME generation in the D3
state, this bit returns 0 when read.
device
COLD
4
3
AUX_PWR
PME_CLK
R
R
R
PME clock. This bit returns 0 when read, indicating that no host bus clock is required for the
TSB12LV23 to generate PME.
Power management version. This field returns 001b when read, indicating that the TSB12LV23 is
compatible with the registers described in the PCI Bus Power Management Interface Specification.
2−0
PM_VERSION
3−13
3.20 Power Management Control and Status Register
The power management control and status register implements the control and status of the PCI power management
function. This register is not affected by the internally generated reset caused by the transition from the D3
state.
to D0
HOT
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Type
Default
Power management control and status
RC
0
R
0
R
0
R
0
R
0
R
0
R
0
R/W
0
R
0
R
0
R
0
R
0
R
0
R
0
R/W
0
R/W
0
Register:
Type:
Offset:
Default:
Power management control and status
Read/Write/Clear
48h
0000h
Table 3−17. Power Management Control and Status Register Description
BIT
FIELD NAME
TYPE
DESCRIPTION
This bit is set when the TSB12LV23 would normally be asserting the PME signal, independent of the
state of the PME_ENB bit. This bit is cleared by a write back of 1, and this also clears the PME signal
driven by the TSB12LV23. Writing a 0 to this bit has no effect.
15
PME_STS
RC
Dynamic data control. This field returns 0s when read since the TSB12LV23 does not report dynamic
data.
14−9
DYN_CTRL
PME_ENB
R
PME enable. This bit enables the function to assert PME. If this bit is cleared, then assertion of PME is
disabled.
8
R/W
7−5
4
RSVD
DYN_DATA
RSVD
R
R
R
Reserved. Bits 7−5 return 0s when read.
Dynamic data. This bit returns 0 when read since the TSB12LV23 does not report dynamic data.
Reserved. Bits 3−2 return 0s when read.
3−2
Power state. This 2-bit field is used to set the TSB12LV23 device power state and is encoded as
follows:
00 = Current power state is D0
01 = Current power state is D1
10 = Current power state is D2
11 = Current power state is D3
1−0
PWR_STATE
R/W
3.21 Power Management Extension Registers
The power management extension register provides extended power management features not applicable to the
TSB12LV23, thus it is read-only and returns 0 when read.
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Type
Default
Power management extension
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
Register:
Type:
Offset:
Default:
Power management extension
Read-only
4Ah
0000h
Table 3−18. Power Management Extension Registers Description
BIT
FIELD NAME
TYPE
DESCRIPTION
Power management data. This field returns 00h when read since the TSB12LV23 does not report
dynamic data.
15−8
PM_DATA
R
Power management CSR − bridge support extensions. This field returns 00h when read since the
TSB12LV23 does not provide P2P bridging.
7−0
PMCSR_BSE
R
3−14
3.22 PCI Miscellaneous Configuration Register
The PCI miscellaneous configuration register provides miscellaneous PCI-related configuration.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Type
Default
Bit
PCI miscellaneous configuration
R
0
R
0
R
0
R
0
R
0
R
0
R
0
9
R
0
8
R
0
7
R
0
6
R
0
5
R
0
4
R
0
3
R
0
2
R
0
1
R
0
0
15
14
13
12
11
10
Name
Type
Default
PCI miscellaneous configuration
R/W
0
R
0
R/W
1
R
0
R
0
R/W
1
R
0
R
0
R
0
R
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Register:
Type:
Offset:
Default:
PCI miscellaneous configuration
Read/Write
F0h
0000 2400h
Table 3−19. PCI Miscellaneous Configuration Register
BIT
FIELD NAME
TYPE
DESCRIPTION
Reserved. Bits 31−16 return 0s when read.
PME support from D3 . This bit is used to program bit 15 (PME_D3COLD) in the power
31−16
RSVD
PME_ D3COLD
RSVD
R
cold
15
14
R/W
R
management capabilities register (see Section 3.19).
Reserved. Bit 14 returns 0 when read.
PME support. This bit is used to program bit 13 (PME_SUPPORT_D2) in the power management
capabilities register (see Section 3.19). If wake from the D2 power state implemented in the
TSB12LV23 is not desired, then this bit may be cleared to indicate to power management software
that wake-up from D2 is not supported.
13
12−11
10
PME_SUPPORT_D2
RSVD
R/W
R
Reserved. Bits 12−11 return 0s when read.
D2 support. This bit is used to program bit 10 (D2_SUPPORT) in the power management
capabilities register (see Section 3.19). If the D2 power state implemented in the TSB12LV23 is
not desired, then this bit may be cleared to indicate to power management software that D2 is not
supported.
D2_SUPPORT
RSVD
R/W
R
9−5
Reserved. Bits 9−5 return 0s when read.
This bit defaults to 0, which provides OHCI-Lynx compatible target abort signaling. When this bit is
set to 1, it enables the no-target-abort mode, in which the TSB12LV23 returns indeterminate data
instead of signaling target abort.
The link is divided into the PCI_CLK and SCLK domains. If software tries to access registers in the
link that are not active because the SCLK is disabled, a target abort is issued by the link. On some
systems this can cause a problem resulting in a fatal system error. Enabling this bit allows the link
to respond to these types of requests by returning FFh.
4
DIS_TGT_ABT
R/W
It is recommended that this bit be set to 1.
When this bit is set to 1, the GPIO3 and GPIO2 signals are internally routed to the SCL and SDA,
respectively. The GPIO3 and GPIO2 terminals are also placed in a high impedance state.
3
2
1
0
GP2IIC
R/W
R/W
R/W
R/W
When this bit is set to 1, the internal SCLK runs identically with the chip input. This bit is a test
feature only and should be cleared to 0 (all applications).
DISABLE_SCLKGATE
DISABLE_PCIGATE
KEEP_PCLK
When this bit is set, the internal PCI clock runs identically with the chip input. This bit is a test
feature only and should be cleared to 0 (all applications).
When this bit is set to 1, the PCI clock is always kept running through the CLKRUN protocol. When
this bit is cleared, the PCI clock may be stopped using CLKRUN.
3−15
3.23 Link Enhancement Control Register
The link enhancement control register implements TI proprietary bits that are initialized by software or by a serial
EEPROM, if present. After these bits are set, their functionality is enabled only if bit 22 (aPhyEnhanceEnable) in the
host controller control register (see Section 4.16) is set.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Type
Default
Bit
Link enhancement control
R
0
R
0
R
0
R
0
R
0
R
0
R
0
9
R
0
8
R
0
7
R
0
6
R
0
5
R
0
4
R
0
3
R
0
2
R
0
1
R
0
0
15
14
13
12
11
10
Name
Type
Default
Link enhancement control
R
0
R
0
R/W
0
R/W
1
R
0
R
0
R
0
R
0
R/W
0
R
0
R
0
R
0
R
0
R/W
0
R/W
0
R
0
Register:
Type:
Offset:
Default:
Link enhancement control
Read/Write
F4h
0000 1000h
Table 3−20. Link Enhancement Control Register Description
BIT
FIELD NAME
TYPE
DESCRIPTION
Reserved. Bits 31−14 return 0s when read.
31−14
RSVD
R
This field sets the initial AT threshold value, which is used until the AT FIFO is underrun. When the
TSB12LV23 retries the packet, it uses a 2-Kbyte threshold resulting in a store-and-forward operation.
00 = Threshold ~ 2K bytes resulting in a store-and-forward operation
01 = Threshold ~ 1.7K bytes (default)
10 = Threshold ~ 1K
11 = Threshold ~ 512 bytes
These bits fine-tune the asynchronous transmit thershold. For most applications the 1.7K threshold
is optimal. Changing this value may increase or decrease the 1394 latency depending on the average
PCI bus latency.
13−12
atx_thresh
R/W
Setting the AT threshold to 1.7K, 1K, or 512 bytes results in data being transmitted at these thresholds,
or when an entire packet has been checked into the FIFO. If the packet to be transmitted is larger than
the AT threshold, then the remaning data must be received before the AT FIFO is emptied; otherwise,
an underrun condition will occur, resulting in a packet error at the receiving node. As a result, the link
will then commence store-and-forward operation, i.e., wait until it has the complete packet in the FIFO
before retransmitting it on the second attempt, to ensure delivery.
An AT threshold of 2K results in store-and-forward operation, which means that asynchronous data
will not be transmitted until an end-of-packet token is received. Restated, setting the AT threshold to
2K results in only complete packets being transmitted.
11−8
RSVD
R
Reserved. Bits 11−8 return 0s when read.
Enable asynchronous priority requests. OHCI-Lynx compatible. Setting this bit to 1 enables the link
to respond to requests with priority arbitration. It is recommended that this bit be set to 1.
7
enab_unfair
R/W
This bit is not assigned in the TSB12LV23 follow-on products since this bit location loaded by the serial
ROM from the Enhancements field corresponds to bit 23 (programPhyEnable) in the host controller
control register (see Section 4.16).
6
RSVD
RSVD
R
R
5−3
Reserved. Bits 5−3 return 0s when read.
Enable insert idle. OHCI-Lynx compatible. When the PHY has control of the Ct[0:1] control lines and
D[0:8] data lines and the link requests control, the PHY drives 11 on the Ct[0:1] lines. The link can then
start driving these lines immediately. Setting this bit to 1 inserts an idle state, so the link waits one clock
cycle before it starts diving the lines (turnaround time). It is recommended that this bit be set to 1.
2
enab_insert_idle
R/W
Enable acceleration enhancements. OHCI-Lynx compatible. This bit notifies the PHY that the link
supports the 1394a acceleration enhancements, i.e., ack-accelerated, fly-by concatenation, etc. It is
recommended that this bit be set to 1.
1
0
enab_accel
RSVD
R/W
R
Reserved. Bit 0 returns 0 when read.
3−16
3.24 Subsystem Access Register
Write access to the subsystem access register updates the subsystem identification registers identically to
OHCI-Lynx. The system ID value written to this register may also be read back from this register.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Type
Default
Bit
Subsystem access
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Type
Default
Subsystem access
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Register:
Type:
Offset:
Default:
Subsystem access
Read/Write
F8h
0000 0000h
Table 3−21. Subsystem Access Register Description
BIT
FIELD NAME
SUBDEV_ID
SUBVEN_ID
TYPE
DESCRIPTION
31−16
15−0
R/W
R/W
Subsystem device ID. This field indicates the subsystem device ID.
Subsystem vendor ID. This field indicates the subsystem vendor ID.
3−17
3.25 GPIO Control Register
The GPIO control register has the control and status bits for the GPIO2 and GPIO3 ports.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Type
Default
Bit
GPIO control
RWU R/W
R/W
0
R
0
R/W
0
R/W
0
R
0
R
0
R
0
9
R
0
6
R/W
0
R/W
0
R
0
3
R
0
2
R
0
1
RWU
0
0
0
15
14
13
12
11
10
8
7
5
4
0
Name
Type
Default
GPIO control
R
0
R
0
R
0
R
1
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
1
R
0
R
0
R
0
R
0
Register:
Type:
Offset:
Default:
GPIO control
Read/Write/Update
FCh
0000 1010h
Table 3−22. General-Purpose Input/Output Control Register Description
BIT
FIELD NAME
TYPE
DESCRIPTION
When this bit is set, a TSB12LV23 GPInterrupt event occurs on a level change of the GPIO3 input. This
event may generate an interrupt, with mask and event status reported through the OHCI interrupt mask
(see Section 4.22) and interrupt event (see Section 4.21) registers.
31
INT_3EN
R/W
30
29
RSVD
R
Reserved. Bit 30 returns 0 when read.
GPIO_INV3
R/W
GPIO3 polarity invert. When this bit is set, the polarity of GPIO3 is inverted.
GPIO3 enable control. When this bit is set, the output is enabled. Otherwise, the output is high
impedance.
28
27−25
24
GPIO_ENB3
RSVD
R/W
R
Reserved. Bits 27−25 return 0s when read.
GPIO3 data. Reads from this bit return the logical value of the input to GPIO3. Writes to this bit update
the value to drive to GPIO3 when output is enabled.
GPIO_DATA3
RWU
When this bit is set, a TSB12LV23 GPInterrupt event occurs on a level change of the GPIO3 input. This
event may generate an interrupt, with mask and event status reported through the OHCI interrupt mask
(see Section 4.22) and interrupt event (see Section 4.21) registers.
23
INT_2EN
R/W
22
21
RSVD
R
Reserved. Bit 22 returns 0 when read.
GPIO_INV2
R/W
GPIO2 polarity invert. When this bit is set, the polarity of GPIO2 is inverted.
GPIO2 enable control. When this bit is set, the output is enabled. Otherwise, the output is high
impedance.
20
19−17
16
GPIO_ENB2
RSVD
R/W
R
Reserved. Bits 19−17 return 0s when read.
GPIO2 data. Reads from this bit return the logical value of the input to GPIO2. Writes to this bit update
the value to drive to GPIO2 when the output is enabled.
GPIO_DATA2
RSVD
RWU
R
15−0
Reserved. Bits 15−0 return 0s when read.
3−18
4 OHCI Registers
The OHCI registers defined by the 1394 Open Host Controller Interface Specification are memory mapped into a
2-Kbyte region of memory pointed to by the OHCI base address register at offset 10h in PCI configuration space.
These registers are the primary interface for controlling the TSB12LV23 IEEE1394 link function.
This section provides the register interface and bit descriptions. There are several set and clear register pairs in this
programming model, which are implemented to solve various issues with typical read-modify-write control registers.
There are two addresses for a set/clear register: RegisterSet and RegisterClear. Refer to Table 4−1 for an illustration.
A 1 bit written to RegisterSet causes the corresponding bit in the set/clear register to be set, while a 0 bit leaves the
corresponding bit unaffected. A 1 bit written to RegisterClear causes the corresponding bit in the set/clear register
to be reset, while a 0 bit leaves the corresponding bit in the set/clear register unaffected.
Typically, a read from either RegisterSet or RegisterClear returns the contents of the set or clear register. However,
sometimes reading the RegisterClear provides a masked version of the set or clear register. The interrupt event
register is an example of this behavior.
Table 4−1. OHCI Register Map
DMA CONTEXT
REGISTER NAME
OHCI version
ABBREVIATION
Version
OFFSET
00h
04h
08h
0Ch
10h
14h
18h
1Ch
20h
24h
28h
2Ch
30h
34h
38h
3Ch
40h
44h
46h
48h
4Ah
4Ch
50h
54h
58h
5Ch
—
Global unique ID ROM
Asynchronous transmit retries
CSR data
GUID_ROM
ATRetries
CSRData
CSRCompareData
CSRControl
ConfigROMhdr
BusID
CSR compare data
CSR control
Configuration ROM header
Bus identification
Bus options
BusOptions
GUIDHi
Global unique ID high
Global unique ID low
PCI subsystem identification
Reserved
GUIDLo
SSID
—
Configuration ROM map
Posted write address low
Posted write address high
Vendor identification
ConfigROMmap
PostedWriteAddressLo
PostedWriteAddressHi
VendorID
CAP_ID
Capability ID and next item pointer
Power management capabilities
Power management control and status
Power management extensions
Reserved
PM_CAP
PMCSR
PM_Ext
—
HCControlSet
HCControlClr
—
Host controller control
Reserved
Reserved
—
4−1
Table 4−1. OHCI Register Map (Continued)
DMA CONTEXT
REGISTER NAME
ABBREVIATION
OFFSET
60h
Self ID
Reserved
—
Self ID buffer
Self ID count
Reserved
SelfIDBuffer
64h
SelfIDCount
68h
—
6Ch
—
IRChannelMaskHiSet
IRChannelMaskHiClear
IRChannelMaskLoSet
IRChannelMaskLoClear
IntEventSet
70h
Isochronous receive channel mask high
Isochronous receive channel mask low
Interrupt event
74h
78h
7Ch
80h
IntEventClear
84h
IntMaskSet
88h
Interrupt mask
IntMaskClear
8Ch
IsoXmitIntEventSet
IsoXmitIntEventClear
IsoXmitIntMaskSet
IsoXmitIntMaskClear
IsoRecvIntEventSet
IsoRecvIntEventClear
IsoRecvIntMaskSet
IsoRecvIntMaskClear
90h
Isochronous transmit interrupt event
Isochronous transmit interrupt mask
Isochronous receive interrupt event
Isochronous receive interrupt mask
94h
98h
9Ch
—
A0h
A4h
A8h
ACh
B0−D8h
DCh
E0h
Reserved
Fairness control
FairnessControl
LinkControlSet
LinkControlClear
NodeID
Link control
E4h
Node identification
PHY layer control
Isochronous cycle timer
Reserved
E8h
PhyControl
ECh
F0h
Isocyctimer
F4h
Reserved
F8h
Reserved
FCh
100h
104h
108h
10Ch
110h
114h
118h
11Ch
120h
124h−17Ch
AsyncRequestFilterHiSet
AsyncRequestFilterHiClear
AsyncRequestFilterLoSet
AsyncRequestFilterloClear
PhysicalRequestFilterHiSet
PhysicalRequestFilterHiClear
PhysicalRequestFilterLoSet
PhysicalRequestFilterloClear
PhysicalUpperBound
Asynchronous request filter high
Asynchronous request filter low
Physical request filter high
Physical request filter low
Physical upper bound
Reserved
—
4−2
Table 4−1. OHCI Register Map (Continued)
DMA CONTEXT
REGISTER NAME
ABBREVIATION
OFFSET
180h
ContextControlSet
ContextControlClear
—
Context control
Asychronous
Request Transmit
[ ATRQ ]
184h
Reserved
188h
Command pointer
Reserved
CommandPtr
—
18Ch
190h−19Ch
1A0h
ContextControlSet
ContextControlClear
—
Asychronous
Response Transmit
[ ATRS ]
Context control
1A4h
Reserved
1A8h
Command pointer
Reserved
CommandPtr
—
1ACh
1B0h−1BCh
1C0h
ContextControlSet
ContextControlClear
—
Asychronous
Request Receive
[ ARRQ ]
Context control
1C4h
Reserved
1C8h
Command pointer
Reserved
CommandPtr
—
1CCh
1D0h−1DCh
1E0h
ContextControlSet
ContextControlClear
—
Asychronous
Response Receive
[ ARRS ]
Context control
1E4h
Reserved
1E8h
Command pointer
Reserved
CommandPtr
—
1ECh
1F0h−1FCh
200h + 16*n
204h + 16*n
208h + 16*n
20Ch + 16*n
400h + 32*n
404h + 32*n
408h + 32*n
40Ch + 32*n
410h + 32*n
Isochronous
Transmit Context n
n = 0, 1, 2, 3, … 7
ContextControlSet
ContextControlClear
—
Context control
Reserved
Command pointer
CommandPtr
ContextControlSet
ContextControlClear
—
Isochronous
Receive Context n
n = 0, 1, 2, 3, … 4
Context control
Reserved
Command pointer
Context match
CommandPtr
ContextMatch
4−3
4.1 OHCI Version Register
This register indicates the OHCI version support, and whether or not the serial ROM is present.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Type
Default
Bit
OHCI version
R
0
R
0
R
0
R
0
R
0
R
0
R
0
9
R
X
8
R
0
7
R
0
6
R
0
5
R
0
4
R
0
3
R
0
2
R
0
1
R
1
0
15
14
13
12
11
10
Name
Type
Default
OHCI version
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
Register:
Type:
Offset:
Default:
OHCI version
Read-only
00h
0X01 0000h
Table 4−2. OHCI Version Register Description
BIT
31−25
24
FIELD NAME
RSVD
TYPE
DESCRIPTION
R
R
Reserved. Bits 31−25 return 0s when read.
GUID_ROM
The TSB12LV23 sets this bit if the serial ROM is detected. If the serial ROM is present, then the
Bus_Info_Block is automatically loaded on hardware reset.
23−16
version
R
Major version of the OHCI. The TSB12LV23 is compliant with the 1394 Open Host Controller Interface
Specification; thus, this field reads 01h.
15−8
7−0
RSVD
R
R
Reserved. Bits 15−8 return 0s when read.
revision
Minor version of the OHCI. The TSB12LV23 is compliant with the 1394 Open Host Controller Interface
Specification; thus, this field reads 00h.
4−4
4.2 GUID ROM Register
The GUID ROM register is used to access the serial ROM, and is only applicable if bit 24 (GUID_ROM) in the OHCI
version register (see Section 4.1) is set.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Type
Default
Bit
GUID ROM
RSU
0
R
0
R
0
R
0
R
0
R
0
RSU
R
0
8
RU
X
RU
X
RU
X
RU
X
RU
X
RU
X
RU
X
RU
X
0
15
14
13
12
11
10
9
7
6
5
4
3
2
1
0
Name
Type
Default
GUID ROM
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
Register:
Type:
Offset:
Default:
GUID ROM
Read/Set/Update
04h
00XX 0000h
Table 4−3. GUID ROM Register Description
BIT
FIELD NAME
TYPE
DESCRIPTION
31
addrReset
RSU
Software sets this bit to reset the GUID ROM address to 0. When the TSB12LV23 completes the reset,
it clears this bit. The TSB12LV23 does not automatically fill bits 23−16 (rdData field) with the 0 byte.
th
30−26
RSVD
rdStart
R
Reserved. Bits 30−26 return 0s when read.
25
RSU
A read of the currently addressed byte is started when this bit is set. This bit is automatically cleared
when the TSB12LV23 completes the read of the currently addressed GUID ROM byte.
24
RSVD
rdData
RSVD
R
RU
R
Reserved. Bit 24 returns 0 when read.
23−16
15−0
This field represents the data read from the GUID ROM.
Reserved. Bits 15−0 return 0s when read.
4−5
4.3 Asynchronous Transmit Retries Register
The asynchronous transmit retries register indicates the number of times the TSB12LV23 attempts a retry for
asynchronous DMA request transmit and for asynchronous physical and DMA response transmit.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Type
Default
Bit
Asynchronous transmit retries
R
0
R
0
R
0
R
0
R
0
R
0
R
0
9
R
0
8
R
0
7
R
0
6
R
0
5
R
0
4
R
0
3
R
0
2
R
0
1
R
0
0
15
14
13
12
11
10
Name
Type
Default
Asynchronous transmit retries
R
0
R
0
R
0
R
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Register:
Type:
Offset:
Default:
Asynchronous transmit retries
Read/Write
08h
0000 0000h
Table 4−4. Asynchronous Transmit Retries Register Description
BIT
FIELD NAME
TYPE
R
DESCRIPTION
31−29
28−16
15−12
11−8
secondLimit
cycleLimit
The second limit field returns 0s when read, since outbound dual-phase retry is not implemented.
The cycle limit field returns 0s when read, since outbound dual-phase retry is not implemented.
Reserved. Bits 15−12 return 0s when read.
R
RSVD
R
maxPhysRespRetries
R/W
This field tells the physical response unit how many times to attempt to retry the transmit operation
for the response packet when a busy acknowledge or ack_data_error is received from the target
node.
7−4
3−0
maxATRespRetries
maxATReqRetries
R/W
R/W
This field tells the asynchronous transmit response unit how many times to attempt to retry the
transmit operation for the response packet when a busy acknowledge or ack_data_error is re-
ceived from the target node.
This field tells the asynchronous transmit DMA request unit how many times to attempt to retry the
transmit operation for the response packet when a busy acknowledge or ack_data_error is re-
ceived from the target node.
4.4 CSR Data Register
The CSR data register is used to access the bus management CSR registers from the host through compare-swap
operations. This register contains the data to be stored in a CSR if the compare is successful.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Type
Default
Bit
CSR data
R
X
R
X
R
X
R
X
R
X
R
X
R
X
9
R
X
8
R
X
7
R
X
6
R
X
5
R
X
4
R
X
3
R
X
2
R
X
1
R
X
0
15
14
13
12
11
10
Name
Type
Default
CSR data
R
X
R
X
R
X
R
X
R
X
R
X
R
X
R
X
R
X
R
X
R
X
R
X
R
X
R
X
R
X
R
X
Register:
Type:
Offset:
Default:
CSR data
Read-only
0Ch
XXXX XXXXh
4−6
4.5 CSR Compare Register
The CSR compare register is used to access the bus management CSR registers from the host through
compare-swap operations. This register contains the data to be compared with the existing value of the CSR
resource.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Type
Default
Bit
CSR compare
R
X
R
X
R
X
R
X
R
X
R
X
R
X
9
R
X
8
R
X
7
R
X
6
R
X
5
R
X
4
R
X
3
R
X
2
R
X
1
R
X
0
15
14
13
12
11
10
Name
Type
Default
CSR compare
R
X
R
X
R
X
R
X
R
X
R
X
R
X
R
X
R
X
R
X
R
X
R
X
R
X
R
X
R
X
R
X
Register:
Type:
Offset:
Default:
CSR compare
Read-only
10h
XXXX XXXXh
4.6 CSR Control Register
The CSR control register is used to access the bus management CSR registers from the host through compare-swap
operations. This register is used to control the compare-swap operation and to select the CSR resource.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Type
Default
Bit
CSR control
RU
1
R
0
R
0
R
0
R
0
R
0
R
0
9
R
0
8
R
0
7
R
0
6
R
0
5
R
0
4
R
0
3
R
0
2
R
0
1
R
0
0
15
14
13
12
11
10
Name
Type
Default
CSR control
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R/W
X
R/W
X
Register:
Type:
Offset:
Default:
CSR control
Read/Write/Update
14h
8000 000Xh
Table 4−5. CSR Control Register Description
BIT
FIELD NAME
TYPE
DESCRIPTION
31
csrDone
RU
This bit is set by the TSB12LV23 when a compare-swap operation is complete. It is reset whenever this
register is written.
30−2
1−0
RSVD
csrSel
R
Reserved. Bits 30−2 return 0s when read.
R/W
This field selects the CSR resource as follows:
00 = BUS_MANAGER_ID
01 = BANDWIDTH_AVAILABLE
10 = CHANNELS_AVAILABLE_HI
11 = CHANNELS_AVAILABLE_LO
4−7
4.7 Configuration ROM Header Register
The configuration ROM header register externally maps to the first quadlet of the 1394 configuration ROM, offset
48’hFFFF_F000_0400.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Type
Default
Bit
Configuration ROM header
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Type
Default
Configuration ROM header
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
Register:
Type:
Offset:
Default:
Configuration ROM header
Read/Write
18h
0000 XXXXh
Table 4−6. Configuration ROM Header Register Description
BIT
FIELD NAME
TYPE
DESCRIPTION
31−24
info_length
R/W
IEEE1394 bus management field. Must be valid when bit 17 (linkEnable) of the host controller control
register (see Section 4.16) is set.
23−16
15−0
crc_length
R/W
R/W
IEEE1394 bus management field. Must be valid when bit 17 (linkEnable) of the host controller control
register (see Section 4.16) is set.
rom_crc_value
IEEE1394 bus management field. Must be valid at any time bit 17 (linkEnable) of the host controller
control register (see Section 4.16) is set. The reset value is undefined if no serial ROM is present. If a
serial ROM is present, then this field is loaded from the serial ROM.
4.8 Bus Identification Register
The bus identification register externally maps to the first quadlet in the Bus_Info_Block, and contains the constant
32’h31333934, which is the ASCII value of 1394.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Type
Default
Bit
Bus identification
R
0
R
0
R
1
R
1
R
0
R
0
R
0
9
R
1
8
R
0
7
R
0
6
R
1
5
R
1
4
R
0
3
R
0
2
R
1
1
R
1
0
15
14
13
12
11
10
Name
Type
Default
Bus identification
R
0
R
0
R
1
R
1
R
1
R
0
R
0
R
1
R
0
R
0
R
1
R
1
R
0
R
1
R
0
R
0
Register:
Type:
Offset:
Default:
Bus identification
Read-only
1Ch
3133 3934h
4−8
4.9 Bus Options Register
The bus options register externally maps to the second quadlet of the Bus_Info_Block.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Type
Default
Bit
Bus options
R/W
X
R/W
X
R/W
X
R/W
X
R/W
0
R
0
R
0
9
R
0
8
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
15
14
13
12
11
10
7
6
5
4
3
2
1
0
Name
Type
Default
Bus options
R/W
1
R/W
0
R/W
1
R/W
0
R
0
R
0
R
0
R
0
R/W
X
R/W
X
R
0
R
0
R
0
R
0
R
1
R
0
Register:
Type:
Offset:
Default:
Bus options
Read/Write
20h
X0XX A0X2h
Table 4−7. Bus Options Register Description
BIT
FIELD NAME
TYPE
DESCRIPTION
31
irmc
R/W
Isochronous resource manager capable. IEEE1394 bus management field. Must be valid when bit 17
(linkEnable) of the host controller control register (see Section 4.16) is set.
30
29
28
27
cmc
isc
R/W
R/W
R/W
R/W
Cycle master capable. IEEE1394 bus management field. Must be valid when bit 17 (linkEnable) of the
host controller control register (see Section 4.16) is set.
Isochronous support capable. IEEE1394 bus management field. Must be valid when bit 17 (linkEnable)
of the host controller control register (see Section 4.16) is set.
bmc
pmc
Bus manager capable. IEEE1394 bus management field. Must be valid when bit 17 (linkEnable) of the
host controller control register (see Section 4.16) is set.
IEEE1394 bus management field. Must be valid when bit 17 (linkEnable) of the host controller control
register (see Section 4.16) is set.
26−24
23−16
RSVD
R
Reserved. Bits 26−24 return 0s when read.
cyc_clk_acc
R/W
Cycle master clock accuracy. (accuracy in parts per million) IEEE1394 bus management field. Must be
valid when bit 17 (linkEnable) of the host controller control register (see Section 4.16) is set.
15−12
max_rec
R/W
IEEE 1394 bus management field. Hardware initializes this field to indicate the maximum number of
bytes in a block request packet that is supported by the implementation. This value, max_rec_bytes
must be 512 greater, and is calculated by 2^(max_rec + 1). Software may change this field; however,
this field must be valid at any time bit 17 (linkEnable) of the host controller control register (see
Section 4.16) is set. A received block write request packet with a length greater than max_rec_bytes
may generate an ack_type_error. This field is not affected by a soft reset, and defaults to value
indicating 2048 bytes on a hard reset.
11−8
7−6
RSVD
g
R
Reserved. Bits 11−8 return 0s when read.
R/W
Generation counter. This field is incremented if any portion of the configuration ROM has been
incremented since the prior bus reset.
5−3
2−0
RSVD
R
R
Reserved. Bits 5−3 return 0s when read.
Lnk_spd
Link speed. This field returns 010, indicating that the link speeds of 100, 200, and 400 Mbits/s are
supported.
4−9
4.10 GUID High Register
The GUID high register represents the upper quadlet in a 64-bit global unique ID (GUID) which maps to the third
quadlet in the Bus_Info_Block. This register contains node_vendor_ID and chip_ID_hi fields. This register initializes
to 0s on a hardware reset, which is an illegal GUID value. If a serial ROM is detected, then the contents of this register
are loaded through the serial ROM interface after a PCI reset. At that point, the contents of this register cannot be
changed. If no serial ROM is detected, then the contents of this register are loaded by the BIOS after a PCI reset.
At that point, the contents of this register cannot be changed.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Type
Default
Bit
GUID high
R
0
R
0
R
0
R
0
R
0
R
0
R
0
9
R
0
8
R
0
7
R
0
6
R
0
5
R
0
4
R
0
3
R
0
2
R
0
1
R
0
0
15
14
13
12
11
10
Name
Type
Default
GUID high
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
Register:
Type:
Offset:
Default:
GUID high
Read-only
24h
0000 0000h
4.11 GUID Low Register
The GUID low register represents the lower quadlet in a 64-bit global unique ID (GUID) which maps to chip_ID_lo
in the Bus_Info_Block. This register initializes to 0s on a hardware reset and behaves identical to the GUID high
register (see Section 4.10).
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Type
Default
Bit
GUID low
R
0
R
0
R
0
R
0
R
0
R
0
R
0
9
R
0
8
R
0
7
R
0
6
R
0
5
R
0
4
R
0
3
R
0
2
R
0
1
R
0
0
15
14
13
12
11
10
Name
Type
Default
GUID low
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
Register:
Type:
Offset:
Default:
GUID low
Read-only
28h
0000 0000h
4−10
4.12 Configuration ROM Mapping Register
The configuration ROM mapping register contains the start address within system memory that maps to the start
address of 1394 configuration ROM for this node.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Type
Default
Bit
Configuration ROM mapping
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Type
Default
Configuration ROM mapping
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
Register:
Type:
Offset:
Default:
Configuration ROM mapping
Read/Write
34h
0000 0000h
Table 4−8. Configuration ROM Mapping Register Description
BIT
FIELD NAME
TYPE
DESCRIPTION
31−10
configROMaddr
R/W
If a quadlet read request to 1394 offset 48’hFFFF_F000_0400 through offset 48’hFFFF_F000_07FF is
received, then the low order 10 bits of the offset are added to this register to determine the host memory
address of the read request.
9−0
RSVD
R
Reserved. Bits 9−0 return 0s when read.
4.13 Posted Write Address Low Register
The posted write address low register is used to communicate error information if a write request is posted and an
error occurs while writing the posted data packet.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Type
Default
Bit
Posted write address low
RU
X
RU
X
RU
X
RU
X
RU
X
RU
X
RU
X
RU
X
RU
X
RU
X
RU
X
RU
X
RU
X
RU
X
RU
X
RU
X
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Type
Default
Posted write address low
RU
X
RU
X
RU
X
RU
X
RU
X
RU
X
RU
X
RU
X
RU
X
RU
X
RU
X
RU
X
RU
X
RU
X
RU
X
RU
X
Register:
Type:
Offset:
Default:
Posted write address low
Read/Update
38h
XXXX XXXXh
Table 4−9. Posted Write Address Low Register Description
BIT
FIELD NAME
TYPE
DESCRIPTION
The lower 32 bits of the 1394 destination offset of the write request that failed.
31−0
offsetLo
RU
4−11
4.14 Posted Write Address High Register
The posted write address high register is used to communicate error information if a write request is posted and an
error occurs while writing the posted data packet.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Type
Default
Bit
Posted write address high
RU
X
RU
X
RU
X
RU
X
RU
X
RU
X
RU
X
RU
X
RU
X
RU
X
RU
X
RU
X
RU
X
RU
X
RU
X
RU
X
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Type
Default
Posted write address high
RU
X
RU
X
RU
X
RU
X
RU
X
RU
X
RU
X
RU
X
RU
X
RU
X
RU
X
RU
X
RU
X
RU
X
RU
X
RU
X
Register:
Type:
Offset:
Default:
Posted write address high
Read/Update
3Ch
XXXX XXXXh
Table 4−10. Posted Write Address High Register Description
BIT
FIELD NAME
sourceID
TYPE
RU
DESCRIPTION
31−16
15−0
This field is the bus and node number of the node that issued the write request that failed.
The upper 16 bits of the 1394 destination offset of the write request that failed.
offsetHi
RU
4.15 Vendor ID Register
The vendor ID register holds the company ID of an organization that specifies any vendor-unique registers. The
TSB12LV23 does not implement Texas Instruments unique behavior with regards to OHCI. Thus, this register is
read-only and returns 0s when read.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Type
Default
Bit
Vendor ID
R
0
R
0
R
0
R
0
R
0
R
0
R
0
9
R
0
8
R
0
7
R
0
6
R
0
5
R
0
4
R
0
3
R
0
2
R
0
1
R
0
0
15
14
13
12
11
10
Name
Type
Default
Vendor ID
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
Register:
Type:
Offset:
Default:
Vendor ID
Read-only
40h
0000 0000h
4−12
4.16 Host Controller Control Register
The host controller control set/clear register pair provides flags for controlling the TSB12LV23.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Type
Default
Bit
Host controller control
R
0
RSC
X
R
0
R
0
R
0
R
0
R
0
9
R
0
8
RC
0
RSC
R
0
5
R
0
4
RSC
RSC
X
RSC RSCU
0
0
0
0
15
14
13
12
11
10
7
6
3
2
1
0
Name
Type
Default
Host controller control
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
Register:
Type:
Offset:
Host controller control
Read/Set/Clear/Update
50h
54h
set register
clear register
Default:
X00X 0000h
Table 4−11. Host Controller Control Register Description
BIT
31
FIELD NAME
TYPE
R
DESCRIPTION
RSVD
Reserved. Bit 31 returns 0 when read.
30
noByteSwapData
RSC
This bit is used to control whether physical accesses to locations outside the TSB12LV23 itself as
well as any other DMA data accesses should be swapped.
29−24
RSVD
R
Reserved. Bits 29−24 return 0s when read.
23
programPhyEnable
RC
This bit informs upper level software that lower level software has consistently configured the
P1394a enhancements in the Link and PHY. When this bit is 1, generic software such as the OHCI
driver is responsible for configuring P1394a enhancements in the PHY and bit 22
(aPhyEnhanceEnable) in the TSB12LV23. When this bit is 0, the generic software may not modify
the P1394a enhancements in the TSB12LV23 or PHY and cannot interpret the setting of bit 22
(aPhyEnhanceEnable). This bit is initialized from serial EEPROM.
22
aPhyEnhanceEnable
RSC
When bits 23 (programPhyEnable) and 17 (linkEnable) are 1, the OHCI driver can set this bit to
use all P1394a enhancements. When bit 23 (programPhyEnable) is set to 0, the software does
not change PHY enhancements or this bit.
21−20
RSVD
LPS
R
Reserved. Bits 21−20 return 0s when read.
19
RSC
This bit is used to control the link power status. Software must set this bit to 1 to permit the
link-PHY communication. A 0 prevents link-PHY communication.
18
17
postedWriteEnable
linkEnable
RSC
RSC
This bit is used to enable (1) or disable (0) posted writes. Software should change this bit only
when bit 17 (linkEnable) is 0.
This bit is cleared to 0 by either a hardware or software reset. Software must set this bit to 1 when
the system is ready to begin operation and then force a bus reset. This bit is necessary to keep
other nodes from sending transactions before the local system is ready. When this bit is cleared,
the TSB12LV23 is logically and immediately disconnected from the 1394 bus, no packets are
received or processed nor are packets transmitted.
16
SoftReset
RSVD
RSCU When this bit is set, all TSB12LV23 states are reset, all FIFOs are flushed, and all OHCI registers
are set to their hardware reset values unless otherwise specified. PCI registers are not affected by
this bit. This bit remains set while the softReset is in progress and reverts back to 0 when the reset
has completed.
15−0
R
Reserved. Bits 15−0 return 0s when read.
4−13
4.17 Self ID Buffer Pointer Register
The self ID buffer pointer register points to the 2-Kbyte aligned base address of the buffer in host memory where the
self ID packets are stored during bus initialization. Bits 31−11 are read/write accessible.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Type
Self ID buffer pointer
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
Default
Default
Bit
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Type
Self ID buffer pointer
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
Default
Register:
Type:
Offset:
Default:
Self ID buffer pointer
Read/Write
64h
XXXX XX00h
4.18 Self ID Count Register
The self ID count register keeps a count of the number of times the bus self ID process has occurred, flags self ID
packet errors, and keeps a count of the amount of self ID data in the self ID buffer.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Type
Default
Bit
Self ID count
RU
X
R
0
R
0
R
0
R
0
R
0
R
0
9
R
0
8
RU
X
RU
X
RU
X
RU
X
RU
X
RU
X
RU
X
RU
X
15
14
13
12
11
10
7
6
5
4
3
2
1
0
Name
Type
Default
Self ID count
R
0
R
0
R
0
R
0
R
0
RU
0
RU
0
RU
0
RU
0
RU
0
RU
0
RU
0
RU
0
RU
0
R
0
R
0
Register:
Type:
Offset:
Default:
Self ID count
Read/Update
68h
X0XX 0000h
Table 4−12. Self ID Count Register Description
BIT
FIELD NAME
TYPE
DESCRIPTION
31
selfIDError
RU
When this bit is 1, an error was detected during the most recent self ID packet reception. The contents
of the self ID buffer are undefined. This bit is cleared after a self ID reception in which no errors are
detected. Note that an error can be a hardware error or a host bus write error.
30−24
23−16
RSVD
R
Reserved. Bits 30−24 return 0s when read.
selfIDGeneration
RU
The value in this field increments each time a bus reset is detected. This field rolls over to 0 after
reaching 255.
15−11
10−2
RSVD
R
Reserved. Bits 15−11 return 0s when read.
selfIDSize
RU
This field indicates the number of quadlets that have been written into the self ID buffer for the current
bits 23−16 (selfIDGeneration field). This includes the header quadlet and the self ID data. This field is
cleared to 0 when the self ID reception begins.
1−0
RSVD
R
Reserved. Bits 1−0 return 0s when read.
4−14
4.19 Isochronous Receive Channel Mask High Register
The isochronous receive channel mask high set/clear register is used to enable packet receives from the upper 32
isochronous data channels. A read from either the set register or clear register returns the content of the isochronous
receive channel mask high register.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Type
Isochronous receive channel mask high
RSC
X
RSC
X
RSC
X
RSC
X
RSC
X
RSC
X
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
Default
Default
Bit
X
0
9
X
0
8
X
0
7
X
0
6
X
0
5
X
0
4
X
0
3
X
0
2
X
0
1
X
0
0
0
0
0
0
0
0
15
14
13
12
11
10
Name
Type
Isochronous receive channel mask high
RSC
X
RSC
X
RSC
X
RSC
X
RSC
X
RSC
X
RSC
X
RSC
X
RSC
X
RSC
X
RSC
X
RSC
X
RSC
X
RSC
X
RSC
X
RSC
X
Default
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Register:
Type:
Offset:
Isochronous receive channel mask high
Read/Set/Clear
70h
74h
set register
clear register
Default:
XXXX XXXXh
Table 4−13. Isochronous Receive Channel Mask High Register Description
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
FIELD NAME
isoChannel63
isoChannel62
isoChannel61
isoChannel60
isoChannel59
isoChannel58
isoChannel57
isoChannel56
isoChannel55
isoChannel54
isoChannel53
isoChannel52
isoChannel51
isoChannel50
isoChannel49
isoChannel48
isoChannel47
isoChannel46
isoChannel45
isoChannel44
isoChannel43
isoChannel42
isoChannel41
isoChannel40
isoChannel39
TYPE
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
DESCRIPTION
When this bit is set, the TSB12LV23 is enabled to receive from iso channel number 63.
When this bit is set, the TSB12LV23 is enabled to receive from iso channel number 62.
When this bit is set, the TSB12LV23 is enabled to receive from iso channel number 61.
When this bit is set, the TSB12LV23 is enabled to receive from iso channel number 60.
When this bit is set, the TSB12LV23 is enabled to receive from iso channel number 59.
When this bit is set, the TSB12LV23 is enabled to receive from iso channel number 58.
When this bit is set, the TSB12LV23 is enabled to receive from iso channel number 57.
When this bit is set, the TSB12LV23 is enabled to receive from iso channel number 56.
When this bit is set, the TSB12LV23 is enabled to receive from iso channel number 55.
When this bit is set, the TSB12LV23 is enabled to receive from iso channel number 54.
When this bit is set, the TSB12LV23 is enabled to receive from iso channel number 53.
When this bit is set, the TSB12LV23 is enabled to receive from iso channel number 52.
When this bit is set, the TSB12LV23 is enabled to receive from iso channel number 51.
When this bit is set, the TSB12LV23 is enabled to receive from iso channel number 50.
When this bit is set, the TSB12LV23 is enabled to receive from iso channel number 49.
When this bit is set, the TSB12LV23 is enabled to receive from iso channel number 48.
When this bit is set, the TSB12LV23 is enabled to receive from iso channel number 47.
When this bit is set, the TSB12LV23 is enabled to receive from iso channel number 46.
When this bit is set, the TSB12LV23 is enabled to receive from iso channel number 45.
When this bit is set, the TSB12LV23 is enabled to receive from iso channel number 44.
When this bit is set, the TSB12LV23 is enabled to receive from iso channel number 43.
When this bit is set, the TSB12LV23 is enabled to receive from iso channel number 42.
When this bit is set, the TSB12LV23 is enabled to receive from iso channel number 41.
When this bit is set, the TSB12LV23 is enabled to receive from iso channel number 40.
When this bit is set, the TSB12LV23 is enabled to receive from iso channel number 39.
8
7
4−15
Table 4−13. Isochronous Receive Channel Mask High Register Description (Continued)
BIT
6
FIELD NAME
isoChannel38
isoChannel37
isoChannel36
isoChannel35
isoChannel34
isoChannel33
isoChannel32
TYPE
RSC
RSC
RSC
RSC
RSC
RSC
RSC
DESCRIPTION
When this bit is set, the TSB12LV23 is enabled to receive from iso channel number 38.
When this bit is set, the TSB12LV23 is enabled to receive from iso channel number 37.
When this bit is set, the TSB12LV23 is enabled to receive from iso channel number 36.
When this bit is set, the TSB12LV23 is enabled to receive from iso channel number 35.
When this bit is set, the TSB12LV23 is enabled to receive from iso channel number 34.
When this bit is set, the TSB12LV23 is enabled to receive from iso channel number 33.
When this bit is set, the TSB12LV23 is enabled to receive from iso channel number 32.
5
4
3
2
1
0
4.20 Isochronous Receive Channel Mask Low Register
The isochronous receive channel mask low set/clear register is used to enable packet receives from the lower 32
isochronous data channels.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Type
Isochronous receive channel mask low
RSC
X
RSC
X
RSC
X
RSC
X
RSC
X
RSC
X
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
Default
Default
Bit
X
0
9
X
0
8
X
0
7
X
0
6
X
0
5
X
0
4
X
0
3
X
0
2
X
0
1
X
0
0
0
0
0
0
0
0
15
14
13
12
11
10
Name
Type
Isochronous receive channel mask low
RSC
X
RSC
X
RSC
X
RSC
X
RSC
X
RSC
X
RSC
X
RSC
X
RSC
X
RSC
X
RSC
X
RSC
X
RSC
X
RSC
X
RSC
X
RSC
X
Default
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Register:
Type:
Offset:
Isochronous receive channel mask low
Read/Set/Clear
78h
7Ch
set register
clear register
Default:
XXXX XXXXh
Table 4−14. Isochronous Receive Channel Mask Low Register Description
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
FIELD NAME
isoChannel31
isoChannel30
isoChannel29
isoChannel28
isoChannel27
isoChannel26
isoChannel25
isoChannel24
isoChannel23
isoChannel22
isoChannel21
isoChannel20
isoChannel19
isoChannel18
isoChannel17
isoChannel16
TYPE
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
DESCRIPTION
When this bit is set, the TSB12LV23 is enabled to receive from iso channel number 31.
When this bit is set, the TSB12LV23 is enabled to receive from iso channel number 30.
When this bit is set, the TSB12LV23 is enabled to receive from iso channel number 29.
When this bit is set, the TSB12LV23 is enabled to receive from iso channel number 28.
When this bit is set, the TSB12LV23 is enabled to receive from iso channel number 27.
When this bit is set, the TSB12LV23 is enabled to receive from iso channel number 26.
When this bit is set, the TSB12LV23 is enabled to receive from iso channel number 25.
When this bit is set, the TSB12LV23 is enabled to receive from iso channel number 24.
When this bit is set, the TSB12LV23 is enabled to receive from iso channel number 23.
When this bit is set, the TSB12LV23 is enabled to receive from iso channel number 22.
When this bit is set, the TSB12LV23 is enabled to receive from iso channel number 21.
When this bit is set, the TSB12LV23 is enabled to receive from iso channel number 20.
When this bit is set, the TSB12LV23 is enabled to receive from iso channel number 19.
When this bit is set, the TSB12LV23 is enabled to receive from iso channel number 18.
When this bit is set, the TSB12LV23 is enabled to receive from iso channel number 17.
When this bit is set, the TSB12LV23 is enabled to receive from iso channel number 16.
4−16
Table 4−14. Isochronous Receive Channel Mask Low Register Description (Continued)
BIT
15
14
13
12
11
10
9
FIELD NAME
isoChannel15
isoChannel14
isoChannel13
isoChannel12
isoChannel11
isoChannel10
isoChannel9
isoChannel8
isoChannel7
isoChannel6
isoChannel5
isoChannel4
isoChannel3
isoChannel2
isoChannel1
isoChannel0
TYPE
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
DESCRIPTION
When this bit is set, the TSB12LV23 is enabled to receive from iso channel number 15.
When this bit is set, the TSB12LV23 is enabled to receive from iso channel number 14.
When this bit is set, the TSB12LV23 is enabled to receive from iso channel number 13.
When this bit is set, the TSB12LV23 is enabled to receive from iso channel number 12.
When this bit is set, the TSB12LV23 is enabled to receive from iso channel number 11.
When this bit is set, the TSB12LV23 is enabled to receive from iso channel number 10.
When this bit is set, the TSB12LV23 is enabled to receive from iso channel number 9.
When this bit is set, the TSB12LV23 is enabled to receive from iso channel number 8.
When this bit is set, the TSB12LV23 is enabled to receive from iso channel number 7.
When this bit is set, the TSB12LV23 is enabled to receive from iso channel number 6.
When this bit is set, the TSB12LV23 is enabled to receive from iso channel number 5.
When this bit is set, the TSB12LV23 is enabled to receive from iso channel number 4.
When this bit is set, the TSB12LV23 is enabled to receive from iso channel number 3.
When this bit is set, the TSB12LV23 is enabled to receive from iso channel number 2.
When this bit is set, the TSB12LV23 is enabled to receive from iso channel number 1.
When this bit is set, the TSB12LV23 is enabled to receive from iso channel number 0.
8
7
6
5
4
3
2
1
0
4−17
4.21 Interrupt Event Register
The interrupt event set/clear register reflects the state of the various TSB12LV23 interrupt sources. The interrupt bits
are set by an asserting edge of the corresponding interrupt signal or by writing a 1 in the corresponding bit in the set
register. The only mechanism to clear the bits in this register is to write a 1 to the corresponding bit in the clear register.
This register is fully compliant with OHCI and the TSB12LV23 adds OHCI 1.0 compliant vendor-specific interrupt
function to bit 30. When reading the interrupt event register, the return value is the bit-wise AND function of the
interrupt event and interrupt mask registers per the 1394 Open Host Controller Interface Specification.
Bit
31
30
29
28
27
26
25
24
Interrupt event
RSCU RSCU RSCU RSCU RSCU RSCU RSCU RSCU
23
22
21
20
19
18
17
16
Name
Type
Default
Bit
R
0
RSC
X
R
0
R
0
R
0
R
0
2
RSCU RSCU
X
X
X
X
X
X
X
X
X
X
15
14
13
12
11
10
9
8
7
6
5
4
3
1
0
Name
Type
Default
Interrupt event
R
0
R
0
R
0
R
0
R
0
R
0
RSCU RSCU
RU
X
RU
X
RSCU RSCU RSCU RSCU RSCU RSCU
X
X
X
X
X
X
X
X
Register:
Type:
Offset:
Interrupt event
Read/Set/Clear/Update
80h
84h
set register
clear register [returns the content of the interrupt event and interrupt mask registers
when read]
Default:
XXXX 0XXXh
Table 4−15. Interrupt Event Register Description
BIT
31
FIELD NAME
RSVD
TYPE
R
DESCRIPTION
Reserved. Bit 31 returns 0 when read.
30
vendorSpecific
RSC
This vendor-specific interrupt event is reported when either of the general-purpose interrupts occur
which are enabled via INT_EN3 and INT_EN2.
29−27
RSVD
R
Reserved. Bits 29−27 return 0s when read.
26
phyRegRcvd
RSCU The TSB12LV23 has received a PHY register data byte which can be read from the PHY layer control
register (see Section 4.30).
25
24
23
22
cycleTooLong
RSCU If bit 21 (cycleMaster) of the link control register (see Section 4.28) is set, then this indicates that over
125 μs have elapsed between the start of sending a cycle start packet and the end of a subaction gap.
The link control register bit 21 (cycleMaster) is cleared by this event.
unrecoverableError RSCU This event occurs when the TSB12LV23 encounters any error that forces it to stop operations on any
or all of its subunits, for example, when a DMA context sets its dead bit. While this bit is set, all normal
interrupts for the context(s) that caused this interrupt are blocked from being set.
cycleInconsistent
RSCU A cycle start was received that had values for cycleSeconds and cycleCount fields that are different
from the values in bits 31−25 (cycleSeconds field) and bits 24−12 (cycleCount field) of the
isochronous cycle timer register (see Section 4.31).
cycleLost
RSCU A lost cycle is indicated when no cycle_start packet is sent/received between two successive
cycleSynch events. A lost cycle can be predicted when a cycle_start packet does not immediately
follow the first subaction gap after the cycleSynch event or if an arbitration reset gap is detected after
a cycleSynch event without an intervening cycle start. This bit may be set either when it occurs or
when logic predicts that it will occur.
th
21
20
cycle64Seconds
cycleSynch
RSCU Indicates that the 7 bit of the cycle second counter has changed.
RSCU Indicates that a new isochronous cycle has started. This bit is set when the low order bit of the cycle
count toggles.
19
18
phy
RSCU Indicates the PHY requests an interrupt through a status transfer.
RSVD
R
Reserved. Bit 18 returns 0 when read.
4−18
Table 4−15. Interrupt Event Register Description (Continued)
BIT
17
FIELD NAME
busReset
TYPE
DESCRIPTION
RSCU Indicates that the PHY chip has entered bus reset mode.
16
selfIDcomplete
RSCU A selfID packet stream has been received. It is generated at the end of the bus initialization process.
This bit is turned off simultaneously when bit 17 (busReset) is turned on.
15−10
RSVD
R
Reserved. Bits 15−10 return 0s when read.
9
lockRespErr
RSCU Indicates that the TSB12LV23 sent a lock response for a lock request to a serial bus register, but did
not receive an ack_complete.
8
7
postedWriteErr
isochRx
RSCU Indicates that a host bus error occurred while the TSB12LV23 was trying to write a 1394 write request,
which had already been given an ack_complete, into system memory.
RU
Isochronous receive DMA interrupt. Indicates that one or more isochronous receive contexts have
generated an interrupt. This is not a latched event, it is the OR’ing of all bits in the isochronous receive
interrupt event and isochronous receive interrupt mask registers. The isochronous receive interrupt
event register (see Section 4.25) indicates which contexts have interrupted.
6
isochTx
RU
Isochronous transmit DMA interrupt. Indicates that one or more isochronous transmit contexts have
generated an interrupt. This is not a latched event, it is the OR’ing of all bits in the isochronous
transmit interrupt event and isochronous transmit interrupt mask registers. The isochronous transmit
interrupt event register (see Section 4.23) indicates which contexts have interrupted.
5
4
3
2
1
0
RSPkt
RQPkt
RSCU Indicates that a packet was sent to an asynchronous receive response context buffer and the
descriptor’s xferStatus and resCount fields have been updated.
RSCU Indicates that a packet was sent to an asynchronous receive request context buffer and the
descriptor’s xferStatus and resCount fields have been updated.
ARRS
RSCU Async receive response DMA interrupt. This bit is conditionally set upon completion of an ARRS DMA
context command descriptor.
ARRQ
RSCU Async receive request DMA interrupt. This bit is conditionally set upon completion of an ARRQ DMA
context command descriptor.
respTxComplete
reqTxComplete
RSCU Asynchronous response transmit DMA interrupt. This bit is conditionally set upon completion of an
ATRS DMA command.
RSCU Asynchronous request transmit DMA interrupt. This bit is conditionally set upon completion of an
ATRQ DMA command.
4−19
4.22 Interrupt Mask Register
The interrupt mask set/clear register is used to enable the various TSB12LV23 interrupt sources. Reads from either
the set register or the clear register always return the contents of the interrupt mask register. In all cases except
masterIntEnable (bit 31), the enables for each interrupt event align with the interrupt event register bits detailed in
Table 4−15.
This register is fully compliant with OHCI and the TSB12LV23 adds an OHCI 1.0 compliant interrupt function to bit 30.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Type
Default
Bit
Interrupt mask
R
X
RSC
X
R
0
R
0
R
0
RSCU RSCU RSCU RSCU RSCU RSCU RSCU RSCU
R
0
2
RSCU RSCU
X
X
X
X
X
X
X
X
X
X
15
14
13
12
11
10
9
8
7
6
5
4
3
1
0
Name
Type
Default
Interrupt mask
R
0
R
0
R
0
R
0
R
0
R
0
RSCU RSCU
RU
X
RU
X
RSCU RSCU RSCU RSCU RSCU RSCU
X
X
X
X
X
X
X
X
Register:
Type:
Offset:
Interrupt mask
Read/Set/Clear/Update
88h
8Ch
set register
clear register
Default:
XXXX 0XXXh
Table 4−16. Interrupt Mask Register Description
BIT
FIELD NAME
TYPE
DESCRIPTION
31
masterIntEnable
RSCU Master interrupt enable. If this bit is set, then external interrupts are generated in accordance with the
interrupt mask register. If this bit is cleared, then external interrupts are not generated regardless of the
interrupt mask register settings.
30
VendorSpecific
RSC
When this bit is set, this vendor-specific interrupt mask enables interrupt generation when bit 30
(vendorSpecific) of the interrupt event register (see Section 4.21) is set.
29−0
See Table 4−15
4−20
4.23 Isochronous Transmit Interrupt Event Register
The isochronous transmit interrupt event set/clear register reflects the interrupt state of the isochronous transmit
contexts. An interrupt is generated on behalf of an isochronous transmit context if an OUTPUT_LAST command
completes and its interrupt bits are set. Upon determining that the interrupt event register isochTx (bit 6) interrupt has
occurred, software can check this register to determine which context(s) caused the interrupt. The interrupt bits are
set by an asserting edge of the corresponding interrupt signal, or by writing a 1 in the corresponding bit in the set
register. The only mechanism to clear the bits in this register is to write a 1 to the corresponding bit in the clear register.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Type
Default
Bit
Isochronous transmit interrupt event
R
0
R
0
R
0
R
0
R
0
R
0
R
0
9
R
0
8
R
0
7
R
0
6
R
0
5
R
0
4
R
0
3
R
0
2
R
0
1
R
0
0
15
14
13
12
11
10
Name
Type
Default
Isochronous transmit interrupt event
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
RSC
X
RSC
X
RSC
X
RSC
X
RSC
X
RSC
X
RSC
X
RSC
X
Register:
Type:
Offset:
Isochronous transmit interrupt event
Read/Set/Clear
90h
84h
set register
clear register [returns IsoXmitEvent and IsoXmitMask when read]
Default:
0000 00XXh
Table 4−17. Isochronous Transmit Interrupt Event Register Description
BIT
FIELD NAME
RSVD
TYPE
R
DESCRIPTION
31−8
Reserved. Bits 31−8 return 0s when read.
7
6
5
4
3
2
1
0
isoXmit7
isoXmit6
isoXmit5
isoXmit4
isoXmit3
isoXmit2
isoXmit1
isoXmit0
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
Isochronous transmit channel 7 caused the interrupt event register bit 6 (isochTx) interrupt.
Isochronous transmit channel 6 caused the interrupt event register bit 6 (isochTx) interrupt.
Isochronous transmit channel 5 caused the interrupt event register bit 6 (isochTx) interrupt.
Isochronous transmit channel 4 caused the interrupt event register bit 6 (isochTx) interrupt.
Isochronous transmit channel 3 caused the interrupt event register bit 6 (isochTx) interrupt.
Isochronous transmit channel 2 caused the interrupt event register bit 6 (isochTx) interrupt.
Isochronous transmit channel 1 caused the interrupt event register bit 6 (isochTx) interrupt.
Isochronous transmit channel 0 caused the interrupt event register bit 6 (isochTx) interrupt.
4−21
4.24 Isochronous Transmit Interrupt Mask Register
The isochronous transmit interrupt mask set/clear register is used to enable the isochTx interrupt source on a per
channel basis. Reads from either the set register or the clear register always return the contents of the isochronous
transmit interrupt mask register. In all cases the enables for each interrupt event align with the event register bits
detailed in Table 4−17.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Type
Default
Bit
Isochronous transmit interrupt mask
R
0
R
0
R
0
R
0
R
0
R
0
R
0
9
R
0
8
R
0
7
R
0
6
R
0
5
R
0
4
R
0
3
R
0
2
R
0
1
R
0
0
15
14
13
12
11
10
Name
Type
Default
Isochronous transmit interrupt mask
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
RSC
X
RSC
X
RSC
X
RSC
X
RSC
X
RSC
X
RSC
X
RSC
X
Register:
Type:
Offset:
Isochronous transmit interrupt mask
Read/Set/Clear
98h
9Ch
set register
clear register
Default:
0000 00XXh
4.25 Isochronous Receive Interrupt Event Register
The isochronous receive interrupt event set/clear register reflects the interrupt state of the isochronous receive
contexts. An interrupt is generated on behalf of an isochronous receive context if an INPUT_* command completes
and its interrupt bits are set. Upon determining that the interrupt event register isochRx (bit 7) interrupt has occurred,
software can check this register to determine which context(s) caused the interrupt. The interrupt bits are set by an
asserting edge of the corresponding interrupt signal, or by writing a 1 in the corresponding bit in the set register. The
only mechanism to clear the bits in this register is to write a 1 to the corresponding bit in the clear register.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Type
Default
Bit
Isochronous receive interrupt event
R
0
R
0
R
0
R
0
R
0
R
0
R
0
9
R
0
8
R
0
7
R
0
6
R
0
5
R
0
4
R
0
3
R
0
2
R
0
1
R
0
0
15
14
13
12
11
10
Name
Type
Default
Isochronous receive interrupt event
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
RSC
X
RSC
X
RSC
X
RSC
X
Register:
Type:
Offset:
Isochronous receive interrupt event
Read/Set/Clear
A0h
A4h
set register
clear register [returns the contents of isochronous receive interrupt event and
isochronous receive mask registers when read]
Default:
0000 000Xh
Table 4−18. Isochronous Receive Interrupt Event Register Description
BIT
FIELD NAME
RSVD
TYPE
R
DESCRIPTION
Reserved. Bits 31−4 return 0s when read.
31−4
3
2
1
0
isoRecv3
isoRecv2
isoRecv1
isoRecv0
RSC
RSC
RSC
RSC
Isochronous receive channel 3 caused the interrupt event register bit 7 (isochRx) interrupt.
Isochronous receive channel 2 caused the interrupt event register bit 7 (isochRx) interrupt.
Isochronous receive channel 1 caused the interrupt event register bit 7 (isochRx) interrupt.
Isochronous receive channel 0 caused the interrupt event register bit 7 (isochRx) interrupt.
4−22
4.26 Isochronous Receive Interrupt Mask Register
The isochronous receive interrupt mask register is used to enable the isochRx interrupt source on a per channel basis.
Reads from either the set register or the clear register always return the contents of the isochronous receive interrupt
mask register. In all cases the enables for each interrupt event align with the event register bits detailed in Table 4−18.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Type
Default
Bit
Isochronous receive interrupt mask
R
0
R
0
R
0
R
0
R
0
R
0
R
0
9
R
0
8
R
0
7
R
0
6
R
0
5
R
0
4
R
0
3
R
0
2
R
0
1
R
0
0
15
14
13
12
11
10
Name
Type
Default
Isochronous receive interrupt mask
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
RSC
X
RSC
X
RSC
X
RSC
X
Register:
Type:
Offset:
Isochronous receive interrupt mask
Read/Set/Clear
A8h
ACh
set register
clear register
Default:
0000 000Xh
4.27 Fairness Control Register
The fairness control register provides a mechanism by which software can direct the host controller to transmit
multiple asynchronous requests during a fairness interval.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Type
Fairness control
R
0
R
0
R
0
R
0
R
0
R
0
R
0
0
9
R
0
0
8
R
0
0
7
R
0
0
6
R
0
0
5
R
0
0
4
R
0
0
3
R
0
0
2
R
0
0
1
R
0
0
0
Default
Default
Bit
0
0
0
0
0
0
15
14
13
12
11
10
Name
Type
Fairness control
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Default
Register:
Type:
Offset:
Default:
Fairness control
Read-only
DCh
0000 0000h
Table 4−19. Fairness Control Register Description
BIT
31−8
7−0
FIELD NAME
RSVD
TYPE
DESCRIPTION
Reserved. Bits 31−8 return 0s when read.
R
pri_req
R/W
This field specifies the maximum number of priority arbitration requests for asynchronous request
packets that the link is permitted to make of the PHY during fairness interval.
4−23
4.28 Link Control Register
The link control set/clear register provides the control flags that enable and configure the link core protocol portions
of the TSB12LV23. It contains controls for the receiver and cycle timer.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Type
Default
Bit
Link control
R
0
R
0
R
0
R
0
R
0
R
0
R
0
9
R
0
8
R
0
7
RSC RSCU RSC
R
0
3
R
0
2
R
0
1
R
0
0
X
X
X
15
14
13
12
11
10
6
5
4
Name
Type
Default
Link control
R
0
R
0
R
0
R
0
R
0
RSC
X
RSC
X
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
Register:
Type:
Offset:
Link control
Read/Set/Clear/Update
E0h
E4h
set register
clear register
Default:
00X0 0X00h
Table 4−20. Link Control Register Description
BIT
31−23
22
FIELD NAME
RSVD
TYPE
R
DESCRIPTION
Reserved. Bits 31−23 return 0s when read.
cycleSource
RSC
When this bit is set, the cycle timer uses an external source (CYCLEIN) to determine when to roll over
the cycle timer. When this bit is cleared, the cycle timer rolls over when the timer reaches 3072 cycles
of the 24.576 MHz clock (125 μs).
21
20
cycleMaster
RSCU When this bit is set, and the PHY has notified the TSB12LV23 that it is root, the TSB12LV23 generates
a cycle start packet every time the cycle timer rolls over, based on the setting of bit 22. When this bit is
cleared, the OHCI-Lynx accepts received cycle start packets to maintain synchronization with the
node which is sending them. This bit is automatically reset when bit 25 (cycleTooLong) of the interrupt
event register (see Section 4.21) is set and cannot be set until bit 25 (cycleTooLong) is cleared.
CycleTimerEnable
RSC
When this bit is set, the cycle timer offset counts cycles of the 24.576 MHz clock and rolls over at the
appropriate time based on the settings of the above bits. When this bit is cleared, the cycle timer offset
does not count.
19−11
RSVD
R
Reserved. Bits 19−11 return 0s when read.
10
RcvPhyPkt
RSC
When this bit is set, the receiver accepts incoming PHY packets into the AR request context if the AR
request context is enabled. This does not control receipt of self-identification packets.
9
RcvSelfID
RSVD
RSC
R
When this bit is set, the receiver accepts incoming self-identification packets. Before setting this bit to
1, software must ensure that the self ID buffer pointer register contains a valid address.
8−0
Reserved. Bits 8−0 return 0s when read.
4−24
4.29 Node Identification Register
The node identification register contains the address of the node on which the OHCI-Lynx chip resides, and indicates
the valid node number status. The 16-bit combination of the busNumber field (bits 15−6) and the NodeNumber field
(bits 5−0) is referred to as the node ID.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Type
Default
Bit
Node identification
RU
0
RU
0
R
0
R
0
RU
0
R
0
R
0
9
R
0
8
R
0
7
R
0
6
R
0
5
R
0
4
R
0
3
R
0
2
R
0
1
R
0
0
15
14
13
12
11
10
Name
Type
Default
Node identification
RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU
RU
X
RU
X
RU
X
RU
X
RU
X
RU
X
1
1
1
1
1
1
1
1
1
1
Register:
Type:
Offset:
Default:
Node identification
Read/Write/Update
E8h
0000 FFXXh
Table 4−21. Node Identification Register Description
BIT
FIELD NAME
TYPE
DESCRIPTION
31
iDValid
RU
This bit indicates whether or not the TSB12LV23 has a valid node number. It is cleared when a 1394 bus
reset is detected and set when the TSB12LV23 receives a new node number from the PHY.
30
root
RSVD
RU
R
This bit is set during the bus reset process if the attached PHY is root.
Reserved. Bits 29−28 return 0s when read.
29−28
27
CPS
RU
R
Set if the PHY is reporting that cable power status is OK.
Reserved. Bits 26−16 return 0s when read.
26−16
15−6
RSVD
busNumber
RWU
This number is used to identify the specific 1394 bus the TSB12LV23 belongs to when multiple
1394-compatible buses are connected via a bridge.
5−0
NodeNumber
RU
This number is the physical node number established by the PHY during self-identification. It is
automatically set to the value received from the PHY after the self-identification phase. If the PHY sets
the nodeNumber to 63, then software should not set ContextControl.run for either of the AT DMA
contexts.
4−25
4.30 PHY Layer Control Register
The PHY layer control register is used to read or write a PHY register.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Type
Default
Bit
PHY layer control
RU
0
R
0
R
0
R
0
RU
0
RU
0
RU
0
RU
0
RU
0
RU
0
RU
0
RU
0
RU
0
RU
0
RU
0
RU
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Type
Default
PHY layer control
RWU RWU
R
0
R
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
0
0
Register:
Type:
Offset:
Default:
PHY layer control
Read/Write/Update
ECh
0000 0000h
Table 4−22. PHY Control Register Description
BIT
FIELD NAME
TYPE
DESCRIPTION
31
rdDone
RU
This bit is cleared to 0 by the TSB12LV23 when either bit 15 (rdReg) or bit 14 (wrReg) is set. This bit is
set when a register transfer is received from the PHY.
30−28
27−24
23−16
15
RSVD
rdAddr
rdData
rdReg
R
Reserved. Bits 30−28 return 0s when read.
RU
This is the address of the register most recently received from the PHY.
This field is the contents of a PHY register which has been read.
RU
RWU
This bit is set by software to initiate a read request to a PHY register and is cleared by hardware when
the request has been sent. Bits 14 (wrReg) and 15 (rdReg) must be used exclusively.
14
wrReg
RWU
This bit is set by software to initiate a write request to a PHY register and is cleared by hardware when
the request has been sent. Bits 14 (wrReg) and 15 (rdReg) must be used exclusively.
13−12
11−8
7−0
RSVD
regAddr
wrData
R
Reserved. Bits 13−12 return 0s when read.
R/W
R/W
This field is the address of the PHY register to be written or read.
This field is the data to be written to a PHY register and is ignored for reads.
4−26
4.31 Isochronous Cycle Timer Register
The isochronous cycle timer register indicates the current cycle number and offset. When the TSB12LV23 is cycle
master, this register is transmitted with the cycle start message. When the TSB12LV23 is not cycle master, this
register is loaded with the data field in an incoming cycle start. In the event that the cycle start message is not received,
the fields can continue incrementing on their own (if programmed) to maintain a local time reference.
Bit
31
30
29
28
27
26
25
Isochronous cycle timer
RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU
24
23
22
21
20
19
18
17
16
Name
Type
Default
Default
Bit
X
0
X
0
X
0
X
0
X
0
X
0
X
0
9
X
0
8
X
0
7
X
0
6
X
0
5
X
0
4
X
0
3
X
0
2
X
0
1
X
0
0
15
14
13
12
11
10
Name
Type
Isochronous cycle timer
RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU
Default
Default
X
0
X
0
X
0
X
0
X
0
X
0
X
0
X
0
X
0
X
0
X
0
X
0
X
0
X
0
X
0
X
0
Register:
Type:
Offset:
Default:
Isochronous cycle timer
Read/Write/Update
F0h
XXXX XXXXh
Table 4−23. Isochronous Cycle Timer Register Description
BIT
FIELD NAME
cycleSeconds
cycleCount
TYPE
RWU
RWU
RWU
DESCRIPTION
31−25
24−12
11−0
This field counts seconds [rollovers from bits 24−12 (cycleCount field)] modulo 128.
This field counts cycles [rollovers from bits 11−0 (cycleOffset field)] modulo 8000.
cycleOffset
This field counts 24.576 MHz clocks modulo 3072, i.e., 125 μs. If an external 8 kHz clock configuration
is being used, then this bit must be set to 0 at each tick of the external clock.
4−27
4.32 Asynchronous Request Filter High Register
The asynchronous request filter high set/clear register is used to enable asynchronous receive requests on a per
node basis, and handles the upper node IDs. When a packet is destined for either the physical request context or
the ARRQ context, the source node ID is examined. If the bit corresponding to the node ID is not set in this register,
then the packet is not acknowledged and the request is not queued. The node ID comparison is done if the source
node is on the same bus as the TSB12LV23. All nonlocal bus sourced packets are not acknowledged unless bit 31
in this register is set.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Type
Default
Bit
Asynchronous request filter high
RSC
0
RSC
0
RSC
0
RSC
0
RSC
0
RSC
0
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Type
Default
Asynchronous request filter high
RSC
0
RSC
0
RSC
0
RSC
0
RSC
0
RSC
0
RSC
0
RSC
0
RSC
0
RSC
0
RSC
0
RSC
0
RSC
0
RSC
0
RSC
0
RSC
0
Register:
Type:
Offset:
Asynchronous request filter high
Read/Set/Clear
100h set register
104h clear register
0000 0000h
Default:
Table 4−24. Asynchronous Request Filter High Register Description
BIT
FIELD NAME
TYPE
DESCRIPTION
31
asynReqAllBuses
asynReqResource62
asynReqResource61
asynReqResource60
asynReqResource59
asynReqResource58
asynReqResource57
asynReqResource56
asynReqResource55
asynReqResource54
asynReqResource53
asynReqResource52
asynReqResource51
RSC
If this bit is set, then all asynchronous requests received by the TSB12LV23 from non-local bus
nodes are accepted.
30
29
28
27
26
25
24
23
22
21
20
19
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
If this bit is set for local bus node number 62, then asynchronous requests received by the
TSB12LV23 from that node are accepted.
If this bit is set for local bus node number 61, then asynchronous requests received by the
TSB12LV23 from that node are accepted.
If this bit is set for local bus node number 60, then asynchronous requests received by the
TSB12LV23 from that node are accepted.
If this bit is set for local bus node number 59, then asynchronous requests received by the
TSB12LV23 from that node are accepted.
If this bit is set for local bus node number 58, then asynchronous requests received by the
TSB12LV23 from that node are accepted.
If this bit is set for local bus node number 57, then asynchronous requests received by the
TSB12LV23 from that node are accepted.
If this bit is set for local bus node number 56, then asynchronous requests received by the
TSB12LV23 from that node are accepted.
If this bit is set for local bus node number 55, then asynchronous requests received by the
TSB12LV23 from that node are accepted.
If this bit is set for local bus node number 54, then asynchronous requests received by the
TSB12LV23 from that node are accepted.
If this bit is set for local bus node number 53, then asynchronous requests received by the
TSB12LV23 from that node are accepted.
If this bit is set for local bus node number 52, then asynchronous requests received by the
TSB12LV23 from that node are accepted.
If this bit is set for local bus node number 51, then asynchronous requests received by the
TSB12LV23 from that node are accepted.
4−28
Table 4−24. Asynchronous Request Filter High Register Description (Continued)
BIT
FIELD NAME
TYPE
DESCRIPTION
18
asynReqResource50
RSC
If this bit is set for local bus node number 50, then asynchronous requests received by the
TSB12LV23 from that node are accepted.
17
16
15
14
13
12
11
10
9
asynReqResource49
asynReqResource48
asynReqResource47
asynReqResource46
asynReqResource45
asynReqResource44
asynReqResource43
asynReqResource42
asynReqResource41
asynReqResource40
asynReqResource39
asynReqResource38
asynReqResource37
asynReqResource36
asynReqResource35
asynReqResource34
asynReqResource33
asynReqResource32
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
If this bit is set for local bus node number 49, then asynchronous requests received by the
TSB12LV23 from that node are accepted.
If this bit is set for local bus node number 48, then asynchronous requests received by the
TSB12LV23 from that node are accepted.
If this bit is set for local bus node number 47, then asynchronous requests received by the
TSB12LV23 from that node are accepted.
If this bit is set for local bus node number 46, then asynchronous requests received by the
TSB12LV23 from that node are accepted.
If this bit is set for local bus node number 45, then asynchronous requests received by the
TSB12LV23 from that node are accepted.
If this bit is set for local bus node number 44, then asynchronous requests received by the
TSB12LV23 from that node are accepted.
If this bit is set for local bus node number 43, then asynchronous requests received by the
TSB12LV23 from that node are accepted.
If this bit is set for local bus node number 42, then asynchronous requests received by the
TSB12LV23 from that node are accepted.
If this bit is set for local bus node number 41, then asynchronous requests received by the
TSB12LV23 from that node are accepted.
8
If this bit is set for local bus node number 40, then asynchronous requests received by the
TSB12LV23 from that node are accepted.
7
If this bit is set for local bus node number 39, then asynchronous requests received by the
TSB12LV23 from that node are accepted.
6
If this bit is set for local bus node number 38, then asynchronous requests received by the
TSB12LV23 from that node are accepted.
5
If this bit is set for local bus node number 37, then asynchronous requests received by the
TSB12LV23 from that node are accepted.
4
If this bit is set for local bus node number 36, then asynchronous requests received by the
TSB12LV23 from that node are accepted.
3
If this bit is set for local bus node number 35, then asynchronous requests received by the
TSB12LV23 from that node are accepted.
2
If this bit is set for local bus node number 34, then asynchronous requests received by the
TSB12LV23 from that node are accepted.
1
If this bit is set for local bus node number 33, then asynchronous requests received by the
TSB12LV23 from that node are accepted.
0
If this bit is set for local bus node number 32, then asynchronous requests received by the
TSB12LV23 from that node are accepted.
4−29
4.33 Asynchronous Request Filter Low Register
The asynchronous request filter low set/clear register is used to enable asynchronous receive requests on a per node
basis, and handles the lower node IDs. Other than filtering different node IDs, this register behaves identically to the
asynchronous request filter high register.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Type
Default
Bit
Asynchronous request filter low
RSC
0
RSC
0
RSC
0
RSC
0
RSC
0
RSC
0
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Type
Default
Asynchronous request filter low
RSC
0
RSC
0
RSC
0
RSC
0
RSC
0
RSC
0
RSC
0
RSC
0
RSC
0
RSC
0
RSC
0
RSC
0
RSC
0
RSC
0
RSC
0
RSC
0
Register:
Type:
Offset:
Asynchronous request filter low
Read/Set/Clear
108h set register
10Ch clear register
0000 0000h
Default:
Table 4−25. Asynchronous Request Filter Low Register Description
BIT
FIELD NAME
TYPE
DESCRIPTION
31
asynReqResource31
asynReqResource30
asynReqResource29
asynReqResource28
asynReqResource27
asynReqResource26
asynReqResource25
asynReqResource24
asynReqResource23
asynReqResource22
asynReqResource21
asynReqResource20
asynReqResource19
asynReqResource18
asynReqResource17
RSC
If this bit is set for local bus node number 31, then asynchronous requests received by the
TSB12LV23 from that node are accepted.
30
29
28
27
26
25
24
23
22
21
20
19
18
17
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
If this bit is set for local bus node number 30, then asynchronous requests received by the
TSB12LV23 from that node are accepted.
If this bit is set for local bus node number 29, then asynchronous requests received by the
TSB12LV23 from that node are accepted.
If this bit is set for local bus node number 28, then asynchronous requests received by the
TSB12LV23 from that node are accepted.
If this bit is set for local bus node number 27, then asynchronous requests received by the
TSB12LV23 from that node are accepted.
If this bit is set for local bus node number 26, then asynchronous requests received by the
TSB12LV23 from that node are accepted.
If this bit is set for local bus node number 25, then asynchronous requests received by the
TSB12LV23 from that node are accepted.
If this bit is set for local bus node number 24, then asynchronous requests received by the
TSB12LV23 from that node are accepted.
If this bit is set for local bus node number 23, then asynchronous requests received by the
TSB12LV23 from that node are accepted.
If this bit is set for local bus node number 22, then asynchronous requests received by the
TSB12LV23 from that node are accepted.
If this bit is set for local bus node number 21, then asynchronous requests received by the
TSB12LV23 from that node are accepted.
If this bit is set for local bus node number 20, then asynchronous requests received by the
TSB12LV23 from that node are accepted.
If this bit is set for local bus node number 19, then asynchronous requests received by the
TSB12LV23 from that node are accepted.
If this bit is set for local bus node number 18, then asynchronous requests received by the
TSB12LV23 from that node are accepted.
If this bit is set for local bus node number 17, then asynchronous requests received by the
TSB12LV23 from that node are accepted.
4−30
Table 4−25. Asynchronous Request Filter Low Register Description (Continued)
BIT
FIELD NAME
TYPE
DESCRIPTION
16
asynReqResource16
RSC
If this bit is set for local bus node number 16, then asynchronous requests received by the
TSB12LV23 from that node are accepted.
15
14
13
12
11
10
9
asynReqResource15
asynReqResource14
asynReqResource13
asynReqResource12
asynReqResource11
asynReqResource10
asynReqResource9
asynReqResource8
asynReqResource7
asynReqResource6
asynReqResource5
asynReqResource4
asynReqResource3
asynReqResource2
asynReqResource1
asynReqResource0
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
If this bit is set for local bus node number 15, then asynchronous requests received by the
TSB12LV23 from that node are accepted.
If this bit is set for local bus node number 14, then asynchronous requests received by the
TSB12LV23 from that node are accepted.
If this bit is set for local bus node number 13, then asynchronous requests received by the
TSB12LV23 from that node are accepted.
If this bit is set for local bus node number 12, then asynchronous requests received by the
TSB12LV23 from that node are accepted.
If this bit is set for local bus node number 11, then asynchronous requests received by the
TSB12LV23 from that node are accepted.
If this bit is set for local bus node number 10, then asynchronous requests received by the
TSB12LV23 from that node are accepted.
If this bit is set for local bus node number 9, then asynchronous requests received by the
TSB12LV23 from that node are accepted.
8
If this bit is set for local bus node number 8, then asynchronous requests received by the
TSB12LV23 from that node are accepted.
7
If this bit is set for local bus node number 7, then asynchronous requests received by the
TSB12LV23 from that node are accepted.
6
If this bit is set for local bus node number 6, then asynchronous requests received by the
TSB12LV23 from that node are accepted.
5
If this bit is set for local bus node number 5, then asynchronous requests received by the
TSB12LV23 from that node are accepted.
4
If this bit is set for local bus node number 4, then asynchronous requests received by the
TSB12LV23 from that node are accepted.
3
If this bit is set for local bus node number 3, then asynchronous requests received by the
TSB12LV23 from that node are accepted.
2
If this bit is set for local bus node number 2, then asynchronous requests received by the
TSB12LV23 from that node are accepted.
1
If this bit is set for local bus node number 1, then asynchronous requests received by the
TSB12LV23 from that node are accepted.
0
If this bit is set for local bus node number 0, then asynchronous requests received by the
TSB12LV23 from that node are accepted.
4−31
4.34 Physical Request Filter High Register
The physical request filter high set/clear register is used to enable physical receive requests on a per node basis and
handles the upper node IDs. When a packet is destined for the physical request context and the node ID has been
compared against the ARRQ registers, then the comparison is done again with this register. If the bit corresponding
to the node ID is not set in this register, then the request is handled by the ARRQ context instead of the physical
request context.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Type
Default
Bit
Physical request filter high
RSC
0
RSC
0
RSC
0
RSC
0
RSC
0
RSC
0
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Type
Default
Physical request filter high
RSC
0
RSC
0
RSC
0
RSC
0
RSC
0
RSC
0
RSC
0
RSC
0
RSC
0
RSC
0
RSC
0
RSC
0
RSC
0
RSC
0
RSC
0
RSC
0
Register:
Type:
Offset:
Physical request filter high
Read/Set/Clear
110h set register
114h clear register
0000 0000h
Default:
Table 4−26. Physical Request Filter High Register Description
BIT
FIELD NAME
TYPE
DESCRIPTION
31
physReqAllBusses
physReqResource62
physReqResource61
physReqResource60
physReqResource59
physReqResource58
physReqResource57
physReqResource56
physReqResource55
physReqResource54
physReqResource53
physReqResource52
physReqResource51
physReqResource50
RSC
If this bit is set, then all asynchronous requests received by the TSB12LV23 from non-local bus
nodes are accepted.
30
29
28
27
26
25
24
23
22
21
20
19
18
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
If this bit is set for local bus node number 62, then physical requests received by the TSB12LV23
from that node are handled through the physical request context.
If this bit is set for local bus node number 61, then physical requests received by the TSB12LV23
from that node are handled through the physical request context.
If this bit is set for local bus node number 60, then physical requests received by the TSB12LV23
from that node are handled through the physical request context.
If this bit is set for local bus node number 59, then physical requests received by the TSB12LV23
from that node are handled through the physical request context.
If this bit is set for local bus node number 58, then physical requests received by the TSB12LV23
from that node are handled through the physical request context.
If this bit is set for local bus node number 57, then physical requests received by the TSB12LV23
from that node are handled through the physical request context.
If this bit is set for local bus node number 56, then physical requests received by the TSB12LV23
from that node are handled through the physical request context.
If this bit is set for local bus node number 55, then physical requests received by the TSB12LV23
from that node are handled through the physical request context.
If this bit is set for local bus node number 54, then physical requests received by the TSB12LV23
from that node are handled through the physical request context.
If this bit is set for local bus node number 53, then physical requests received by the TSB12LV23
from that node are handled through the physical request context.
If this bit is set for local bus node number 52, then physical requests received by the TSB12LV23
from that node are handled through the physical request context.
If this bit is set for local bus node number 51, then physical requests received by the TSB12LV23
from that node are handled through the physical request context.
If this bit is set for local bus node number 50, then physical requests received by the TSB12LV23
from that node are handled through the physical request context.
4−32
Table 4−26. Physical Request Filter High Register Description (Continued)
BIT
FIELD NAME
TYPE
DESCRIPTION
17
physReqResource49
RSC
If this bit is set for local bus node number 49, then physical requests received by the TSB12LV23
from that node are handled through the physical request context.
16
15
14
13
12
11
10
9
physReqResource48
physReqResource47
physReqResource46
physReqResource45
physReqResource44
physReqResource43
physReqResource42
physReqResource41
physReqResource40
physReqResource39
physReqResource38
physReqResource37
physReqResource36
physReqResource35
physReqResource34
physReqResource33
physReqResource32
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
If this bit is set for local bus node number 48, then physical requests received by the TSB12LV23
from that node are handled through the physical request context.
If this bit is set for local bus node number 47, then physical requests received by the TSB12LV23
from that node are handled through the physical request context.
If this bit is set for local bus node number 46, then physical requests received by the TSB12LV23
from that node are handled through the physical request context.
If this bit is set for local bus node number 45, then physical requests received by the TSB12LV23
from that node are handled through the physical request context.
If this bit is set for local bus node number 44, then physical requests received by the TSB12LV23
from that node are handled through the physical request context.
If this bit is set for local bus node number 43, then physical requests received by the TSB12LV23
from that node are handled through the physical request context.
If this bit is set for local bus node number 42, then physical requests received by the TSB12LV23
from that node are handled through the physical request context.
If this bit is set for local bus node number 41, then physical requests received by the TSB12LV23
from that node are handled through the physical request context.
8
If this bit is set for local bus node number 40, then physical requests received by the TSB12LV23
from that node are handled through the physical request context.
7
If this bit is set for local bus node number 39, then physical requests received by the TSB12LV23
from that node are handled through the physical request context.
6
If this bit is set for local bus node number 38, then physical requests received by the TSB12LV23
from that node are handled through the physical request context.
5
If this bit is set for local bus node number 37, then physical requests received by the TSB12LV23
from that node are handled through the physical request context.
4
If this bit is set for local bus node number 36, then physical requests received by the TSB12LV23
from that node are handled through the physical request context.
3
If this bit is set for local bus node number 35, then physical requests received by the TSB12LV23
from that node are handled through the physical request context.
2
If this bit is set for local bus node number 34, then physical requests received by the TSB12LV23
from that node are handled through the physical request context.
1
If this bit is set for local bus node number 33, then physical requests received by the TSB12LV23
from that node are handled through the physical request context.
0
If this bit is set for local bus node number 32, then physical requests received by the TSB12LV23
from that node are handled through the physical request context.
4−33
4.35 Physical Request Filter Low Register
The physical request filter low set/clear register is used to enable physical receive requests on a per node basis and
handles the lower node IDs. When a packet is destined for the physical request context and the node ID has been
compared against the asynchronous request filter registers, then the node ID comparison is done again with this
register. If the bit corresponding to the node ID is not set in this register, then the request is handled by the
asynchronous request context instead of the physical request context.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Type
Default
Bit
Physical request filter low
RSC
0
RSC
0
RSC
0
RSC
0
RSC
0
RSC
0
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Type
Default
Physical request filter low
RSC
0
RSC
0
RSC
0
RSC
0
RSC
0
RSC
0
RSC
0
RSC
0
RSC
0
RSC
0
RSC
0
RSC
0
RSC
0
RSC
0
RSC
0
RSC
0
Register:
Type:
Offset:
Physical request filter low
Read/Set/Clear
118h set register
11Ch clear register
0000 0000h
Default:
Table 4−27. Physical Request Filter Low Register Description
BIT
FIELD NAME
TYPE
DESCRIPTION
31
physReqResource31
physReqResource30
physReqResource29
physReqResource28
physReqResource27
physReqResource26
physReqResource25
physReqResource24
physReqResource23
physReqResource22
physReqResource21
physReqResource20
physReqResource19
physReqResource18
RSC
If this bit is set for local bus node number 31, then physical requests received by the TSB12LV23
from that node are handled through the physical request context.
30
29
28
27
26
25
24
23
22
21
20
19
18
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
If this bit is set for local bus node number 30, then physical requests received by the TSB12LV23
from that node are handled through the physical request context.
If this bit is set for local bus node number 29, then physical requests received by the TSB12LV23
from that node are handled through the physical request context.
If this bit is set for local bus node number 28, then physical requests received by the TSB12LV23
from that node are handled through the physical request context.
If this bit is set for local bus node number 27, then physical requests received by the TSB12LV23
from that node are handled through the physical request context.
If this bit is set for local bus node number 26, then physical requests received by the TSB12LV23
from that node are handled through the physical request context.
If this bit is set for local bus node number 25, then physical requests received by the TSB12LV23
from that node are handled through the physical request context.
If this bit is set for local bus node number 24, then physical requests received by the TSB12LV23
from that node are handled through the physical request context.
If this bit is set for local bus node number 23, then physical requests received by the TSB12LV23
from that node are handled through the physical request context.
If this bit is set for local bus node number 22, then physical requests received by the TSB12LV23
from that node are handled through the physical request context.
If this bit is set for local bus node number 21, then physical requests received by the TSB12LV23
from that node are handled through the physical request context.
If this bit is set for local bus node number 20, then physical requests received by the TSB12LV23
from that node are handled through the physical request context.
If this bit is set for local bus node number 19, then physical requests received by the TSB12LV23
from that node are handled through the physical request context.
If this bit is set for local bus node number 18, then physical requests received by the TSB12LV23
from that node are handled through the physical request context.
4−34
Table 4−27. Physical Request Filter Low Register Description (Continued)
BIT
FIELD NAME
TYPE
DESCRIPTION
17
physReqResource17
RSC
If this bit is set for local bus node number 17, then physical requests received by the TSB12LV23
from that node are handled through the physical request context.
16
15
14
13
12
11
10
9
physReqResource16
physReqResource15
physReqResource14
physReqResource13
physReqResource12
physReqResource11
physReqResource10
physReqResource9
physReqResource8
physReqResource7
physReqResource6
physReqResource5
physReqResource4
physReqResource3
physReqResource2
physReqResource1
physReqResource0
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
If this bit is set for local bus node number 16, then physical requests received by the TSB12LV23
from that node are handled through the physical request context.
If this bit is set for local bus node number 15, then physical requests received by the TSB12LV23
from that node are handled through the physical request context.
If this bit is set for local bus node number 14, then physical requests received by the TSB12LV23
from that node are handled through the physical request context.
If this bit is set for local bus node number 13, then physical requests received by the TSB12LV23
from that node are handled through the physical request context.
If this bit is set for local bus node number 12, then physical requests received by the TSB12LV23
from that node are handled through the physical request context.
If this bit is set for local bus node number 11, then physical requests received by the TSB12LV23
from that node are handled through the physical request context.
If this bit is set for local bus node number 10, then physical requests received by the TSB12LV23
from that node are handled through the physical request context.
If this bit is set for local bus node number 9, then physical requests received by the TSB12LV23
from that node are handled through the physical request context.
8
If this bit is set for local bus node number 8, then physical requests received by the TSB12LV23
from that node are handled through the physical request context.
7
If this bit is set for local bus node number 7, then physical requests received by the TSB12LV23
from that node are handled through the physical request context.
6
If this bit is set for local bus node number 6, then physical requests received by the TSB12LV23
from that node are handled through the physical request context.
5
If this bit is set for local bus node number 5, then physical requests received by the TSB12LV23
from that node are handled through the physical request context.
4
If this bit is set for local bus node number 4, then physical requests received by the TSB12LV23
from that node are handled through the physical request context.
3
If this bit is set for local bus node number 3, then physical requests received by the TSB12LV23
from that node are handled through the physical request context.
2
If this bit is set for local bus node number 2, then physical requests received by the TSB12LV23
from that node are handled through the physical request context.
1
If this bit is set for local bus node number 1, then physical requests received by the TSB12LV23
from that node are handled through the physical request context.
0
If this bit is set for local bus node number 0, then physical requests received by the TSB12LV23
from that node are handled through the physical request context.
4−35
4.36 Physical Upper Bound Register (Optional Register)
The physical upper bound register is an optional register and is not implemented. It returns all 0s when read.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Type
Default
Bit
Physical upper bound
R
0
R
0
R
0
R
0
R
0
R
0
R
0
9
R
0
8
R
0
7
R
0
6
R
0
5
R
0
4
R
0
3
R
0
2
R
0
1
R
0
0
15
14
13
12
11
10
Name
Type
Default
Physical upper bound
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
Register:
Type:
Offset:
Default:
Physical upper bound
Read-only
120h
0000 0000h
4−36
4.37 Asynchronous Context Control Register
The asynchronous context control set/clear register controls the state and indicates status of the DMA context.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Type
Default
Bit
Asynchronous context control
R
0
R
0
R
0
R
0
R
0
R
0
R
0
9
R
0
8
R
0
7
R
0
6
R
0
5
R
0
4
R
0
3
R
0
2
R
0
1
R
0
0
15
14
13
12
11
10
Name
Type
Default
Asynchronous context control
RSCU
0
R
0
R
0
RSU
X
RU
0
RU
0
R
0
R
0
RU
X
RU
X
RU
X
RU
X
RU
X
RU
X
RU
X
RU
X
Register:
Type:
Offset:
Asynchronous context control
Read/Set/Clear/Update
180h set register
184h clear register [ATRQ]
1A0h set register [ATRS]
1A4h clear register [ATRS]
1C0h set register [ARRQ]
1C4h clear register [ARRQ]
1E0h set register [ATRS]
[ATRQ]
1E4h clear register [ATRS]
0000 X0XXh
Default:
Table 4−28. Asynchronous Context Control Register Description
BIT
31−16
15
FIELD NAME
RSVD
TYPE
DESCRIPTION
Reserved. Bits 31−16 return 0s when read.
R
run
RSCU This bit is set by software to enable descriptor processing for the context and cleared by software to
stop descriptor processing. The TSB12LV23 changes this bit only on a hardware or software reset.
14−13
RSVD
wake
R
Reserved. Bits 14−13 return 0s when read.
12
RSU
Software sets this bit to cause the TSB12LV23 to continue or resume descriptor processing. The
TSB12LV23 clears this bit on every descriptor fetch.
11
dead
RU
The TSB12LV23 sets this bit when it encounters a fatal error and clears the bit when software resets
bit 15 (run).
10
active
RSVD
spd
RU
R
The TSB12LV23 sets this bit to 1 when it is processing descriptors.
9−8
7−5
Reserved. Bits 9−8 return 0s when read.
RU
This field indicates the speed at which a packet was received or transmitted, and only contains
meaningful information for receive contexts. This field is encoded as:
000 = 100 Mbits/sec,
001 = 200 Mbits/sec,
010 = 400 Mbits/sec, and all other values are reserved.
4−0
eventcode
RU
This field holds the acknowledge sent by the Link core for this packet or an internally generated error
code if the packet was not transferred successfully.
4−37
4.38 Asynchronous Context Command Pointer Register
The asynchronous context command pointer register contains a pointer to the address of the first descriptor block
that the TSB12LV23 accesses when software enables the context by setting the asynchronous context control
register bit 15 (run).
Bit
31
30
29
28
27
26
Asynchronous context command pointer
RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU
25
24
23
22
21
20
19
18
17
16
Name
Type
Default
Bit
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Type
Default
Asynchronous context command pointer
RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Register:
Type:
Offset:
Asynchronous context command pointer
Read/Write/Update
19Ch [ATRQ]
1ACh [ATRS]
1CCh [ATRQ]
1ECh [ATRS]
XXXX XXXXh
Default:
Table 4−29. Asynchronous Context Command Pointer Register Description
BIT
31−4
3−0
FIELD NAME
descriptorAddress
Z
TYPE
RWU
RWU
DESCRIPTION
Contains the upper 28 bits of the address of a 16-byte aligned descriptor block.
Indicates the number of contiguous descriptors at the address pointed to by the descriptor address. If
Z is 0, then it indicates that the descriptorAddress field (bits 31−4) is not valid.
4−38
4.39 Isochronous Transmit Context Control Register
The isochronous transmit context control set/clear register controls options, state, and status for the isochronous
transmit DMA contexts. The n value in the following register addresses indicates the context number (n = 0, 1, 2, 3,…).
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Type
Default
Bit
Isochronous transmit context control
RSCU RSC
RSC
X
RSC
X
RSC
X
RSC
X
RSC
X
RSC RSC
RSC
X
RSC
X
RSC
X
RSC
X
RSC
X
RSC
X
RSC
X
X
X
X
X
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Type
Default
Isochronous transmit context control
RSC
0
R
0
R
0
RSU
X
RU
0
RU
0
R
0
R
0
RU
X
RU
X
RU
X
RU
X
RU
X
RU
X
RU
X
RU
X
Register:
Type:
Offset:
Isochronous transmit context control
Read/Set/Clear/Update
200h + (16 * n)
204h + (16 * n)
XXXX X0XXh
set register
clear register
Default:
Table 4−30. Isochronous Transmit Context Control Register Description
BIT
FIELD NAME
TYPE
DESCRIPTION
31
cycleMatchEnable
RSCU When this bit is set to 1, processing occurs such that the packet described by the context’s first
descriptor block is transmitted in the cycle whose number is specified in the cycleMatch field
(bits 30−16). The cycleMatch field (bits 30−16) must match the low order 2 bits of cycleSeconds and
the 13-bit cycleCount field in the cycle start packet that is sent or received immediately before
isochronous transmission begins. Since the isochronous transmit DMA controller may work ahead,
the processing of the first descriptor block may begin slightly in advance of the actual cycle in which
the first packet is transmitted.
The effects of this bit, however, are impacted by the values of other bits in this register and are
explained in the 1394 Open Host Controller Interface Specification. Once the context has become
active, hardware clears this bit.
30−16
cycleMatch
RSC
Contains a 15-bit value, corresponding to the low order 2 bits of the bus isochronous cycle timer
register cycleSeconds field (bits 31−25) and the cycleCount field (bits 24−12). If bit 31
(cycleMatchEnable) is set, then this isochronous transmit DMA context becomes enabled for
transmits when the low order 2 bits of the bus isochronous cycle timer register cycleSeconds field
(bits 31−25) and the cycleCount field (bits 24−12) value equal this field’s (cycleMatch) value.
15
run
RSC
This bit is set by software to enable descriptor processing for the context and cleared by software to
stop descriptor processing. The TSB12LV23 changes this bit only on a hardware or software reset.
14−13
RSVD
wake
R
Reserved. Bits 14−13 return 0s when read.
12
RSU
Software sets this bit to cause the TSB12LV23 to continue or resume descriptor processing. The
TSB12LV23 clears this bit on every descriptor fetch.
11
dead
RU
The TSB12LV23 sets this bit when it encounters a fatal error and clears the bit when software resets
bit 15 (run).
10
active
RSVD
RU
R
The TSB12LV23 sets this bit to 1 when it is processing descriptors.
Reserved. Bits 9−8 return 0s when read.
9−8
7−5
4−0
spd
RU
RU
This field in not meaningful for isochronous transmit contexts.
event code
Following an OUTPUT_LAST* command, the error code is indicated in this field. Possible values
are: ack_complete, evt_descriptor_read, evt_data_read, and evt_unknown.
4−39
4.40 Isochronous Transmit Context Command Pointer Register
The isochronous transmit context command pointer register contains a pointer to the address of the first descriptor
block that the TSB12LV23 accesses when software enables an isochronous transmit context by setting the
isochronous transmit context control register bit 15 (run). The n value in the following register addresses indicates
the context number (n = 0, 1, 2, 3,…).
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Type
Default
Bit
Isochronous transmit context command pointer
R
X
R
X
R
X
R
X
R
X
R
X
R
X
9
R
X
8
R
X
7
R
X
6
R
X
5
R
X
4
R
X
3
R
X
2
R
X
1
R
X
0
15
14
13
12
11
10
Name
Type
Default
Isochronous transmit context command pointer
R
X
R
X
R
X
R
X
R
X
R
X
R
X
R
X
R
X
R
X
R
X
R
X
R
X
R
X
R
X
R
X
Register:
Type:
Offset:
Default:
Isochronous transmit context command pointer
Read-only
20Ch + (16 * n)
XXXX XXXXh
4.41 Isochronous Receive Context Control Register
The isochronous receive context control set/clear register controls options, state, and status for the isochronous
receive DMA contexts. The n value in the following register addresses indicates the context number (n = 0, 1, 2, 3,…).
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Type
Default
Bit
Isochronous receive context control
RSC
X
RSC RSCU RSC
R
0
R
0
R
0
9
R
0
8
R
0
7
R
0
6
R
0
5
R
0
4
R
0
3
R
0
2
R
0
1
R
0
0
X
X
X
15
14
13
12
11
10
Name
Type
Default
Isochronous receive context control
RSCU
0
R
0
R
0
RSU
X
RU
0
RU
0
R
0
R
0
RU
X
RU
X
RU
X
RU
X
RU
X
RU
X
RU
X
RU
X
Register:
Type:
Offset:
Isochronous receive context control
Read/Set/Clear/Update
400h + (32 * n)
404h + (32 * n)
X000 X0XXh
set register
clear register
Default:
Table 4−31. Isochronous Receive Context Control Register Description
BIT
FIELD NAME
TYPE
DESCRIPTION
31
bufferFill
RSC
When this bit is set, received packets are placed back-to-back to completely fill each receive buffer.
When this bit is cleared, each received packet is placed in a single buffer. If bit 28 (multiChanMode)
is set to 1, then this bit must also be set to 1. The value of this bit must not be changed while bit 10
(active) or bit 15 (run) is set.
30
isochHeader
RSC
When this bit is 1, received isochronous packets include the complete 4-byte isochronous packet
header seen by the link layer. The end of the packet is marked with a xferStatus in the first doublet,
and a 16-bit timeStamp indicating the time of the most recently received (or sent) cycleStart packet.
When this bit is cleared, the packet header is stripped off of received isochronous packets. The
packet header, if received, immediately precedes the packet payload. The value of this bit must not
be changed while bit 10 (active) or bit 15 (run) is set.
4−40
Table 4−31. Isochronous Receive Context Control Register Description (Continued)
BIT
FIELD NAME
TYPE
DESCRIPTION
29
cycleMatchEnable
RSCU When this bit is set, the context begins running only when the 13-bit cycleMatch field (bits 24−12) in
the isochronous receive context match register matches the 13-bit cycleCount field in the cycleStart
packet. The effects of this bit, however, are impacted by the values of other bits in this register. Once
the context has become active, hardware clears this bit. The value of this bit must not be changed
while bit 10 (active) or bit 15 (run) is set.
28
multiChanMode
RSC
When this bit is set, the corresponding isochronous receive DMA context receives packets for all
isochronous channels enabled in the isochronous receive channel mask high and isochronous
receive channel mask low registers. The isochronous channel number specified in the isochronous
receive DMA context match register is ignored.
When this bit is cleared, the isochronous receive DMA context receives packets for that single
channel. Only one isochronous receive DMA context may use the isochronous receive channel
mask registers. If more that one isochronous receive context control register has this bit set, then
results are undefined. The value of this bit must not be changed while bit 10 (active) or bit 15 (run) is
set to 1.
27−16
RSVD
run
R
Reserved. Bits 27−16 return 0s when read.
15
RSCU This bit is set by software to enable descriptor processing for the context and cleared by software to
stop descriptor processing. The TSB12LV23 changes this bit only on a hardware or software reset.
14−13
RSVD
wake
R
Reserved. Bits 14−13 return 0s when read.
12
RSU
Software sets this bit to cause the TSB12LV23 to continue or resume descriptor processing. The
TSB12LV23 clears this bit on every descriptor fetch.
11
dead
RU
The TSB12LV23 sets this bit when it encounters a fatal error and clears the bit when software resets
bit 15 (run).
10
active
RSVD
spd
RU
R
The TSB12LV23 sets this bit to 1 when it is processing descriptors.
9−8
7−5
Reserved. Bits 9−8 return 0s when read.
RU
This field indicates the speed at which the packet was received.
000 = 100 Mbits/sec,
001 = 200 Mbits/sec, and
010 = 400 Mbits/sec. All other values are reserved.
4−0
event code
RU
Following an INPUT* command, the error code is indicated in this field.
4.42 Isochronous Receive Context Command Pointer Register
The isochronous receive context command pointer register contains a pointer to the address of the first descriptor
block that the TSB12LV23 accesses when software enables an isochronous receive context by setting the
isochronous receive context control register bit 15 (run). The n value in the following register addresses indicates the
context number (n = 0, 1, 2, 3,…).
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Type
Default
Bit
Isochronous receive context command pointer
R
X
R
X
R
X
R
X
R
X
R
X
R
X
9
R
X
8
R
X
7
R
X
6
R
X
5
R
X
4
R
X
3
R
X
2
R
X
1
R
X
0
15
14
13
12
11
10
Name
Type
Default
Isochronous receive context command pointer
R
X
R
X
R
X
R
X
R
X
R
X
R
X
R
X
R
X
R
X
R
X
R
X
R
X
R
X
R
X
R
X
Register:
Type:
Offset:
Default:
Isochronous receive context command pointer
Read-only
40Ch + (32 * n)
XXXX XXXXh
4−41
4.43 Isochronous Receive Context Match Register
The isochronous receive context match register is used to start an isochronous receive context running on a specified
cycle number, to filter incoming isochronous packets based on tag values, and to wait for packets with a specified
sync value. The n value in the following register addresses indicates the context number (n = 0, 1, 2, 3,…).
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Type
Default
Bit
Isochronous receive context match
R/W
X
R/W
X
R/W
X
R/W
X
R
0
R
0
R
0
9
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
15
14
13
12
11
10
8
7
6
5
4
3
2
1
0
Name
Type
Default
Isochronous receive context match
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R
0
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
Register:
Type:
Offset:
Default:
Isochronous receive context match
Read/Write
410Ch + (32 * n)
XXXX XXXXh
Table 4−32. Isochronous Receive Context Match Register Description
BIT
31
FIELD NAME
tag3
TYPE
R/W
R/W
R/W
R/W
R
DESCRIPTION
If this bit is set, then this context matches on iso receive packets with a tag field of 11b.
If this bit is set, then this context matches on iso receive packets with a tag field of 10b.
If this bit is set, then this context matches on iso receive packets with a tag field of 01b.
If this bit is set, then this context matches on iso receive packets with a tag field of 00b.
Reserved. Bits 27−25 return 0s when read.
30
tag2
29
tag1
28
tag0
27−25
24−12
RSVD
cycleMatch
R/W
Contains a 15-bit value, corresponding to the low order 2 bits of cycleSeconds and the 13-bit
cycleCount field in the cycleStart packet. If isochronous receive context control register bit 29
(cycleMatchEnable) is set, then this context is enabled for receives when the 2 low order bits of the bus
isochronous cycle timer register cycleSeconds field (bits 31−25) and cycleCount field (bits 24−12)
value equal this field’s (cycleMatch) value.
11−8
sync
R/W
This field contains the 4-bit field which is compared to the sync field of each iso packet for this channel
when the command descriptor’s w field is set to 11b.
7
6
RSVD
R
Reserved. Bit 7 returns 0 when read.
tag1SyncFilter
R/W
If this bit and bit 29 (tag1) are set , then packets with tag2b01 are accepted into the context if the two
most significant bits of the packets sync field are 00b. Packets with tag values other than 01b are
filtered according to tag0, tag2, and tag3 (bits 28, 30, and 31, respectively) without any additional
restrictions.
If this bit is cleared, then this context matches on isochronous receive packets as specified in
bits 28−31 (tag0−tag3) with no additional restrictions.
5−0
channelNumber
R/W
This 6-bit field indicates the isochronous channel number for which this isochronous receive DMA
context accepts packets.
4−42
5 GPIO Interface
The general-purpose input/output (GPIO) interface consists of two GPIO ports. GPIO2 and GPIO3 power up as
general-purpose inputs and are programmable via the GPIO control register. Figure 5−1 shows the schematic for
GPIO2 and GPIO3 implementation.
GPIO0 and GPIO1 are not implemented in the TSB12LV23. The terminals for these legacy GPIOs from the
TSB12LV23 have been dedicated to BMC/LINKON and LPS, respectively.
GPIO Read Data
GPIO Port
GPIO Write Data
D
Q
GPIO_Invert
GPIO Enable
Figure 5−1. GPIO2 and GPIO3
5−1
5−2
6 Serial EEPROM Interface
The TSB12LV23 provides a serial bus interface to initialize the 1394 global unique ID register and a few PCI
configuration registers through a serial EEPROM. The TSB12LV23 communicates with the serial EEPROM via the
2-wire serial interface.
After power-up the serial interface initializes the locations listed in Table 6−1. While the TSB12LV23 is accessing the
serial ROM, all incoming PCI slave accesses are terminated with retry status. Table 6−2 shows the serial ROM
memory map required for initializing the TSB12LV23 registers.
Table 6−1. Registers and Bits Loadable through Serial EEPROM
BITS LOADED
FROM EEPROM
OFFSET
REGISTER
OHCI register (24h)
OHCI register(28h)
OHCI register (50h)
PCI register (2Ch)
PCI register (2Dh)
PCI register (3Eh)
PCI register (F4h)
PCI register (F0h)
PCI register (40h)
1394 GlobalUniqueIDHi
31−0
1394 GlobalUniqueIDLo
Host control register
31−0
23
PCI subsystem ID
15−0
15−0
PCI vendor ID
PCI maximum latency, PCI minimum grant
Link enhancements control register
PCI miscellaneous register
PCI OHCI register
15−0
13, 12, 9, 8, 7, 2, 1
15, 13, 10, 5−0
0
6−1
Table 6−2. Serial EEPROM Map
BYTE
ADDRESS
BYTE DESCRIPTION
00
01
02
03
04
05
PCI maximum latency (0h)
PCI_minimum grant (0h)
PCI vendor ID
PCI vendor ID (msbyte)
PCI subsystem ID (lsbyte)
PCI subsystem ID
[7]
[6]
[5]
[4]
[3]
[2]
[1]
[0]
RSVD
Link_enhancement-
HCControl.
RSVD
RSVD
RSVD Link_enhancement- Link_enhancement-
Control.enab_unfair ProgramPhy
Enable
Control.enab_
insert_idle
Control.enab_accel
06
07
08
09
0A
0B
0C
0D
0E
0F
10
Mini ROM address
1394 GlobalUniqueIDHi (lsbyte 0)
1394 GlobalUniqueIDHi (byte 1)
1394 GlobalUniqueIDHi (byte 2)
1394 GlobalUniqueIDHi (msbyte 3)
1394 GlobalUniqueIDLo (lsbyte 0)
1394 GlobalUniqueIDLo (byte 1)
1394 GlobalUniqueIDLo (byte 2)
1394 GlobalUniqueIDLo (msbyte 3)
Checksum
[15]
RSVD
[14]
RSVD
[13−12]
[11]
RSVD
[10]
RSVD
[9]
RSVD
[8]
RSVD
AT threshold
11
12
13
[7]
RSVD
[6]
RSVD
[5]
RSVD
[4]
[3]
[2]
[1]
[0]
Keep PCI
Disable GP2IIC Disable SCLK gate
Target
Abort
Disable PCI gate
[15]
PME D3 Cold
[14]
RSVD
[13]
PME
Support
D2
[12]
RSVD
[11]
RSVD
[10]
D2 support
[9]
RSVD
[8]
RSVD
[7]
RSVD
[6]
RSVD
[5]
RSVD
[4]
RSVD
[3]
RSVD
[2]
RSVD
[1]
RSVD
[0]
Global
swap
14
15−1E
1F
CIS offset address
RSVD
RSVD
6−2
7 Electrical Characteristics
7.1 Absolute Maximum Ratings Over Operating Temperature Ranges†
Supply voltage range, V
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 3.6 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 5.5 V
CC
CCP
Input voltage range for PCI, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 to V
Input voltage range for Miscellaneous and PHY interface, V . . . . . . . . . . . . . . . . . . . . . . . −0.5 to V
Output voltage range for PCI, V
Input voltage range for Miscellaneous and PHY interface, V . . . . . . . . . . . . . . . . . . . . . . −0.5 to V
+ 0.5 V
+ 0.5 V
+ 0.5 V
+ 0.5 V
I
CCP
I
CCI
CCP
CCP
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 to V
O
O
Input clamp current, I (V < 0 or V > V ) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
IK
I
I
CC
Output clamp current, I (V < 0 or V > V ) (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
OK
O
O
CC
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
†
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied.
Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. Applies to external input and bidirectional buffers. For 5-V tolerant use V > V . For PCI use V > V .
I
CC
I
CCP
2. Applies to external output and bidirectional buffers. For 5-V tolerant use V > V . For PCI use V > V .
O
CC
O
CCP
7−1
7.2 Recommended Operating Conditions
OPERATION
3.3 V
MIN
NOM
3.3
3.3
5
MAX
3.6
UNIT
V
V
Core voltage
Commercial
Commercial
3
V
CC
3.3 V
3
3.6
PCI I/O clamping voltage
V
V
CCP
5 V
4.5
5.5
3.3 V
0.475 V
V
CCP
V
CCP
CCP
PCI
5 V
2
2
2
0
0
0
0
0
0
0
0
0
0
0
0
0
†
V
V
High-level input voltage
Low-level input voltage
IH
PHY interface
Miscellaneous
V
CC
CC
‡
V
3.3 V
5 V
0.325 V
0.8
CCP
PCI
†
V
IL
PHY interface
Miscellaneous
PCI
0.8
‡
‡
‡
0.8
3.3 V
3.3 V
V
V
V
V
V
V
CCP
PHY interface
Miscellaneous
PCI
V
V
Input voltage
V
V
CCP
CCP
CCP
CCP
I
§
PHY interface
Miscellaneous
PCI
Output voltage
O
CCP
t
t
Input transition time (t and t )
6
ns
°C
°C
r
f
T
A
Operating ambient temperature
Virtual junction temperature
25
25
70
¶
T
J
115
†
‡
§
¶
Applies for external inputs and bidirectional buffers without hysteresis.
Miscellaneous pins are: GPIO2, GPIO3, SDA, SCL, CYCLEOUT.
Applies for external output buffers.
The junction temperatures reflect simulation conditions. Customer is responsible for verifying junction temperature.
7−2
7.3 Electrical Characteristics Over Recommended Operating Conditions (unless
otherwise noted)
TEST
CONDITIONS
OPERATION
MIN
MAX
UNIT
I
I
I
I
I
I
I
I
I
I
= − 0.5 mA
= − 2 mA
= − 4 μA
= − 8 mA
= − 4 mA
= 1.5 mA
= 6 mA
0.9 V
OH
OH
OH
OH
OH
OL
OL
OL
OL
OL
CC
PCI
2.4
2.8
V
High-level output voltage
Low-level output voltage
V
OH
PHY interface
Miscellaneous
V
CC
V
CC
− 0.6
‡
− 0.6
0.1 V
CC
PCI
0
0.55
0.4
†
= 4 mA
V
OL
V
PHY interface
= 8 mA
‡
Miscellaneous
Output pins
Input pins
= 4 mA
0.5
20
20
I
I
3-state output high-impedance
Low-level input current
3.6 V
3.6 V
3.6 V
3.6 V
3.6 V
V
= V or GND
μA
μA
OZ
O
CC
‡
V = GND
I
IL
†
‡
I/O pins
V = GND
20
20
I
†
‡
PCI
V = V
20
I
CC
CC
I
IH
High-level input current
μA
†
‡
Others
V = V
I
†
‡
For I/O pins, input leakage (I and I ) includes I of the disabled output.
Miscellaneous pins are: GPIO2, GPIO3, SDA, SCL, CYCLEOUT.
IL
IH
OZ
7.4 Switching Characteristics for PCI Interface§
PARAMETER
MEASURED
−50% to 50%
−50% to 50%
−50% to 50%
MIN
7
TYP
MAX
UNIT
ns
t
su
Setup time before PCLK
t
h
Hold time before PCLK
0
ns
t
d
Delay time, PHY_CLK to data valid
2
11
ns
§
These parameters are ensured by design.
7.5 Switching Characteristics for PHY-Link Interface§
PARAMETER
MEASURED
−50% to 50%
−50% to 50%
−50% to 50%
MIN
6
TYP
MAX
UNIT
ns
t
su
Setup time, Dn, CTLn, LREQ to PHY_CLK
Hold time, Dn, CTLn, LREQ before PHY_CLK
Delay time, PHY_CLK to Dn, CTLn
t
h
1
ns
t
d
2
11
ns
§
These parameters are ensured by design.
7−3
7−4
8 Mechanical Information
The TSB12LV23 is packaged in a 100-pin PZ package. The following shows the mechanical dimensions for the PZ
package.
PZ (S-PQFP-G100)
PLASTIC QUAD FLATPACK
0,27
0,17
0,50
75
M
0,08
51
50
76
26
100
0,13 NOM
1
25
12,00 TYP
Gage Plane
14,20
SQ
13,80
0,25
16,20
SQ
0,05 MIN
0°−ꢀ7°
15,80
1,45
1,35
0,75
0,45
Seating Plane
0,08
1,60 MAX
4040149/B 11/96
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MO-136
8−1
8−2
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