TSV914AQDRQ1 [TI]
TSV91xA-Q1 Automotive Rail-to-Rail Input/Output, 8-MHz Operational Amplifiers;
| 型号： | TSV914AQDRQ1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | TSV91xA-Q1 Automotive Rail-to-Rail Input/Output, 8-MHz Operational Amplifiers |
| 文件： | 总37页 (文件大小：2643K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TSV912A-Q1,TSV914A-Q1
SBOSA18B – JUNE 2020 – REVISED FEBRUARY 2021
TSV91xA-Q1 Automotive Rail-to-Rail Input/Output, 8-MHz Operational Amplifiers
1 Features
3 Description
•
•
•
•
•
•
•
•
•
Rail-to-rail input and output
Low noise: 18 nV/√Hz at 1 kHz
Low power consumption: 550 µA (typical)
High-gain bandwidth: 8 MHz
Operating supply voltage from 2.5 V to 5.5 V
Low input bias current: 1 pA (typical)
Low input offset voltage: 1.5 mV (maximum)
Low offset voltage drift: ±0.5 µV/°C (typical)
ESD internal protection: ±4-kV human-body model
(HBM)
The TSV91xA-Q1 family, which includes single-,
dual-, and quad-channel operational amplifiers (op
amps), is specifically designed for general-purpose
automotive applications. Featuring rail-to-rail input
and output (RRIO) swings, wide bandwidth (8 MHz),
and low offset voltage (0.3 mV, typical), this family is
designed for a variety of applications that require a
good balance between speed and power
consumption. The op amps are unity-gain stable and
feature an ultra-low input bias current, which enables
the family to be used in applications with high-source
impedances. The low input bias current allows the
devices to be used for sensor interfaces, and active
filtering.
•
Extended temperature range: –40°C to 125°C
2 Applications
•
•
•
•
•
•
•
•
•
Optimized for AEC-Q100 grade 1 applications
Infotainment and cluster
Passive safety
The robust design of the TSV91xA-Q1 provides ease-
of-use to the circuit designer. Features include a unity-
gain stable, integrated RFI-EMI rejection filter, no
phase reversal in overdrive condition, and high
electrostatic discharge (ESD) protection (4-kV HBM).
Body electronics and lighting
HEV/EV inverter and motor control
On-board (OBC) and wireless charger
Powertrain current sensor
Advanced driver assistance systems (ADAS)
Single-supply, low-side, unidirectional current-
sensing circuit
Device Information
PACKAGE
SOT-23 (5)(2)
PART NUMBER(1)
BODY SIZE (NOM)
1.60 mm × 2.90 mm
3.91 mm × 4.90 mm
3.00 mm × 3.00 mm
8.65 mm × 3.91 mm
4.40 mm × 5.00 mm
TSV911A-Q1
SOIC (8)
TSV912A-Q1
TSV914A-Q1
VSSOP (8)
SOIC (14)
TSSOP (14)
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
(2) Package is preview only for TSV91xA-Q1.
VBUS
60
50
40
30
20
ILOAD
ZLOAD
5 V
+
TSV91x
VOUT
RSHUNT
VSHUNT
0.1 ꢀ
RF
165 kꢀ
10
0
Overshoot+
Overshoot-
RG
0
50
100
150
200
250
300
3.4 kꢀ
Capacitive Load (pF)
C025
Small-Signal Overshoot vs Load Capacitance
Low-Side Motor Control
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TSV912A-Q1, TSV914A-Q1
SBOSA18B – JUNE 2020 – REVISED FEBRUARY 2021
www.ti.com
Table of Contents
1 Features............................................................................1
2 Applications.....................................................................1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Device Comparison Table...............................................3
6 Pin Configuration and Functions...................................4
7 Specifications.................................................................. 6
7.1 Absolute Maximum Ratings........................................ 6
7.2 ESD Ratings............................................................... 6
7.3 Recommended Operating Conditions.........................6
7.4 Thermal Information: TSV912A-Q1............................ 6
7.5 Thermal Information: TSV914A-Q1............................ 7
7.6 Electrical Characteristics.............................................8
7.7 Typical Characteristics..............................................10
8 Detailed Description......................................................16
8.1 Overview...................................................................16
8.2 Functional Block Diagram.........................................16
8.3 Feature Description...................................................17
8.4 Device Functional Modes..........................................17
9 Application and Implementation..................................18
9.1 Application Information............................................. 18
9.2 Typical Application.................................................... 18
10 Power Supply Recommendations..............................20
10.1 Input and ESD Protection....................................... 20
11 Layout...........................................................................21
11.1 Layout Guidelines................................................... 21
11.2 Layout Example...................................................... 21
12 Device and Documentation Support..........................22
12.1 Related Links.......................................................... 22
12.2 Receiving Notification of Documentation Updates..22
12.3 Support Resources................................................. 22
12.4 Trademarks.............................................................22
12.5 Electrostatic Discharge Caution..............................22
12.6 Glossary..................................................................22
13 Mechanical, Packaging, and Orderable
Information.................................................................... 23
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (December 2020) to Revision B (February 2021)
Page
•
•
Deleted preview tag from VSSOP package in Device Information table............................................................ 1
Updated thermal information for DGK (VSSOP) package in Thermal Information: TSV912A-Q1 table.............6
Changes from Revision * (June 2020) to Revision A (December 2020)
Page
•
•
•
•
•
Updated the numbering format for tables, figures, and cross-references throughout the document..................1
Deleted preview tag from TSSOP package in Device Information table............................................................ 1
Deleted package preview note from TSV914-Q1 pinout drawing and Pin Functions table ............................... 4
Added note 4 to differential input voltage in Absolute Maximum Ratings table..................................................6
Added thermal information for TSSOP (14) to Thermal Information: TSV914A-Q1 table.................................. 7
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5 Device Comparison Table
PACKAGE LEADS
NO. OF
DEVICE
CHANNELS
DBV
5
D
—
8
DGK
—
PW
—
TSV911A-Q1
TSV912A-Q1
TSV914A-Q1
1
2
4
—
8
—
—
14
—
14
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6 Pin Configuration and Functions
OUT A
-IN A
+IN A
V-
1
2
3
4
8
7
6
5
V+
OUT B
-IN B
+IN B
Figure 6-1. TSV912A-Q1 D and DGK Package
8-Pin SOIC and VSSOP
Top View
Table 6-1. Pin Functions: TSV912A-Q1
PIN
I/O
DESCRIPTION
NAME
–IN A
+IN A
–IN B
+IN B
OUT A
OUT B
V–
NO.
2
I
I
Inverting input, channel A
Noninverting input, channel A
Inverting input, channel B
Noninverting input, channel B
Output, channel A
3
6
I
5
I
1
O
O
—
—
7
Output, channel B
4
Negative (lowest) supply or ground (for single-supply operation)
Positive (highest) supply
V+
8
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OUT A
-IN A
+IN A
V+
1
2
3
4
5
6
7
14 OUT D
13 -IN D
12 +IN D
11 V-
A
D
+IN B
-IN B
OUT B
10 +IN C
9
8
-IN C
B
C
OUT C
Figure 6-2. TSV914A-Q1 D and PW Package
14-Pin SOIC and TSSOP
Top View
Table 6-2. Pin Functions: TSV914A-Q1
PIN
I/O
DESCRIPTION
NAME
–IN A
+IN A
–IN B
+IN B
–IN C
+IN C
–IN D
+IN D
OUT A
OUT B
OUT C
OUT D
V–
NO.
2
I
I
Inverting input, channel A
Noninverting input, channel A
Inverting input, channel B
Noninverting input, channel B
Inverting input, channel C
Noninverting input, channel C
Inverting input, channel D
Noninverting input, channel D
Output, channel A
3
6
I
5
I
9
I
10
13
12
1
I
I
I
O
O
O
O
—
—
7
Output, channel B
8
Output, channel C
14
11
4
Output, channel D
Negative (lowest) supply or ground (for single-supply operation)
Positive (highest) supply
V+
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature (unless otherwise noted)(1)
MIN
(V–) – 0.5
–10
MAX
UNIT
Supply voltage
6
(V+) + 0.5
(V+) – (V–) + 0.2
10
V
Common-mode
Voltage(2)
V
Signal input pins
Differential(4)
Current(2)
mA
mA
°C
Output short-circuit(3)
Specified, TA
Continuous
–40
125
150
150
Junction, TJ
°C
Storage, Tstg
–65
°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Input pins are diode-clamped to the power-supply rails. Current limit input signals that can swing more than 0.5 V beyond the supply
rails to 10 mA or less.
(3) Short-circuit to ground, one amplifier per package.
(4) Differential input voltages greater than 0.5 V applied continuously can result in a shift to the input offset voltage above the maximum
specification of this parameter. The magnitude of this effect increases as the ambient operating temperature rises.
7.2 ESD Ratings
VALUE
±4000
±1500
UNIT
Human-body model (HBM), per AEC Q100-002(1)
Charged-device model (CDM), per AEC Q100-011
V(ESD)
Electrostatic discharge
V
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with ANSI/ESDA/JEDEC JS-001 Specification.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
2.5
MAX
5.5
UNIT
VS
Supply voltage
V
Specified temperature
–40
125
°C
7.4 Thermal Information: TSV912A-Q1
TSV912A-Q1
THERMAL METRIC(1)
D (SOIC)
8 PINS
157.6
104.6
99.7
DGK (VSSOP)
8 PINS
198.5
UNIT
RθJA
RθJC(top)
RθJB
ψJT
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
87.2
120.3
Junction-to-top characterization parameter
Junction-to-board characterization parameter
55.6
23.8
ψJB
99.2
118.7
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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7.5 Thermal Information: TSV914A-Q1
TSV914A-Q1
THERMAL METRIC(1)
D (SOIC)
14 PINS
111.1
67.6
PW (TSSOP)
14 PINS
133.8
UNIT
RθJA
RθJC(top)
RθJB
ψJT
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
62.1
67
76.9
Junction-to-top characterization parameter
Junction-to-board characterization parameter
27.4
13.2
ψJB
66.6
76.3
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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7.6 Electrical Characteristics
VS (Total Supply Voltage) = (V+) – (V–) = 2.5 V to 5.5 V at TA = 25°C, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and
VOUT = VS / 2 (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OFFSET VOLTAGE
VS = 5 V
VS = 5 V
±0.3
±1.5
±3
VOS
Input offset voltage
mV
TA = –40°C to 125°C
VS = 5 V
TA = –40°C to 125°C
dVOS/dT Drift
±0.5
µV/°C
PSRR
Power-supply rejection ratio
Channel separation, DC
INPUT VOLTAGE RANGE
VS = 2.5 V – 5.5 V, VCM = (V–)
At DC
±7
µV/V
dB
100
VCM
Common-mode voltage range
VS = 2.5 V to 5.5 V
(V–) – 0.1
80
(V+) + 0.1
V
VS = 5.5 V
(V–) – 0.1 V < VCM < (V+) – 1.4 V
TA = –40°C to 125°C
103
VS = 5.5 V, VCM = –0.1 V to 5.6 V
TA = –40°C to 125°C
57
75
88
70
CMRR
Common-mode rejection ratio
dB
VS = 2.5 V, (V–) – 0.1 V < VCM < (V+) – 1.4 V
TA = –40°C to 125°C
VS = 2.5 V, VCM = –0.1 V to 1.9 V
TA = –40°C to 125°C
INPUT BIAS CURRENT
IB
Input bias current
Input offset current
±5
±5
pA
pA
IOS
NOISE
En
Input voltage noise (peak-to-peak)
Input voltage noise density
Input current noise density
VS = 5 V, f = 0.1 Hz to 10 Hz
VS = 5 V, f = 10 kHz
VS = 5 V, f = 1 kHz
f = 1 kHz
4.77
12
µVPP
en
nV/√ Hz
fA/√ Hz
18
in
23
INPUT CAPACITANCE
CID
CIC
Differential
2
4
pF
pF
Common-mode
OPEN-LOOP GAIN
VS = 2.5 V, (V–) + 0.04 V < VO < (V+) – 0.04 V
RL = 10 kΩ
100
130
100
130
VS = 5.5 V, (V–) + 0.05 V < VO < (V+) – 0.05 V
RL = 10 kΩ
104
AOL
Open-loop voltage gain
dB
VS = 2.5 V, (V–) + 0.06 V < VO < (V+) – 0.06 V
RL = 2 kΩ
VS = 5.5 V, (V–) + 0.15 V < VO < (V+) – 0.15 V
RL = 2 kΩ
FREQUENCY RESPONSE
GBP
φm
Gain bandwidth product
VS = 5 V, G = 1
VS = 5 V, G = 1
8
MHz
°
Phase margin
55
VS = 5 V, G = 1
RL = 2 kΩ
SR
Slew rate
4.5
V/µs
CL = 100 pF
To 0.1%, VS = 5 V, 2-V step , G = 1
CL = 100 pF
0.5
1
tS
Settling time
µs
µs
To 0.01%, VS = 5 V, 2-V step , G = 1
CL = 100 pF
tOR
Overload recovery time
VS = 5 V, VIN × gain > VS
0.2
THD + N Total harmonic distortion + noise(1)
VS = 5 V, VO = 1 VRMS, G = 1, f = 1 kHz
0.0008%
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7.6 Electrical Characteristics (continued)
VS (Total Supply Voltage) = (V+) – (V–) = 2.5 V to 5.5 V at TA = 25°C, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and
VOUT = VS / 2 (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OUTPUT
VS = 5.5 V, RL = 10 kΩ
20
60
Voltage output swing from supply
rails
VO
mV
VS = 5.5 V, RL = 2 kΩ
VS = 5 V
ISC
ZO
Short-circuit current
±50
100
mA
Ω
Open-loop output impedance
VS = 5 V, f = 10 MHz
POWER SUPPLY
VS = 5.5 V, IO = 0 mA
550
750
IQ Quiescent current per amplifier
µA
VS = 5.5 V, IO = 0 mA TA = –40°C to 125°C
1100
(1) Third-order filter; bandwidth = 80 kHz at –3 dB.
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7.7 Typical Characteristics
at TA = 25°C, VS = 5.5 V, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS / 2 (unless otherwise noted)
35
30
25
20
15
10
5
50
40
30
20
10
0
0
Offset Voltage Drift (µV/C)
C001
C002
Offset Voltage (µV)
TA = –40°C to 125°C
Figure 7-2. Offset Voltage Drift Distribution
Figure 7-1. Offset Voltage Production Distribution
500
400
2500
2000
1500
1000
500
300
200
100
0
0
œ500
œ1000
œ1500
œ2000
œ2500
œ100
œ200
œ300
œ400
œ500
-4
-3
-2
-1
0
1
2
3
4
0
25
50
75
100
125
150
œ50
œ25
Input Common Mode Voltage (V)
Temperature (°C)
C005
C003
V+ = 2.75 V, V– = –2.75 V
Figure 7-4. Offset Voltage vs Common-Mode Voltage
Figure 7-3. Offset Voltage vs Temperature
1000
120
100
80
60
40
20
0
210
180
150
120
90
Gain
Phase
500
0
60
500
1000
30
-20
100
0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
1k
10k 100k
Frequency (Hz)
1M
10M
Supply Voltage (V)
C004
C006
VS = 2.5 V to 5.5 V
CL = 10 pF
Figure 7-5. Offset Voltage vs Power Supply
Figure 7-6. Open-Loop Gain and Phase vs Frequency
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7.7 Typical Characteristics (continued)
at TA = 25°C, VS = 5.5 V, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS / 2 (unless otherwise noted)
40
30
250
200
150
100
50
IBN
IBP
IOS
20
10
0
-10
-20
-30
-40
0
G = +1
G = +10
G = -1
œ50
0
25
Temperature (°C)
Figure 7-8. Input Bias Current vs Temperature
50
75
100
125
œ50
œ25
1k
10k
100k
Frequency (Hz)
1M
10M
C008
C007
Figure 7-7. Closed-Loop Gain vs Frequency
120
100
80
60
40
20
0
3
PSRR-
PSRR+
CMRR
2
1
-40°C
-40°C
125°C
85°C
25°C
0
25°C
85°C
œ1
œ2
œ3
125°C
10
20
30
40
50
60
Output Current (mA)
C009
1k
10k
100k
Frequency (Hz)
1M
10M
C011
V+ = 2.75 V, V– = –2.75 V
Figure 7-9. Output Voltage Swing vs Output Current
Figure 7-10. CMRR and PSRR vs Frequency (Referred to Input)
55
10
9
8
7
6
5
4
3
2
1
50
45
40
35
30
0
25
50
75
100
125
0
25
50
75
100
125
150
œ50
œ25
œ50
œ25
Temperature (°C)
Temperature (°C)
C012
C016
VCM = (V–) – 0.1 V to
(V+) + 0.1 V
VCM = (V–) –0.1 V to (V
+) –1.4 V
VS = 5.5 V
RL= 10 kΩ
VS = 5.5 V
RL= 10 kΩ
TA= –40°C to 125°C
TA= –40°C to 125°C
Figure 7-11. CMRR vs Temperature
Figure 7-12. CMRR vs Temperature
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7.7 Typical Characteristics (continued)
at TA = 25°C, VS = 5.5 V, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS / 2 (unless otherwise noted)
10
9
8
7
6
5
Time (1s/div)
0
25
50
75
100
125
œ50
œ25
Temperature (°C)
C014
C013
VS = 2.5 V to 5.5 V
VS = 2.5 V to 5.5 V
Figure 7-14. 0.1-Hz to 10-Hz Input Voltage Noise
Figure 7-13. PSRR vs Temperature
120
100
80
60
40
20
0
-90
-95
-100
-105
-110
-115
-120
10
100
1k
Frequency (Hz)
10k
100k
100
1k
Frequency (Hz)
10k
C015
C017
VS = 5.5 V
G = 1
VCM = 2.5 V
VOUT = 0.5 VRMS
RL = 2 kΩ
BW = 80 kHz
Figure 7-15. Input Voltage Noise Spectral Density vs Frequency
Figure 7-16. THD + N vs Frequency
œ40
œ40
œ60
œ60
œ80
œ80
œ100
œ100
œ120
œ120
0.001
0.01
0.1
1
0.001
0.01
0.1
1
Output Voltage Amplitude (VRMS
)
Output Voltage Amplitude (VRMS
)
C018
C019
VS = 5.5 V
G = 1
VCM = 2.5 V
RL = 2 kΩ
f = 1 kHz
VS = 5.5 V
G = –1
VCM = 2.5 V
RL = 2 kΩ
f = 1 kHz
BW = 80 kHz
BW = 80 kHz
Figure 7-17. THD + N vs Amplitude
Figure 7-18. THD + N vs Amplitude
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7.7 Typical Characteristics (continued)
at TA = 25°C, VS = 5.5 V, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS / 2 (unless otherwise noted)
600
580
560
540
520
500
800
700
600
500
400
300
200
100
0
0
25
50
75
100
125
œ50
œ25
1.5
2
2.5
3
3.5
4
4.5
5
5.5
Temperature (°C)
C021
Supply Voltage (V)
C020
Figure 7-20. Quiescent Current vs Temperature
Figure 7-19. Quiescent Current vs Supply Voltage
200
60
50
40
30
20
160
120
80
40
0
10
0
Overshoot+
Overshoot-
250
0
50
100
150
200
300
Capacitive Load (pF)
C025
10k
100k
Frequency (Hz)
1M
10M
C024
V+ = 2.75 V
RL = 10 kΩ
V– = –2.75 V
VOUT step = 100 mVp-p
G = 1 V/V
Figure 7-22. Small-Signal Overshoot vs Load Capacitance
Figure 7-21. Open-Loop Output Impedance vs Frequency
60
50
40
30
20
Input
Output
10
0
Overshoot(+)
Overshoot(-)
Time (200 µs/div)
0
50
100
150
200
250
300
Capacitive Load (pF)
C026
C036
V+ = 2.75 V
G = –1 V/V
V– = –2.75 V
VOUT step = 100 mVp-p
RL = 10 kΩ
V+ = 2.75 V, V– = –2.75 V
Figure 7-24. No Phase Reversal
Figure 7-23. Small-Signal Overshoot vs Load Capacitance
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7.7 Typical Characteristics (continued)
at TA = 25°C, VS = 5.5 V, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS / 2 (unless otherwise noted)
Input
Output
INPUT
OUTPUT
Time (1 µs/div)
Time (0.1µs/div)
C028
C030
V+ = 2.75 V, V– = –2.75 V, G = –10 V/V
V+ = 2.75 V, V– = –2.75 V, G = 1 V/V
Figure 7-25. Overload Recovery
Figure 7-26. Small-Signal Step Response
80
60
40
20
Sinking
0
Sourcing
œ20
œ40
œ60
œ80
Input
Output
Time (1 µs/div)
0
25
50
75
100
125
œ50
œ25
Temperature (°C)
C034
C031
V+ = 2.75 V
G = 1 V/V
V– = –2.75 V
CL = 100 pF
Figure 7-28. Short-Circuit Current vs Temperature
Figure 7-27. Large-Signal Step Response
0
140
120
100
80
-20
-40
-60
60
-80
40
-100
-120
-140
20
0
10M
100M
Frequency (Hz)
1G
C041
100
1k
10k 100k
Frequency (Hz)
1M
10M
C038
PRF = –10 dBm
V+ = 2.75 V, V– = –2.75 V
Figure 7-30. Channel Separation vs Frequency
Figure 7-29. Electromagnetic Interference Rejection Ratio
Referred to Noninverting Input (EMIRR+) vs Frequency
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7.7 Typical Characteristics (continued)
at TA = 25°C, VS = 5.5 V, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS / 2 (unless otherwise noted)
90
75
60
45
30
15
0
200
160
120
80
40
0
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
0
10
20
30
40
50
60
70
80
90 100
Output Voltage (V)
Capacitive Load (pF)
C023
C037
A.
VS = 5.5 V
VS = 5.5 V
Figure 7-32. Open Loop Voltage Gain vs Output Voltage
Figure 7-31. Phase Margin vs Capacitive Load
100
100
75
75
50
50
25
25
0
0
-25
-50
-75
-100
-125
-150
œ25
œ50
œ75
œ100
0
0.3
0.6
0.9
0
0.3
0.6
0.9
1.2
1.5
Settling time (µs)
Settling time (µs)
C032
C033
Figure 7-33. Large Signal Settling Time (Positive)
Figure 7-34. Large Signal Settling Time (Negative)
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8 Detailed Description
8.1 Overview
The TSV91xA-Q1 series is a family of low-power, rail-to-rail input and output op amps. These devices operate
from 2.5 V to 5.5 V, are unity-gain stable, and are designed for a wide range of general-purpose automotive
applications. The input common-mode voltage range includes both rails and allows the TSV91xA-Q1 series to be
used in virtually any single-supply application. Rail-to-rail input and output swing significantly increases dynamic
range, especially in low-supply applications and are designed for driving sampling analog-to-digital converters
(ADCs).
8.2 Functional Block Diagram
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8.3 Feature Description
8.3.1 Rail-to-Rail Input
The input common-mode voltage range of the TSV91xA-Q1 family extends 100 mV beyond the supply rails for
the full supply voltage range of 2.5 V to 5.5 V. This performance is achieved with a complementary input stage:
an N-channel input differential pair in parallel with a P-channel differential pair, as shown in the Functional Block
Diagram. The N-channel pair is active for input voltages close to the positive rail, typically (V+) – 1.4 V to 100
mV above the positive supply, whereas the P-channel pair is active for inputs from 100 mV below the negative
supply to approximately (V+) – 1.4 V. There is a small transition region, typically (V+) – 1.2 V to (V+) – 1 V, in
which both pairs are on. This 200-mV transition region can vary up to 200 mV with process variation. Thus, the
transition region (with both stages on) can range from (V+) – 1.4 V to (V+) – 1.2 V on the low end, and up to (V+)
– 1 V to (V+) – 0.8 V on the high end. Within this transition region, PSRR, CMRR, offset voltage, offset drift, and
THD can degrade compared to device operation outside this region.
8.3.2 Rail-to-Rail Output
Designed as a low-power, low-voltage operational amplifier, the TSV91xA-Q1 series delivers a robust output
drive capability. A class AB output stage with common-source transistors achieves full rail-to-rail output swing
capability. For resistive loads of 10 kΩ, the output swings to within 15 mV of either supply rail, regardless of the
applied power-supply voltage. Different load conditions change the ability of the amplifier to swing close to the
rails.
8.3.3 Packages With an Exposed Thermal Pad
The TSV91xA-Q1 family is available in packages such as the WSON-8 (DSG) which feature an exposed thermal
pad. Inside the package, the die is attached to this thermal pad using an electrically conductive compound. For
this reason, when using a package with an exposed thermal pad, the thermal pad must either be connected to
V– or left floating. Attaching the thermal pad to a potential other then V– is not allowed, and the performance of
the device is not assured when doing so.
8.3.4 Overload Recovery
Overload recovery is defined as the time required for the operational amplifier output to recover from a saturated
state to a linear state. The output devices of the operational amplifier enter a saturation region when the output
voltage exceeds the rated operating voltage, because of the high input voltage or the high gain. After the device
enters the saturation region, the charge carriers in the output devices require time to return to the linear state.
After the charge carriers return to the linear state, the device begins to slew at the specified slew rate. Therefore,
the propagation delay (in case of an overload condition) is the sum of the overload recovery time and the slew
time. The overload recovery time for the TSV91xA-Q1 series is approximately 200 ns.
8.4 Device Functional Modes
The TSV91xA-Q1 family has a single functional mode. These devices are powered on as long as the power-
supply voltage is between 2.5 V (±1.25 V) and 5.5 V (±2.75 V).
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9 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
9.1 Application Information
The TSV91xA-Q1 series features 8-MHz bandwidth and 4.5-V/µs slew rate with only 550 µA of supply current
per channel, providing good AC performance at low power consumption. DC applications are well served with a
low input noise voltage of 18 nV / √ Hz at 1 kHz, low input bias current, and a typical input offset voltage of 0.3
mV.
9.2 Typical Application
Figure 9-1 shows the TSV91xA-Q1 configured in a low-side, motor-control application.
VBUS
ILOAD
ZLOAD
5 V
+
TSV91x
VOUT
RSHUNT
VSHUNT
0.1 ꢀ
RF
165 kꢀ
RG
3.4 kꢀ
Figure 9-1. TSV91xA-Q1 in a Low-Side, Motor-Control Application
9.2.1 Design Requirements
The design requirements for this design are:
•
•
•
Load current: 0 A to 1 A
Output voltage: 4.95 V
Maximum shunt voltage: 100 mV
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9.2.2 Detailed Design Procedure
The transfer function of the circuit in Figure 9-1 is shown in Equation 1.
VOUT = ILOAD ìRSHUNT ìGain
(1)
The load current (ILOAD) produces a voltage drop across the shunt resistor (RSHUNT). The load current is set from
0 A to 1 A. To keep the shunt voltage below 100 mV at maximum load current, the largest shunt resistor is
defined using Equation 2.
VSHUNT _MAX
100mV
1A
RSHUNT
=
=
=100mW
ILOAD_MAX
(2)
Using Equation 2, RSHUNT is 100 mΩ. The voltage drop produced by ILOAD and RSHUNT is amplified by the
TSV91xA-Q1 to produce an output voltage of approximately 0 V to 4.95 V. The gain required by the TSV91xA-
Q1 to produce the necessary output voltage is calculated using Equation 3:
V
OUT _MAX - VOUT _MIN
(
)
Gain =
VIN_MAX - V
IN_MIN
(3)
Using Equation 3, the required gain is calculated to be 49.5 V/V, which is set with resistors RF and RG. Equation
4 is used to size the resistors, RF and RG, to set the gain of the TSV91xA-Q1 to 49.5 V/V.
R
(
)
F
Gain = 1+
R
G
(4)
Selecting RF as 165 kΩ and RG as 3.4 kΩ provides a combination that equals roughly 49.5 V/V. Figure 9-2
shows the measured transfer function of the circuit shown in Figure 9-1.
9.2.3 Application Curve
5
4
3
2
1
0
0
0.2
0.4
0.6
0.8
1
ILOAD (A)
C219
Figure 9-2. Low-Side, Current-Sense, Transfer Function
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10 Power Supply Recommendations
The TSV91xA-Q1 series is specified for operation from 2.5 V to 5.5 V (±1.25 V to ±2.75 V); many specifications
apply from –40°C to 125°C. Typical Characteristics presents parameters that can exhibit significant variance with
regard to operating voltage or temperature.
CAUTION
Supply voltages larger than 6 V can permanently damage the device; see the Absolute Maximum
Ratings table.
Place 0.1-µF bypass capacitors close to the power-supply pins to reduce errors coupling in from noisy or high-
impedance power supplies. For more detailed information on bypass capacitor placement, see Layout Example.
10.1 Input and ESD Protection
The TSV91xA-Q1 series incorporates internal ESD protection circuits on all pins. For input and output pins, this
protection consists of current-steering diodes connected between the input and power-supply pins. These ESD
protection diodes provide in-circuit, input overdrive protection, as long as the current is limited to 10-mA, as
stated in the Absolute Maximum Ratings table. Figure 10-1 shows how a series input resistor is added to the
driven input to limit the input current. The added resistor contributes thermal noise at the amplifier input and the
value must be kept to a minimum in noise-sensitive applications.
V+
IOVERLOAD
10-mA maximum
VOUT
Device
VIN
5 kW
Figure 10-1. Input Current Protection
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11 Layout
11.1 Layout Guidelines
For best operational performance of the device, use good printed-circuit board (PCB) layout practices, including:
•
Noise can propagate into analog circuitry through the power pins of the circuit as a whole and of op amp
itself. Bypass capacitors are used to reduce the coupled noise by providing low-impedance power sources
local to the analog circuitry.
– Connect low-ESR, 0.1-µF ceramic bypass capacitors between each supply pin and ground, placed as
close to the device as possible. A single bypass capacitor from V+ to ground is applicable for single-
supply applications.
•
•
Separate grounding for analog and digital portions of circuitry is one of the simplest and most-effective
methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground planes.
A ground plane helps distribute heat and reduces electromagnetic interference (EMI) noise pickup. Make
sure to physically separate digital and analog grounds, paying attention to the flow of the ground current.
To reduce parasitic coupling, run the input traces as far away from the supply or output traces as possible. If
these traces cannot be kept separate, crossing the sensitive trace perpendicular is much better as opposed
to in parallel with the noisy trace.
•
•
•
Place the external components as close to the device as possible. As shown in Figure 11-2, keeping RF and
RG close to the inverting input minimizes parasitic capacitance on the inverting input.
Keep the length of input traces as short as possible. Always remember that the input traces are the most
sensitive part of the circuit.
Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly reduce
leakage currents from nearby traces that are at different potentials.
•
•
Cleaning the PCB following board assembly is recommended for best performance.
Any precision integrated circuit can experience performance shifts resulting from moisture ingress into the
plastic package. Following any aqueous PCB cleaning process, baking the PCB assembly is recommended
to remove moisture introduced into the device packaging during the cleaning process. A low-temperature,
post-cleaning bake at 85°C for 30 minutes is sufficient for most circumstances.
11.2 Layout Example
VIN A
VIN B
+
+
VOUT A
VOUT B
RG
RG
RF
RF
Figure 11-1. Schematic Representation of Layout Example
Place components
close to device and to
each other to reduce
parasitic errors.
OUT A
Use low-ESR,
ceramic bypass
capacitor. Place as
close to the device
as possible.
VS+
GND
OUT A
V+
RF
OUT B
GND
-IN A
+IN A
Vœ
OUT B
-IN B
RF
RG
GND
VIN A
RG
+IN B
VIN B
Keep input traces short
and run the input traces
as far away from
the supply lines
Use low-ESR,
ceramic bypass
capacitor. Place as
close to the device
as possible.
GND
VSœ
Ground (GND) plane on another layer
as possible.
Figure 11-2. Layout Example
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12 Device and Documentation Support
12.1 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to order now.
Table 12-1. Related Links
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
PARTS
PRODUCT FOLDER
ORDER NOW
TSV912A-Q1
TSV914A-Q1
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
12.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
12.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.6 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
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13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
2-Apr-2021
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TSV912AQDGKRQ1
TSV912AQDRQ1
TSV914AQDRQ1
TSV914AQPWRQ1
ACTIVE
ACTIVE
ACTIVE
ACTIVE
VSSOP
SOIC
DGK
D
8
8
2500 RoHS & Green
2500 RoHS & Green
2500 RoHS & Green
2000 RoHS & Green
NIPDAU
Level-1-260C-UNLIM
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 125
-40 to 125
-40 to 125
-40 to 125
29IT
NIPDAU
NIPDAU
NIPDAU
TS912Q
SOIC
D
14
14
TSV914AQD
T914AQ
TSSOP
PW
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
2-Apr-2021
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Apr-2021
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TSV912AQDGKRQ1
TSV912AQDRQ1
TSV914AQDRQ1
TSV914AQPWRQ1
VSSOP
SOIC
DGK
D
8
8
2500
2500
2500
2000
330.0
330.0
330.0
330.0
12.4
12.4
16.4
12.4
5.3
6.4
6.5
6.9
3.4
5.2
9.0
5.6
1.4
2.1
2.1
1.6
8.0
8.0
8.0
8.0
12.0
12.0
16.0
12.0
Q1
Q1
Q1
Q1
SOIC
D
14
14
TSSOP
PW
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Apr-2021
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TSV912AQDGKRQ1
TSV912AQDRQ1
TSV914AQDRQ1
TSV914AQPWRQ1
VSSOP
SOIC
DGK
D
8
8
2500
2500
2500
2000
366.0
853.0
853.0
853.0
364.0
449.0
449.0
449.0
50.0
35.0
35.0
35.0
SOIC
D
14
14
TSSOP
PW
Pack Materials-Page 2
PACKAGE OUTLINE
D0008A
SOIC - 1.75 mm max height
SCALE 2.800
SMALL OUTLINE INTEGRATED CIRCUIT
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A
PIN 1 ID AREA
6X .050
[1.27]
8
1
2X
.189-.197
[4.81-5.00]
NOTE 3
.150
[3.81]
4X (0 -15 )
4
5
8X .012-.020
[0.31-0.51]
B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.010 [0.25]
C A B
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
[0.11-0.25]
0 - 8
.016-.050
[0.41-1.27]
DETAIL A
TYPICAL
(.041)
[1.04]
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
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EXAMPLE BOARD LAYOUT
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
SEE
DETAILS
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED
METAL
EXPOSED
METAL
.0028 MAX
[0.07]
.0028 MIN
[0.07]
ALL AROUND
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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