TUSB1044RNQR [TI]
USB TYPE-C™ 10Gbps 多协议双向线性转接驱动器 | RNQ | 40 | 0 to 70;
| 型号： | TUSB1044RNQR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | USB TYPE-C™ 10Gbps 多协议双向线性转接驱动器 | RNQ | 40 | 0 to 70 驱动 驱动器 |
| 文件： | 总67页 (文件大小：2062K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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TUSB1044
ZHCSHJ2C –FEBRUARY 2018–REVISED OCTOBER 2018
TUSB1044 USB TYPE-C™ 10Gbps 多协议双向线性转接驱动器
1 特性
2 应用
1
•
支持高达 10Gbps 数据速率的协议无关正反两用式
4 通道线性转接驱动器
•
•
•
•
平板电脑
笔记本电脑
台式机
–
带有 USB 3.1 第 2 代和 DisplayPort 1.4 作为交
替模式的 USB Type-C。
扩展坞
•
支持集成有 USB 3.1 和 DisplayPort 多路复用器，
适用于 Type-C 应用的处理器
3 说明
•
•
•
支持信号调节内部 Type-C 线缆
TUSB1044 是一款支持高达 10Gbps 的数据速率的
USB Type-C 交替模式转接驱动器开关。该协议无关线
性转接驱动器能够支持 USB Type-C 交替模式接口
（包括 DisplayPort）。
适用于 SBU 信号的交叉点多路复用器
频率为 4.05GHz 时，支持高达 11dB 的线性均衡功
能
用于通道方向和均衡的 GPIO 和 I2C 控制
•
•
TUSB1044 提供多个接收线性均衡级别，用于补偿由
于电缆和电路板迹线损耗而产生的码间串扰 (ISI)。该
器件由 3.3V 单电源供电，支持商业级和工业级温度范
围。
通过监控 USB 功耗状态和嗅探 DP 链路训练可实
现高级电源管理
可通过 GPIO 或 I2C 进行配置
•
•
•
•
•
•
支持热插拔
3.3V 单电源
TUSB1044 的全部四个通道均为正反两用式，这使其
成为可用于诸多应用的多用途信号调节器。 系统。
工业级温度范围：–40ºC 至 85ºC (TUSB1044I)
商业级温度范围：0ºC 至 70ºC (TUSB1044)
4mm × 6mm、0.4mm 间距、40 引脚 QFN 封装
器件信息(1)
器件型号
TUSB1044
TUSB1044I
封装
WQFN (40)
WQFN (40)
封装尺寸（标称值）
4.00mm x 6.00mm
4.00mm x 6.00mm
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
简化原理图
D+/-
TUSB1044
URX2
UTX2
UTX1
URX1
DRX2
DTX2
DTX1
DRX1
TUSB1044
USB/DP/
Custom
Source
AUXp
AUXn
SBU1
SBU2
CTL
0 1
FLIP
HPD
Control
CC1
CC2
USB PD
Controller
1
本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。 有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确
性和有效性。 在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLLSF47
TUSB1044
ZHCSHJ2C –FEBRUARY 2018–REVISED OCTOBER 2018
www.ti.com.cn
目录
7.5 Programming .......................................................... 34
7.6 Register Maps ........................................................ 36
Application and Implementation ........................ 45
8.1 Application Information............................................ 45
8.2 Typical Application ................................................. 45
8.3 System Examples .................................................. 49
Power Supply Recommendations...................... 56
1
2
3
4
5
6
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 6
6.1 Absolute Maximum Ratings ...................................... 6
6.2 ESD Ratings.............................................................. 6
6.3 Recommended Operating Conditions....................... 6
6.4 Thermal Information.................................................. 6
6.5 Electrical Characteristics........................................... 7
6.6 Switching Characteristics........................................ 10
6.7 Timing Requirements.............................................. 11
6.8 Typical Characteristics............................................ 15
Detailed Description ............................................ 18
7.1 Overview ................................................................. 18
7.2 Functional Block Diagram ....................................... 19
7.3 Feature Description................................................. 20
7.4 Device Functional Modes........................................ 21
8
9
10 Layout................................................................... 57
10.1 Layout Guidelines ................................................. 57
10.2 Layout Example .................................................... 58
11 器件和文档支持 ..................................................... 59
11.1 文档支持 ............................................................... 59
11.2 接收文档更新通知 ................................................. 59
11.3 社区资源................................................................ 59
11.4 商标....................................................................... 59
11.5 静电放电警告......................................................... 59
11.6 术语表 ................................................................... 59
12 机械、封装和可订购信息....................................... 59
7
4 修订历史记录
注：之前版本的页码可能与当前版本有所不同。
Changes from Revision B (April 2018) to Revision C
Page
•
•
•
•
Added pull-down indicator (PD) in the I/O column on SWAP, SLP_S0#, DIR0, DIR1, FLIP. CTL0 pins. ............................ 3
Added junction temperature of 105℃ for TUSB1044. ........................................................................................................... 6
Changed junction temperature from 105℃ to 125℃ for TUSB1044I .................................................................................... 6
Changed RPD_CTL1 From: Internal pull-down resistance for CTL1 To: Internal pull-down resistance for CTL1, CTL0,
DIR0, DIR1, FLIP, and SLP_S0#. .......................................................................................................................................... 7
•
Added RPD_SWAP parameter of 200kΩ..................................................................................................................................... 7
Changes from Revision A (February 2018) to Revision B
Page
•
更改了简化原理图................................................................................................................................................................... 1
Changes from Original (February 2018) to Revision A
Page
•
•
Changed text in the Detailed Design Procedure From: "This AC-coupling capacitor should be no more than 220 nF."
To: This AC-coupling capacitor should be no smaller than 297 nF. A value of 330 nF is recommended."......................... 46
Changed 220 nF to 330 nF on DRX2P, DRX2N and DRX1P, DRX1N in 图 36.................................................................. 47
2
Copyright © 2018, Texas Instruments Incorporated
TUSB1044
www.ti.com.cn
ZHCSHJ2C –FEBRUARY 2018–REVISED OCTOBER 2018
5 Pin Configuration and Functions
RNQ Package
40-Pin (WQFN)
Top View
VCC
1
28
27
26
25
24
23
22
21
VCC
UEQ1/A1
CFG0
2
3
SBU1
SBU2
CFG1
SWAP
VCC
4
5
6
7
8
AUXn
Thermal
Pad
AUXp
CTL1
SLP_S0#
DIR0
CTL0/SDA
FLIP/SCL
Not to scale
Pin Functions
PIN
NAME
VCC
I/O
DESCRIPTION
NO.
1
P
3.3 V Power Supply
This pin along with UEQ0 sets the high-frequency equalizer gain for upstream facing URX1, URX2, UTX1,
UTX2 receivers. In I2C Mode, this pin will also set TUSB1044 I2C address. Refer to 表 9.
2
3
4
UEQ1/A1
CFG0
4 Level I
CFG0. This pin along with CFG1 will select VOD linearity range and DC gain for all the downstream and
upstream channels. Refer to 表 8 for VOD linearity range and DC gain options.
4 Level I
4 Level I
CFG1. This pin along with CFG0 will set VOD linearity range and DC gain for all the downstream and
upstream channels. Refer to 表 8 for VOD linearity range and DC gain options.
CFG1
This pin swaps all the channel directions and EQ settings of downstream facing and upstream facing data
path inputs.
0 – Do not swap channel directions and EQ settings (Default)
1. – Swap channel directions and EQ settings.
2 Level I
(PD)
5
6
SWAP
VCC
P
3.3V Power Supply
This pin when asserted low will disable Receiver Detect functionality. While this pin is low and TUSB1044
is in U2/U3, TUSB1044 will disable LOS and LFPS detection circuitry and RX termination for both
channels will remain enabled. If this pin is low and TTUSB1044 is in Disconnect state, the RX detect
functionality will be disabled and RX termination for both channels will be disabled.
0 – RX Detect disabled
2 Level I
(PD)
7
8
SLP_S0#
1 – RX Detect enabled (Default)
This pin along with DIR1 sets the data path signal direction format. Refer to 表 4 for signal direction
formats.
0 - Source Side (DFP) Alt Mode format
1 - Sink Side (UFP) Alt Mode format
2 Level I
(PD)
DIR0
9
URX2p
URX2n
Diff I/O
Diff I/O
Differential positive input/output for upstream facing RX2 port.
Differential negative input/output for upstream facing RX2 port.
10
This pin along with DIR0 sets the data path signal direction format. Refer to 表 4 for signal direction
2 Level I/O
(PD)
formats.
0 - DisplayPort Alt Mode format
1 - Custom Alt Mode format
11
DIR1
Copyright © 2018, Texas Instruments Incorporated
3
TUSB1044
ZHCSHJ2C –FEBRUARY 2018–REVISED OCTOBER 2018
www.ti.com.cn
Pin Functions (continued)
PIN
I/O
DESCRIPTION
NO.
12
NAME
UTX2p
UTX2n
Diff I/O
Diff I/O
Differential positive input/output for upstream facing TX2 port.
Differential negative input/output for upstream facing TX2 port.
13
This pin selects I/O voltage levels for the 2-level GPIO configuration pins and the I2C interface:
0 = 3.3-V configuration I/O voltage, 3.3-V I2C interface (Default)
R = 3.3-V configuration I/O voltage, 1.8-V I2C interface
14
VIO_SEL
4 Level I/O
F = 1.8-V configuration I/O voltage, 3.3-V I2C interface
1 = 1.8-V configuration I/O voltage, 1.8-V I2C interface.
15
16
UTX1n
UTX1p
Diff I/O
Diff I/O
Differential negative input/output for upstream facing TX1 port.
Differential positive input/output for upstream facing TX1 port.
I2C Programming or Pin Strap Programming Select.
0 = GPIO Mode, AUX Snoop Enabled (I2C disabled)
R = TI Test Mode (I2C enabled)
F = GPIO Mode, AUX Snoop Disabled (I2C disabled)
1 = I2C enabled.
17
I2C_EN
4 Level I
18
19
20
URX1n
URX1p
VCC
Diff I/O
Diff I/O
P
Differential negative input/output for upstream facing RX1 port.
Differential positive input/output for upstream facing RX1 port.
3.3V Power Supply
2 Level I
(PD)
(Failsafe)
In GPIO mode, this is Flip control pin, otherwise this pin is I2C clock.
21
22
FLIP/SCL
2 Level I
(PD)
In GPIO mode, this is a USB3.1 Switch control pin, otherwise this pin is I2C data.
CTL0/SDA
(Failsafe)
DP Alt mode Switch Control Pin. In GPIO mode, this pin will enable or disable DisplayPort functionality.
Otherwise DisplayPort functionality is enabled and disabled through I2C registers.
L = DisplayPort Disabled.
H = DisplayPort Enabled.
In I2C Mode, this pin is not used by TUSB1044.
2 Level I
(PD)
23
24
CTL1
AUXp
AUXp. DisplayPort AUX positive I/O connected to the DisplayPort source or sink through an AC coupling
capacitor. In addition to AC coupling capacitor, this pin also requires a 100-kΩ resistor to GND between
the AC coupling capacitor and the AUXp pin if the TUSB1044 is used on the DisplayPort source side, or a
1-MΩ resistor to DP_PWR (3.3V) between the AC coupling capacitor and the AUXp pin if TUSB1044 is
used on the DisplayPort sink side. This pin along with AUXn is used by the TUSB1044 for AUX snooping
and is routed to SBU1/2 based on the orientation of the Type-C plug.
I/O,
CMOS
AUXn. DisplayPort AUX I/O connected to the DisplayPort source or sink through an AC coupling
capacitor. In addition to AC coupling capacitor, this pin also requires a 100-kΩ resistor to DP_PWR (3.3V)
between the AC coupling capacitor and the AUXn pin if the TUSB1044 is used on the DisplayPort source
side, or a 1-MΩ resistor to GND between the AC coupling capacitor and the AUXn pin if TUSB1044 is
used on the DisplayPort sink side. This pin along with AUXp is used by the TUSB1044 for AUX snooping
and is routed to SBU1/2 based on the orientation of the Type-C plug.
I/O,
CMOS
25
AUXn
SBU2. When the TUSB1044 is used on the DisplayPort source side, this pin should be DC coupled to the
SBU2 pin of the Type-C receptacle. When the TUSB1044 is used on the DisplayPort sink side, this pin
should be DC coupled to the SBU1 pin of the Type-C receptacle. A 2-MΩ resistor to GND is also
recommended.
I/O,
CMOS
26
27
SBU2
SBU1
SBU1. When the TTUSB1044 is used on the DisplayPort source side, this pin should be DC coupled to
the SBU1 pin of the Type-C receptacle. When the TUSB1044 is used on the DisplayPort sink side, this pin
should be DC coupled to the SBU2 pin of the Type-C receptacle. A 2-MΩ resistor to GND is also
recommended.
I/O,
CMOS
28
29
VCC
P
3.3V Power Supply
This pin along with DEQ0 sets the high-frequency equalizer gain for downstream facing DRX1, DRX2,
DTX1, DTX2 receivers.
DEQ1
4 Level I
30
31
DRX1p
DRX1n
Diff I/O
Diff I/O
Differential positive input/output for downstream facing RX1 port.
Differential negative input/output for downstream facing RX1 port.
This pin is an input for Hot Plug Detect received from DisplayPort sink. When HPDIN is low for greater
than 2ms, all DisplayPort lanes are disabled and AUX to SBU switch will remain closed. When HPDIN is
high, the enabled DisplayPort lanes from AUX snoop or registers will be active.
2 Level I
(PD)
32
HPDIN
33
34
DTX1p
DTX1n
Diff I/O
Diff I/O
Differential positive input/output for downstream facing TX1 port.
Differential negative input/output for downstream facing TX1 port.
This pin along with UEQ1 sets the high-frequency equalizer gain for upstream facing URX1, URX2, UTX1,
UTX2 receivers. In I2C mode, this pin will also set TUSB1044 I2C address. Refer to 表 9.
35
UEQ0/A0
4 Level I
36
37
DTX2n
DTX2p
Diff I/O
Diff I/O
Differential negative input/output for downstream facing TX2 port.
Differential positive input/output for downstream facing TX2 port.
4
Copyright © 2018, Texas Instruments Incorporated
TUSB1044
www.ti.com.cn
ZHCSHJ2C –FEBRUARY 2018–REVISED OCTOBER 2018
Pin Functions (continued)
PIN
I/O
DESCRIPTION
NO.
NAME
This pin along with DEQ1 sets the high-frequency equalizer gain for downstream facing URX1, URX2,
UTX1, UTX2 receivers.
38
DEQ0
4 Level I
39
40
DRX2n
DRX2p
Diff I/O
Diff I/O
GND
Differential negative input/output for downstream facing RX2 port.
Differential positive input/output for downstream facing RX2 port.
Ground
Thermal Pad
Copyright © 2018, Texas Instruments Incorporated
5
TUSB1044
ZHCSHJ2C –FEBRUARY 2018–REVISED OCTOBER 2018
www.ti.com.cn
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
4
UNIT
V
VCC
Supply voltage range
-0.3
VIN_DIFF
VIN_SE
VIN_CMOS
Tstg
Differential voltage at differential input pins.
Single-ended input voltage at differential input pins.
Input voltage at CMOS inputs
±2.5
4
V
-0.5
-0.3
-65
V
4
V
Storage temperature
150
°C
(1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
UNIT
Human body model (HBM), per
±5000
ANSI/ESDA/JEDEC JS-001, all pins(1)
V(ESD)
Electrostatic discharge
V
Charged device model (CDM), per JEDEC
specification JESD22-C101, all pins(2)
±1500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
3
NOM
MAX
3.6
UNIT
V
VCC
VI2C
VPSN
TA
Supply voltage
3.3
Supply that external resistors on SDA and SCL are pulled up to.
Power supply noise on VCC
1.7
3.6
V
100
70
mV
°C
°C
°C
°C
TUSB1044 Ambient temperature
TUSB1044i Ambient temperature
TUSB1044 Junction temperature
TUSB1044I Junction temperature
0
TA
-40
85
105
125
TJ
6.4 Thermal Information
TUSB1044
THERMAL METRIC(1)
RNQ (WQFN)
UNIT
40 PINS
37.6
20.7
9.5
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
ΨJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
0.2
ΨJB
9.4
RθJC(bot)
2.3
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6
版权 © 2018, Texas Instruments Incorporated
TUSB1044
www.ti.com.cn
ZHCSHJ2C –FEBRUARY 2018–REVISED OCTOBER 2018
6.5 Electrical Characteristics
over operating free-air temperature and voltage range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Power
Link in U0 with GEN2 data transmission;
EQ control pins = NC; K28.5 pattern at
10 Gbps; VID = 1000mVp-p; VOD
Linearity = 900mVp-p; CTL1 = L; CTL0 =
H
PUSB-
ACTIVE
Average power when configured for USB
3.1 only mode.
297
mW
Link in U0 with GEN2 data transmission
and DP active; EQ control pins = NC;
PUSB-DP- Average power when configured for USB
K28.5 pattern at 10 Gbps; VID
=
578
578
mW
mW
3.1 and 2 lane DP.
ACTIVE
1000mVp-p; VOD Linearity = 900mVp-p;
CTL1 = H; CTL0 = H
Link in U0 with GEN2 data transmission
and custom alt mode active; EQ control
pins = NC; K28.5 pattern at 10 Gbps; VID
= 1000mVp-p; VOD Linearity = 900mVp-
p; CTL1 = H; CTL0 = H
PCUSTOM- Average power when configured for USB
3.1 and 2 channel custom alt mode.
ACTIVE
Four active DP lanes; EQ control pins =
P4DP-
ACTIVE
Average power when configured for Four NC; K28.5 pattern at 10 Gbps; VID
DP lanes
=
1000mVp-p; VOD Linearity = 900mVp-p;
CTL1 = H; CTL0 = L
564
2.5
mW
mW
Average power when configured for
No USB device connected; CTL1 = L;
CTL0 = H
PUSB-NC USB3.1 only and nothing connected to
TXP/N pins.
PUSB-
U2U3
Average power when configured for
USB3.1 only and link in U2 or U3 state.
Link in U2 or U3 state; CTL1 = L; CTL0
= H
2
mW
mW
PSHUTDO Average power when device in
WN
CTL1 = L; CTL0 = L; I2C_EN = 0;
0.65
Shutdown
4-State CMOS Inputs(UEQ[1:0];DEQ[1:0], CFG[1:0], A[1:0], I2C_EN, VIO_SEL)
IIH
IIL
High-level input current
Low-level input current
Threshold 0 / R
VCC = 3.6 V; VIN = 3.6 V
VCC = 3.6 V; VIN = 0 V
VCC = 3.3 V
20
80
µA
µA
V
-160
-40
0.55
1.65
2.7
35
4-Level
VTH
Threshold R/ Float
VCC = 3.3 V
V
Threshold Float / 1
VCC = 3.3 V
V
RPU
RPD
Internal pull up resistance
Internal pull-down resistance
kΩ
kΩ
95
2-State CMOS Input (CTL0, CTL1, FLIP, HPDIN, SLP_S0#, SWAP, DIR[1:0]).
VIH-3.3V
VIL-3.3V
VIH-1.8V
VIL-1.8V
High-level input voltage
Low-level input voltage
High-level input voltage
Low-level input voltage
VCC = 3.3V; VIO_SEL = "0" or "R";
VCC = 3.3V; VIO_SEL = "0" or "R";
VCC = 3.3V; VIO_SEL = "F" or "1";
VCC = 3.3V; VIO_SEL = "F" or "1";
2
0
3.6
0.8
3.6
0.4
V
V
V
V
1.2
0
Internal pull-down resistance for CTL1,
CTL0, DIR0, DIR1, FLIP, SLP_S0#.
RPD_CTL1
500
500
200
kΩ
kΩ
kΩ
RPD_HPDI
N
Internal pull-down resistance for HPDIN
Internal pull-down resistance for SWAP.
RPD_SWA
P
IIH
High-level input current
Low-level input current
VIN = 3.6 V
-25
-25
25
25
µA
µA
IIL
VIN = GND, VCC = 3.6 V
I2C Control Pins SCL, SDA
VCC = 3.3V; VIO_SEL = "0" or "R"; I2C
Mode Enabled;
VIH-3.3V
VIL-3.3V
High-level input voltage
Low-level input voltage
2
0
3.6
0.8
V
V
VCC = 3.3V; VIO_SEL = "0" or "R"; I2C
Mode Enabled;
Copyright © 2018, Texas Instruments Incorporated
7
TUSB1044
ZHCSHJ2C –FEBRUARY 2018–REVISED OCTOBER 2018
www.ti.com.cn
Electrical Characteristics (continued)
over operating free-air temperature and voltage range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VCC = 3.3V; VIO_SEL = "F" or "1"; I2C
Mode Enabled;
VIH-1.8V
VIL-1.8V
High-level input voltage
1.2
3.6
V
VCC = 3.3V; VIO_SEL = "F" or "1"; I2C
Mode Enabled;
Low-level input voltage
0
0.4
0.4
V
VOL
Low-level output voltage
Low-level output current
Input current on SDA pin
Input capacitance
I2C_EN ! = 0; IOL = 3 mA
I2C_EN ! = 0; VOL = 0.4 V
0.1*VI2C < Input voltage < 3.3 V
0
20
V
IOL
mA
µA
pF
II_I2C
Ci_I2C
-10
0.5
10
5
USB Gen 2 Differential Receiver (UTX1P/N, UTX2P/N, DRX1P/N, DRX2P/N)
AC-coupled differential peak-to-peak
signal measured post CTLE through a
reference channel
VRX-DIFF- Input differential peak-peak voltage
2000
0
mVpp
swing dynamic range
PP
VRX-DC-
CM
Common-mode voltage bias in the
receiver (DC)
V
Ω
Ω
RRX-DIFF-
DC
Present after a GEN 2 device is detected
on TXP/TXN
Differential input impedance (DC)
72
18
120
30
RRX-CM-
DC
Present after a GEN 2 device is detected
on TXP/TXN
Receiver DC Common Mode impedance
Present when no GEN 2 device is
detected on TXP/TXN. Measured over
the range of 0-500 mV with respect to
GND.
ZRX-HIGH-
IMP-DC-
POS
Common-mode input impedance with
termination disabled (DC)
25
kΩ
VSIGNAL-
DET-DIFF-
PP
Input Differential peak-to-peak Signal
Detect Assert Level
10 Gbps PRBS7 pattern; low loss input
channel;
80
60
mV
mV
mV
VRX-IDLE-
DET-DIFF-
PP
Input Differential peak-to-peak Signal
Detect De-assert Level
10 Gbps PRBS7 pattern; low loss input
channel;
VRX-LFPS-
DET-DIFF-
PP
Low-frequency Periodic Signaling (LFPS)
Detect Threshold
Below the minimum is squelched.
100
300
0.3
CRX
RX input capacitance to GND
Differential Return Loss
At 5 GHz
pF
dB
RLRX-
DIFF
50 MHz – 2.5 GHz at 90 Ω
-13
RLRX-
DIFF
5 GHz at 90 Ω
-12
-10.5
10
dB
dB
dB
RLRX-CM Common Mode Return Loss
50 MHz – 5 GHz at 90 Ω
UEQ[1:0] and DEQ[1:0]. at 5 GHz.
Receiver equalization at maximum
EQSSP
setting
USB Gen 2 Differential Transmitter (DTX1P/N, DTX2P/N, URX1P/N, URX2P/N)
VTX-DIFF- Transmitter dynamic differential voltage
1500
mVpp
mV
swing range.
PP
VTX-RCV- Amount of voltage change allowed
At 3.3 V
600
600
2.3
during Receiver Detection
DETECT
VTX-CM-
IDLE-
Transmitter idle common-mode voltage
change while in U2/U3 and not actively
transmitting LFPS
measured at the connector side of the
AC coupling caps with 50 ohm load
-600
mV
V
DELTA
VTX-DC-
CM
Common-mode voltage bias in the
transmitter (DC)
1.75
VTX-CM-
AC-PP-
ACTIVE
Rx EQ setting matches input channel
loss; Max mismatch from Txp + Txn for
both time and amplitude; -40℃ to 85℃;
Tx AC Common-mode voltage active
100
mVpp
VTX-IDLE-
DIFF-AC-
PP
AC Electrical idle differential peak-to-
peak output voltage
At package pins
0
10
mV
8
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Electrical Characteristics (continued)
over operating free-air temperature and voltage range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
0
TYP
MAX
14
UNIT
mV
Ω
VTX-IDLE- DC Electrical idle differential output
At package pins after low-pass filter to
remove AC component
voltage
DIFF-DC
RTX-DIFF Differential impedance of the driver
75
75
120
265
CAC-
COUPLING
AC Coupling capacitor
nF
Measured with respect to AC ground
over 0-500 mV
RTX-CM
Common-mode impedance of the driver
18
30
74
Ω
ITX-SHORT TX short circuit current
RLTX-DIFF Differential Return Loss
RLTX-DIFF Differential Return Loss
RLTX-CM Common Mode Return Loss
AC Characteristics
TX + /- shorted to GND
50 MHz – 2.5 GHz at 90 Ω
5 GHz at 90 Ω
mA
dB
dB
dB
-13
-10.5
-10
50 MHz – 5 GHz at 90 Ω
Differential Cross Talk between TX and
RX signal Pairs
Crosstalk
GLF
At 5 GHz
-30
0
dB
dB
Low-frequency voltage gain for 0dB
setting.
At 100 MHz; 200 mVpp < VID < 2000
mVpp; 0 dB DC Gain;
-1
1
CP1 dB-
LF-1100
CP1 dB-
HF-1100
fLF
At 100 MHz; 200 mVpp < VID < 2000
mVpp; 1100mVpp linearity setting;
Low-frequency 1-dB compression point
1100
mVpp
At 5 GHz; 200 mVpp < VID < 2000
mVpp; 1100mVpp linearity setting;
High-frequency 1-dB compression point
Low-frequency cutoff
1200
22
mVpp
kHz
200 mVpp < VID < 2000 mVpp
50
200 mVpp < VID < 2000 mVpp, PRBS7,
10 Gbps
DJ
DJ
TJ
TJ
TX output deterministic jitter
0.07
UIpp
200 mVpp < VID < 2000 mVpp, PRBS7,
8.1 Gbps
TX output deterministic jitter
TX output total jitter
0.07
0.11
0.11
UIpp
UIpp
UIpp
200 mVpp < VID < 2000 mVpp, PRBS7,
10 Gbps
200 mVpp < VID < 2000 mVpp, PRBS7,
8.1 Gbps
TX output total jitter
DisplayPort Receiver (UTX1P/N, UTX2P/N, URX1P/N, URX2P/N)
Peak-to-peak input differential dynamic
voltage range
VID_PP
1500
0
V
VIC
Input Common Mode Voltage
AC coupling capacitance
Receiver Equalizer
V
nF
CAC
EQDP
dR
75
80
265
DPEQ1, DPEQ0 at 4.05 GHz
HBR3
9.5
dB
Data rate
8.1
Gbps
Ω
Rti
Input Termination resistance
100
120
DisplayPort Transmitter (DTX1P/N, DTX2P/N, DRX1P/N, DRX2P/N)
VTX-
DIFFPP
VOD dynamic range
1500
5
mV
AUXP/N and SBU1/2
VCC = 3.3 V; VI = 0 to 0.4 V for AUXP; VI
= 2.7 V to 3.6 V for AUXN
RON
Output ON resistance
12
Ω
Ω
VCC = 3.3 V; VI = 0 to 0.4 V for AUXP; VI
= 2.7 V to 3.6 V for AUXN
ΔRON
ON resistance mismatch within pair
ON resistance flatness (RON max –
1.3
VCC = 3.3 V; VI = 0 to 0.4 V for AUXP; VI
= 2.7 V to 3.6 V for AUXN
RON_FLAT RON min) measured at identical VCC
and temperature
2
Ω
VAUXP_D AUX Channel DC common mode voltage
VCC = 3.3 V
VCC = 3.3 V
0
0.4
3.6
V
V
for AUXP and SBU1.
C_CM
VAUXN_D AUX Channel DC common mode voltage
2.7
for AUXN and SBU2
C_CM
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www.ti.com.cn
6.6 Switching Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
USB 3.1
tIDLEEntry Delay from U0 to electrical idle
Refer to 图 4
Refer to 图 4
0.16
0.16
ns
ns
tIDLEExit_U U1 exist time: break in electrical idle to
the transmission of LFPS
1
tIDLEExit_U U2/U3 exit time: break in electrical idle to
5
µs
ms
ms
transmission of LFPS
2U3
tRXDET_IN
TVL
RX detect interval while in Disconnect
12
tIDLEExit_D
ISC
Disconnect Exit Time
12
tExit_SHTD
N
Shutdown Exit Time
CTL0 = Vcc/2 to U2U3
0.5
ms
ps
tDIFF_DLY Differential Propagation Delay
Refer to 图 3
300
1
tPWRUPAC Time when Vcc reaches 70% to device
TIVE
ms
active
20%-80% of differential voltage
measured 1.7 inch from the output pin;
Input signal rise/fall faster than 35ps;
Refer to 图 5
tR/F
Output Rise/Fall Time
35
ps
ps
20%-80% of differential voltage
measured 1.7 inch from the output pin
tRF-MM
Output Rise/Fall time mismatch
2.6
AUXP/N and SBU1/2
tAUX_PD
Switch propagation delay
Refer to 图 3
Refer to 图 7
1050
500
ps
ns
tAUX_SW_
OFF
Switching time CTL1 to switch OFF.
Switching time CTL1 to switch ON
Intra-pair output skew
tAUX_SW_
ON
Refer to 图 6
500
100
ns
ps
tAUX_INTR
A
10
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6.7 Timing Requirements
MIN
NOM
MAX
UNIT
I2C Timing
fSCL
tBUF
I2C clock frequency
1
MHz
µs
Bus free time between START and STOP conditions
0.5
Hold time after repeated START condition. After this period, the first clock
pulse is generated
tHDSTA
0.26
µs
tLOW
Low period of the I2C clock
High period of the I2C clock
Setup time for a repeated START condition
Data hold time
0.5
0.26
0.26
0
µs
µs
µs
µs
ns
ns
tHIGH
tSUSTA
tHDDAT
tSUDAT
tR
Data setup time
50
Rise time of both SDA and SCL signals
120
120
20 ×
(VI2C/5.5
V)
tF
Fall time of both SDA and SCL signals
ns
tSUSTO
CBUS
Setup time for STOP condition
Capacitive load for each bus line
0.26
µs
pF
100
HPDIN and CTL1
tCTL1_DEBO CTL1 and HPDIN debounce time when transitioning from H to L. DP lanes
2.5
4
ms
µs
will be disabled if low is greater than min value.
UNCE
USB3.1 and DisplayPort mode transition requirement GPIO mode
tGP_USB_4D Min overlap of CTL0 and CTL1 when transitioning from USB 3.1 only mode
to 4-Lane DisplayPort mode or vice versa. Refer to 图 2
P
Power-on timings
td_pg
VCC(MIN) to Internal power good asserted high. Refer to 图 8
CFG pins setup. Refer to 图 8
500
µs
µs
tcfg_su
tcfg_hd
tctl_db
350
10
CFG pin hold. Refer to 图 8
µs
CTL[1:0] and FLIP pin debounce. Refer to 图 8
16
ms
ms
tVCC_RAMP VCC supply ramp requirement. Refer to 图 8
0.1
100
70%
SDA
30%
t
t
t
F
HDSTA
R
tHIGH
t
t
LOW
BUF
70%
30%
SCL
S
P
P
S
t
t
SUSTO
t
t
SUDAT
HDDAT
HDSTA
t
SUSTA
图 1. I2C Timing Diagram Definitions
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4us
(min)
CTL1 pin
CTL0 pin
图 2. USB3.1 to 4-Lane DisplayPort in GPIO Mode
IN
T
T
DIFF_DLY
DIFF_DLY
OUT
图 3. Propagation Delay
IN+
V
Vcm
RX-LFPS-DET-DIFF-PP
IN-
T
T
IDLEEntry
IDLEExit
OUT+
Vcm
OUT-
图 4. Electrical Idle Mode Exit and Entry Delay
12
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80%
20%
t
r
t
f
图 5. Output Rise and Fall Times
VIH(min)
CTL1
tAUX-SW-ON
SBU2
Copyright © 2017, Texas Instruments Incorporated
图 6. AUX to SBU Switch ON Timing Diagram
tAUX-SW-OFF
CTL1
VIL(max)
SBU2
Copyright © 2017, Texas Instruments Incorporated
图 7. AUX to SBU Switch OFF Timing Diagram
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Tctl_db
Mode of operation
determined by value of
FLIPSEL bit and CTLSEL[1:0]
bits at offset 0x0A. Default
is USB3.1-only no Flip.
USB3.1-only
FLIP = 0
In I2C mode
DISABLED
If ((CTL[1:0] == 2'b00 | CTL[1:0] == 2'b01) & FLIP == 0 ) {
USB3.1-only no FLIP;
} ELSEIF ((CTL[1:0] == 2'b00 | CTL[1:0] == 2'b01) & FLIP == 1 ) {
USB3.1-only with FLIP;
} ELSEIF (CTL[1:0] == 2'b10 & FLIP == 0) {
4-Lane DP no FLIP;
} ELSEIF (CTL[1:0] == 2'b10 & FLIP == 1) {
4-Lane DP with FLIP;
USB3.1-only
FLIP = 0
In GPIO mode
DISABLED
} ELSEIF (CTL[1:0] == 2'b11 & FLIP == 0) {
2-Lane DP USB3.1 no FLIP;
}ELSE {
2-lane DP USB3.1 with FLIP;
};
CTL[1:0] pins
FLIP pin
VCC (min)
VCC
Td_pg
Internal
Power
Good
Tcfg_hd
Tcfg_su
CFG pins
图 8. Power-Up Timing Diagram
14
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6.8 Typical Characteristics
0
-5
0
-5
-10
-15
-20
-25
-30
-35
-40
-45
-10
-15
-20
-25
-30
-35
0
5
10
15
20
0
5
10
15
20
Frequency (GHz)
Frequency (GHz)
D001
D002
图 9. Input Return Loss Performance of the Downstream
图 10. Output Return Loss Performance of the Downstream
Ports
Ports
0
-5
0
-5
-10
-15
-20
-25
-30
-35
-40
-45
-10
-15
-20
-25
-30
-35
-40
-45
0
5
10
15
20
0
5
10
15
20
Frequency (GHz)
Frequency (GHz)
D003
D004
图 11. Input Return Loss Performance of the Upstream Ports
图 12. Output Return Loss Performance of the Upstream
Ports
1800
1600
1400
1200
1000
1600
1400
1200
1000
800
600
400
200
0
800
EQ 0
EQ 2
EQ 4
EQ 6
EQ 8
EQ 10
EQ 12
EQ 15
EQ0
EQ2
EQ4
EQ6
EQ8
EQ10
EQ12
EQ15
600
400
200
0
0
200 400 600 800 1000 1200 1400 1600 1800 2000
0
500
1000
1500
2000
Differential Input Voltage (mVpp)
Differential Input Voltage (mVpp)
D008
D001
4.05 GHz
5 GHz
图 14. Downstream-to-Upstream Linearity Performance at
图 13. Downstream-to-Upstream Linearity Performance at 5
4.05 GHz
GHz
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Typical Characteristics (接下页)
1600
1400
1200
1000
800
600
400
200
0
1600
1400
1200
1000
800
600
400
200
0
EQ0
EQ2
EQ4
EQ6
EQ8
EQ10
EQ12
EQ15
EQ 0
0
200 400 600 800 1000 1200 1400 1600 1800 2000
0
500
1000
1500
2000
Differential Input Voltage (mVpp)
D009
Differential Input Voltage (mVpp)
D002
100 MHz
5 GHz
图 15. Downstream-to-Upstream Linearity Performance at
图 16. Upstream-to-Downstream Linearity Performance at 5
100 MHz
GHz
1600
1400
1200
1000
1600
1400
1200
1000
800
800
EQ 0
EQ 2
EQ 4
600
600
EQ 6
EQ 8
EQ 10
EQ 12
EQ 15
400
200
0
400
200
EQ 0
0
0
200 400 600 800 1000 1200 1400 1600 1800 2000
0
200 400 600 800 1000 1200 1400 1600 1800 2000
Differential Input Voltage (mVpp)
D011
D012
4.05 GHz
100 MHz
图 17. Upstream-to-Downstream Linearity Performance at
图 18. Upstream-to-Downstream Linearity Performance at
4.05 GHz
100 MHz
Source:
Data Rate: 8.1 Gbps; Data Pattern: PRBS7;
Swing: 1 Vpp
Upstream-to-Downstream, 12 in 6 mil Input
PCB Channel
EQ Setting: 7; DC Gain Setting: 0 dB;
Linear Range Setting: 1100 mVpp
Source:
Data Rate: 10 Gbps; Data Pattern: PRBS7;
Swing: 1 Vpp
Upstream-to-Downstream, 12 in 6 mil Input
PCB Channel
EQ Setting: TBD; DC Gain Setting: 0 dB;
Linear Range Setting: 1100 mVpp
Channel:
Settings:
Channel:
Settings:
图 20. Output Eye-Pattern Performance at 8.1 Gbps
版权 © 2018, Texas Instruments Incorporated
图 19. Output Eye-Pattern Performance at 10 Gbps
16
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Typical Characteristics (接下页)
15
EQ0
EQ1
EQ2
EQ3
EQ4
EQ5
EQ6
EQ7
EQ8
EQ9
EQ10
EQ11
EQ12
EQ13
EQ14
EQ15
10
5
0
-5
-10
0.01
0.1
1
10
20
Frequency (GHz)
D005
图 21. Upstream-to-Downstream EQ Settings Curves
15
10
5
EQ0
EQ1
EQ2
EQ3
EQ4
EQ5
EQ6
EQ7
EQ8
EQ9
EQ10
EQ11
EQ12
EQ13
EQ14
EQ15
0
-5
-10
0.01
0.1
1
10
20
Frequency (GHz)
D006
图 22. Downstream-to-Upstream EQ Settings Curves
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7 Detailed Description
7.1 Overview
The TUSB1044 is a USB Type-C Alt Mode redriver switch supporting data rates up to 8.1 Gbps. This device
implements 5th generation USB redriver technology. The device is used for configurations C, D, E, and F from
the VESA DisplayPort Alt Mode on USB Type-C Standard. It can also be configured to support custom USB
Type-C alternate modes.
The TUSB1044 provides several levels of receive equalization to compensate for cable and board trace loss due
to inter-symbol interference (ISI) when USB 3.1 Gen 2 or DisplayPort (or other Alt modes) signals travel across a
PCB or cable. This device requires a 3.3V power supply. It comes for both commercial temperature range and
industrial temperature range operation.
For host (source) or device (sink) applications, the TUSB1044 enables the system to pass both transmitter
compliance and receiver jitter tolerance tests for USB 3.1 Gen 2 and DisplayPort version 1.4 HBR3. The re-driver
recovers incoming data by applying equalization that compensates for channel loss, and drives out signals with a
high differential voltage. Each channel has a receiver equalizer with selectable gain settings. Equalization control
for upstream and downstream facing ports can be set using UEQ[1:0], and DEQ[1:0] pins respectively or through
the I2C interface.
Moreover, the CFG[1:0] or the equivalent I2C registers provide the ability to control the EQ DC gain and the
voltage linearity range for all the channels (Refer to 表 8). This flexible control makes it easy to set up the device
to pass various standard compliance requirements.
The TUSB1044 advanced state machine makes it transparent to hosts and devices. After power up, the
TUSB1044. periodically performs receiver detection on the TX pairs. If it detects a USB 3.1 receiver, the RX
termination is enabled, and the TUSB1044 is ready to re-drive.
The TUSB1044 provides extremely flexible data path signal direction control using the CTL[1:0], FLIP, DIR[1:0],
and SWAP pins or through the I2C interface. Refer to 表 4 for detailed information on the input to output signal
pin mapping.
The device ultra-low-power architecture operates at a 3.3 V power supply and achieves enhanced performance.
The automatic LFPS De-Emphasis control further enables the system to be USB 3.1 compliant.
18
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TUSB1044
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ZHCSHJ2C –FEBRUARY 2018–REVISED OCTOBER 2018
7.2 Functional Block Diagram
DRX2EQ_SEL
Driver
EQ
URX2EQ_SEL
URX2p
CHANNEL 0
URX2n
DRX2p
Driver
EQ
EQ
CHANNEL 0
DRX2n
DTX2EQ_SEL
Driver
EQ
UTX2EQ_SEL
UTX2p
DTX2p
Driver
EQ
EQ
CHANNEL 1
CHANNEL 1
UTX2n
DTX2n
DTX1EQ_SEL
Driver
EQ
UTX1EQ_SEL
UTX1n
CHANNEL 2
UTX1p
DTX1n
Driver
EQ
EQ
CHANNEL 2
DTX1p
DRX1EQ_SEL
Driver
EQ
URX1EQ_SEL
URX1n
CHANNEL 3
URX1p
DRX1n
Driver
EQ
EQ
CHANNEL 3
DRX1p
DTX[2:1]EQ_SEL
DRX[2:1]EQ_SEL
UTX[2:1]EQ_SEL
URX[2:1]EQ_SEL
UEQ1/A1
UEQ0/A0
I2C_EN
DEQ[1:0]
SWAP
DIR[1:0]
FSM, Control Logic &
Registers
FLIP/SCL
CTL0/SDA
CTL1
I2C
Slave
SLP_S0#
VIO_SEL
CFG[1:0]
M
U
X
SBU1
SBU2
AUXp
AUXn
VREG
VCC
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7.3 Feature Description
7.3.1 USB 3.1
The TUSB1044 supports USB 3.1 data rates up to 10 Gbps. The TUSB1044 supports all the USB defined power
states (U0, U1, U2, and U3). Because the TUSB1044 is a linear redriver, it can’t decode USB3.1 physical layer
traffic. The TUSB1044 monitors the actual physical layer conditions like receiver termination, electrical idle,
LFPS, and SuperSpeed signaling rate to determine the USB power state of the USB3.1 interface.
The TUSB1044 features an intelligent low frequency periodic signaling (LFPS) detector. The LFPS detector
automatically senses the low frequency signals and disables receiver equalization functionality. When not
receiving LFPS, the TUSB1044 enables receiver equalization based on the UEQ[1:0] and DEQ[1:0] pins or
values programmed into UEQ[3:0]_SEL, and DEQ[3:0]_SEL registers.
7.3.2 DisplayPort
The TUSB1044 supports up to 4 DisplayPort lanes at data rates up to 8.1 Gbps (HBR3). The TUSB1044, when
configured in DisplayPort mode, monitors the native AUX traffic as it traverses between DisplayPort source and
DisplayPort sink. For the purposes of reducing power, the TUSB1044 manages the number of active DisplayPort
lanes based on the content of the AUX transactions. The TUSB1044 snoops native AUX writes to DisplayPort
sink’s DPCD registers 00101h (LANE_COUNT_SET) and 00600h (SET_POWER_STATE). TUSB1044 disable or
enable lanes based on value written to LANE_COUNT_SET. The TUSB1044 disables all lanes when
SET_POWER_STATE is in the D3. Otherwise, active lanes are based on value of LANE_COUNT_SET.
DisplayPort AUX snooping is enabled by default but can be disabled by changing the AUX_SNOOP_DISABLE
register. Once AUX snoop is disabled, management of TUSB1044 DisplayPort lanes are controlled through
various configuration registers.
7.3.3 4-level Inputs
The TUSB1044 has (I2C_EN, UEQ[1:0], DEQ[1:0], CFG[1:0], and A[1:0]) 4-level inputs pins that are used to
control the equalization gain, voltage linearity range, and place TUSB1044 into different modes of operation.
These 4-level inputs utilize a resistor divider to help set the 4 valid levels and provide a wider range of control
settings. There is an internal pull-up and a pull-down resistors. These resistors, together with the external resistor
connection combine to achieve the desired voltage level.
表 1. 4-Level Control Pin Settings
LEVEL
SETTINGS
Option 1: Tie 1 KΩ 5% to GND.
Option 2: Tie directly to GND.
0
R
F
Tie 20 KΩ 5% to GND.
Float (leave pin open)
Option 1: Tie 1 KΩ 5%to VCC
.
1
Option 2: Tie directly to VCC
.
注
All four-level inputs are latched on rising edge of internal reset. After Tcfg_hd, the internal
pull-up and pull-down resistors will be isolated in order to save power.
7.3.4 Receiver Linear Equalization
The purpose of receiver equalization is to compensate for channel insertion loss and inter-symbol interference in
the system. The receiver overcomes these losses by attenuating the low frequency components of the signals
with respect to the high frequency components. The proper gain setting should be selected to match the channel
insertion loss. Two 4-level input pins enable up to 16 possible equalization settings. The upstream path, and the
downstream path each have their own two 4-level inputs for equalization settings; UEQ[1:0] and DEQ[1:0]
respectively. The TUSB1044 also provides the flexibility of adjusting equalization settings through I2C registers
URX[2:1]EQ_SEL, UTX[2:1]EQ_SEL, DRX[2:1]EQ_SEL, and DTX[2:1]EQ_SEL for each individual channel and
for each direction (upstream or downstream) .
20
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7.4 Device Functional Modes
7.4.1 Device Configuration in GPIO mode
The TUSB1044 is in GPIO configuration when I2C_EN = “0” or I2C_EN = "F". The TUSB1044 supports
operational combinations with USB and two different Type-C Alternate Modes. One combination includes USB
and Alternate Mode DisplayPort, and the other combination includes USB and custom Alternate Mode. For each
operational combination the data path directions can be further set using the DIR[1:0] pins or through I2C to
enable the device to operate in the source or sink sides. Please refer to 表 2 for all the configuration of all the
operational modes.
When the device is set to operate in a USB and Alternate Mode DisplayPort the following configurations can be
further set: USB3.1 only, 2 DisplayPort lanes + USB3.1, or 4 DisplayPort lanes (no USB3.1). The CTL1 pin
controls whether DisplayPort mode is enabled. The combination of CTL1 and CTL0 selects between USB3.1
only, 2 lanes of DisplayPort, or 4-lanes of DisplayPort as detailed in 表 2. The AUXP/N to SBU1/2 mapping is
controlled based on 表 3..
When the device is set to operate in a USB and custom Alternate Mode, the following configurations can be
further set: USB3.1 only, 2 Channels of custom Alternate Mode + USB3.1, or 4 Channels of custom Alternate
Mode (no USB3.1). The CTL1 pin controls whether custom Alternate Mode is enabled. The combination of CTL1
and CTL0 selects between USB3.1 only, 2 channels of custom Alternate Mode, or 4 channels of custom
Alternate Mode as detailed in 表 2. The AUXP/N to SBU1/2 mapping is controlled based on 表 3.
Further data path direction control can be achieved using the SWAP pin. When set high, the SWAP pin reverses
the data path direction on all the channels and swaps the equalization settings of the upstream and downstream
facing input ports. This pin may be found useful in active cable application with TUSB1044 installed on only one
end. The SWAP pin can be set based on which cable end is plugged to the source or sink side receptacle
After power-up (VCC from 0 V to 3.3 V), the TUSB1044 will default to USB3.1 mode. The USB PD controller,
upon detecting no device attached to Type-C port or USB3.1 operation not required by attached device, must
take TUSB1044 out of USB3.1 mode by transitioning the CTL0 pin from L to H and back to L.
表 2. GPIO Configuration Control
VESA DisplayPort ALT
MODE
DFP_D Configuration
DIR1
PIN
DIR0
PIN
CTL1
PIN
CTL0
PIN
FLIP
PIN
TUSB1044 CONFIGURATION
USB + DisplayPort Alternate Mode (Source Side)
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
L
Power Down
Power Down
—
—
L
H
H
L
One Port USB 3.1 - No Flip
One Port USB 3.1 – With Flip
4 Lane DP - No Flip
—
L
H
L
—
H
H
C and E
C and E
L
H
4 Lane DP – with Flip
One Port USB 3.1 + 2 Lane DP- No
Flip
L
L
L
L
H
H
H
H
L
D and F
D and F
One Port USB 3.1 + 2 Lane DP– with
Flip
H
USB + DisplayPort Alternate Mode (Sink Side)
L
L
L
L
L
L
H
H
H
H
H
H
L
L
L
L
L
H
L
Power Down
Power Down
–
–
L
H
H
L
One Port USB 3.1 - No Flip
One Port USB 3.1 – With Flip
4 Lane DP - No Flip
–
L
H
L
–
H
H
C and E
C and E
L
H
4 Lane DP – With Flip
One Port USB 3.1 + 2 Lane DP- No
Flip
L
L
H
H
H
H
H
H
L
D and F
D and F
One Port USB 3.1 + 2 Lane DP– With
Flip
H
版权 © 2018, Texas Instruments Incorporated
21
TUSB1044
ZHCSHJ2C –FEBRUARY 2018–REVISED OCTOBER 2018
www.ti.com.cn
Device Functional Modes (接下页)
表 2. GPIO Configuration Control (接下页)
VESA DisplayPort ALT
MODE
DFP_D Configuration
DIR1
PIN
DIR0
PIN
CTL1
PIN
CTL0
PIN
FLIP
PIN
TUSB1044 CONFIGURATION
USB + Custom Alternate Mode (Source Side)
H
H
H
H
H
L
L
L
L
L
L
L
L
L
H
L
L
L
H
L
Power Down
Power Down
–
–
–
–
–
H
H
L
One Port USB 3.1 - No Flip
One Port USB 3.1 – With Flip
4 Channel Custom Alt Mode - No Flip
H
L
4 Channel Custom Alt Mode– With
Flip
H
H
H
L
L
L
H
H
H
L
H
H
H
L
–
–
–
One Port USB 3.1 + 2 Channel
Custom Alt Mode- No Flip
One Port USB 3.1 + 2 Channel
Custom Alt Mode – With Flip
H
USB + Custom Alternate Mode (Sink Side)
H
H
H
H
H
H
H
H
H
H
L
L
L
L
H
L
L
L
H
L
Power Down
Power Down
-
-
-
-
-
H
H
L
One Port USB 3.1 - No Flip
One Port USB 3.1 – With Flip
4 Channel Custom Alt Mode - No Flip
H
L
4 Channel Custom Alt Mode– With
Flip
H
H
H
H
H
H
H
H
H
L
H
H
H
L
-
-
-
One Port USB 3.1 + 2 Channel
Custom Alt Mode- No Flip
One Port USB 3.1 + 2 Channel
Custom Alt Mode – With Flip
H
表 3. GPIO AUXP/N to SBU1/2 Mapping
CTL1 pin
FLIP pin
Mapping
AUXP -> SBU1
AUXN -> SBU2
H
L
AUXP -> SBU2
AUXN -> SBU1
H
H
X
L > 2ms
Open
22
版权 © 2018, Texas Instruments Incorporated
TUSB1044
www.ti.com.cn
ZHCSHJ2C –FEBRUARY 2018–REVISED OCTOBER 2018
表 4 details the TUSB1044 mux routing. This table is valid for GPIO Mode. This table is also valid for I2C mode if
CH_SWAP_SEL = 4'b0000 or 4'b1111.
表 4. INPUT to OUTPUT Mapping
SWAP = L
From
SWAP = H
From
From
To
From
To
Rx EQ
Control
PINS
Rx EQ
Control
PINS
DIR1
PIN
DIR0 CTL1
PIN PIN
CTL0
PIN
FLIP
PIN
Input
PIN
Output
PIN
Input
PIN
Output
PIN
USB + DisplayPort Alternate Mode (Source Side)
L
L
L
L
L
L
L
L
L
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
H
URX1P
(SSRXP)
URX1P
(SSTXP)
DEQ[1:0]
DEQ[1:0]
UEQ[1:0]
UEQ[1:0]
DEQ[1:0]
DEQ[1:0]
UEQ[1:0]
UEQ[1:0]
UEQ[1:0]
UEQ[1:0]
UEQ[1:0]
UEQ[1:0]
UEQ[1:0]
UEQ[1:0]
UEQ[1:0]
UEQ[1:0]
DRX1P
DRX1N
DEQ[1:0]
DEQ[1:0]
UEQ[1:0]
UEQ[1:0]
DEQ[1:0]
DEQ[1:0]
UEQ[1:0]
UEQ[1:0]
UEQ[1:0]
UEQ[1:0]
UEQ[1:0]
UEQ[1:0]
UEQ[1:0]
UEQ[1:0]
UEQ[1:0]
UEQ[1:0]
DRX1P
DRX1N
URX1N
(SSRXN)
URX1N
(SSTXN)
L
L
L
H
L
UTX1P
(SSTXP)
UTX1P
(SSRXP)
DTX1P
DTX1N
DTX1P
DTX1N
UTX1N
(SSTXN)
UTX1N
(SSRXN)
URX2P
(SSRXP)
URX2P
(SSTXP)
DRX2P
DRX2N
DRX2P
DRX2N
URX2N
(SSRXN)
URX2N
(SSTXN)
L
L
L
H
H
UTX2P
(SSTXP)
UTX2P
(SSRXP)
DTX2P
DTX2N
DRX2P
DRX2N
DTX2P
DTX2N
DTX1P
DTX1N
DRX1P
DRX1N
DTX2P
DTX2N
DRX2P
DRX2N
DTX2P
DTX2N
DTX1P
DTX1N
DRX1P
DRX1N
UTX2N
(SSTXN)
UTX2N
(SSRXN)
URX2P
(DP0P)
URX2P
(DP0P)
URX2N
(DP0N)
URX2N
(DP0N)
UTX2P
(DP1P)
UTX2P (DP1P)
UTX2N
(DP1N)
UTX2N
(DP1N)
L
L
H
L
L
UTX1P
(DP2P)
UTX1P (DP2P)
UTX1N
(DP2N)
UTX1N
(DP2N)
URX1P
(DP3P)
URX1P
(DP3P)
URX1N
(DP3N)
URX1N
(DP3N)
版权 © 2018, Texas Instruments Incorporated
23
TUSB1044
ZHCSHJ2C –FEBRUARY 2018–REVISED OCTOBER 2018
www.ti.com.cn
表 4. INPUT to OUTPUT Mapping (接下页)
SWAP = L
From
SWAP = H
From
From
To
From
To
Rx EQ
Control
PINS
Rx EQ
Control
PINS
DIR1
PIN
DIR0 CTL1
CTL0
PIN
FLIP
PIN
Input
PIN
Output
PIN
Input
PIN
Output
PIN
PIN
PIN
URX1P
(DP0P)
URX1P
(DP0P)
UEQ[1:0]
UEQ[1:0]
UEQ[1:0]
UEQ[1:0]
UEQ[1:0]
UEQ[1:0]
UEQ[1:0]
UEQ[1:0]
DEQ[1:0]
DEQ[1:0]
UEQ[1:0]
UEQ[1:0]
UEQ[1:0]
UEQ[1:0]
UEQ[1:0]
UEQ[1:0]
DEQ[1:0]
DEQ[1:0]
UEQ[1:0]
UEQ[1:0]
UEQ[1:0]
UEQ[1:0]
UEQ[1:0]
UEQ[1:0]
DRX1P
DRX1N
DTX1P
DTX1N
DTX2P
DTX2N
DRX2P
DRX2N
UEQ[1:0]
UEQ[1:0]
UEQ[1:0]
UEQ[1:0]
UEQ[1:0]
UEQ[1:0]
UEQ[1:0]
UEQ[1:0]
DEQ[1:0]
DEQ[1:0]
UEQ[1:0]
UEQ[1:0]
UEQ[1:0]
UEQ[1:0]
UEQ[1:0]
UEQ[1:0]
DEQ[1:0]
DEQ[1:0]
UEQ[1:0]
UEQ[1:0]
UEQ[1:0]
UEQ[1:0]
UEQ[1:0]
UEQ[1:0]
DRX1P
DRX1N
DTX1P
DTX1N
DTX2P
DTX2N
DRX2P
DRX2N
URX1N
(DP0N)
URX1N
(DP0N)
UTX1P
(DP1P)
UTX1P (DP1P)
UTX1N
(DP1N)
UTX1N
(DP1N)
L
L
L
L
H
L
H
H
H
UTX2P
(DP2P)
UTX2P (DP2P)
UTX2N
(DP2N)
UTX2N
(DP2N)
URX2P
(DP3P)
URX2P
(DP3P)
URX2N
(DP3N)
URX2N
(DP3N)
URX1P
(SSRXP)
URX1P
(SSTXP)
DRX1P
DRX1N
DRX1P
DRX1N
URX1N
(SSRXN)
URX1N
(SSTXN)
UTX1P
(SSTXP)
UTX1P
(SSRXP)
DTX1P
DTX1N
DRX2P
DRX2N
DTX2P
DTX2N
DTX1P
DTX1N
DRX2P
DRX2N
DTX2P
DTX2N
UTX1N
(SSTXN)
UTX1N
(SSRXN)
L
H
L
URX2P
(DP0P)
URX2P
(DP0P)
URX2N
(DP0N)
URX2N
(DP0N)
UTX2P
(DP1P)
UTX2P (DP1P)
UTX2N
(DP1N)
UTX2N
(DP1N)
URX2P
(SSRXP)
URX2P
(SSTXP)
DRX2P
DRX2N
DRX2P
DRX2N
URX2N
(SSRXN)
URX2N
(SSTXN)
UTX2P
(SSTXP)
UTX2P
(SSRXP)
DTX2P
DTX2N
DRX1P
DRX1N
DTX1P
DTX1N
DTX2P
DTX2N
DRX1P
DRX1N
DTX1P
DTX1N
UTX2N
(SSTXN)
UTX2N
(SSRXN)
L
H
H
URX1P
(DP0P)
URX1P
(DP0P)
URX1N
(DP0N)
URX1N
(DP0N)
UTX1P
(DP1P)
UTX1P (DP1P)
UTX1N
(DP1N)
UTX1N
(DP1N)
USB + DisplayPort Alternate Mode (Sink Side)
L
L
H
H
L
L
L
L
L
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
H
24
版权 © 2018, Texas Instruments Incorporated
TUSB1044
www.ti.com.cn
ZHCSHJ2C –FEBRUARY 2018–REVISED OCTOBER 2018
表 4. INPUT to OUTPUT Mapping (接下页)
SWAP = L
From
SWAP = H
From
From
To
From
To
Rx EQ
Control
PINS
Rx EQ
Control
PINS
DIR1
PIN
DIR0 CTL1
CTL0
PIN
FLIP
PIN
Input
PIN
Output
PIN
Input
PIN
Output
PIN
PIN
PIN
DTX2P
(SSRXP)
DTX2P
(SSTXP)
UEQ[1:0]
UEQ[1:0]
DEQ[1:0]
DEQ[1:0]
UEQ[1:0]
UEQ[1:0]
DEQ[1:0]
DEQ[1:0]
UEQ[1:0]
UEQ[1:0]
UEQ[1:0]
UEQ[1:0]
UEQ[1:0]
UEQ[1:0]
UEQ[1:0]
UEQ[1:0]
UEQ[1:0]
UEQ[1:0]
UEQ[1:0]
UEQ[1:0]
UEQ[1:0]
UEQ[1:0]
UEQ[1:0]
UEQ[1:0]
UTX2P
UTX2N
UEQ[1:0]
UEQ[1:0]
DEQ[1:0]
DEQ[1:0]
UEQ[1:0]
UEQ[1:0]
DEQ[1:0]
DEQ[1:0]
UEQ[1:0]
UEQ[1:0]
UEQ[1:0]
UEQ[1:0]
UEQ[1:0]
UEQ[1:0]
UEQ[1:0]
UEQ[1:0]
UEQ[1:0]
UEQ[1:0]
UEQ[1:0]
UEQ[1:0]
UEQ[1:0]
UEQ[1:0]
UEQ[1:0]
UEQ[1:0]
UTX2P
UTX2N
DTX2N
(SSRXN)
DTX2N
(SSTXN)
L
H
L
H
L
DRX2P
(SSTXP)
DRX2P
(SSRXP)
URX2P
URX2N
URX2P
URX2N
DRX2N
(SSTXN)
DRX2N
(SSRXN)
DTX1P
(SSRXP)
DTX1P
(SSTXP)
UTX1P
UTX1N
UTX1P
UTX1N
DTX1N
(SSRXN)
DTX1N
(SSTXN)
L
H
L
H
H
DRX1P
(SSTXP)
DRX1P
(SSRXP)
URX1P
URX1N
URX1P
URX1N
DRX1N
(SSTXN)
DRX1N
(SSRXN)
DRX2P
(DP3P)
DRX2P
(DP3P)
URX2P
URX2N
UTX2P
UTX2N
UTX1P
UTX1N
URX1P
URX1P
URX1P
URX1N
UTX1P
UTX1N
UTX2P
UTX2N
URX2P
URX2N
URX2P
URX2N
UTX2P
UTX2N
UTX1P
UTX1N
URX1P
URX1N
URX1P
URX1N
UTX1P
UTX1N
UTX2P
UTX2N
URX2P
URX2N
DRX2N
(DP3N)
DRX2N
(DP3N)
DTX2P
(DP2P)
DTX2P
(DP2P)
DTX2N
(DP2N)
DTX2N
(DP2N)
L
H
H
L
L
DTX1P
(DP1P)
DTX1P
(DP1P)
DTX1N
(DP1N)
DTX1N
(DP1N)
DRX1P
(DP0P)
DRX1P
(DP0P)
DRX1N
(DP0P)
DRX1N
(DP0N)
DRX1P
(DP3P)
DRX1P
(DP3P)
DRX1N
(DP3N)
DRX1N
(DP3N)
DTX1P
(DP2P)
DTX1P
(DP2P)
DTX1N
(DP2N)
DTX1N
(DP2N)
L
H
H
L
H
DTX2P
(DP1P)
DTX2P
(DP1P)
DTX2N
(DP1N)
DTX2N
(DP1N)
DRX2P
(DP0P)
DRX2P
(DP0P)
DRX2N
(DP0N)
DRX2N
(DP0N)
版权 © 2018, Texas Instruments Incorporated
25
TUSB1044
ZHCSHJ2C –FEBRUARY 2018–REVISED OCTOBER 2018
www.ti.com.cn
表 4. INPUT to OUTPUT Mapping (接下页)
SWAP = L
From
SWAP = H
From
From
To
From
To
Rx EQ
Control
PINS
Rx EQ
Control
PINS
DIR1
PIN
DIR0 CTL1
CTL0
PIN
FLIP
PIN
Input
PIN
Output
PIN
Input
PIN
Output
PIN
PIN
PIN
DRX2P
(SSRXP)
DRX2P
(SSRXP)
DEQ[1:0]
DEQ[1:0]
UEQ[1:0]
UEQ[1:0]
UEQ[1:0]
UEQ[1:0]
UEQ[1:0]
UEQ[1:0]
DEQ[1:0]
DEQ[1:0]
UEQ[1:0]
UEQ[1:0]
UEQ[1:0]
UEQ[1:0]
UEQ[1:0]
UEQ[1:0]
URX2P
URX2N
DEQ[1:0]
DEQ[1:0]
UEQ[1:0]
UEQ[1:0]
UEQ[1:0]
UEQ[1:0]
UEQ[1:0]
UEQ[1:0]
DEQ[1:0]
DEQ[1:0]
UEQ[1:0]
UEQ[1:0]
UEQ[1:0]
UEQ[1:0]
UEQ[1:0]
UEQ[1:0]
URX2P
URX2N
DRX2N
(SSRXN)
DRX2N
(SSRXN)
DTX2P
(SSTXP)
DTX2P
(SSTXP)
UTX2P
UTX2N
URX1P
URX1N
UTX1P
UTX1N
UTX2P
UTX2N
URX1P
URX1N
UTX1P
UTX1N
DTX2N
(SSTXN)
DTX2N
(SSTXN)
L
H
H
H
L
DRX1P
(DP0P)
DRX1P
(DP0P)
DRX1N
(DP0N)
DRX1N
(DP0N)
DTX1P
(DP1P)
DTX1P
(DP1P)
DTX1N
(DP1N)
DTX1N
(DP1N)
DRX1P
(SSRXP)
DRX1P
(SSRXP)
URX1P
URX1N
URX1P
URX1N
DRX1N
(SSRXN)
DRX1N
(SSRXN)
DTX1P
(SSTXP)
DTX1P
(SSTXP)
UTX1P
UTX1N
URX2P
URX2N
UTX2P
UTX2N
UTX1P
UTX1N
URX2P
URX2N
UTX2P
UTX2N
DTX1N
(SSTXN)
DTX1N
(SSTXN)
L
H
H
H
H
DRX2P
(DP0P)
DRX2P
(DP0P)
DRX2N
(DP0N)
DRX2N
(DP0N)
DTX2P
(DP1P)
DTX2P
(DP1P)
DTX2N
(DP1N)
DTX2N
(DP1N)
USB + Custom Alternate Mode (Source Side)
H
H
L
L
L
L
L
L
L
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
H
URX1P
(SSRXP)
URX1P
(SSTXP)
DEQ[1:0]
DEQ[1:0]
UEQ[1:0]
UEQ[1:0]
DEQ[1:0]
DEQ[1:0]
UEQ[1:0]
UEQ[1:0]
DRX1P
DRX1N
DEQ[1:0]
DEQ[1:0]
UEQ[1:0]
UEQ[1:0]
DEQ[1:0]
DEQ[1:0]
UEQ[1:0]
UEQ[1:0]
DRX1P
DRX1N
URX1N
(SSRXN)
URX1N
(SSTXN)
H
L
L
H
L
UTX1P
(SSTXP)
UTX1P
(SSRXP)
DTX1P
DTX1N
DTX1P
DTX1N
UTX1N
(SSTXN)
UTX1N
(SSRXN)
URX2P
(SSRXP)
URX2P
(SSTXP)
DRX2P
DRX2N
DRX2P
DRX2N
URX2N
(SSRXN)
URX2N
(SSTXN)
H
L
L
H
H
UTX2P
(SSTXP)
UTX2P
(SSRXP)
DTX2P
DTX2N
DTX2P
DTX2N
UTX2N
(SSTXN)
UTX2N
(SSRXN)
26
版权 © 2018, Texas Instruments Incorporated
TUSB1044
www.ti.com.cn
ZHCSHJ2C –FEBRUARY 2018–REVISED OCTOBER 2018
表 4. INPUT to OUTPUT Mapping (接下页)
SWAP = L
From
SWAP = H
From
From
To
From
To
Rx EQ
Control
PINS
Rx EQ
Control
PINS
DIR1
PIN
DIR0 CTL1
CTL0
PIN
FLIP
PIN
Input
PIN
Output
PIN
Input
PIN
Output
PIN
PIN
PIN
URX2P
(LN1RXP)
URX2P
(LN1RXP)
DEQ[1:0]
DEQ[1:0]
UEQ[1:0]
UEQ[1:0]
UEQ[1:0]
UEQ[1:0]
DEQ[1:0]
DEQ[1:0]
DEQ[1:0]
DEQ[1:0]
UEQ[1:0]
UEQ[1:0]
UEQ[1:0]
UEQ[1:0]
DEQ[1:0]
DEQ[1:0]
DEQ[1:0]
DEQ[1:0]
UEQ[1:0]
UEQ[1:0]
UEQ[1:0]
UEQ[1:0]
DEQ[1:0]
DEQ[1:0]
DRX2P
DRX2N
DEQ[1:0]
DEQ[1:0]
UEQ[1:0]
UEQ[1:0]
UEQ[1:0]
UEQ[1:0]
DEQ[1:0]
DEQ[1:0]
DEQ[1:0]
DEQ[1:0]
UEQ[1:0]
UEQ[1:0]
UEQ[1:0]
UEQ[1:0]
DEQ[1:0]
DEQ[1:0]
DEQ[1:0]
DEQ[1:0]
UEQ[1:0]
UEQ[1:0]
UEQ[1:0]
UEQ[1:0]
DEQ[1:0]
DEQ[1:0]
DRX2P
DRX2N
URX2N
(LN1RXN)
URX2N
(LN1RXN)
UTX2P
(LN1TXP)
UTX2P
(LN1TXP)
DTX2P
DTX2N
DTX1P
DTX1N
DTX2P
DTX2N
DTX1P
DTX1N
UTX2N
(LN1TXN)
UTX2N
(LN1TXN)
H
L
H
L
L
UTX1P
(LN0TXP)
UTX1P
(LN0TXP)
UTX1N
(LN0TXN)
UTX1N
(LN0TXN)
URX1P
(LN0RXP)
URX1P
(LN0RXP)
DRX1P
DRX1N
DRX1P
DRX1N
DRX1P
DRX1N
DRX1P
DRX1N
URX1N
(LN0RXN)
URX1N
(LN0RXN)
URX1P
(LN1RXP)
URX1P
(LN1RXP)
URX1N
(LN1RXN)
URX1N
(LN1RXN)
UTX1P
(LN1TXP)
UTX1P
(LN1TXP)
DTX1P
DTX1N
DTX2P
DTX2N
DTX1P
DTX1N
DTX2P
DTX2N
H
L
H
L
H
UTX1N
(LN1TXN)
UTX1N
(LN1TXN)
UTX2P
(LN0TXP)
UTX2P
(LN0TXP)
UTX2N
(LN0TXN)
UTX2N
(LN0TXN)
URX2P
(LN0RXP)
URX2P
(LN0RXP)
DRX2P
DRX2N
DRX1P
DRX1N
DRX2P
DRX2N
DRX1P
DRX1N
URX2N
(LN0RXN)
URX2N
(LN0RXN)
URX1P
(SSRXP)
URX1P
(SSTXP)
URX1N
(SSRXN)
URX1N
(SSTXN)
UTX1P
(SSTXP)
UTX1P
(SSRXP)
DTX1P
DTX1N
DTX2P
DTX2N
DTX1P
DTX1N
DTX2P
DTX2N
H
L
H
H
L
UTX1N
(SSTXN)
UTX1N
(SSRXN)
UTX2P
(LN0TXP)
UTX2P
(LN0TXP)
UTX2N
(LN0TXN)
UTX2N
(LN0TXN)
URX2P
(LN0RXP)
URX2P
(LN0RXP)
DRX2P
DRX2N
DRX2P
DRX2N
URX2N
(LN0RXN)
URX2N
(LN0RXN)
版权 © 2018, Texas Instruments Incorporated
27
TUSB1044
ZHCSHJ2C –FEBRUARY 2018–REVISED OCTOBER 2018
www.ti.com.cn
表 4. INPUT to OUTPUT Mapping (接下页)
SWAP = L
From
SWAP = H
From
From
To
From
To
Rx EQ
Control
PINS
Rx EQ
Control
PINS
DIR1
PIN
DIR0 CTL1
CTL0
PIN
FLIP
PIN
Input
PIN
Output
PIN
Input
PIN
Output
PIN
PIN
PIN
URX2P
(SSRXP)
URX2P
(SSTXP)
DEQ[1:0]
DEQ[1:0]
UEQ[1:0]
UEQ[1:0]
UEQ[1:0]
UEQ[1:0]
DEQ[1:0]
DEQ[1:0]
DRX2P
DRX2N
DEQ[1:0]
DEQ[1:0]
UEQ[1:0]
UEQ[1:0]
UEQ[1:0]
UEQ[1:0]
DEQ[1:0]
DEQ[1:0]
DRX2P
DRX2N
URX2N
(SSRXN)
URX2N
(SSTXN)
UTX2P
(SSTXP)
UTX2P
(SSRXP)
DTX2P
DTX2N
DTX1P
DTX1N
DTX2P
DTX2N
DTX1P
DTX1N
UTX2N
(SSTXN)
UTX2N
(SSRXN)
H
L
H
H
H
UTX1P
(LN0TXP)
UTX1P
(LN0TXP)
UTX1N
(LN0TXN)
UTX1N
(LN0TXN)
URX1P
(LN0RXP)
URX1P
(LN0RXP)
DRX1P
DRX1N
DRX1P
DRX1N
URX1N
(LN0RXN)
URX1N
(LN0RXN)
USB + Custom Alternate Mode (Sink Side)
H
H
H
H
L
L
L
L
L
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
H
DTX2P
(SSRXP)
DTX2P
(SSTXP)
UEQ[1:0]
UEQ[1:0]
DEQ[1:0]
DEQ[1:0]
UEQ[1:0]
UEQ[1:0]
DEQ[1:0]
DEQ[1:0]
DEQ[1:0]
DEQ[1:0]
UEQ[1:0]
UEQ[1:0]
UEQ[1:0]
UEQ[1:0]
DEQ[1:0]
DEQ[1:0]
UTX2P
UTX2N
UEQ[1:0]
UEQ[1:0]
DEQ[1:0]
DEQ[1:0]
UEQ[1:0]
UEQ[1:0]
DEQ[1:0]
DEQ[1:0]
DEQ[1:0]
DEQ[1:0]
UEQ[1:0]
UEQ[1:0]
UEQ[1:0]
UEQ[1:0]
DEQ[1:0]
DEQ[1:0]
UTX2P
UTX2N
DTX2N
(SSRXN)
DTX2N
(SSTXN)
H
H
L
H
L
DRX2P
(SSTXP)
DRX2P
(SSRXP)
URX2P
URX2N
URX2P
URX2N
DRX2N
(SSTXN)
DRX2N
(SSRXN)
DTX1P
(SSRXP)
DTX1P
(SSTXP)
UTX1P
UTX1N
UTX1P
UTX1N
DTX1N
(SSRXN)
DTX1N
(SSTXN)
H
H
L
H
H
DRX1P
(SSTXP)
DRX1P
(SSRXP)
URX1P
URX1N
URX1P
URX1N
DRX1N
(SSTXN)
DRX1N
(SSRXN)
URX2P
(LN1TXP)
URX2P
(LN1TXP)
DRX2P
DRX2N
DRX2P
DRX2N
URX2N
(LN1TXN)
URX2N
(LN1TXN)
UTX2P
(LN1RXP)
UTX2P
(LN1RXP)
DTX2P
DTX2N
DTX1P
DTX1N
DTX2P
DTX2N
DTX1P
DTX1N
UTX2N
(LN1RXN)
UTX2N
(LN1RXN)
H
H
H
L
L
UTX1P
(LN0RXP)
UTX1P
(LN0RXP)
UTX1N
(LN0RXN)
UTX1N
(LN0RXN)
URX1P
(LN0RXP)
URX1P
(LN0RXP)
DRX1P
DRX1N
DRX1P
DRX1N
URX1N
(LN0RXN)
URX1N
(LN0RXN)
28
版权 © 2018, Texas Instruments Incorporated
TUSB1044
www.ti.com.cn
ZHCSHJ2C –FEBRUARY 2018–REVISED OCTOBER 2018
表 4. INPUT to OUTPUT Mapping (接下页)
SWAP = L
From
SWAP = H
From
From
To
From
To
Rx EQ
Control
PINS
Rx EQ
Control
PINS
DIR1
PIN
DIR0 CTL1
CTL0
PIN
FLIP
PIN
Input
PIN
Output
PIN
Input
PIN
Output
PIN
PIN
PIN
URX2P
(LN0RXP)
URX2P
(LN0RXP)
DEQ[1:0]
DEQ[1:0]
UEQ[1:0]
UEQ[1:0]
UEQ[1:0]
UEQ[1:0]
DEQ[1:0]
DEQ[1:0]
UEQ[1:0]
UEQ[1:0]
DEQ[1:0]
DEQ[1:0]
UEQ[1:0]
UEQ[1:0]
DEQ[1:0]
DEQ[1:0]
UEQ[1:0]
UEQ[1:0]
DEQ[1:0]
DEQ[1:0]
DEQ[1:0]
DEQ[1:0]
UEQ[1:0]
UEQ[1:0]
DRX2P
DRX2N
DEQ[1:0]
DEQ[1:0]
UEQ[1:0]
UEQ[1:0]
UEQ[1:0]
UEQ[1:0]
DEQ[1:0]
DEQ[1:0]
UEQ[1:0]
UEQ[1:0]
DEQ[1:0]
DEQ[1:0]
UEQ[1:0]
UEQ[1:0]
DEQ[1:0]
DEQ[1:0]
UEQ[1:0]
UEQ[1:0]
DEQ[1:0]
DEQ[1:0]
DEQ[1:0]
DEQ[1:0]
UEQ[1:0]
UEQ[1:0]
DRX2P
DRX2N
URX2N
(LN0RXN)
URX2N
(LN0RXN)
UTX2P
(LN0RXP)
UTX2P
(LN0RXP)
DTX2P
DTX2N
DTX1P
DTX1N
DTX2P
DTX2N
DTX1P
DTX1N
UTX2N
(LN0RXN)
UTX2N
(LN0RXN)
H
H
H
H
H
L
H
H
H
UTX1P
(LN0RXP)
UTX1P
(LN0RXP)
UTX1N
(LN0RXN)
UTX1N
(LN0RXN)
URX1P
(LN0TXP)
URX1P
(LN0TXP)
DRX1P
DRX1N
UTX2P
UTX2N
DRX1P
DRX1N
UTX2P
UTX2N
URX1N
(LN0TXN)
URX1N
(LN0TXN)
DTX2P
(SSRXP)
DTX2P
(SSTXP)
DTX2N
(SSRXN)
DTX2N
(SSTXN)
DRX2P
(SSTXP)
DRX2P
(SSRXP)
URX2P
URX2N
URX2P
URX2N
DRX2N
(SSTXN)
DRX2N
(SSRXN)
H
H
L
DTX1P
(LN0RXP)
DTX1P
(LN0RXP)
UTX1P
UTX1N
UTX1P
UTX1N
DTX1N(LN0R
XN)
DTX1N(LN0R
XN)
DRX1P
(LN0TXP)
DRX1P
(LN0TXP)
URX1P
URX1N
URX1P
URX1N
DRX1N
(LN0TXN)
DRX1N
(LN0TXN)
DTX1P
(SSRXP)
DTX1P
(SSSXP)
UTX1P
UTX1N
UTX1P
UTX1N
DTX1N
(SSRXN)
DTX1N
(SSSXN)
DRX1P
(SSTXP)
DRX1P
(SSRXP)
URX1P
URX1N
URX1P
URX1N
DRX1N
(SSTXN)
DRX1N
(SSRXN)
H
H
H
URX2P
(LN0TXP)
URX2P
(LN0TXP)
DRX2P
DRX2N
DRX2P
DRX2N
URX2N
(LN0TXN)
URX2N
(LN0TXN)
UTX2P
(LN0RXP)
UTX2P
(LN0RXP)
DTX2P
DTX2N
DTX2P
DTX2N
UTX2N
(LN0RXN)
UTX2N
(LN0RXN)
版权 © 2018, Texas Instruments Incorporated
29
TUSB1044
ZHCSHJ2C –FEBRUARY 2018–REVISED OCTOBER 2018
www.ti.com.cn
7.4.2 Device Configuration in I2C Mode
The TUSB1044 is in I2C mode when I2C_EN is equal to “1”. The same configurations defined in GPIO mode are
also available in I2C mode. The TUSB1044 USB3.1, DisplayPort, and custom Alternate Mode configuration is
controlled based on 表 5. The AUXP/N to SBU1/2 mapping control is based on 表 5.
表 5. I2C Configuration Control
Registers
CTLSEL1
VESA DisplayPort Alt Mode
DFP_D Configuration
TUSB1044 Configuration
DIRSEL1
DIRSEL0
CTLSEL0
FLIPSEL
USB + DisplayPort Alternate Mode (Source Side)
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
L
Power Down
–
Power Down
–
L
H
H
L
One Port USB 3.1 - No Flip
One Port USB 3.1 – With Flip
4 Lane DP - No Flip
4 Lane DP – With Flip
–
L
H
L
–
H
H
C and E
C and E
L
H
One Port USB 3.1 + 2 Lane
DP- No Flip
L
L
L
L
H
H
H
H
L
D and F
D and F
One Port USB 3.1 + 2 Lane
DP– With Flip
H
USB + DisplayPort Alternate Mode (Sink Side)
L
L
L
L
L
L
H
H
H
H
H
H
L
L
L
L
L
H
L
Power Down
–
Power Down
–
L
H
H
L
One Port USB 3.1 - No Flip
One Port USB 3.1 – With Flip
4 Lane DP - No Flip
4 Lane DP – With Flip
–
L
H
L
–
H
H
C and E
C and E
L
H
One Port USB 3.1 + 2 Lane
DP- No Flip
L
L
H
H
H
H
H
H
L
D and F
D and F
One Port USB 3.1 + 2 Lane
DP– With Flip
H
USB + Custom Alternate Mode (Source Side)
H
H
H
H
L
L
L
L
L
L
L
L
L
L
L
H
L
Power Down
–
–
–
–
Power Down
H
H
One Port USB 3.1 - No Flip
One Port USB 3.1 – With Flip
H
4 Channel Custom Alt Mode -
No Flip
H
H
L
L
H
H
L
L
L
–
–
4 Channel Custom Alt Mode–
With Flip
H
One Port USB 3.1 + 2
Channel Custom Alt Mode-
No Flip
H
H
L
L
H
H
H
H
L
–
–
One Port USB 3.1 + 2
Channel Custom Alt Mode –
With Flip
H
USB + Custom Alternate Mode (Sink Side)
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
H
L
Power Down
–
–
–
–
Power Down
H
H
One Port USB 3.1 - No Flip
One Port USB 3.1 – With Flip
H
4 Channel Custom Alt Mode -
No Flip
H
H
H
L
L
–
30
版权 © 2018, Texas Instruments Incorporated
TUSB1044
www.ti.com.cn
ZHCSHJ2C –FEBRUARY 2018–REVISED OCTOBER 2018
表 5. I2C Configuration Control (接下页)
Registers
CTLSEL1
VESA DisplayPort Alt Mode
DFP_D Configuration
TUSB1044 Configuration
DIRSEL1
DIRSEL0
CTLSEL0
FLIPSEL
4 Channel Custom Alt Mode–
With Flip
H
H
H
L
H
–
–
One Port USB 3.1 + 2
Channel Custom Alt Mode-
No Flip
H
H
H
H
H
H
H
L
One Port USB 3.1 + 2
Channel Custom Alt Mode –
With Flip
H
H
–
表 6. I2C AUXP/N to SBU1/2 Mapping
Registers
AUX_SBU_OVR
CTLSEL1
FLIPSEL
Mapping
AUXp -> SBU1
AUXn -> SBU2
00
H
L
AUXp -> SBU2
AUXn -> SBU1
00
00
01
H
L
H
X
X
Open
AUXp -> SBU1
AUXn -> SBU2
X
AUXp -> SBU2
AUXn -> SBU1
10
11
X
X
X
X
Open
7.4.3 DisplayPort Mode
The TUSB1044 supports up to four DisplayPort lanes at datarates up to 8.1Gbps. TUSB1044 can be enabled for
DisplayPort through GPIO control or through I2C register control. When in GPIO mode, DisplayPort is controlled
based on 表 2. When not in GPIO mode, enable of DisplayPort functionality is controlled through I2C registers.
7.4.4 Custom Alternate Mode
The TUSB1044 supports up to two lanes (or 4 channels) of custom Alternate Mode at datarates up to 10 Gbps.
TUSB1044 can be enabled for custom Alternate Mode through GPIO control or through I2C register control.
Custom Alternate mode is not supported for GPIO mode which has AUX snoop disabled. When in GPIO mode,
custom Alternate Mode is controlled based on 表 2. When not in GPIO mode, enable of custom Alternate Mode
functionality is controlled through I2C registers. In I2C mode, the operation of this mode requires leaving
AUX_SNOOP_DISABLE register 13h bit 7 at 0.
7.4.5 Linear EQ Configuration
TUSB1044 receiver lanes have controls for receiver equalization for upstream and downstream facing ports. The
receiver equalization gain value can be controlled either through I2C registers or through GPIOs. 表 7 details the
gain value for each available combination when TUSB1044 is in GPIO mode. These same options are also
available per channel and for upstream and downstream facing ports in I2C mode by updating registers
URX[2:1]EQ_SEL, UTX[2:1]EQ_SEL, DRX[2:1]EQ_SEL, and DTX[2:1]EQ_SEL.
表 7. TUSB1044 Receiver Equalization GPIO Control
Downstream Facing Ports using 1100mV linearity
Upstream Facing Port using 1100mV linearity setting
setting
EQ
Setting
#
DEQ1
pin
Level
DEQ0
pin
Level
EQ GAIN
5GHz
(dB)
EQ GAIN
4.05GHz
(dB)
UEQ1
pin
Level
UEQ0
pin
Level
EQ GAIN
5GHz
(dB)
EQ GAIN
4.05GHz
(dB)
0
1
2
0
0
0
0
R
F
-2.1
0
-1.4
0.4
1.7
0
0
0
0
R
F
-4.4
-2.2
0.7
-3.3
-1.5
0.0
1.5
版权 © 2018, Texas Instruments Incorporated
31
TUSB1044
ZHCSHJ2C –FEBRUARY 2018–REVISED OCTOBER 2018
www.ti.com.cn
表 7. TUSB1044 Receiver Equalization GPIO Control (接下页)
Downstream Facing Ports using 1100mV linearity
setting
Upstream Facing Port using 1100mV linearity setting
3
4
0
R
R
R
R
F
F
F
F
1
1
0
3.0
4.0
5.0
5.9
6.7
7.4
8.0
8.5
9.0
9.4
9.8
10.1
10.5
3.2
4.1
0
R
R
R
R
F
F
F
F
1
1
0
0.9
1.9
3.0
3.8
4.7
5.4
6.0
6.5
7.1
7.5
7.9
8.3
8.6
1.4
2.4
3.5
4.3
5.2
6.0
6.6
7.2
7.7
8.1
8.6
9.0
9.4
5
R
F
1
5.2
R
F
1
6
6.1
7
6.9
8
0
7.7
0
9
R
F
1
8.3
R
F
1
10
11
12
13
14
15
8.8
9.4
0
9.8
0
1
R
F
1
10.3
10.6
11.0
1
R
F
1
1
1
1
1
7.4.6 Adjustable VOD Linear Range and DC Gain
The CFG0 and CFG1 pins can be used to adjust the TUSB1044 differential output voltage (VOD) swing linear
range and receiver equalization DC gain for both downstream and upstream data path directions. 表 8 details the
available options.
表 8. VOD Linear Range and DC Gain
Downstream
VOD Linear
Range
Upstream
VOD Linear
Range
Downstream
DC Gain
(dB)
Setting
#
CFG1 pin
Level
CFG0 pin
Level
Upstream
DC Gain (dB)
(mVpp)
(mVpp)
0
1
0
0
0
R
F
1
1
0
900
900
900
900
0
1
2
0
0
0
900
900
3
0
1
1
900
900
4
R
R
R
R
F
F
F
F
1
0
0
0
1100
1100
5
R
F
1
1
0
1100
1100
6
0
1
1100
1100
7
2
2
1100
1100
8
0
Reserved
Reserved
0
Reserved
Reserved
0
Reserved
Reserved
1300
Reserved
Reserved
1300
9
R
F
1
10
11
12
13
14
15
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
0
1
R
F
1
1
1
32
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TUSB1044
www.ti.com.cn
ZHCSHJ2C –FEBRUARY 2018–REVISED OCTOBER 2018
7.4.7 USB3.1 Modes
The TUSB1044 monitors the physical layer conditions like receiver termination, electrical idle, LFPS, and
SuperSpeed signaling rate to determine the state of the USB3.1 interface. Depending on the state of the USB
3.1 interface, the TUSB1044 can be in one of four primary modes of operation when USB 3.1 is enabled (CTL0 =
H or CTLSEL0 = 1b1): Disconnect, U2/U3, U1, and U0.
The Disconnect mode is the state in which TUSB1044 has not detected far-end termination on both upstream
facing port (UFP) or downstream facing port (DFP). The disconnect mode is the lowest power mode of each of
the four modes. The TUSB1044 remains in this mode until far-end receiver termination has been detected on
both UFP and DFP. The TUSB1044 immediately exits this mode and enter U0 once far-end termination is
detected.
Once in U0 mode, the TUSB1044 redrives all traffic received on UFP and DFP. U0 is the highest power mode of
all USB3.1 modes. The TUSB1044 remains in U0 mode until electrical idle occurs on both UFP and DFP. Upon
detecting electrical idle, the TUSB1044 immediately transitions to U1.
The U1 mode is the intermediate mode between U0 mode and U2/U3 mode. In U1 mode, the TUSB1044 UFP
and DFP receiver termination remain enabled. The UFP and DFP transmitter DC common mode is maintained.
The power consumption in U1 is similar to power consumption of U0.
Next to the disconnect mode, the U2 and U3 mode is next lowest power state. While in this mode, the
TUSB1044 periodically performs far-end receiver detection. Anytime the far-end receiver termination is not
detected on either UFP or DFP, the TUSB1044 leaves the U2 and U3 mode and transition to the Disconnect
mode. It also monitors for a valid LFPS. Upon detection of a valid LFPS, the TUSB1044 immediately transitions
to the U0 mode. In U2 and U3 mode, the TUSB1044 receiver terminations remains enabled, but the TX DC
common mode voltage is not maintained.
When SLP_S0# is asserted low, it disables Receiver Detect functionality. While SLP_S0# is low and TUSB1044
is in U2 and U3, TUSB1044 disables LOS and LFPS detection circuitry and RX termination for both channels
remains enabled. This allows even lower TUSB1044 power consumption while in the U2 and U3 mode. Once
SLP_S0# is asserted high, the TUSB1044 will again start performing far-end receiver detection as well as
monitor LFPS so it can know when to exit the U2 and U3 mode.
When SLP_S0# is asserted low and the TUSB1044 is in Disconnect mode, the TUSB1044 will remain in
Disconnect mode and never perform far-end receiver detection. This allows even lower TUSB1044 power
consumption while in the Disconnect mode. Once SLP_S0# is asserted high, the TUSB1044 will again start
performing far-end receiver detection so it can know when to exit the Disconnect mode.
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7.5 Programming
For further programmability, the TUSB1044 can be controlled using I2C. The SCL and SDA terminals are used
for I2C clock and I2C data respectively.
表 9. I2C Slave Address
TUSB1044 I2C Slave Address
UEQ1/A1
Pin Level
UEQ0/A0
Pin Level
Bit 0
(W/R)
Bit 7 (MSB)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
0
0
0
R
F
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0
0
R
R
R
R
F
F
F
F
1
0
R
F
1
0
R
F
1
0
1
R
F
1
1
1
7.5.1 Use The Following Procedure to Write to TUSB1044 I2C Registers:
1. The master initiates a write operation by generating a start condition (S), followed by the TUSB1044 7-bit
address and a zero-value “W/R” bit to indicate a write cycle .
2. The TUSB1044 acknowledges the address cycle.
3. The master presents the sub-address (I2C register within TUSB10444) to be written, consisting of one byte of
data, MSB-first.
4. The TUSB1044 acknowledges the sub-address cycle.
5. The master presents the first byte of data to be written to the I2C register.
6. The TUSB1044 acknowledges the byte transfer.
7. The master may continue presenting additional bytes of data to be written, with each byte transfer completing
with an acknowledge from the TUSB1044.
8. The master terminates the write operation by generating a stop condition (P).
7.5.2 Use The Following Procedure to Read the TUSB1044 I2C Registers:
1. The master initiates a read operation by generating a start condition (S), followed by the TUSB1044 7-bit
address and a one-value “W/R” bit to indicate a read cycle
2. The TUSB1044 acknowledges the address cycle.
3. The TUSB1044 transmit the contents of the memory registers MSB-first starting at register 00h or last read
sub-address+1. If a write to the T I2C register occurred prior to the read, then the TUSB1044 shall start at
the sub-address specified in the write.
4. The TUSB1044 shall wait for either an acknowledge (ACK) or a not-acknowledge (NACK) from the master
after each byte transfer; the I2C master acknowledges reception of each data byte transfer.
5. If an ACK is received, the TUSB1044 transmits the next byte of data.
6. The master terminates the read operation by generating a stop condition (P).
34
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7.5.3 Use The Following Procedure for Setting a Starting Sub-Address for I2C Reads:
1. The master initiates a write operation by generating a start condition (S), followed by the TUSB1044 7-bit
address and a zero-value “W/R” bit to indicate a write cycle.
2. The TUSB1044 acknowledges the address cycle.
3. The master presents the sub-address (I2C register within TUSB1044) to be written, consisting of one byte of
data, MSB-first.
4. The TUSB1044 acknowledges the sub-address cycle.
5. The master terminates the write operation by generating a stop condition (P).
注
If no sub-addressing is included for the read procedure, and reads start at register offset
00h and continue byte by byte through the registers until the I2C master terminates the
read operation. If a I2C address write occurred prior to the read, then the reads start at the
sub-address specified by the address write.
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7.6 Register Maps
7.6.1 TUSB1044 Registers
Table 10 lists the memory-mapped registers for the TUSB1044. All register offset addresses not listed in
Table 10 should be considered as reserved locations and the register contents should not be modified.
Table 10. TUSB1044 Registers
Offset
Ah
Acronym
Register Name
Section
Go
General_1
General_2
General_3
UFP2_EQ
General Registers 1
General Registers 2
General Registers 3
UFP2 EQ Control
Bh
Go
Ch
Go
10h
11h
12h
13h
1Bh
20h
21h
22h
23h
Go
UFP1_EQ
UFP1 EQ Control
Go
DisplayPort_1
DisplayPort_2
SOFT_RESET
DFP2_EQ
AUX Snoop Status
Go
DP Lane Enable/Disable Control
I2C and DPCD Soft Resets
DFP2 EQ Control
Go
Go
Go
DFP1_EQ
DFP1 EQ Control
Go
USB3_MISC
USB3_LOS
Misc USB3 Controls
USB3 LOS Threshold Controls
Go
Go
Complex bit access types are encoded to fit into small table cells. Table 11 shows the codes that are used for
access types in this section.
Table 11. TUSB1044 Access Type Codes
Access Type
Code
Description
Read Type
R
R
Read
RH
H
R
Set or cleared by hardware
Read
Write Type
H
H
Set or cleared by hardware
Write
W
W
WSH
H
W
Set or cleared by hardware
Write
WS
Reset or Default Value
-n
Value after reset or the default value
Register Array Variables
i,j,k,l,m,n
When these variables are used in a register name,
an offset, or an address, they refer to the value of a
register array where the register is part of a group
of repeating registers. The register groups form a
hierarchical structure and the array is represented
with a formula.
y
When this variable is used in a register name, an
offset, or an address it refers to the value of a
register array.
36
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7.6.1.1 General_1 Register (Offset = Ah) [reset = 1h]
General_1 is shown in Figure 23 and described in Table 12.
Return to Summary Table.
Figure 23. General_1 Register
7
6
5
4
3
2
1
0
RESERVED
RESERVED
SWAP_SEL
EQ_OVERRID HPDIN_OVER
FLIP_SEL
CTLSEL[1:0]
R/W-1h
E
RIDE
R-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
Table 12. General_1 Register Field Descriptions
Bit
Field
Type
Reset
Description
Reserved
Reserved
7
RESERVED
RESERVED
SWAP_SEL
R
0h
6
5
R/W
R/W
0h
0h
Setting this field performs
channels.
a global direction swap on all the
0h = Channel directions and EQ settings are in normal mode
1h = Reverse all channel directions and EQ settings for the input
ports.
4
EQ_OVERRIDE
R/W
0h
Setting this field will allow software to use EQ settings from registers
instead of value sampled from pins.
0h = EQ settings based on sampled state of EQ pins.
1h = EQ settings based on programmed value of each of the EQ
registers.
3
2
HPDIN_OVERRIDE
FLIP_SEL
R/W
R/W
R/W
0h
0h
1h
Overrides HPDIN pin state.
0h = HPD_IN based on HPD_IN pin.
1h = HPD_IN high.
FLIPSEL
0h = Normal Orientation
1h = Flip orientation.
1-0
CTLSEL[1:0]
Controls the DP and USB modes.
0h = Disabled. All RX and TX for USB3 and DisplayPort are
disabled.
1h = USB3.1 only enabled.
2h = Four Lanes of DisplayPort enabled.
3h = USB3.1 and Two DisplayPort Lanes.
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7.6.1.2 General_2 Register (Offset = Bh) [reset = 0h]
General_2 is shown in Figure 24 and described in Table 13.
Return to Summary Table.
Figure 24. General_2 Register
7
6
5
4
3
2
1
0
RESERVED
R-0h
CH_SWAP_SEL
R/W-0h
Table 13. General_2 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-4
3-0
RESERVED
R
0h
Reserved
CH_SWAP_SEL
R/W
0h
Swaps direction (TX to Rx and Rx to Tx) and EQ settings of
individual channels. Channels are numbered from 0 to 3. 1 bit per
lane.
0h = Channel and EQ settings normal.
1h = Reverse channel direction and EQ setting.
7.6.1.3 General_3 Register (Offset = Ch) [reset = 0h]
General_3 is shown in Figure 25 and described in Table 14.
Return to Summary Table.
Figure 25. General_3 Register
7
6
5
4
3
2
1
0
RESERVED
VOD_DCGAIN
_OVERRIDE
VOD_DCGAIN_SEL
DIR_SEL
R/W-0h
R-0h
R/W-0h
R/W-0h
Table 14. General_3 Register Field Descriptions
Bit
Field
RESERVED
Type
Reset
Description
7
R
0h
Reserved
6
VOD_DCGAIN_OVERRID R/W
E
0h
Setting of this field will allow software to use VOD linearity range and
DC gain settings from registers instead of value sampled from pins
0h = VOD linearity and DC gain settings based on sampled CFG[2:1]
pins.
1h = EQ settings based on programmed value of each VOD linearity
and DC Gain registers.
5-2
VOD_DCGAIN_SEL
R/W
0h
Field selects VOD linearity range and DC gain for all the channels
and in all directions. When VOD_DCGAIN_OVERRIDE = 0b, this
field reflects the sampled state of CFG[1:0] pins. When
VOD_DCGAIN_OVERRIDE = 1b software can change the VOD
linearity range and DC gain for all the channels and in all directions
based on value written to this field. Each CFG is a 2-bit value. The
register-to-CFG1/0 mapping is: [5:2] = {CFG1[1:0], CFG0[1:0]} where
CFGx[1:0] mapping is:
0h = 0
1h = R
2h = F
3h = 1
38
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Table 14. General_3 Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
1-0
DIR_SEL
R/W
0h
Sets the operation mode.
0h = USB + DP Alt Mode Source
1h = USB + DP Alt Mode Sink.
2h = USB + Custom Alt Mode Source
3h = USB + Custom Alt Mode Sink.
7.6.1.4 UFP2_EQ Register (Offset = 10h) [reset = 0h]
UFP2_EQ is shown in Figure 26 and described in Table 15.
Return to Summary Table.
Figure 26. UFP2_EQ Register
7
6
5
4
3
2
1
0
UTX2EQ_SEL
R/W-0h
URX2EQ_SEL
R/W-0h
Table 15. UFP2_EQ Register Field Descriptions
Bit
Field
Type
Reset
Description
7-4
UTX2EQ_SEL
R/W
0h
Field selects EQ for UTX2P/N pins. When EQ_OVERRIDE = 0b, this
field reflects the sampled state of UEQ[1:0] pins. When
EQ_OVERRIDE = 1b, software can change the EQ setting for
UTX2P/N pins based on value written to this field.
3-0
URX2EQ_SEL
R/W
0h
Field selects EQ for URX2P/N pins. When EQ_OVERRIDE = 0b, this
field reflects the sampled state of UEQ[1:0] pins. When
EQ_OVERRIDE = 1b, software can change the EQ setting for
URX2P/N pins based on value written to this field.
7.6.1.5 UFP1_EQ Register (Offset = 11h) [reset = 0h]
UFP1_EQ is shown in Figure 27 and described in Table 16.
Return to Summary Table.
Figure 27. UFP1_EQ Register
7
6
5
4
3
2
1
0
UTX1EQ_SEL
R/W-0h
URX1EQ_SEL
R/W-0h
Table 16. UFP1_EQ Register Field Descriptions
Bit
Field
Type
Reset
Description
7-4
UTX1EQ_SEL
R/W
0h
Field selects EQ for UTX1P/N pins. When EQ_OVERRIDE = 0b, this
field reflects the sampled state of UEQ[1:0] pins. When
EQ_OVERRIDE = 1b, software can change the EQ setting for
UTX1P/N pins based on value written to this field.
3-0
URX1EQ_SEL
R/W
0h
Field selects EQ for URX1P/N pins. When EQ_OVERRIDE = 0b, this
field reflects the sampled state of UEQ[1:0] pins. When
EQ_OVERRIDE = 1b, software can change the EQ setting for
URX1P/N pins based on value written to this field.
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7.6.1.6 DisplayPort_1 Register (Offset = 12h) [reset = 0h]
DisplayPort_1 is shown in Figure 28 and described in Table 17.
Return to Summary Table.
Figure 28. DisplayPort_1 Register
7
6
5
4
3
2
1
0
RESERVED
R-0h
SET_POWER_STATE
RH-0h
LANE_COUNT_SET
RH-0h
Table 17. DisplayPort_1 Register Field Descriptions
Bit
Field
Type
Reset
Description
7
RESERVED
R
0h
Reserved
6-5
SET_POWER_STATE
RH
0h
This field represents the snooped value of the AUX write to DPCD
address 0x00600. When AUX_SNOOP_DISABLE 0b, the
=
enable/disable of DP lanes based on the snooped value. When
AUX_SNOOP_DISABLE = 1b, then DP lane enable/disable are
determined by state of DPx_DISABLE registers, where x = 0, 1, 2, or
3. This field is reset to 0h by hardware when CTLSEL1 changes
from a 1b to a 0b.
4-0
LANE_COUNT_SET
RH
0h
This field represents the snooped value of AUX write to DPCD
address 0x00101 register. When AUX_SNOOP_DISABLE = 0b, DP
lanes enabled specified by the snoop value. Unused DP lanes will
be disabled to save power. When AUX_SNOOP_DISABLE = 1b,
then DP lanes enable/disable are determined by DPx_DISABLE
registers, where x = 0, 1, 2, or 3. This field is reset to 0h by
hardware when CTLSEL1 changes from a 1b to a 0b.
40
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7.6.1.7 DisplayPort_2 Register (Offset = 13h) [reset = 0h]
DisplayPort_2 is shown in Figure 29 and described in Table 18.
Return to Summary Table.
Figure 29. DisplayPort_2 Register
7
6
5
4
3
2
1
0
AUX_SNOOP_
DISABLE
RESERVED
AUX_SBU_OVR
DP3_DISABLE DP2_DISABLE DP1_DISABLE DP0_DISABLE
R/W-0h
R-0h
R/W-0h
R/W-0h R/W-0h R/W-0h R/W-0h
Table 18. DisplayPort_2 Register Field Descriptions
Bit
Field
Type
Reset
Description
7
AUX_SNOOP_DISABLE
R/W
0h
Controls whether DP lanes are enabled based on AUX snooped
value or registers.
0h = AUX snoop enabled.
1h = AUX snoop disabled. DP lanes are controlled by registers.
6
RESERVED
R
0h
0h
Reserved
5-4
AUX_SBU_OVR
R/W
This field overrides the AUXP/N to SBU1/2 connect and disconnect
based on CTL1 and FLIP. Changing this field to 1b will allow traffic
to pass through AUX to SBU regardless of the state of CTLSEL1
and FLIPSEL register.
0h = AUX to SBU connection determined by CTLSEL1 and FLIPSEL
1h = AUXP -> SBU1 and AUXN -> SBU2
2h = AUXP -> SBU2 and AUXN -> SBU1
3h = AUX to SBU open.
3
2
1
0
DP3_DISABLE
DP2_DISABLE
DP1_DISABLE
DP0_DISABLE
R/W
R/W
R/W
R/W
0h
0h
0h
0h
When AUX_SNOOP_DISABLE = 1b, this field can be used to enable
or disable DP lane 3. When AUX_SNOOP_DISABLE = 0b, changes
to this field will have no effect on lane 3 functionality.
0h = DP Lane 3 enabled.
1h = DP Lane 3 disabled.
When AUX_SNOOP_DISABLE = 1b, this field can be used to enable
or disable DP lane 2. When AUX_SNOOP_DISABLE = 0b, changes
to this field will have no effect on lane 2 functionality.
0h = DP Lane 2 enabled.
1h = DP Lane 2 disabled.
When AUX_SNOOP_DISABLE = 1b, this field can be used to enable
or disable DP lane 1. When AUX_SNOOP_DISABLE = 0b, changes
to this field will have no effect on lane 1 functionality.
0h = DP Lane 1 enabled.
1h = DP Lane 1 disabled.
When AUX_SNOOP_DISABLE = 1b, this field can be used to enable
or disable DP lane 0. When AUX_SNOOP_DISABLE = 0b, changes
to this field will have no effect on lane 0 functionality.
0h = DP Lane 0 enabled.
1h = DP Lane 0 disabled.
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7.6.1.8 SOFT_RESET Register (Offset = 1Bh) [reset = 0h]
SOFT_RESET is shown in Figure 30 and described in Table 19.
Return to Summary Table.
Figure 30. SOFT_RESET Register
7
6
5
4
3
2
1
0
I2C_RST
RH/WS-0h
DPCD_RST
RH/WS-0h
RESERVED
R-0h
Table 19. SOFT_RESET Register Field Descriptions
Bit
Field
Type
Reset
Description
7
I2C_RST
RH/WS
0h
Resets I2C registers to default values. This field is self-clearing.
Resets DPCD registers to default values. This field is self-clearing.
Reserved
6
DPCD_RST
RESERVED
RH/WS
R
0h
0h
5-0
7.6.1.9 DFP2_EQ Register (Offset = 20h) [reset = 0h]
DFP2_EQ is shown in Figure 31 and described in Table 20.
Return to Summary Table.
Figure 31. DFP2_EQ Register
7
6
5
4
3
2
1
0
DTX2EQ_SEL
R/W-0h
DRX2EQ_SEL
R/W-0h
Table 20. DFP2_EQ Register Field Descriptions
Bit
Field
Type
Reset
Description
7-4
DTX2EQ_SEL
R/W
0h
Field selects EQ for DTX2P/N pins. When EQ_OVERRIDE = 0b, this
field reflects the sampled state of DEQ[1:0] pins. When
EQ_OVERRIDE = 1b, software can change the EQ setting for
DTX2P/N pins based on value written to this field.
3-0
DRX2EQ_SEL
R/W
0h
Field selects EQ for DRX2P/N pins. When EQ_OVERRIDE = 0b, this
field reflects the sampled state of DEQ[1:0] pins. When
EQ_OVERRIDE = 1b, software can change the EQ setting for
DRX2P/N pins based on value written to this field.
42
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7.6.1.10 DFP1_EQ Register (Offset = 21h) [reset = 0h]
DFP1_EQ is shown in Figure 32 and described in Table 21.
Return to Summary Table.
Figure 32. DFP1_EQ Register
7
6
5
4
3
2
1
0
DTX1EQ_SEL
R/W-0h
DRX1EQ_SEL
R/W-0h
Table 21. DFP1_EQ Register Field Descriptions
Bit
Field
Type
Reset
Description
7-4
DTX1EQ_SEL
R/W
0h
Field selects EQ for DTX1P/N pins. When EQ_OVERRIDE = 0b, this
field reflects the sampled state of DEQ[1:0] pins. When
EQ_OVERRIDE = 1b, software can change the EQ setting for
DTX1P/N pins based on value written to this field.
3-0
DRX1EQ_SEL
R/W
0h
Field selects EQ for DRX1P/N pins. When EQ_OVERRIDE = 0b, this
field reflects the sampled state of DEQ[1:0] pins. When
EQ_OVERRIDE = 1b, software can change the EQ setting for
DRX1P/N pins based on value written to this field.
7.6.1.11 USB3_MISC Register (Offset = 22h) [reset = 4h]
USB3_MISC is shown in Figure 33 and described in Table 22.
Return to Summary Table.
Figure 33. USB3_MISC Register
7
6
5
4
3
2
1
0
CM_ACTIVE
LFPS_EQ
U2U3_LFPS_D DISABLE_U2U
DFP_RXDET_INTERVAL
USB_COMPLIANCE_CTRL
EBOUNCE
3_RXDET
RH-0h
R/W-0h
R/W-0h
R/W-0h
R/W-1h
R/W-0h
Table 22. USB3_MISC Register Field Descriptions
Bit
Field
CM_ACTIVE
Type
Reset
Description
7
RH
0h
Compliance mode status.
0h = Not in USB3.1 compliance mode.
1h = In USB3.1 compliance mode.
6
LFPS_EQ
R/W
0h
Controls whether settings of EQ based on URX[2:1]EQ_SEL,
UTX[2:1]EQ_SEL, DRX[2:1]EQ_SEL, and DTX[2:1]EQ_SEL applies
to received LFPS signal.
0h = EQ set to zero when receiving LFPS
1h = EQ set by the related registers when receiving LFPS.
5
4
U2U3_LFPS_DEBOUNCE R/W
DISABLE_U2U3_RXDET R/W
DFP_RXDET_INTERVAL R/W
0h
0h
1h
Controls whether or not incoming LFPS is debounced or not.
0h = No debounce of LFPS before U2/U3 exit.
1h = 200us debounce of LFPS before U2/U3 exit.
Controls whether or not Rx.Detect is performed in U2/U3 state.
0h = Rx.Detect in U2/U3 enabled.
1h = Rx.Detect in U2/U3 disabled.
3-2
This field controls the Rx.Detect interval for the downstream facing
port (DTX1P/N and DTX2P/N).
0h = 8ms
1h = 12ms
2h = Reserved
3h = Reserved.
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Table 22. USB3_MISC Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
1-0
USB_COMPLIANCE_CTR R/W
L
0h
Controls whether compliance mode is determined by FSM or
register.
0h = Compliance mode determined by FSM.
1h = Compliance mode enabled in DFP direction.
2h = Compliance mode enabled in UFP direction.
3h = Compliance mode disabled.
7.6.1.12 USB3_LOS Register (Offset = 23h) [reset = 23h]
USB3_LOS is shown in Figure 34 and described in Table 23.
Return to Summary Table.
Figure 34. USB3_LOS Register
7
6
5
4
3
2
1
0
RESERVED
R-0h
CFG_LOS_HYST
R/W-4h
CFG_LOS_VTH
R/W-3h
Table 23. USB3_LOS Register Field Descriptions
Bit
Field
Type
Reset
Description
7-6
5-3
RESERVED
R
0h
Reserved
CFG_LOS_HYST
R/W
4h
Controls LOS hysteresis defined as 20 log (LOS de-assert
threshold/LOS assert threshold).
0h = 0.15 dB
1h = 0.85 dB
2h = 1.45 dB
3h = 2.00 dB
4h = 2.70 dB
5h = 3.00 dB
6h = 3.40 dB
7h = 3.80 dB
2-0
CFG_LOS_VTH
R/W
3h
Controls LOS assert threshold voltage
0h = 67 mV
1h = 72 mV
2h = 79 mV
3h = 85 mV
4h = 91 mV
5h = 97 mV
6h = 105 mV
7h = 112 mV
44
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TUSB1044
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ZHCSHJ2C –FEBRUARY 2018–REVISED OCTOBER 2018
8 Application and Implementation
注
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The TUSB1044 is a linear redriver designed specifically to compensate for intersymbol interference (ISI) jitter
caused by signal attenuation through a passive medium like PCB traces and cables. Because the TUSB1044
has four independent inputs, it can be optimized to correct ISI on all those seven inputs through 16 different
equalization choices. Placing the TUSB1044 between a USB3.1 Host/DisplayPort 1.4 GPU and a USB3.1 Type-
C receptacle can correct signal integrity issues resulting in a more robust system.
8.2 Typical Application
A
B
F
E
PCB Trace of Length XAB
PCB Trace of Length XEF
URX2P
RX2P
URX2N
UTX2P
RX2N
TX2P
DRX2P
DRX2N
UTX2N
TX2N
DTX2P
DTX2N
USB3.1/
DP1.4
Host
TUSB1044
DTX1N
DTX1P
UTX1N
TX1N
DRX1N
DRX1P
UTX1P
URX1N
URX1P
TX1P
RX1N
RX1P
PCB Trace of Length XCD
PCB Trace of Length XGH
G
H
C
图 35. TUSB1044 in a Host Application
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Typical Application (接下页)
8.2.1 Design Requirements
For this design example, use the parameters shown in 表 24.
表 24. Design Parameters
PARAMETER
A to B PCB trace length, XAB
C to D PCB trace length, XCD
E to F PCB trace length, XEF
G to H PCB trace length, XGH
PCB trace width
VALUE
8 inches (assuming 1 dB/inch at 5GHz).
8 inches (assuming 1 dB/inch at 5GHz).
1.5 inches (assuming 1 dB/inch at 5GHz).
1.5 inches (assuming 1 dB/inch at 5GHz).
4 mils
220 nF
3.3 V
AC-coupling capacitor (75 nF to 265 nF)
VCC supply (3 V to 3.6 V)
I2C Mode or GPIO Mode
I2C Mode.
3.3V I2C. Pull-up the I2C_EN pin to 3.3V with a 1K
ohm resistor.
1.8V or 3.3V I2C Interface
8.2.2 Detailed Design Procedure
A typical usage of the TUSB1044 device is shown in 图 36. The device can be controlled either through its GPIO
pins or through its I2C interface. In 图 36, a Type-C PD controller is used to configure the device through the I2C
interface. In I2C mode, the equalization settings for each receiver can be independently controlled through I2C
registers. For this reason, all of the equalization pins (UEQ[1:0] and DEQ[1:0]) can be left unconnected. If these
pins are left unconnected, the TUSB1044 7-bit I2C slave address is 12h because both UEQ1/A1 and UEQ0/A0
are at pin level "F". If a different I2C slave address is desired, UEQ1/A1 and UEQ0/A0 pins should be set to a
level which produces the desired I2C slave address.
Recent ECN (Engineering Change Notice) to the USB3.1 specification allows for AC-coupling capacitors
between USB receptacle and the USB3.1 receiver pins of a device/host/hub. The TUSB1044 does support the
additional AC-capacitor as depicted in 图 36 on pins DRX2P/N and DRX1P/N. This AC-coupling capacitor should
be no smaller than 297 nF. A value of 330 nF is recommended.
46
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TUSB1044
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ZHCSHJ2C –FEBRUARY 2018–REVISED OCTOBER 2018
3.3 V
10uF
100nF
100nF
100nF
100nF
220 nF
330 nF
DRX2P
DRX2N
DTX2P
DTX2N
RX2P
RX2N
TX2P
TX2N
URX2P
URX2N
UTX2P
UTX2N
330 nF
220 nF
220 nF
220 nF
220 nF
USB Type-C
Receptacle
A12
GND
URXP2
URXN2
VBUS
SBU1
DN1
220 nF
B1
B2
GND
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
TXP2
TXN2
100K
100 nF
100 nF
AUXP
AUXN
AUXP
AUXN
B3
B4
VBUS
CC2
100K
SBU1
SBU2
DP_PWR (3.3V)
B5
USB 3.1/DP1.4
Host
B6
DP2
DN2
2M
DP1
2M
B7
CC1
B8
SBU2
VBUS
VBUS
220 nF
220 nF
220 nF
220 nF
220 nF
DTX1N
TX1N
UTX1N
UTX1P
URX1N
B9
220 nF
330 nF
TXN1
TXP1
DTX1P
DRX1N
TX1P
RX1N
B10
B11
B12
URXN1
URXP1
GND
330 nF
DRX1P
RX1P
URX1P
3.3V
3.3V
GND
SWAP
I2C_EN
3.3V
3.3V
UEQ0/A0
UEQ1/A1
VI2C
3.3V
R
R
VIO_SEL
FLIP/SCL
CTL0/SDA
CTL1
CFG0
CFG1
DEQ0
Type-C
PD
Controller
3.3V
3.3V
3.3V
3.3V
SLP_S0#
HPDIN
DEQ1
3.3V
3.3V
DIR0
DIR1
GPIO Mode Only Connections
GPIO/I2C Mode Connections
图 36. Typical Application Circuit
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8.2.3 Application Curve
0
-5
-10
-15
-20
-25
-30
-35
-40
-45
-50
-55
-60
Length=12in, Width=6mil
Length=16in, Width=6mil
Length=20in, Width=6mil
Length=24in, Width=6mil
Length=4in, Width=4mil
Length=8in, Width=10mil
Length=8in, Width=6mil
0
2
4
6
8
10
12
14
16
Frequency (GHz)
D009
图 37. Insertion Loss of FR4 PCB Traces
48
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TUSB1044
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ZHCSHJ2C –FEBRUARY 2018–REVISED OCTOBER 2018
8.3 System Examples
8.3.1 USB 3.1 only (USB/DP Alternate Mode)
The TUSB1044 is in USB3.1 only when the CTL1 pin is low and CTL0 pin is high.
USB/DP Source (USB
USB/DP Sink
Only œ No Flip)
(USB Only œ No Flip)
D+/-
D+/-
TUSB1044
TUSB1044
URX2
UTX2
UTX1
URX1
DRX2
DTX2
DTX1
DRX1
Type-C Cable
TX1
RX1
URX2
UTX2
UTX1
URX1
DRX2
DTX2
DTX1
DRX1
TX1
RX1
USB/DP
Source
USB/DP
Sink
TX1
RX1
TX1
RX1
AUXp
AUXn
SBU1
SBU2
SBU2
SBU1
AUXn
AUXp
HPDIN
HPDIN
CTL
0 1
FLIP
0
CTL
1
FLIP
HPD
HPD
Control
CC1
CC2
CC1
CC2
PD Controller
PD Controller
Control
DIR1/DIR0/CTL1/CTL0/FLIP = L/L/L/H/L
DIR1/DIR0/CTL1/CTL0/FLIP = L/H/L/H/L
图 38. USB3.1 Only – No Flip
USB/DP Source (USB
USB/DP Sink
Only œ Flip)
(USB Only œ Flip)
D+/-
D+/-
TUSB1044
TUSB1044
URX2
UTX2
UTX1
URX1
DRX2
DTX2
DTX1
DRX1
Type-C Cable
RX2
TX2
RX2
TX2
TX1
URX2
UTX2
UTX1
URX1
DRX2
DTX2
DTX1
DRX1
USB/DP
Source
DP/USB
Sink
RX2
TX2
RX2
TX2
AUXp
AUXn
SBU1
SBU2
SBU2
SBU1
AUXn
AUXp
HPDIN
HPDIN
CTL
0 1
FLIP
0
CTL
1
FLIP
HPD
HPD
Control
CC1
CC2
CC1
CC2
PD Controller
PD Controller
Control
DIR1/DIR0/CTL1/CTL0/FLIP = L/L/L/H/H
DIR1/DIR0/CTL1/CTL0/FLIP = L/H/L/H/H
图 39. USB3.1 Only – With Flip
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System Examples (接下页)
8.3.2 USB3.1 and 2 lanes of DisplayPort
USB/DP Source
USB/DP Sink
(USB + 2 Lane DP œ No Flip)
(USB + 2 Lane DP œ No Flip)
D+/-
D+/-
USB/DP
Sink
TUSB1044
TUSB1044
URX2
UTX2
UTX1
URX1
DRX2
DTX2
DTX1
DRX1
Type-C Cable
ML0
ML1
TX1
RX1
RX2
TX2
TX1
RX1
TX1
RX1
RX2
TX2
URX2
UTX2
DRX2
DTX2
TX1
RX1
USB/DP
Source
DTX1
DRX1
UTX1
URX1
ML1
ML0
AUXp
AUXn
SBU1
SBU2
SBU2
SBU1
AUXn
AUXp
SBU1
SBU2
AUXp
SBU1
SBU2
AUXn
AUXp
AUXn
HPDIN
HPDIN
CTL
1
CTL
FLIP 0 1
FLIP 0
HPD
HPD
Control
CC1
CC2
CC1
CC2
PD Controller
PD Controller
Control
DIR1/DIR0/CTL1/CTL0/FLIP = L/H/H/H/L
DIR1/DIR0/CTL1/CTL0/FLIP = L/L/H/H/L
图 40. USB3.1 + 2 Lane DP – No Flip
USB/DP Source
USB/DP Sink
(USB + 2 Lane DP œ Flip)
(USB + 2 Lane DP œ Flip)
D+/-
D+/-
USB/DP
Sink
TUSB1044
TUSB1044
URX2
UTX2
UTX1
URX1
DRX2
DTX2
DTX1
DRX1
Type-C Cable
DRX2
DTX2
DTX1
DRX1
URX2
UTX2
UTX1
URX1
RX2
TX2
RX2
TX2
TX1
RX1
TX1
RX1
RX2
TX2
ML0
ML1
RX2
TX2
USB/DP
Source
ML1
ML0
SBU2
SBU1
AUXn
AUXp
AUXp
AUXn
SBU1
SBU2
SBU1
SBU2
AUXp
SBU1
SBU2
AUXn
AUXp
AUXn
HPDIN
HPDIN
CTL
1
CTL
FLIP 0 1
FLIP 0
HPD
HPD
Control
CC1
CC2
CC1
CC2
PD Controller
PD Controller
Control
DIR1/DIR0/CTL1/CTL0/FLIP = L/L/H/H/H
DIR1/DIR0/CTL1/CTL0/FLIP = L/H/H/H/H
图 41. USB 3.1 + 2 Lane DP – Flip
50
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TUSB1044
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System Examples (接下页)
8.3.3 DisplayPort Only
USB/DP Source
USB/DP Sink
(4 Lane DP œ No Flip)
(4 Lane DP œ No Flip)
D+/-
D+/-
USB/DP
Sink
TUSB1044
TUSB1044
URX2
UTX2
UTX1
URX1
DRX2
DTX2
DTX1
DRX1
Type-C Cable
URX2
UTX2
UTX1
URX1
DRX2
DTX2
DTX1
DRX1
ML0
ML1
ML2
ML3
RX2
TX2
TX1
RX1
TX1
RX1
RX2
TX2
ML3
ML2
USB/DP
Source
ML1
ML0
SBU2
SBU1
AUXn
AUXp
SBU1
SBU2
AUXp
SBU1
SBU2
AUXp
AUXn
SBU1
SBU2
AUXn
AUXp
AUXn
HPDIN
HPDIN
CTL
1
CTL
FLIP 0 1
FLIP 0
HPD
HPD
Control
CC1
CC2
CC1
CC2
PD Controller
PD Controller
Control
DIR1/DIR0/CTL1/CTL0/FLIP = L/H/H/L/L
DIR1/DIR0/CTL1/CTL0/FLIP = L/L/H/L/L
图 42. Four Lane DP – No Flip
USB/DP Source
USB/DP Sink
(4 Lane DP œ Flip)
(4 Lane DP œ Flip)
D+/-
D+/-
USB/DP
Sink
TUSB1044
TUSB1044
URX2
UTX2
UTX1
URX1
DRX2
DTX2
DTX1
DRX1
Type-C Cable
URX2
UTX2
UTX1
URX1
DRX2
DTX2
DTX1
DRX1
ML3
ML2
ML1
ML0
RX2
TX2
TX1
RX1
TX1
ML0
RX1
RX2
TX2
ML1
ML2
ML3
USB/DP
Source
SBU2
SBU1
AUXn
AUXp
AUXp
AUXn
SBU1
SBU2
SBU1
SBU2
AUXp
SBU1
SBU2
AUXn
AUXn
AUXp
HPDIN
HPDIN
CTL
1
CTL
FLIP 0 1
FLIP 0
HPD
HPD
Control
CC1
CC2
CC1
CC2
PD Controller
PD Controller
Control
DIR1/DIR0/CTL1/CTL0/FLIP = L/L/H/
L/H
DIR1/DIR0/CTL1/CTL0/FLIP = L/H/H/L/H
图 43. Four Lane DP – With Flip
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System Examples (接下页)
8.3.4 USB 3.1 only (USB/Custom Alternate Mode)
USB/Custom Source
USB/Custom Sink
(USB Only œ No Flip)
(USB Only œ No Flip)
D+/-
D+/-
TUSB1044
TUSB1044
URX2
UTX2
UTX1
URX1
DRX2
DTX2
DTX1
DRX1
Type-C Cable
TX1
RX1
URX2
UTX2
UTX1
URX1
DRX2
DTX2
DTX1
DRX1
TX1
RX1
USB/Custom
Source
USB/Custom
TX1
RX1
TX1
RX1
Sink
AUXp
AUXn
SBU1
SBU2
SBU2
SBU1
AUXn
AUXp
HPDIN
HPDIN
CTL
1
CTL
FLIP 0 1
FLIP 0
HPD
HPD
Control
CC1
CC2
CC1
CC2
PD Controller
PD Controller
Control
DIR1/DIR0/CTL1/CTL0/FLIP = H/L/L/H/L
DIR1/DIR0/CTL1/CTL0/FLIP = H/H/L/H/L
图 44. USB3.1 Only – No Flip
USB/Custom Source
USB/Custom Sink
(USB Only œ Flip)
(USB Only œ Flip)
D+/-
D+/-
TUSB1044
TUSB1044
URX2
UTX2
UTX1
URX1
DRX2
DTX2
DTX1
DRX1
Type-C Cable
RX2
TX2
RX2
URX2
UTX2
UTX1
URX1
DRX2
DTX2
DTX1
DRX1
TX2
USB/Custom
Source
Custom/USB
Sink
TX1
RX2
TX2
RX2
TX2
AUXp
AUXn
SBU1
SBU2
SBU2
SBU1
AUXn
AUXp
HPDIN
HPDIN
CTL
1
CTL
FLIP 0 1
FLIP 0
HPD
HPD
Control
CC1
CC2
CC1
CC2
PD Controller
PD Controller
Control
DIR1/DIR0/CTL1/CTL0/FLIP = H/L/L/H/H
DIR1/DIR0/CTL1/CTL0/FLIP = H/H/L/H/H
图 45. USB3.1 Only – With Flip
52
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TUSB1044
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ZHCSHJ2C –FEBRUARY 2018–REVISED OCTOBER 2018
System Examples (接下页)
8.3.5 USB3.1 and 1 Lane of Custom Alt Mode
USB/Custom Sink
USB/Custom Source
(USB + 1 Lane Custom œ No Flip)
(USB + 1 Lane Custom œ No Flip)
D+/-
D+/-
USB/Custom
TUSB1044
TUSB1044
Sink
URX2
UTX2
UTX1
URX1
DRX2
DTX2
DTX1
DRX1
Type-C Cable
RX2
TX2
TX1
RX1
RX2
TX2
TX1
RX1
TX1
RX1
RX2
TX2
URX2
UTX2
DRX2
DTX2
TX1
RX1
RX2
TX2
USB/Custom
Source
DTX1
DRX1
UTX1
URX1
SBU2
SBU1
AUXn
AUXp
AUXp
AUXn
SBU1
SBU2
SBU1
SBU2
AUXp
SBU1
SBU2
AUXn
AUXp
AUXn
HPDIN
HPDIN
CTL
1
CTL
FLIP 0 1
FLIP 0
HPD
HPD
Control
CC1
CC2
CC1
CC2
PD Controller
PD Controller
Control
DIR1/DIR0/CTL1/0/FLIP = H/L/H/H/L
DIR1/DIR0/CTL1/0/FLIP = H/H/H/H/L
图 46. USB3.1 + 1 Lane Custom Alt Mode – No Flip
USB/Custom Source
USB/Custom Sink
(USB + 1 Lane Custom œ Flip)
(USB + 1 Lane Custom œ Flip)
D+/-
D+/-
USB/Custom
Sink
TUSB1044
TUSB1044
URX2
UTX2
UTX1
URX1
DRX2
DTX2
DTX1
DRX1
Type-C Cable
DRX2
DTX2
DTX1
DRX1
URX2
UTX2
UTX1
URX1
RX2
TX2
TX1
RX1
RX2
TX2
TX1
RX1
TX1
RX1
RX2
TX2
TX1
RX1
RX2
TX2
USB/Custom
Source
SBU2
SBU1
AUXn
AUXp
AUXp
AUXn
SBU1
SBU2
SBU1
SBU2
AUXp
SBU1
SBU2
AUXn
AUXp
AUXn
HPDIN
HPDIN
CTL
1
CTL
FLIP 0 1
FLIP 0
CC1
CC2
HPD
CC1
CC2
HPD
PD Controller
PD Controller
Control
Control
DIR1/DIR0/CTL1/0/FLIP = H/L/H/H/H
DIR1/DIR0/CTL1/0/FLIP = H/H/H/H/H
图 47. USB 3.1 + 1 Lane Custom Alt. Mode – Flip
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System Examples (接下页)
8.3.6 USB3.1 and 2 Lane of Custom Alt Mode
USB/Custom Source
USB/Custom Sink
(USB + 2 Lane Custom œ No Flip)
(USB + 2 Lane Custom œ No Flip)
D+/-
D+/-
USB/Custom
Sink
TUSB1044
TUSB1044
URX2
UTX2
UTX1
URX1
DRX2
DTX2
DTX1
DRX1
Type-C Cable
LN0
LN1
TX1
RX1
RX2
TX2
TX1
RX1
TX1
RX1
RX2
TX2
URX2
UTX2
DRX2
TX1
RX1
DTX2
DTX1
DRX1
USB/Custom
Source
UTX1
URX1
LN1
LN0
AUXp
AUXn
SBU1
SBU2
SBU2
SBU1
AUXn
AUXp
SBU1
SBU2
AUXp
SBU1
SBU2
AUXn
AUXp
AUXn
HPDIN
HPDIN
CTL
1
CTL
FLIP 0 1
FLIP 0
HPD
HPD
Control
CC1
CC2
CC1
CC2
PD Controller
PD Controller
Control
DIR1/DIR0/CTL1/CTL0/FLIP = H/L/H/H/L
DIR1/DIR0/CTL1/CTL0/FLIP = H/H/H/H/L
图 48. Two Lane Custom Alternate Mode – No Flip
USB/Custom Source
USB/Custom Sink
(USB + 2 Lane Custom œ Flip)
(USB + 2 Lane Custom œ Flip)
D+/-
D+/-
USB/Custom
Sink
TUSB1044
TUSB1044
DRX2
URX2
UTX2
UTX1
URX1
DRX2
DTX2
DTX1
DRX1
Type-C Cable
URX2
UTX2
UTX1
URX1
RX2
TX2
LN1
LN0
RX2
TX2
TX1
RX1
TX1
RX1
RX2
TX2
LN0
LN1
DTX2
DTX1
DRX1
USB/Custom
Source
RX2
TX2
SBU2
SBU1
AUXn
AUXp
AUXp
AUXn
SBU1
SBU2
SBU1
SBU2
AUXp
SBU1
SBU2
AUXn
AUXp
AUXn
HPDIN
HPDIN
CTL
1
CTL
FLIP 0 1
FLIP 0
HPD
HPD
Control
CC1
CC2
CC1
CC2
PD Controller
PD Controller
Control
DIR1/DIR0/CTL1/CTL0/FLIP = H/L/H/H/H
DIR1/DIR0/CTL1/CTL0/FLIP = H/H/H/H/H
图 49. Two Lane Custom Alternate Mode – With Flip
54
版权 © 2018, Texas Instruments Incorporated
TUSB1044
www.ti.com.cn
ZHCSHJ2C –FEBRUARY 2018–REVISED OCTOBER 2018
System Examples (接下页)
8.3.7 USB3.1 and 4 Lane of Custom Alt Mode
USB/Custom Source
USB/Custom Sink
(4 Lane Custom œ No Flip)
(4 Lane Custom œ No Flip)
D+/-
D+/-
USB/Custom
Sink
TUSB1044
TUSB1044
URX2
UTX2
UTX1
URX1
DRX2
DTX2
DTX1
DRX1
Type-C Cable
URX2
UTX2
UTX1
URX1
DRX2
DTX2
DTX1
DRX1
LN0
LN1
LN2
LN3
RX2
TX2
TX1
RX1
TX1
RX1
RX2
TX2
LN3
LN2
USB/Custom
Source
LN1
LN0
SBU2
SBU1
AUXn
AUXp
SBU1
SBU2
AUXp
SBU1
SBU2
AUXp
AUXn
SBU1
SBU2
AUXn
AUXp
AUXn
HPDIN
HPDIN
CTL
1
CTL
FLIP 0 1
FLIP 0
HPD
HPD
Control
CC1
CC2
CC1
CC2
PD Controller
PD Controller
Control
DIR1/DIR0/CTL1/CTL0/FLIP = H/L/H/L/L
DIR1/DIR0/CTL1/CTL0/FLIP = H/H/H/L/L
图 50. Four Lane Custom Alternate Mode – No Flip
USB/Custom Source
USB/Custom Sink
(4 Lane Custom œ Flip)
(4 Lane Custom œ Flip)
D+/-
D+/-
USB/Custom
Sink
TUSB1044
TUSB1044
URX2
UTX2
UTX1
URX1
DRX2
DTX2
DTX1
DRX1
Type-C Cable
URX2
UTX2
UTX1
URX1
DRX2
DTX2
DTX1
DRX1
LN3
LN2
LN1
LN0
RX2
TX2
TX1
RX1
TX1
RX1
RX2
TX2
LN0
LN1
USB/Custom
Source
LN2
LN3
SBU2
SBU1
AUXn
AUXp
AUXp
AUXn
SBU1
SBU2
SBU1
SBU2
AUXp
SBU1
SBU2
AUXn
AUXn
AUXp
HPDIN
HPDIN
CTL
1
CTL
FLIP 0 1
FLIP 0
HPD
HPD
Control
CC1
CC2
DIR1/DIR0/CTL1/CTL0/FLIP = H/L/H/L/H
CC1
CC2
PD Controller
PD Controller
Control
DIR1/DIR0/CTL1/CTL0/FLIP = H/H/H/L/H
图 51. Four Lane Custom Alternate Mode – With Flip
版权 © 2018, Texas Instruments Incorporated
55
TUSB1044
ZHCSHJ2C –FEBRUARY 2018–REVISED OCTOBER 2018
www.ti.com.cn
9 Power Supply Recommendations
The TUSB1044 is designed to operate with a 3.3-V power supply. Levels above those listed in the table should
not be used. If using a higher voltage system power supply, a voltage regulator can be used to step down to 3.3
V. Decoupling capacitors should be used to reduce noise and improve power supply integrity. A 0.1-µF capacitor
should be used on each power pin.
56
版权 © 2018, Texas Instruments Incorporated
TUSB1044
www.ti.com.cn
ZHCSHJ2C –FEBRUARY 2018–REVISED OCTOBER 2018
10 Layout
10.1 Layout Guidelines
1. RXP/N and TXP/N pairs should be routed with controlled 90-Ω differential impedance (± 15%).
2. Keep away from other high speed signals.
3. Intra-pair routing should be kept to within 2 mils.
4. Length matching should be near the location of mismatch.
5. Each pair should be separated at least by 3 times the signal trace width.
6. The use of bends in differential traces should be kept to a minimum. When bends are used, the number of
left and right bends should be as equal as possible and the angle of the bend should be ≥ 135 degrees. This
will minimize any length mismatch causes by the bends and therefore minimize the impact bends have on
EMI.
7. Route all differential pairs on the same of layer.
8. The number of VIAS should be kept to a minimum. It is recommended to have no more than 1 VIA between
TUSB1044 and Type-C connector and no more than 1 VIA between TUSB1044 and USB3.1 Device/Host.
9. Keep traces on layers adjacent to ground plane.
10. Do NOT route differential pairs over any plane split.
11. Adding Test points will cause impedance discontinuity; and therefore, negatively impacts signal
performance. If test points are used, the test points should be placed in series and symmetrically. The test
points must not be placed in a manner that causes a stub on the differential pair.
12. Assuming 1 dB/inch loss at 5 GHz, the trace length between TUSB1044 and Type-C connector should be
no more than 1.5 inches.
13. Assuming 1 dB/inch loss at 5 GHz, the trace length between TUSB1044 and the USB 3.1 Host/Device
should be no more than 8 inches.
14. ESD protection devices and EMI suppression devices need to be carefully selected and have to have
excellent transient performance at 10 Gbps with flat shunt capacitance characteristics over ±650 mV voltage
range. Note small-signal insertion loss characteristics are insufficient to determine suitability of non-linear
devices (ESD devices) for 10Gbps operation
版权 © 2018, Texas Instruments Incorporated
57
TUSB1044
ZHCSHJ2C –FEBRUARY 2018–REVISED OCTOBER 2018
www.ti.com.cn
10.2 Layout Example
AC Coupling
capacitors
DRX2
DTX2
URX2
UTX2
UTX1
GND
DTX1
DRX1
URX1
图 52. Example Layout
58
版权 © 2018, Texas Instruments Incorporated
TUSB1044
www.ti.com.cn
ZHCSHJ2C –FEBRUARY 2018–REVISED OCTOBER 2018
11 器件和文档支持
11.1 文档支持
11.1.1 相关文档
本节标识的文档均在本规范中引用。为简化文本，文中的大多数参考文献均用文档标签 [文档标签] 标识，而不使用
完整的文档标题。
相关文档如下：
•
•
[USB31] 通用串行总线 3.1 规范。
[TYPEC] 通用串行总线 Type C 线缆和连接器规范
11.2 接收文档更新通知
要接收文档更新通知，请导航至 TI.com.cn 上的器件产品文件夹。单击右上角的通知我 进行注册，即可每周接收产
品信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
11.3 社区资源
下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，
并且不一定反映 TI 的观点；请参阅 TI 的 《使用条款》。
TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在
e2e.ti.com 中，您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。
设计支持
TI 参考设计支持 可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。
11.4 商标
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.5 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
11.6 术语表
SLYZ022 — TI 术语表。
这份术语表列出并解释术语、缩写和定义。
12 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且
不会对此文档进行修订。如需获取此产品说明书的浏览器版本，请查看左侧的导航栏。
版权 © 2018, Texas Instruments Incorporated
59
PACKAGE OPTION ADDENDUM
www.ti.com
7-Jun-2022
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TUSB1044IRNQR
TUSB1044IRNQT
TUSB1044RNQR
TUSB1044RNQT
ACTIVE
ACTIVE
ACTIVE
ACTIVE
WQFN
WQFN
WQFN
WQFN
RNQ
RNQ
RNQ
RNQ
40
40
40
40
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 85
-40 to 85
0 to 70
TUSB44
Samples
Samples
Samples
Samples
NIPDAU
NIPDAU
NIPDAU
TUSB44
TUSB44
TUSB44
0 to 70
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
7-Jun-2022
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TUSB1044IRNQR
TUSB1044IRNQT
TUSB1044RNQR
TUSB1044RNQT
WQFN
WQFN
WQFN
WQFN
RNQ
RNQ
RNQ
RNQ
40
40
40
40
3000
250
330.0
180.0
330.0
180.0
12.4
12.4
12.4
12.4
4.3
4.3
4.3
4.3
6.3
6.3
6.3
6.3
1.1
1.1
1.1
1.1
8.0
8.0
8.0
8.0
12.0
12.0
12.0
12.0
Q2
Q2
Q2
Q2
3000
250
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TUSB1044IRNQR
TUSB1044IRNQT
TUSB1044RNQR
TUSB1044RNQT
WQFN
WQFN
WQFN
WQFN
RNQ
RNQ
RNQ
RNQ
40
40
40
40
3000
250
367.0
210.0
367.0
210.0
367.0
185.0
367.0
185.0
35.0
35.0
35.0
35.0
3000
250
Pack Materials-Page 2
PACKAGE OUTLINE
RNQ0040A
WQFN - 0.8 mm max height
S
C
A
L
E
2
.
5
0
0
PLASTIC QUAD FLATPACK - NO LEAD
6.1
5.9
B
A
PIN 1 INDEX AREA
4.1
3.9
C
0.8 MAX
SEATING PLANE
0.08
0.05
0.00
4.7±0.1
2X 4.4
(0.2) TYP
9
20
EXPOSED
THERMAL PAD
36X 0.4
8
21
2X
2.8
2.7±0.1
1
28
0.25
40X
0.15
29
40
PIN 1 ID
0.1
C A
B
0.5
0.3
(OPTIONAL)
40X
0.05
4222125/B 01/2016
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
RNQ0040A
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(4.7)
2X (2.1)
6X (0.75)
40
29
40X (0.6)
1
28
40X (0.2)
SYMM
4X
(1.1)
(3.8)
(2.7)
36X (0.4)
8
21
(R0.05) TYP
9
20
SYMM
(5.8)
(
0.2) TYP
VIA
LAND PATTERN EXAMPLE
SCALE:15X
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4222125/B 01/2016
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
www.ti.com
EXAMPLE STENCIL DESIGN
RNQ0040A
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
SYMM
4X (1.5)
40
29
40X (0.6)
1
28
40X (0.2)
SYMM
6X
(0.695)
(3.8)
6X
(1.19)
36X (0.4)
8
21
(R0.05) TYP
METAL
TYP
9
20
6X (1.3)
(5.8)
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
EXPOSED PAD
73% PRINTED SOLDER COVERAGE BY AREA
SCALE:18X
4222125/B 01/2016
NOTES: (continued)
5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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