TUSB1210BRHBRQ1 [TI]
汽车类 USB2.0 高速 480Mbps ULPI PHY 收发器 | RHB | 32 | -40 to 85;
| 型号： | TUSB1210BRHBRQ1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 汽车类 USB2.0 高速 480Mbps ULPI PHY 收发器 | RHB | 32 | -40 to 85 以太网：16GBASE-T 电信 电信集成电路 |
| 文件： | 总67页 (文件大小：1758K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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TUSB1210-Q1
ZHCSCV8A –SEPTEMBER 2014–REVISED OCTOBER 2014
TUSB1210-Q1 独立 USB 收发器硅芯片
1 特性
3 说明
1
•
具有符合 AEC-Q100 标准的以下结果：
TUSB1210-Q1 是一款 USB2.0 收发器芯片，可通过
ULPI 接口连接 USB 控制器。 支持所有 USB2.0 数据
速率（高速 480Mbps、全速 12Mbps 以及低速
1.5Mbps），且兼容主机和外设模式。 此外，该器件
还支持 UART 模式及原有 ULPI 串行模式。
–
–
–
温度等级 3：-40°C 至 85°C
人体模型 (HBM) 静电放电 (ESD) 分类等级 1C
充电器件模型 (CDM) ESD 分类等级 C4B
•
USB2.0 物理层 (PHY) 收发器芯片，可通过 ULPI
12 引脚接口连接 USB 控制器，其完全符合：
TUSB1210-Q1 还支持 USB2.0 规范相关的 OTG（1.3
版）可选附件，包括主机协商协议 (HNP) 和会话请求
协议 (SRP)。
–
–
–
通用串行总线规范 2.0 版
USB 2.0 规范移动附录 1.3 版
UTMI+ 低引脚接口 (ULPI) 规范 1.1 版
发送器中的 DP/DM 外部组件补偿可对串联阻抗中的变
化进行补偿，以匹配数据线路阻抗和接收器输入端阻
抗，限制数据反射，从而改善眼图。
•
•
DP/DM 线路外部组件补偿（专利号 US7965100
B1）
连接主机、外设和 OTG 器件内核的接口；针对便
携式器件或具有内置 USB OTG 器件内核的系统
ASIC 进行了优化
器件信息(1)
部件号
封装
封装尺寸（标称值）
•
•
完整的 USB OTG 物理前端支持主机协商协议
(HNP) 与会话请求协议 (SRP)
超薄四方扁平无引线
(VQFN) (32)
TUSB1210-Q1
5.00mm x 5.00mm
ULPI 接口：
(1) 要了解所有可用封装，请见数据表末尾的可订购产品附录。
–
–
–
I/O 接口 (1.8V) 针对无端接 50 Ω 线路阻抗进行
了优化
图
ULPI 时钟引脚 (60 MHz) 可同时支持输入和输
出时钟配置
符合 ULPI 标准的完全可编程寄存器集
•
采用 32 引脚四方扁平无引线
[QFN (RHB)] 封装
2 应用范围
•
•
•
•
•
•
移动电话
平板电脑设备
台式机
便携式计算机
视频游戏控制台
便携式音乐播放器
1
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
English Data Sheet: SLLSEL4
TUSB1210-Q1
ZHCSCV8A –SEPTEMBER 2014–REVISED OCTOBER 2014
www.ti.com.cn
目录
7.4 Device Functional Modes........................................ 18
7.5 Register Map........................................................... 20
Application and Implementation ........................ 49
8.1 Application Information............................................ 49
8.2 Typical Application .................................................. 49
8.3 External Components.............................................. 53
Power Supply Recommendations...................... 54
9.1 TUSB1210 Power Supply ....................................... 54
9.2 Ground .................................................................... 54
9.3 Power Providers...................................................... 54
9.4 Power Modules ....................................................... 54
9.5 Power Consumption................................................ 55
1
2
3
4
5
6
特性.......................................................................... 1
应用范围................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 Handling Ratings....................................................... 4
6.3 Recommended Operating Conditions....................... 5
6.4 Thermal Information.................................................. 5
6.5 Analog I/O Electrical Characteristics ........................ 5
6.6 Digital I/O Electrical Characteristics.......................... 5
6.7 Digital IO Pins (Non-ULPI) ....................................... 5
6.8 PHY Electrical Characteristics .................................. 6
6.9 Pullup/Pulldown Resistors......................................... 8
6.10 OTG Electrical Characteristics................................ 9
6.11 Power Characteristics ........................................... 10
6.12 Switching Characteristics...................................... 10
6.13 Timing Requirements............................................ 11
6.14 Typical Characteristics.......................................... 13
Detailed Description ............................................ 14
7.1 Overview ................................................................. 14
7.2 Functional Block Diagram ....................................... 14
7.3 Feature Description................................................. 15
8
9
10 Layout................................................................... 56
10.1 Layout Guidelines ................................................. 56
10.2 Layout Example .................................................... 56
11 器件和文档支持 ..................................................... 57
11.1 文档支持................................................................ 57
11.2 社区资源................................................................ 57
11.3 商标....................................................................... 57
11.4 静电放电警告......................................................... 57
11.5 术语表 ................................................................... 57
12 机械封装和可订购信息 .......................................... 58
12.1 Via Channel........................................................... 58
12.2 封装信息................................................................ 58
7
4 修订历史记录
Changes from Original (September 2014) to Revision A
Page
•
•
•
•
•
•
•
•
•
已更改特性列表....................................................................................................................................................................... 1
删除了说明部分“TUSB1210-Q1 还支持 OTG（1.3 版）..”之后的 5 个段落 ........................................................................... 1
已更改 图图............................................................................................................................................................................. 1
Added VIL and VIH to the Recommended Operating Conditions table .................................................................................. 5
Changed the Thermal Information table ................................................................................................................................ 5
Changed the Digital I/O Electrical Characteristics table ........................................................................................................ 5
Digital IO Electrical Characteristics sections to the Switching Characteristics..................................................................... 10
Added the Typical Characteristics section............................................................................................................................ 13
Added 5 new paragraphs to the Overview section............................................................................................................... 14
2
Copyright © 2014, Texas Instruments Incorporated
TUSB1210-Q1
www.ti.com.cn
ZHCSCV8A –SEPTEMBER 2014–REVISED OCTOBER 2014
5 Pin Configuration and Functions
RHB Package
Top View
24
23
22
21
20
19
18
REFCLK
NXT
1
2
3
4
5
6
7
N/C
ID
V
DATA0
DATA1
DATA2
DATA3
DATA4
BUS
V
V
BAT
DD33
DM
DP
GND
17
N/C
8
CPEN
Pin Functions
PIN
A/D
TYPE
LEVEL
DESCRIPTION
NAME
NO.
REFCLK clock frequency configuration pin. Two frequencies are supported: 19.2 MHz
when 0, or 26 MHz when 1.
CFG
14
D
I
VDDIO
ULPI 60 MHz clock on which ULPI data is synchronized.
Two modes are possible:
CLOCK
26
D
O
VDDIO
Input Mode: CLOCK defaults as an input.
Output Mode: When an input clock is detected on REFCLK pin (after 4
rising edges) then CLOCK will change to an output.
CPEN
CS
17
11
D
D
O
I
VDD33
VDDIO
CMOS active-high digital output control of external 5V VBUS supply
Active-high chip select pin. When low the IC is in power down and ULPI bus is tri-
stated. When high normal operation. Tie to VDDIO if unused.
DATA0
DATA1
DATA2
DATA3
DATA4
DATA5
DATA6
DATA7
DIR
3
4
D
D
D
D
D
D
D
D
D
A
A
A
–
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDD33
VDD33
VDD33
VDDIO
ULPI DATA input/output signal 0 synchronized to CLOCK
ULPI DATA input/output signal 1 synchronized to CLOCK
ULPI DATA input/output signal 2 synchronized to CLOCK
ULPI DATA input/output signal 3 synchronized to CLOCK
ULPI DATA input/output signal 4 synchronized to CLOCK
ULPI DATA input/output signal 5 synchronized to CLOCK
ULPI DATA input/output signal 6 synchronized to CLOCK
ULPI DATA input/output signal 7 synchronized to CLOCK
ULPI DIR output signal
5
6
7
9
10
13
31
19
18
23
8
DM
I/O
I/O
I/O
–
DM pin of the USB connector
DP
DP pin of the USB connector
ID
Identification (ID) pin of the USB connector
No connect
N/C
15,16, 24,
24
N/C
–
–
–
No connect
NXT
2
D
O
VDDIO
ULPI NXT output signal
Copyright © 2014, Texas Instruments Incorporated
3
TUSB1210-Q1
ZHCSCV8A –SEPTEMBER 2014–REVISED OCTOBER 2014
www.ti.com.cn
Pin Functions (continued)
PIN
A/D
TYPE
LEVEL
DESCRIPTION
NAME
NO.
VDD33 Reference clock input (square-wave only). Tie to GND when pin 26 (CLOCK) is
required to be Input mode. Connect to square-wave reference clock of amplitude in
the range of 3 V to 3.6 V when Pin 26 (CLOCK) is required to be Output mode. See
pin 14 (CFG) description for REFCLK input frequency settings.
REFCLK
1
A
I
3.3 V
VDDIO
When low, all digital logic (except 32 kHz logic required for power up sequencing)
including registers are reset to their default values, and ULPI bus is tri-stated. When
high, normal USB operation.
RESETB
27
D
I
STP
VBAT
29
21
D
A
A
A
A
A
A
I
VDDIO
VBAT
VBUS
ULPI STP input signal
power
power
power
power
power
I
Input supply voltage or battery source
VBUS
22
VBUS pin of the USB connector
VDD15
VDD18
VDD33
VDDIO
12
1.5-V internal LDO output. Connect to external filtering capacitor.
External 1.8-V supply input. Connect to external filtering capacitor.
3.3-V internal LDO output. Connect to external filtering capacitor.
External 1.8V supply input for digital I/Os. Connect to external filtering capacitor.
28, 30
20
VDD18
VDD33
VDDIO
32
Thermal
Pad
GND
A
power
--
Reference Ground
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX UNIT
VCC
Main battery supply voltage (2)
Voltage on any input(3)
0
5
V
Where supply represents the voltage applied
to the power supply pin associated with the
input
–0.3 1 × VCC +0.3
V
VBUS input
–2
–0.3
–0.3
–40
–40
–14
–40
20
5.25
1.98
85
V
V
ID, DP, DM inputs
Stress condition specified 24h
Continuous
VDDIO
TA
IO supply voltage
V
Ambient temperature range
Junction temperature range
°C
°C
°C
°C
TJ
150
125
85
Parametric compliance
Ambient temperature for parametric
compliance
With max 125°C as junction temperature
DP, DM or ID pins short circuited to VBUS
supply, in any mode of TUSB1210-Q1
operation, continuously for 24 hours
DP, DM, ID high voltage short circuit
0
5.25
V
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The product will have negligible reliability impact if voltage spikes of 5.5 V occur for a total (cumulative over lifetime) duration of 5
milliseconds.
(3) Except VBAT input, VBUS, ID, DP, and DM pads
6.2 Handling Ratings
MIN
MAX
UNIT
Tstg
Storage temperature range
–65
150
°C
Human body model (HBM), per AEC Q100-002
Classification Level H1C, all pins(1)
1500
1500
Electrostatic discharge
(ESD) performance:
VESD
V
Corner pins
Other pins
–750
–500
750
500
Charged device model (CDM), per AEC
Q100-011 Classification Level C4B
(1) AEC Q100-002 indicates HBM stressing is done in accordance with ANSI/ESDA/JEDEC JS-001 specifications.
4
Copyright © 2014, Texas Instruments Incorporated
TUSB1210-Q1
www.ti.com.cn
ZHCSCV8A –SEPTEMBER 2014–REVISED OCTOBER 2014
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
2.7
NOM
MAX
UNIT
Battery supply voltage
3.6
4.8
V
VBAT
When VDD33 is supplied internally
3.15
3.05
1.71
Battery supply voltage for USB 2.0
compliancy (USB 2.0 certification)
V
When VDD33 is shorted to VBAT externally
VDDIO
VIL
Digital IO pin supply
1.98
V
V
Low-level input voltage
High-level output voltage
Ambient temperature range
CLOCK, STP, DIR, NXT, DATA0 to DATA7
CLOCK, STP, DIR, NXT, DATA0 to DATA7
0.35 x VDDIO
VIH
0.65 x VDDIO
–40
V
TA
85
°C
6.4 Thermal Information
RHB
THERMAL METRIC(1)
UNIT
(16 Pins)
34.72
37.3
RθJA
Junction-to-ambient thermal resistance
Junction-to-case(top) thermal resistance
RθJC(top)
RθJB
Junction-to-board thermal resistance
10.3
°C/W
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case(bottom) thermal resistance
0.5
ψJB
10.5
RθJC(bottom)
3.6
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
6.5 Analog I/O Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNIT
CPEN Output Pin
VOL
VOH
CPEN low-level output voltage
CPEN high-level output voltage
IOL = 3 mA
IOH = –3 mA
0.3
V
V
VDD33 – 0.3
6.6 Digital I/O Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
CLOCK
VOL
Low-level output voltage
High-level output voltage
0.45
0.45
V
V
Frequency = 60 MHz, Load = 10 pF
VOH
VDDIO - 0.45
STP, DIR, NXT, DATA0 to DATA7
VOL
VOH
Low-level output voltage
High-level output voltage
Frequency = 30 MHz, Load = 10 pF
VDDIO - 0.45
6.7 Digital IO Pins (Non-ULPI)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
CS, CFG, RESETB Input Pins
VIL
VIH
Maximum low-level input voltage
Minimum high-level input voltage
0.35 x VDDIO
V
V
0.65 x VDDIO
RESETB Input Pin Timing Spec
tw(POR) Internal power-on reset pulse
width
0.2
μs
Copyright © 2014, Texas Instruments Incorporated
5
TUSB1210-Q1
ZHCSCV8A –SEPTEMBER 2014–REVISED OCTOBER 2014
www.ti.com.cn
Digital IO Pins (Non-ULPI) (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
tw(RESET)
Applied to external RESETB pin
when CLOCK is toggling.
CLOCK
cycles
External RESETB pulse width
8
6.8 PHY Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
LS/FS Single-Ended Receivers
USB single-ended receivers
COMMENTS
MIN
TYP
MAX
UNIT
SKWVP_VM
VSE_HYS
VIH
Skew between VP and VM
Single-ended hysteresis
High (driven)
Driver outputs unloaded
–2
50
0
2
ns
mV
V
2
VIL
Low
0.8
2
V
VTH
Switching threshold
0.8
V
LS/FS Differential Receiver
VDI
Differential input sensitivity
Ref. USB2.0
Ref. USB2.0
200
0.8
mV
V
VCM
Differential Common mode range
2.5
LS Transmitter
VOL
VOH
Low
Ref. USB2.0
Ref. USB2.0
0
300
3.6
mV
V
High (driven)
2.8
Ref. USB2.0, covered by eye
diagram
VCRS
tr
Output signal crossover voltage
Rise time
1.3
75
2
V
Ref. USB2.0, covered by eye
diagram
300
300
ns
ns
tf
Fall time
75
tFRFM
Differential rise and fall time matching
80%
125%
1.5225
25
Ref. USB2.0, covered by eye
diagram
tFDRATE
tDJ1
Low-speed data rate
1.4775
–25
Mb/s
ns
To next transition
Source jitter total (including frequency
tolerance)
Ref. USB2.0, covered by eye
diagram
For paired
transitions
tDJ2
–10
10
Ref. USB2.0, covered by eye
diagram
tFEOPT
Source SE0 interval of EOP
1.25
0.8
1.5
2.5
µs
Ref. USB2.0, covered by eye
diagram
Downstream eye diagram
VCM
Differential common mode range
Ref. USB2.0
V
FS Transmitter
VOL
VOH
Low
Ref. USB2.0
Ref. USB2.0
0
300
3.6
mV
V
High (driven)
2.8
Ref. USB2.0, covered by eye
diagram
VCRS
Output signal crossover voltage
1.3
2
V
tFR
tFF
Rise time
Fall time
Ref. USB2.0
Ref. USB2.0
4
4
20
20
ns
ns
Ref. USB2.0, covered by eye
diagram
tFRFM
ZDRV
Differential rise and fall time matching
Driver output resistance
90%
28
111.11%
Ref. USB2.0
44
12.03
2
Ω
Ref. USB2.0, covered by eye
diagram
TFDRATE
tDJ1
Full-speed data rate
11.97
–2
Mb/s
To next transition
Source jitter total (including frequency
tolerance)
Ref. USB2.0, covered by eye
diagram
ns
ns
For paired
transitions
tDJ2
–1
1
Ref. USB2.0, covered by eye
diagram
TFEOPT
Source SE0 interval of EOP
Downstream eye diagram
160
175
Ref. USB2.0, covered by eye
diagram
6
Copyright © 2014, Texas Instruments Incorporated
TUSB1210-Q1
www.ti.com.cn
ZHCSCV8A –SEPTEMBER 2014–REVISED OCTOBER 2014
PHY Electrical Characteristics (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
COMMENTS
MIN
TYP
MAX
UNIT
Upstream eye diagram
HS Differential Receiver
High-speed squelch detection threshold (differential signal
amplitude)
VHSSQ
Ref. USB2.0
100
525
150
625
mV
mV
mV
mV
ps
High-speed disconnect detection threshold (differential signal
amplitude)
VHSDSC
Ref. USB2.0
Ref. USB2.0, specified by eye
pattern templates
High-speed differential input signaling levels
High-speed data signaling common mode voltage range
(guidelines for receiver)
VHSCM
Ref. USB2.0
–50
500
150
Ref. USB2.0, specified by eye
pattern templates
Receiver jitter tolerance
HS Transmitter
VHSOI
High-speed idle level
Ref. USB2.0
Ref. USB2.0
Ref. USB2.0
Ref. USB2.0
Ref. USB2.0
–10
360
–10
700
-900
10
440
mV
mV
mV
mV
mV
VHSOH
High-speed data signaling high
High-speed data signaling low
Chirp J level (differential voltage)
Chirp K level (differential voltage)
VHSOL
10
VCHIRPJ
VCHIRPK
1100
-500
Ref. USB2.0, covered by eye
diagram
tr
Rise Time (10% - 90%)
Fall time (10% - 90%)
500
500
ps
ps
Ref. USB2.0, covered by eye
diagram
tf
Driver output resistance (which also serves as high-speed
termination)
ZHSDRV
THSDRAT
Ref. USB2.0
40.5
49.5
Ω
Ref. USB2.0, covered by eye
diagram
High-speed data range
Data source jitter
479.76
480.24
Mb/s
Ref. USB2.0, covered by eye
diagram
Ref. USB2.0, covered by eye
diagram
Downstream eye diagram
Upstream eye diagram
Ref. USB2.0, covered by eye
diagram
CEA-2011/UART Transceiver
UART Transmitter CEA-2011
tPH_UART_EDGE Phone UART edge rates
DP_PULLDOWN asserted
ISOURCE = 4 mA
ISINK = –4 mA
1
3.6
0.4
Μs
V
VOH_SER
VOL_SER
Serial interface output high
Serial interface output low
UART Receiver CEA-2011
Serial interface input high
Serial interface input low
Switching threshold
2.4
0
3.3
0.1
V
VIH_SER
VIL_SER
VTH
DP_PULLDOWN asserted
DP_PULLDOWN asserted
2
V
V
V
0.8
2
0.8
Copyright © 2014, Texas Instruments Incorporated
7
TUSB1210-Q1
ZHCSCV8A –SEPTEMBER 2014–REVISED OCTOBER 2014
www.ti.com.cn
MAX UNIT
6.9 Pullup/Pulldown Resistors
over operating free-air temperature range (unless otherwise noted)
PARAMETER
COMMENTS
MIN
TYP
Bus pullup resistor on upstream port
(idle bus)
RPUI
Bus idle
0.9
1.1
1.575
3.09
kΩ
Bus pullup resistor on upstream port
(receiving)
RPUA
Bus driven/driver's outputs unloaded
1.425
2.2
Pullups/pulldowns on both DP and
DM lines
VIHZ
High (floating)
2.7
3
3.6
3.6
V
V
VPH_DP_UP
Phone D+ pullup voltage
Pulldown resistors
Driver's outputs unloaded
3.3
18
RPH_DP_DWN
RPH_DM_DWN
Phone D+/– pulldown
Driver's outputs unloaded
14.25
2.7
24.8
3.6
kΩ
Pullups/pulldowns on both DP and
DM lines
VIHZ
High (floating)
V
D+/– Data line
CINUB
Upstream facing port
On-the-go device leakage
[1.0]
[2]
22
75
pF
V
VOTG_DATA_LKG
0.342
Input impedance exclusive of
pullup/pulldown
ZINP
Driver's outputs unloaded
300
kΩ
8
Copyright © 2014, Texas Instruments Incorporated
TUSB1210-Q1
www.ti.com.cn
ZHCSCV8A –SEPTEMBER 2014–REVISED OCTOBER 2014
6.10 OTG Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
COMMENTS
MIN
TYP
MAX UNIT
OTG VBUS Electrical
VBUS Comparators
VA_SESS_VLD
VA_VBUS_VLD
VB_SESS_END
VB_SESS_VLD
VBUS Line
A-device session valid
A-device VBUS valid
B-device session end
B-device session valid
0.8
4.4
0.2
2.1
1.4
4.5
0.5
2.4
2.0
4.625
0.8
V
V
V
V
2.7
A-device VBUS input impedance SRP (VBUS pulsing) capable A-device not driving
RA_BUS_IN
40
70
100
kΩ
to ground
VBUS
RB_SRP_DWN
RB_SRP_UP
B-device VBUS SRP pulldown
B-device VBUS SRP pullup
5.25 V / 8 mA, Pullup voltage = 3 V
(5.25 V – 3 V) / 8 mA, Pullup voltage = 3 V
0.656
0.281
10
1
kΩ
kΩ
2
RVBUS = 0 Ω
and R1KSERIES = '0'
31.4
RVBUS = 1000 Ω ±10%
and R1KSERIES = '1'
57.8
64
B-device VBUS SRP rise time
tRISE_SRP_UP_MAX maximum for OTG-A
communication
0 to 2.1 V with < 13 μF
load
ms
RVBUS = 1200 Ω ±10%
and R1KSERIES = '1'
RVBUS = 1800 Ω ±10%
and R1KSERIES = '1'
85.4
RVBUS = 0 Ω
and R1KSERIES = '0'
46.2
96
RVBUS = 1000 Ω ±10%
and R1KSERIES = '1'
B-device VBUS SRP rise time
tRISE_SRP_UP_MIN minimum for standard host
connection
0.8 to 2 V with > 97 μF
load
ms
RVBUS = 1200 Ω ±10%
and R1KSERIES = '1'
100
100
RVBUS = 1800 Ω ±10%
and R1KSERIES = '1'
Table 1. OTG ID Electrical
PARAMETER
COMMENTS
MIN
TYP
MAX UNIT
ID Comparators — ID External Resistors Specifications
RID_GND
ID ground comparator
ID Float comparator
ID Line
ID_GND interrupt
12
20
28
500
kΩ
kΩ
RID_FLOAT
ID_FLOAT interrupt
200
RPH_ID_UP
VPH_ID_UP
Phone ID pullup to VPH_ID_UP
Phone ID pullup voltage
ID line maximum voltage
ID unloaded (VRUSB
)
70
90
286
3.2
kΩ
V
Connected to VRUSB
2.5
5.25
V
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MAX UNIT
6.11 Power Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
VDD33 Internal LDO Regulator Characteristics
VINVDD33
Input voltage
VBAT USB
VVDD33 typ + 0.2
3.6
2.5
2.75
3.0
3.1
3.2
3.3
3.4
3.5
4.5
2.6
2.85
3.1
3.2
3.3
3.4
3.5
3.6
15
V
VUSB3V3_VSEL = ‘000
VUSB3V3_VSEL = ‘001
VUSB3V3_VSEL = ‘010
VUSB3V3_VSEL = ‘011 (default)
VUSB3V3_VSEL = ‘100
VUSB3V3_VSEL = ‘101
VUSB3V3_VSEL = ‘110
VUSB3V3_VSEL = ‘111
Active mode
2.4
2.65
2.9
3.0
3.1
3.2
3.3
3.4
VVDD33
Output voltage
ON mode,
V
IVDD33
Rated output current
VBAT USB
mA
Suspend/reset mode
1
VDD15 Internal LDO Regulator Characteristics
VIN VDD15
VVDD15
IVDD15
Input voltage
On mode, VIN VDD15 = VBAT
VINVDD15 min – VINVDD15 max
On mode
2.7
3.6
1.56
4.5
1.65
30
V
V
Output voltage
Rated output current
1.45
mA
6.12 Switching Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
Electrical Characteristics: Clock Input
Clock input duty cycle
TEST CONDITIONS
MIN
TYP
MAX
UNIT
40
60%
fCLK
Clock nominal frequency
Clock input rise/fall time
60
MHz
In % of clock period tCLK ( = 1/fCLK
)
10%
250
600
Clock input frequency accuracy
Clock input integrated jitter
ppm
ps rms
Electrical Characteristics: REFCLK
REFCLK input duty cycle
40
60%
When CFG pin is tied to GND
When CFG pin is tied to VDDIO
In % of clock period tREFCLK ( =
19.2
26
fREFCLK
REFCLK nominal frequency
REFCLK input rise/fall time
MHz
20%
1/fREFCLK
)
REFCLK input frequency accuracy
REFCLK input integrated jitter
REFCLK HIZ Leakage current
REFCLK HIZ Leakage current
250
600
3
ppm
ps rms
µA
–3
Digital IO Electrical Characteristics: CLOCK
tr
tf
Rise time
Fall time
Frequency = 60 MHz, Load = 10 pF
Frequency = 30 MHz, Load = 10 pF
1
1
ns
ns
Digital IO Electrical Characteristics: STP, DIR, NXT, DATA0 to DATA7
tr
tf
Rise time
Fall time
1
1
ns
ns
Frequency = 30 MHz, Load = 10 pF
10
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6.13 Timing Requirements
INPUT CLOCK
MIN
OUTPUT CLOCK
PARAMETER
UNIT
MAX
MIN
MAX
ULPI Interface Timing
tSC, tSD
tSC, tHD
tDC, tDD
Set-up time (control in, 8-bit data in)
3
6
6
9
ns
ns
ns
Hold time (control in, 8-bit data in)
1.5
0
Output delay (control out, 8-bit data out)
USB UART Interface Timing
tPH_DP_CON
tPH_DISC_DET
fUART_DFLT
Phone D+ connect time
100
150
ms
ms
Phone D+ disconnect time
Default UART signaling rate (typical rate)
9600
bps
VBAT , VDD33
VDDIO, VDD18
IORST
CS
TVBBDET (10us)
TBGAP (2ms)
ICACT
BGOK
TPWONVDD15 (100us)
VDD15
DIGPOR
CK32K
TCK32K_PWON (125us)
TDELRSTPWR (61us)
CK32KOK
RESETN_PWR
MNTR_(VDD18,VIO)_OK
MNTR_VDD33_OK
(input 60M) CLOCK
RESETB
TDELMNTRVIOEN (91.5us)
TMNTR (183.1us)
TDELVDD33EN (91.5us)
TMNTR (183.1us)
TDELRESETB (244.1us)
TPLL (300us)
PLL 480M LOCKED
DIR
TDEL_RST_DIR (0.54ms)
TDEL_CS_SUPPLYOK (2.84ms)
Figure 1. TUSB1210-Q1 Power-Up Timing (ULPI Clock Input Mode)
Table 2. Timers and Debounce
PARAMETER
COMMENTS
MIN
TYP
MAX
UNIT
tDEL_CS_SUPPLYOK
tDEL_RST_DIR
Chip-select-to-supplies OK delay
2.84
4.10
ms
RESETB to PHY PLL locked and DIR falling-
edge delay
0.54
0.647
ms
tVBBDET
VBAT detection delay
10
2
µs
ms
µs
µs
µs
µs
µs
µs
µs
µs
tBGAP
Bandgap power-on delay
VDD15 power-on delay
32-KHz RC-OSC power-on delay
Power control reset delay
Monitor enable delay
tPWONVDD15
tPWONCK32K
tDELRSTPWR
tDELMNTRVIOEN
tMNTR
100
125
61
91.5
183.1
93.75
244.1
300
Supply monitoring debounce
VDD33 LDO enable delay
RESETB internal delay
PLL lock time
tDELVDD33EN
tDELRESETB
tPLL
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6.13.1 Timing Parameter Definitions
The timing parameter symbols used in the timing requirement and switching characteristic tables are created in
accordance with JEDEC Standard 100. To shorten the symbols, some pin names and other related terminologies
have been abbreviated as shown in Table 3.
Table 3. Timing Parameter Definitions
LOWERCASE SUBSCRIPTS
SYMBOL
PARAMETER
Cycle time (period)
Delay time
C
D
Dis
En
H
Disable time
Enable time
Hold time
Su
START
T
Setup time
Start bit
Transition time
Valid time
V
W
Pulse duration (width)
Unknown, changing, or don't care level
High
X
H
L
Low
V
Valid
IV
Invalid
AE
FE
LE
Z
Active edge
First edge
Last edge
High impedance
6.13.2 Interface Target Frequencies
Table 4 assumes testing over the recommended operating conditions.
Table 4. TUSB1210-Q1 Interface Target Frequencies
IO
TARGET FREQUENCY
1.5 V
INTERFACE DESIGNATION
INTERFACE
High speed
Universal serial bus Full speed
Low speed
480 Mbits/s
12 Mbits/s
1.5 Mbits/s
USB
12
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6.14 Typical Characteristics
Figure 2. High-Speed Eye Diagram
Figure 3. Full-Speed Eye Diagram
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7 Detailed Description
7.1 Overview
The TUSB1210-Q1 is a USB2.0 transceiver chip, designed to interface with a USB controller via a ULPI
interface. It supports all USB2.0 data rates High-Speed, Full-Speed, and Low-Speed. Compliant to both Host and
Peripheral (OTG) modes. It additionally supports a UART mode and legacy ULPI serial modes. TUSB1210-Q1
Integrates a 3.3-V LDO, which makes it flexible to work with either battery operated systems or pure 3.3 V
supplied systems. Also, it has an integrated PLL Supporting 2 Clock Frequencies 19.2 MHz/26 MHz. The ULPI
clock pin (60 MHz) supports both input and output clock configurations. TUSB1210-Q1 has low power
consumption, optimized for portable devices, and complete USB OTG Physical Front-End that supports Host
Negotiation Protocol (HNP) and Session Request Protocol (SRP).
TUSB1210-Q1 is optimized to be interfaced through a 12-pin SDR UTMI Low Pin Interface (ULPI), supporting
both input clock and output clock modes, with 1.8 V interface supply voltage.
TUSB1210-Q1 integrates a 3.3 V LDO, which makes it flexible to work with either battery operated systems or
pure 3.3 V supplied systems. Both the main supply and the 3.3 V power domain can be supplied through an
external switched-mode converter for optimized power efficiency.
TUSB1210-Q1 includes a POR circuit to detect supply presence on VBAT and VDDIO pins. TUSB1210-Q1 can be
disabled or configured in low power mode for energy saving.
TUSB1210-Q1 is protected against accidental shorts to 5 V or ground on its exposed interface (DP/DM/ID). It is
also protected against up to 20 V surges on VBUS
.
TUSB1210-Q1 integrates a high-performance low-jitter 480 MHz PLL and supports two clock configurations.
Depending on the required link configuration, TUSB1210-Q1 supports both ULPI input and output clock mode :
input clock mode, in which case a square-wave 60 MHz clock is provided to TUSB1210-Q1 at the ULPI interface
CLOCK pin; and output clock mode in which case TUSB1210-Q1 can accept a square-wave reference clock at
REFCLK of either 19.2 MHz, 26 MHz. Frequency is indicated to TUSB1210-Q1 via the configuration pin CFG.
This can be useful if a reference clock is already available in the system.
7.2 Functional Block Diagram
POR
VIO
VDDIO (32)
CTRL
POR
VBAT
VBAT (21)
( 1) REFCLK
POR
DIG
BGAP
& REF
1V5
32K
RST_DIG
(11) CS
(14) CFG
(27) RESETB
VDD15 (12)
(
)
N/C
8
DIG
(
(
(
)
15 N/C
USB-IP
1V8
)
16 N/C
VDD18 (30)
VDD18 (28)
VDD33 (20)
PWR_ FSM
PHY
PLL
)
25 N/C
N/C
DIG
+
(24)
3V3
OTG
PHY
ANA
ULPI
+
REGS
DP (18)
DM (19)
ID (23)
OTG
(17) CPEN
TEST
(22)
VBUS
PKG Substrate
(Ground )
14
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7.3 Feature Description
7.3.1 Processor Subsystem
7.3.1.1 Clock Specifications
7.3.1.1.1 USB PLL Reference Clock
The USB PLL block generates the clocks used to synchronize :
•
•
the ULPI interface (60 MHz clock)
the USB interface (depending on the USB data rate, 480 Mbps, 12 Mbps or 1.5 Mbps)
TUSB1210-Q1 requires an external reference clock which is used as an input to the 480 MHz USB PLL block.
Depending on the clock configuration, this reference clock can be provided either at REFCLK pin or at CLOCK
pin. By default CLK pin is configured as an input.
Two clock configurations are possible:
•
•
Input clock configuration (see ULPI Input Clock Configuration)
Output clock configuration (see ULPI Output Clock Configuration)
7.3.1.1.2 ULPI Input Clock Configuration
In this mode REFCLK must be externally tied to GND. CLOCK remains configured as an input.
When the ULPI interface is used in input clock configuration, that is, the 60 MHz ULPI clock is provided to
TUSB1210-Q1 on Clock pin, then this is used as the reference clock for the 480 MHz USB PLL block. See
Switching Characteristics.
7.3.1.1.3 ULPI Output Clock Configuration
In this mode a reference clock must be externally provided on REFCLK pin When an input clock is detected on
REFCLK pin then CLK will automatically change to an output, i.e., 60 MHz ULPI clock is output by TUSB1210-
Q1 on CLK pin.
Two reference clock input frequencies are supported. REFCLK input frequency is communicated to TUSB1210-
Q1 via a configuration pin, CFG, see fREFCLK in Table 11 for frequency correspondence. TUSB1210-Q1 supports
square-wave reference clock input only. Reference clock input must be square-wave of amplitude in the range 3
V to 3.6 V. See Switching Characteristics.
7.3.1.1.4 Clock 32 kHz
An internal clock generator running at 32 kHz has been implemented to provide a low-speed, low-power clock to
the system See Clock 32 kHz
7.3.1.1.5 Reset
All logic is reset if CS = 0 or VBAT are not present.
All logic (except 32 kHz logic) is reset if VDDIO is not present.
PHY logic is reset when any supplies are not present (VDDIO, VDD15, VDD18, VDD33) or if RESETB pin is low.
TUSB1210-Q1 may be reset manually by toggling the RESETB pin to GND for at lease 200 ns.
If manual reset via RESETB is not required then RESETB pin may be tied to VDDIO permanently.
7.3.1.2 USB Transceiver
The TUSB1210-Q1 device includes a universal serial bus (USB) on-the-go (OTG) transceiver that supports USB
480 Mb/s high-speed (HS), 12 Mb/s full-speed (FS), and USB 1.5 Mb/s low-speed (LS) through a 12-pin UTMI+
low pin interface (ULPI).
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Feature Description (continued)
NOTE
LS device mode is not allowed by a USB2.0 HS capable PHY, therefore it is not supported
by TUSB1210-Q1. This is stated in USB2.0 standard Chapter 7, page 119, second
paragraph: “A high-speed capable upstream facing transceiver must not support low-
speed signaling mode..” There is also some related commentary in Chapter 7.1.2.3.
7.3.1.2.1 PHY Electrical Characteristics
The PHY is the physical signaling layer of the USB 2.0. It essentially contains all the drivers and receivers
required for physical data and protocol signaling on the DP and DM lines.
The PHY interfaces to the USB controller through a standard 12-pin digital interface called UTMI+ low pin
interface (ULPI).
The transmitters and receivers inside the PHY are classified into two main classes.
•
•
The full-speed (FS) and low-speed (LS) transceivers. These are the legacy USB1.x transceivers.
The HS (HS) transceivers
In order to bias the transistors and run the logic, the PHY also contains reference generation circuitry which
consists of:
•
A DPLL which does a frequency multiplication to achieve the 480-MHz low-jitter lock necessary for USB and
also the clock required for the switched capacitor resistance block.
•
A switched capacitor resistance block which is used to replicate an external resistor on chip.
Built-in pullup and pulldown resistors are used as part of the protocol signaling.
Apart from this, the PHY also contains circuitry which protects it from accidental 5-V short on the DP and DM
lines.
7.3.1.2.1.1 LS/FS Single-Ended Receivers
In addition to the differential receiver, there is a single-ended receiver (SE–, SE+) for each of the two data lines
D+/–. The main purpose of the single-ended receivers is to qualify the D+ and D– signals in the full-speed/low-
speed modes of operation. See PHY Electrical Characteristics.
7.3.1.2.1.2 LS/FS Differential Receiver
A differential input receiver (Rx) retrieves the LS/FS differential data signaling. The differential voltage on the line
is converted into digital data by a differential comparator on DP/DM. This data is then sent to a clock and data
recovery circuit which recovers the clock from the data. An additional serial mode exists in which the differential
data is directly output on the RXRCV pin. See Switching Characteristics.
7.3.1.2.1.3 LS/FS Transmitter
The USB transceiver (Tx) uses a differential output driver to drive the USB data signal D+/– onto the USB cable.
The driver's outputs support 3-state operation to achieve bidirectional half-duplex transactions. See Switching
Characteristics.
7.3.1.2.1.4 HS Differential Receiver
The HS receiver consists of the following blocks:
A differential input comparator to receive the serial data
•
•
A squelch detector to qualify the received data
An oversampler-based clock data recovery scheme followed by a NRZI decoder, bit unstuffing, and serial-to-
parallel converter to generate the ULPI DATAOUT
See Switching Characteristics.
16
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Feature Description (continued)
7.3.1.2.1.5 HS Differential Transmitter
The HS transmitter is always operated via the ULPI parallel interface. The parallel data on the interface is
serialized, bit stuffed, NRZI encoded, and transmitted as a dc output current on DP or DM depending on the
data. Each line has an effective 22.5-Ω load to ground, which generates the voltage levels for signaling.
A disconnect detector is also part of the HS transmitter. A disconnect on the far end of the cable causes the
impedance seen by the transmitter to double thereby doubling the differential amplitude seen on the DP/DM lines
of Switching Characteristics.
7.3.1.2.1.6 UART Transceiver
In this mode, the ULPI data bus is redefined as a 2-pin UART interface, which exchanges data through a direct
access to the FS/LS analog transmitter and receiver. See Switching Characteristics.
Figure 4. USB UART Data Flow
7.3.1.2.2 OTG Characteristics
The on-the-go (OTG) block integrates three main functions:
•
•
•
The USB plug detection function on VBUS and ID
The ID resistor detection
The VBUS level detection
See OTG Electrical Characteristics.
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7.4 Device Functional Modes
7.4.1 TUSB1210-Q1 Modes vs ULPI Pin Status
Table 5, Table 6, and Table 7 show the status of each of the 12 ULPI pins including input/output direction and
whether output pins are driven to ‘0’ or to ‘1’, or pulled up/pulled down via internal pullup/pulldown resistors.
Note that pullup/pulldown resistors are automatically replaced by driven ‘1’/’0’ levels respectively once internal
IORST is released, with the exception of the pullup on STP which is maintained in all modes.
Pin assignment changes in ULPI 3-pin serial mode, ULPI 6-pin serial mode, and UART mode. Unused pins are
tied low in these modes as shown below.
Table 5. TUSB1210-Q1 Modes vs ULPI Pin Status:ULPI Synchronous Mode Power-Up
ULPI SYNCHRONOUS MODE POWER-UP
UNTIL IORST RELEASE
PLL OFF
PLL ON + STP HIGH
PLL ON + STP LOW
PIN
NO.
PIN NAME
DIR
PU/PD
DIR
PU/PD
DIR
PU/PD
DIR
PU/PD
26
31
2
CLOCK
DIR
Hiz
Hiz
Hiz
Hiz
Hiz
Hiz
Hiz
Hiz
Hiz
Hiz
Hiz
Hiz
PD
PU
PD
PU
PD
PD
PD
PD
PD
PD
PD
PD
I
PD
IO
-
IO
O
-
O, (‘1’)
O, (‘0’)
I
-
O, (‘0’)
-
-
NXT
-
O, (‘0’)
-
O
-
29
3
STP
PU
I
I
I
I
I
I
I
I
I
PU
PD
PD
PD
PD
PD
PD
PD
PD
I
PU
DATA0
DATA1
DATA2
DATA3
DATA4
DATA5
DATA6
DATA7
O, (‘0’)
O, (‘0’)
O, (‘0’)
O, (‘0’)
O, (‘0’)
O, (‘0’)
O, (‘0’)
O, (‘0’)
-
-
-
-
-
-
-
-
IO
IO
IO
IO
IO
IO
IO
IO
-
-
-
-
-
-
-
-
4
5
6
7
9
10
13
Table 6. TUSB1210-Q1 Modes vs ULPI Pin Status: USB Suspend Mode
LINK / EXTERNAL RECOMMENDED SETTING DURING
SUSPEND MODE
SUSPEND MODE
PIN NO.
PIN NAME
CLOCK
DIR
DIR
PU/PD
DIR
PU/PD
26
31
2
I
-
O
-
-
-
-
-
-
-
-
-
-
-
-
O, (‘1’)
O, (‘0’)
I
-
I
NXT
-
I
29
3
STP
PU(1)
O, (‘0’)
DATA0
DATA1
DATA2
DATA3
DATA4
DATA5
DATA6
DATA7
O, (LINESTATE0)
O, (LINESTATE1)
O, (‘0’)
-
-
-
-
-
-
-
-
I
I
I
I
I
I
I
I
4
5
6
O, (INT)
7
O, (‘0’)
9
O, (‘0’)
10
13
O, (‘0’)
O, (‘0’)
(1) Can be disabled by software before entering Suspend Mode to reduce current consumption
18
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Table 7. TUSB1210-Q1 Modes vs ULPI Pin Status: ULPI 6-Pin Serial Mode and UART Mode
ULPI 6-PIN SERIAL MODE
ULPI 3-PIN SERIAL MODE
UART MODE
PIN NO.
PIN NAME
DIR
IO
O
O
I
PU/PD
PIN NAME
DIR
IO
O
O
I
PU/PD
PIN NAME
CLOCK (1)
DIR
DIR
IO
O
O
I
PU/PD
26
31
2
CLOCK (1)
DIR
-
CLOCK (1)
DIR
-
-
-
-
-
NXT
-
NXT
-
NXT
-
29
3
STP
PU
STP
PU
STP
PU
TX_ENABLE
TX_DAT
TX_SE0
INT
I
-
-
-
-
-
-
-
-
TX_ENABLE
DAT
I
-
-
-
-
-
-
-
-
TXD
I
-
-
-
-
-
-
-
4
I
IO
IO
O
O
O
O
O
RXD
IO
O
O
O
O
O
O
5
I
SE0
tie low
INT
6
O
O
O
O
O
INT
7
RX_DP
RX_DM
RX_RCV
tie low
tie low
tie low
tie low
tie low
tie low
tie low
tie low
tie low
9
10
13
-
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7.5 Register Map
Table 8. USB Register Summary
REGISTER NAME
VENDOR_ID_LO
TYPE
R
REGISTER WIDTH (BITS)
PHYSICAL ADDRESS
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
0x10
0x11
0x12
0x13
0x14
0x15
0x16
0x17
0x18
0x19 0x2E
0x2F
0x30 0x3C
0x3D
0x3E
0x3F
0x80
0x81
0x82
0x83
0x84
0x85
0x86
0x87
VENDOR_ID_HI
R
PRODUCT_ID_LO
PRODUCT_ID_HI
R
R
FUNC_CTRL
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
R
FUNC_CTRL_SET
FUNC_CTRL_CLR
IFC_CTRL
IFC_CTRL_SET
IFC_CTRL_CLR
OTG_CTRL
OTG_CTRL_SET
OTG_CTRL_CLR
USB_INT_EN_RISE
USB_INT_EN_RISE_SET
USB_INT_EN_RISE_CLR
USB_INT_EN_FALL
USB_INT_EN_FALL_SET
USB_INT_EN_FALL_CLR
USB_INT_STS
USB_INT_LATCH
R
DEBUG
R
SCRATCH_REG
RW
RW
RW
R
SCRATCH_REG_SET
SCRATCH_REG_CLR
Reserved
ACCESS_EXT_REG_SET
Reserved
RW
R
VENDOR_SPECIFIC1
VENDOR_SPECIFIC1_SET
VENDOR_SPECIFIC1_CLR
VENDOR_SPECIFIC2
VENDOR_SPECIFIC2_SET
VENDOR_SPECIFIC2_CLR
VENDOR_SPECIFIC1_STS
VENDOR_SPECIFIC1_LATCH
VENDOR_SPECIFIC3
VENDOR_SPECIFIC3_SET
VENDOR_SPECIFIC3_CLR
RW
RW
RW
RW
RW
RW
R
R
RW
RW
RW
20
Copyright © 2014, Texas Instruments Incorporated
TUSB1210-Q1
www.ti.com.cn
ZHCSCV8A –SEPTEMBER 2014–REVISED OCTOBER 2014
7.5.1 VENDOR_ID_LO
ADDRESS OFFSET
PHYSICAL ADDRESS
DESCRIPTION
TYPE
0x00
0x00
INSTANCE
USB_SCUSB
Lower byte of vendor ID supplied by USB-IF (TI Vendor ID = 0x0451)
R
WRITE LATENCY
7
6
5
4
3
2
1
0
0
0
VENDOR_ID
BITS
FIELD NAME
DESCRIPTION
TYPE
RESET
7:00
VENDOR_ID
R
0x51
7.5.2 VENDOR_ID_HI
ADDRESS OFFSET
PHYSICAL ADDRESS
DESCRIPTION
TYPE
0x01
0x01
INSTANCE
USB_SCUSB
Upper byte of vendor ID supplied by USB-IF (TI Vendor ID = 0x0451)
R
WRITE LATENCY
7
6
5
4
3
2
1
VENDOR_ID
BITS
FIELD NAME
DESCRIPTION
TYPE
RESET
7:00
VEN DOR_ID
R
0x04
7.5.3 PRODUCT_ID_LO
ADDRESS OFFSET
PHYSICAL ADDRESS
DESCRIPTION
TYPE
0x02
0x02
INSTANCE
USB_SCUSB
Lower byte of Product ID supplied by Vendor (TUSB1210-Q1 Product ID is 0x1507).
R
WRITE LATENCY
7
6
5
4
3
2
1
PRODUCT_ID
BITS
FIELD NAME
DESCRIPTION
TYPE
RESET
7:00
PRODUCT_ID
R
0x07
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www.ti.com.cn
7.5.4 PRODUCT_ID_HI
ADDRESS OFFSET
PHYSICAL ADDRESS
DESCRIPTION
TYPE
0x03
0x03
INSTANCE
USB_SCUSB
Upper byte of Product ID supplied by Vendor (TUSB1210-Q1 Product ID is 0x1507).
R
WRITE LATENCY
7
6
5
4
3
2
1
0
PRODUCT_ID
BITS
FIELD NAME
DESCRIPTION
TYPE
RESET
7:00
PRODUCT_ID
R
0x15
7.5.5 FUNC_CTRL
ADDRESS OFFSET
PHYSICAL ADDRESS
DESCRIPTION
TYPE
0x04
0x04
INSTANCE USB_SCUSB
Controls UTMI function settings of the PHY.
RW
WRITE LATENCY
7
6
SUSPENDM
FIELD NAME
Reserved
5
4
3
2
1
0
Reserved
BITS
RESET
OPMODE
TERMSELECT
XCVRSELECT
DESCRIPTION
TYPE
R
RESET
7
6
0
1
SUSPENDM
Active low PHY suspend. Put PHY into Low Power Mode. In Low Power
Mode the PHY power down all blocks except the full speed receiver, OTG
comparators, and the ULPI interface pins. The PHY automatically set this bit
to '1' when Low Power Mode is exited.
RW
5
RESET
Active high transceiver reset. Does not reset the ULPI interface or ULPI
register set.
RW
RW
0
Once set, the PHY asserts the DIR signal and reset the UTMI core. When the
reset is completed, the PHY de-asserts DIR and clears this bit. After de-
asserting DIR, the PHY re-assert DIR and send an RX command update.
Note: This bit is auto-cleared, this explain why it can't be read at '1'.
Select the required bit encoding style during transmit
0x0: Normal operation
4:03
OPMODE
0x0
0x1: Non-driving
0x2: Disable bit-stuff and NRZI encoding
0x3: Reserved (No SYNC and EOP generation feature not supported)
2
TERMSELECT
XCVRSELECT
Controls the internal 1.5Kohms pull-up resistor and 45ohms HS terminations.
Control over bus resistors changes depending on XcvrSelect, OpMode,
DpPulldown and DmPulldown.
RW
RW
0
1:00
Select the required transceiver speed.
0x0: Enable HS transceiver
0x1
0x1: Enable FS transceiver
0x2: Enable LS transceiver
0x3: Enable FS transceiver for LS packets
(FS preamble is automatically pre-pended)
7.5.6 FUNC_CTRL_SET
ADDRESS OFFSET
0x05
PHYSICAL ADDRESS
0x05
INSTANCE
USB_SCUSB
22
Copyright © 2014, Texas Instruments Incorporated
TUSB1210-Q1
www.ti.com.cn
DESCRIPTION
ZHCSCV8A –SEPTEMBER 2014–REVISED OCTOBER 2014
This register doesn't physically exist.
It is the same as the func_ctrl register with read/set-only property (write '1' to set a particular bit, a write
'0' has no-action).
TYPE
RW
WRITE LATENCY
7
6
5
4
3
2
1
0
Reserved
SUSPENDM
RESET
OPMODE
TERMSELECT
XCVRSELECT
BITS
7
FIELD NAME
Reserved
DESCRIPTION
TYPE
R
RESET
0
1
6
SUSPENDM
RESET
RW
RW
RW
RW
RW
5
0
4:03
2
OPMODE
0x0
0
TERMSELECT
XCVRSELECT
1:00
0x1
7.5.7 FUNC_CTRL_CLR
ADDRESS OFFSET
PHYSICAL ADDRESS
DESCRIPTION
0x06
0x06
INSTANCE
USB_SCUSB
This register doesn't physically exist.
It is the same as the func_ctrl register with read/clear-only property (write '1' to clear a particular bit, a
write '0' has no-action).
TYPE
RW
WRITE LATENCY
7
6
5
4
3
2
1
0
Reserved
SUSPENDM
RESET
OPMODE
TERMSELECT
XCVRSELECT
BITS
FIELD NAME
Reserved
DESCRIPTION
TYPE
R
RESET
7
6
0
1
SUSPENDM
RESET
RW
RW
RW
RW
RW
5
0
4:03
2
OPMODE
0x0
0
TERMSELECT
XCVRSELECT
1:00
0x1
Copyright © 2014, Texas Instruments Incorporated
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TUSB1210-Q1
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www.ti.com.cn
7.5.8 IFC_CTRL
ADDRESS OFFSET
PHYSICAL ADDRESS
DESCRIPTION
TYPE
0x07
0x07
INSTANCE
USB_SCUSB
Enables alternative interfaces and PHY features.
RW
WRITE LATENCY
7
6
5
4
3
2
1
0
INTERFACE_P
ROTECT_DISA
BLE
INDICATORPA INDICATORCO
CLOCKSUSPE
NDM
FSLSSERIALM FSLSSERIALM
AUTORESUME
CARKITMODE
SSTHRU
MPLEMENT
ODE_3PIN
ODE_6PIN
BITS
FIELD NAME
DESCRIPTION
TYPE
RESET
7
6
5
4
INTERFACE_PROTECT_DISA Controls circuitry built into the PHY for protecting the ULPI interface when the link tri-
RW
0
BLE
states stp and data.
0b: Enables the interface protect circuit
1b: Disables the interface protect circuit
INDICATORPASSTHRU
Controls whether the complement output is qualified with the internal vbusvalid
comparator before being used in the VBUS State in the RXCMD.
RW
RW
RW
0
0
1
0b: Complement output signal is qualified with the internal VBUSVALID comparator.
1b: Complement output signal is not qualified with the internal VBUSVALID comparator.
INDICATORCOMPLEMENT
AUTORESUME
Tells the PHY to invert EXTERNALVBUSINDICATOR input signal, generating the
complement output.
0b: PHY will not invert signal EXTERNALVBUSINDICATOR (default)
1b: PHY will invert signal EXTERNALVBUSINDICATOR
Enables the PHY to automatically transmit resume signaling.
Refer to USB specification 7.1.7.7 and 7.9 for more details.
0 = AutoResume disabled
1 = AutoResume enabled (default)
3
CLOCKSUSPENDM
Active low clock suspend. Valid only in Serial Modes. Powers down the internal clock
circuitry only. Valid only when SuspendM = 1b. The PHY must ignore ClockSuspend
when SuspendM = 0b. By default, the clock will not be powered in Serial and Carkit
Modes.
RW
0
0b : Clock will not be powered in Serial and UART Modes.
1b : Clock will be powered in Serial and UART Modes.
2
1
CARKITMODE
Changes the ULPI interface to UART interface. The PHY automatically clear this field
when UART mode is exited.
RW
RW
0
0
0b: UART disabled.
1b: Enable serial UART mode.
FSLSSERIALMODE_3PIN
Changes the ULPI interface to 3-pin Serial.
The PHY must automatically clear this field when serial mode is exited.
0b: FS/LS packets are sent using parallel interface
1b: FS/LS packets are sent using 4-pin serial interface
Changes the ULPI interface to 6-pin Serial.
0
FSLSSERIALMODE_6PIN
RW
0
The PHY must automatically clear this field when serial mode is exited.
0b: FS/LS packets are sent using parallel interface
1b: FS/LS packets are sent using 6-pin serial interface
7.5.9 IFC_CTRL_SET
ADDRESS OFFSET
PHYSICAL ADDRESS
DESCRIPTION
0x08
0x08
INSTANCE
USB_SCUSB
This register doesn't physically exist.
It is the same as the ifc_ctrl register with read/set-only property (write '1' to set a particular bit, a write '0'
has no-action).
TYPE
RW
WRITE LATENCY
24
Copyright © 2014, Texas Instruments Incorporated
TUSB1210-Q1
www.ti.com.cn
7
ZHCSCV8A –SEPTEMBER 2014–REVISED OCTOBER 2014
6
5
4
3
2
1
0
INTERFACE_P INDICATORPA INDICATORCO AUTORESUME CLOCKSUSPE CARKITMODE FSLSSERIALM FSLSSERIALM
ROTECT_DISA
BLE
SSTHRU
MPLEMENT
NDM
ODE_3PIN
ODE_6PIN
BITS
FIELD NAME
DESCRIPTION
TYPE
RESET
7
6
5
4
3
2
1
0
INTERFACE_PROTECT_DISABLE
INDICATORPASSTHRU
INDICATORCOMPLEMENT
AUTORESUME
RW
RW
RW
RW
RW
RW
RW
R
0
0
0
1
0
0
0
0
CLOCKSUSPENDM
CARKITMODE
FSLSSERIALMODE_3PIN
FSLSSERIALMODE_6PIN
Copyright © 2014, Texas Instruments Incorporated
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TUSB1210-Q1
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www.ti.com.cn
7.5.10 IFC_CTRL_CLR
ADDRESS OFFSET
PHYSICAL ADDRESS
DESCRIPTION
0x09
0x09
INSTANCE
USB_SCUSB
This register doesn't physically exist.
It is the same as the ifc_ctrl register with read/clear-only property (write '1' to clear a particular bit, a
write '0' has no-action).
TYPE
RW
WRITE LATENCY
7
6
5
4
3
2
1
0
INTERFACE_P
IN
INDICATORCO AUTORESUME CLOCKSUSPE CARKITMODE FSLSSERIALM FSLSSERIALM
ROTECT_DISA DICATORPAS
MPLEMENT
NDM
ODE_3PIN
ODE_6PIN
BLE STHRU
BITS
FIELD NAME
DESCRIPTION
TYPE
RW
RW
RW
RW
RW
RW
RW
R
RESET
7
6
5
4
3
2
1
0
INTERFACE_PROTECT_DISABLE
INDICATORPASSTHRU
INDICATORCOMPLEMENT
AUTORESUME
0
0
0
1
0
0
0
0
CLOCKSUSPENDM
CARKITMODE
FSLSSERIALMODE_3PIN
FSLSSERIALMODE_6PIN
26
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TUSB1210-Q1
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ZHCSCV8A –SEPTEMBER 2014–REVISED OCTOBER 2014
7.5.11 OTG_CTRL
ADDRESS OFFSET
PHYSICAL ADDRESS
DESCRIPTION
TYPE
0x0A
0x0A
INSTANCE
USB_SCUSB
Controls UTMI+ OTG functions of the PHY.
RW
WRITE LATENCY
7
6
5
4
3
2
1
0
USEEXTERNA DRVVBUSEXT
DRVVBUS
CHRGVBUS
DISCHRGVBU DMPULLDOW DPPULLDOWN
IDPULLUP
LVBUSINDICA
TOR
ERNAL
S
N
BITS
FIELD NAME
DESCRIPTION
TYPE
RESET
7
6
5
USEEXTERNALVBUSINDICATO
R
Tells the PHY to use an external VBUS over-current indicator.
RW
0
0b: Use the internal OTG comparator (VA_VBUS_VLD) or internal VBUS valid
indicator (default)
1b: Use external VBUS valid indicator signal.
DRVVBUSEXTERNAL
Selects between the internal and the external 5 V VBUS supply.
RW
RW
0
0
0b: Pin17 (CPEN) is disabled (output GND level). TUSB1210-Q1 does not
support internal VBUS supply.
1b: Pin17 (CPEN) is set to ‘1’ (output VDD33 voltage level) if DRVVBUS bit is
‘1’, else Pin17 (CPEN) is disabled (output GND level) if DRVVBUS bit is ‘0’
DRVVBUS
VBUS output control bit
0b : do not drive VBUS
1b : drive 5V on VBUS
Note: Both DRVVBUS and DRVVBUSEXTERNAL bits must be set to 1 in order
to to set Pin17 (CPEN). CPEN pin can be used to enable an external VBUS
supply
4
3
CHRGVBUS
Charge VBUS through a resistor. Used for VBUS pulsing SRP. The Link must
first check that VBUS has been discharged (see DischrgVbus register bit), and
that both D+ and D- data lines have been low (SE0) for 2ms.
RW
RW
0
0
0b : do not charge VBUS
1b : charge VBUS
DISCHRGVBUS
Discharge VBUS through a resistor. If the Link sets this bit to 1, it waits for an
RX CMD indicating SessEnd has transitioned from 0 to 1, and then resets this
bit to 0 to stop the discharge.
0b : do not discharge VBUS
1b : discharge VBUS
2
1
0
DMPULLDOWN
DPPULLDOWN
IDPULLUP
Enables the 15k Ohm pull-down resistor on D-.
0b : Pull-down resistor not connected to D-.
1b : Pull-down resistor connected to D-.
Enables the 15k Ohm pull-down resistor on D+.
0b : Pull-down resistor not connected to D+.
1b : Pull-down resistor connected to D+.
Connects a pull-up to the ID line and enables sampling of the signal level.
0b : Disable sampling of ID line.
RW
RW
RW
1
1
0
1b : Enable sampling of ID line.
7.5.12 OTG_CTRL_SET
ADDRESS OFFSET
PHYSICAL ADDRESS
DESCRIPTION
0x0B
0x0B
INSTANCE
USB_SCUSB
This register doesn't physically exist.
It is the same as the otg_ctrl register with read/set-only property (write '1' to set a particular bit, a write
'0' has no-action).
TYPE
RW
WRITE LATENCY
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TUSB1210-Q1
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www.ti.com.cn
0
7
6
5
4
3
2
1
USEEXTERNA
LVBUSINDICA
TOR
DRVVBUSEXT
ERNAL
DISCHRGVBU DMPULLDOW
DRVVBUS
FIELD NAME
CHRGVBUS
DPPULLDOWN
IDPULLUP
S
N
BITS
DESCRIPTION
TYPE
RW
RW
RW
RW
RW
RW
RW
RW
RESET
7
6
5
4
3
2
1
0
USEEXTERNALVBUSINDICATOR
DRVVBUSEXTERNAL
DRVVBUS
0
0
0
0
0
1
1
0
CHRGVBUS
DISCHRGVBUS
DMPULLDOWN
DPPULLDOWN
IDPULLUP
28
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ZHCSCV8A –SEPTEMBER 2014–REVISED OCTOBER 2014
7.5.13 OTG_CTRL_CLR
ADDRESS OFFSET
PHYSICAL ADDRESS
DESCRIPTION
0x0C
0x0C
INSTANCE
USB_SCUSB
This register doesn't physically exist.
It is the same as the otg_ctrl register with read/Clear-only property (write '1' to clear a particular bit, a
write '0' has no-action).
TYPE
RW
WRITE LATENCY
7
6
5
4
3
2
1
0
USEEXTERNA
LVBUSINDICA
TOR
DRVVBUSEXT
ERNAL
DISCHRGVBU DMPULLDOW
DRVVBUS
FIELD NAME
CHRGVBUS
DPPULLDOWN
IDPULLUP
S
N
BITS
DESCRIPTION
TYPE
RW
RW
RW
RW
RW
RW
RW
RW
RESET
7
6
5
4
3
2
1
0
USEEXTERNALVBUSINDICATOR
DRVVBUSEXTERNAL
DRVVBUS
0
0
0
0
0
1
1
0
CHRGVBUS
DISCHRGVBUS
DMPULLDOWN
DPPULLDOWN
IDPULLUP
Copyright © 2014, Texas Instruments Incorporated
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7.5.14 USB_INT_EN_RISE
ADDRESS OFFSET
PHYSICAL ADDRESS
DESCRIPTION
0x0D
0x0D
INSTANCE
USB_SCUSB
If set, the bits in this register cause an interrupt event notification to be generated when the
corresponding PHY signal changes from low to high. By default, all transitions are enabled.
TYPE
RW
WRITE LATENCY
7
6
5
4
3
2
1
0
SESSEND_RIS SESSVALID_RI VBUSVALID_R HOSTDISCON
Reserved
Reserved
Reserved
IDGND_RISE
E
SE
ISE
NECT_RISE
BITS
FIELD NAME
Reserved
DESCRIPTION
TYPE
R
RESET
7
6
5
4
0
0
0
1
Reserved
R
Reserved
R
IDGND_RISE
Generate an interrupt event notification when IdGnd changes from
low to high.
RW
Event is automatically masked if IdPullup bit is clear to 0 and for
50ms after IdPullup is set to 1.
3
2
1
0
SESSEND_RISE
SESSVALID_RISE
Generate an interrupt event notification when SessEnd changes
from low to high.
RW
RW
RW
RW
1
1
1
1
Generate an interrupt event notification when SessValid changes
from low to high. SessValid is the same as UTMI+ AValid.
VBUSVALID_RISE
Generate an interrupt event notification when VbusValid changes
from low to high.
HOSTDISCONNECT_RISE
Generate an interrupt event notification when Hostdisconnect
changes from low to high. Applicable only in host mode
(DpPulldown and DmPulldown both set to 1b).
30
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ZHCSCV8A –SEPTEMBER 2014–REVISED OCTOBER 2014
7.5.15 USB_INT_EN_RISE_SET
ADDRESS OFFSET
PHYSICAL ADDRESS
DESCRIPTION
0x0E
0x0E
INSTANCE
USB_SCUSB
This register doesn't physically exist.
It is the same as the usb_int_en_rise register with read/set-only property (write '1' to set a particular bit,
a write '0' has no-action).
TYPE
RW
WRITE LATENCY
7
6
5
4
3
2
1
0
SESSEND_RIS SESSVALID_RI VBUSVALID_R HOSTDISCON
Reserved
BITS
Reserved
Reserved
IDGND_RISE
E
SE
TYPE
R
ISE
NECT_RISE
FIELD NAME
Reserved
DESCRIPTION
RESET
7
6
5
4
3
2
1
0
0
0
0
1
1
1
1
1
Reserved
R
Reserved
R
IDGND_RISE
SESSEND_RISE
SESSVALID_RISE
VBUSVALID_RISE
RW
RW
RW
RW
RW
HOSTDISCONNECT_RIS
E
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7.5.16 USB_INT_EN_RISE_CLR
ADDRESS OFFSET
PHYSICAL ADDRESS
DESCRIPTION
0x0F
0x0F
INSTANCE
USB_SCUSB
This register doesn't physically exist.
It is the same as the usb_int_en_rise register with read/clear-only property (write '1' to clear a particular
bit, a write '0' has no-action).
TYPE
RW
WRITE LATENCY
7
6
5
4
3
2
1
0
SESSEN
D_RISE
SESSVALID_RI VBUSVALID_R HOSTDISCON
SE ISE NECT_RISE
Reserved
BITS
Reserved
Reserved
IDGND_RISE
FIELD NAME
DESCRIPTION
TYPE
R
RESET
7
6
5
4
3
2
1
0
Reserved
Reserved
0
0
0
1
1
1
1
1
R
Reserved
R
IDGND_RISE
RW
RW
RW
RW
RW
SESSEND_RISE
SESSVALID_RISE
VBUSVALID_RISE
HOSTDISCONNECT_RISE
32
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ZHCSCV8A –SEPTEMBER 2014–REVISED OCTOBER 2014
7.5.17 USB_INT_EN_FALL
ADDRESS OFFSET
PHYSICAL ADDRESS
DESCRIPTION
0x10
0x10
INSTANCE
USB_SCUSB
If set, the bits in this register cause an interrupt event notification to be generated when the
corresponding PHY signal changes from low to high. By default, all transitions are enabled.
TYPE
RW
WRITE LATENCY
7
6
5
4
3
2
1
0
SESSEND_FA SESSVALID_F VBUSVALID_F HOSTDISCON
Reserved
BITS
Reserved
Reserved
IDGND_FALL
LL
ALL
ALL
TYPE
R
NECT_FALL
FIELD NAME
DESCRIPTION
RESET
7
6
5
4
Reserved
0
0
0
1
Reserved
R
Reserved
R
IDGND_FALL
Generate an interrupt event notification when IdGnd changes
from high to low.
RW
Event is automatically masked if IdPullup bit is clear to 0 and for
50ms after IdPullup is set to 1.
3
2
1
0
SESSEND_FALL
Generate an interrupt event notification when SessEnd changes
from high to low.
RW
RW
RW
RW
1
1
1
1
SESSVALID_FALL
VBUSVALID_FALL
HOSTDISCONNECT_FALL
Generate an interrupt event notification when SessValid changes
from high to low. SessValid is the same as UTMI+ AValid.
Generate an interrupt event notification when VbusValid changes
from high to low.
Generate an interrupt event notification when Hostdisconnect
changes from high to low. Applicable only in host mode
(DpPulldown and DmPulldown both set to 1b).
Copyright © 2014, Texas Instruments Incorporated
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TUSB1210-Q1
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7.5.18 USB_INT_EN_FALL_SET
ADDRESS OFFSET
PHYSICAL ADDRESS
DESCRIPTION
0x11
0x11
INSTANCE
USB_SCUSB
This register doesn't physically exist.
It is the same as the usb_int_en_fall register with read/set-only property (write '1' to set a particular bit, a
write '0' has no-action)
TYPE
RW
WRITE LATENCY
7
6
5
4
3
2
1
0
SESSEND_FA SESSVALID_F VBUSVALID_F HOSTDISCON
Reserved
Reserved
Reserved
IDGND_FALL
LL
ALL
ALL
TYPE
R
NECT_FALL
BITS
FIELD NAME
DESCRIPTION
RESET
7
6
5
4
3
2
1
0
Reserved
Reserved
0
0
0
1
1
1
1
1
R
Reserved
R
IDGND_FALL
RW
RW
RW
RW
RW
SESSEND_FALL
SESSVALID_FALL
VBUSVALID_FALL
HOSTDISCONNECT_FALL
34
Copyright © 2014, Texas Instruments Incorporated
TUSB1210-Q1
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ZHCSCV8A –SEPTEMBER 2014–REVISED OCTOBER 2014
7.5.19 USB_INT_EN_FALL_CLR
ADDRESS OFFSET
PHYSICAL ADDRESS
DESCRIPTION
0x12
0x12
INSTANCE
USB_SCUSB
This register doesn't physically exist.
It is the same as the usb_int_en_fall register with read/clear-only property (write '1' to clear a particular
bit, a write '0' has no-action).
TYPE
RW
WRITE LATENCY
7
6
5
4
3
2
1
0
SESSEND_FA SESSVALID_F VBUSVALID_F HOSTDISCON
Reserved
Reserved
Reserved
IDGND_FALL
LL
ALL
ALL
NECT_FALL
BITS
FIELD NAME
DESCRIPTION
TYPE
RESET
7
6
5
4
3
2
1
0
Reserved
R
0
0
0
1
1
1
1
1
Reserved
Reserved
R
R
IDGND_FALL
RW
RW
RW
RW
RW
SESSEN D_FALL
SESSVALID_FALL
VBUSVALID_FALL
HOSTDISCONNECT_FALL
Copyright © 2014, Texas Instruments Incorporated
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TUSB1210-Q1
ZHCSCV8A –SEPTEMBER 2014–REVISED OCTOBER 2014
www.ti.com.cn
7.5.20 USB_INT_STS
ADDRESS OFFSET
PHYSICAL ADDRESS
DESCRIPTION
TYPE
0x13
0x13
INSTANCE
USB_SCUSB
Indicates the current value of the interrupt source signal.
R
WRITE LATENCY
7
6
5
4
3
2
1
0
Reserved
Reserved
Reserved
IDGND
SESSEND
SESSVALID
VBUSVALID
HOSTDISCON
NECT
BITS
FIELD NAME
Reserved
DESCRIPTION
TYPE
RESET
7
6
5
4
R
R
R
R
0
0
0
0
Reserved
Reserved
IDGND
Current value of UTMI+ IdGnd output.
This bit is not updated if IdPullup bit is reset to 0 and for 50 ms after IdPullup is set to
1.
3
2
1
0
SESSEND
Current value of UTMI+ SessEnd output.
R
R
R
R
0
0
0
0
SESSVALID
VBUSVALID
Current value of UTMI+ SessValid output. SessValid is the same as UTMI+ AValid.
Current value of UTMI+ VbusValid output.
HOSTDISCONNECT Current value of UTMI+ Hostdisconnect output.
Applicable only in host mode.
Automatically reset to 0 when Low Power Mode is entered.
NOTE: Reset value is '0' when host is connected.
Reset value is '1' when host is disconnected.
36
Copyright © 2014, Texas Instruments Incorporated
TUSB1210-Q1
www.ti.com.cn
ZHCSCV8A –SEPTEMBER 2014–REVISED OCTOBER 2014
7.5.21 USB_INT_LATCH
ADDRESS OFFSET
PHYSICAL ADDRESS
DESCRIPTION
0x14
0x14
INSTANCE
USB_SCUSB
These bits are set by the PHY when an unmasked change occurs on the corresponding internal signal.
The PHY will automatically clear all bits when the Link reads this register, or when Low Power Mode is
entered. The PHY also clears this register when Serial Mode or Carkit Mode is entered regardless of the
value of ClockSuspendM.
The PHY follows the rules defined in Table 26 of the ULPI spec for setting any latch register bit. It is
important to note that if register read data is returned to the Link in the same cycle that a USB Interrupt
Latch bit is to be set, the interrupt condition is given immediately in the register read data and the Latch
bit is not set.
Note that it is optional for the Link to read the USB Interrupt Latch register in Synchronous Mode
because the RX CMD byte already indicates the interrupt source directly
TYPE
R
WRITE LATENCY
7
6
5
4
3
2
1
0
SESSEND_LA SESSVALID_L VBUSVALID_L HOSTDISCON
Reserved
Reserved
Reserved
IDGND_LATCH
TCH
ATCH
ATCH
NECT_LATCH
BITS
FIELD NAME
DESCRIPTION
TYPE
RESET
7
6
5
4
Reserved
R
R
R
R
0
0
0
0
Reserved
Reserved
IDGND_LATCH
Set to 1 by the PHY when an unmasked event occurs on IdGnd. Cleared
when this register is read.
3
2
SESSEND_LATCH
SESSVALID_LATCH
Set to 1 by the PHY when an unmasked event occurs on SessEnd.
Cleared when this register is read.
R
R
0
0
Set to 1 by the PHY when an unmasked event occurs on SessValid.
Cleared when this register is read. SessValid is the same as UTMI+
AValid.
1
0
VBUSVALID_LATCH
Set to 1 by the PHY when an unmasked event occurs on VbusValid.
Cleared when this register is read.
R
R
0
0
HOSTDISCONNECT_LAT Set to 1 by the PHY when an unmasked event occurs on
CH
Hostdisconnect. Cleared when this register is read. Applicable only in
host mode.
NOTE: As this IT is enabled by default, the reset value depends on the
host status
Reset value is '0' when host is connected.
Reset value is '1' when host is disconnected.
Copyright © 2014, Texas Instruments Incorporated
37
TUSB1210-Q1
ZHCSCV8A –SEPTEMBER 2014–REVISED OCTOBER 2014
www.ti.com.cn
7.5.22 DEBUG
ADDRESS OFFSET
PHYSICAL ADDRESS
DESCRIPTION
TYPE
0x15
0x15
INSTANCE
USB_SCUSB
Indicates the current value of various signals useful for debugging.
R
WRITE LATENCY
7
6
5
4
3
2
1
0
Reserved
LINESTATE
BITS
FIELD NAME
Reserved
DESCRIPTION
TYPE
RESET
7
6
R
R
R
R
R
R
R
0
0
Reserved
Reserved
Reserved
Reserved
Reserved
LINESTATE
5
0
4
0
3
0
2
0
1:00
These signals reflect the current state of the single ended receivers. They directly
reflect the current state of the DP (LineState[0]) and DM (LineState[1]) signals.
0x0
Read 0x0: SE0 (LS/FS), Squelch (HS/Chirp)
Read 0x1: LS: 'K' State,
FS: 'J' State,
HS: !Squelch,
Chirp: !Squelch & HS_Differential_Receiver_Output
Read 0x2: LS: 'J' State,
FS: 'K' State,
HS: Invalid,
Chirp: !Squelch & !HS_Differential_Receiver_Output
Read 0x3: SE1 (LS/FS), Invalid (HS/Chirp)
38
Copyright © 2014, Texas Instruments Incorporated
TUSB1210-Q1
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ZHCSCV8A –SEPTEMBER 2014–REVISED OCTOBER 2014
7.5.23 SCRATCH_REG
ADDRESS OFFSET
PHYSICAL ADDRESS
DESCRIPTION
0x16
0x16
INSTANCE
USB_SCUSB
Empty register byte for testing purposes. Software can read, write, set, and clear this register and the
PHY functionality will not be affected.
TYPE
RW
WRITE LATENCY
7
6
5
4
3
2
1
0
SCRATCH
BITS
FIELD NAME
DESCRIPTION
TYPE
RESET
7:00
SCRATCH
Scratch data.
RW
0x00
7.5.24 SCRATCH_REG_SET
ADDRESS OFFSET
PHYSICAL ADDRESS
DESCRIPTION
0x17
0x17
This register doesn't physically exist.
INSTANCE
USB_SCUSB
It is the same as the scratch_reg register with read/set-only property (write '1' to set a particular bit, a
write '0' has no-action).
TYPE
RW
WRITE LATENCY
7
6
5
4
3
2
1
0
SCRATCH
DESCRIPTION
BITS
FIELD NAME
SCRATCH
TYPE
RESET
7:00
RW
0x00
7.5.25 SCRATCH_REG_CLR
ADDRESS OFFSET
PHYSICAL ADDRESS
DESCRIPTION
0x18
0x18
This register doesn't physically exist.
INSTANCE
USB_SCUSB
It is the same as the scratch_reg with read/clear-only property (write '1' to clear a particular bit, a write
'0' has no-action).
TYPE
RW
WRITE LATENCY
7
6
5
4
3
2
1
0
SCRATCH
DESCRIPTION
BITS
FIELD NAME
TYPE
RESET
7:00
SCRATCH
RW
0x00
Copyright © 2014, Texas Instruments Incorporated
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TUSB1210-Q1
ZHCSCV8A –SEPTEMBER 2014–REVISED OCTOBER 2014
www.ti.com.cn
7.5.26 VENDOR_SPECIFIC1
ADDRESS OFFSET
PHYSICAL ADDRESS
DESCRIPTION
TYPE
0x3D
0x3D
INSTANCE
USB_SCUSB
Power Control register .
RW
WRITE LATENCY
7
6
5
4
3
2
1
0
MNTR_VUSBI
N_OK_EN
ABNORMALST
RESS_EN
SPARE
ID_FLOAT_EN
ID_RES_EN
BVALID_FALL BVALID_RISE
SPARE
BITS
FIELD NAME
SPARE
DESCRIPTION
Reserved. The link must never write a 1b to this bit.
TYPE
RESET
7
6
RW
RW
0
0
MNTR_VUSBIN_OK_EN When set to 1, it enables RX CMDs for high to low or low to high
transitions on MNTR_VUSBIN_OK. This bit is provided for debugging
purposes.
5
4
ID_FLOAT_EN
When set to 1, it enables RX CMDs for high to low or low to high
transitions on ID_FLOAT. This bit is provided for debugging purposes.
RW
RW
0
0
ID_RES_EN
When set to 1, it enables RX CMDs for high to low or low to high
transitions on ID_RESA, ID_RESB and ID_RESC. This bit is provided for
debugging purposes.
3
2
BVALID_FALL
BVALID_RISE
SPARE
Enables RX CMDs for high to low transitions on BVALID. When BVALID
changes from high to low, the USB TRANS will send an RX CMD to the
link with the alt_int bit set to 1b.
RW
RW
0
0
This bit is optional and is not necessary for OTG devices. This bit is
provided for debugging purposes. Disabled by default.
Enables RX CMDs for low to high transitions on BVALID. When BVALID
changes from low to high, the USB Trans will send an RX CMD to the link
with the alt_int bit set to 1b.
This bit is optional and is not necessary for OTG devices. This bit is
provided for debugging purposes. Disabled by default.
1
0
Reserved. The link must never write a 1b to this bit.
RW
RW
0
0
ABNORMALSTRESS_E When set to 1, it enables RX CMDs for low to high and high to low
N
transitions on ABNORMALSTRESS. This bit is provided for debugging
purposes.
40
Copyright © 2014, Texas Instruments Incorporated
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www.ti.com.cn
ZHCSCV8A –SEPTEMBER 2014–REVISED OCTOBER 2014
7.5.27 VENDOR_SPECIFIC1_SET
ADDRESS OFFSET
PHYSICAL ADDRESS
DESCRIPTION
0x3E
0x3E
INSTANCE
USB_SCUSB
This register doesn't physically exist.
It is the same as the func_ctrl register with read/set-only property (write '1' to set a particular bit, a write
'0' has no-action).
TYPE
RW
WRITE LATEN CY
7
6
5
4
3
2
1
0
MNTR_VUSBI
N_OK_EN
ABNORMALST
RESS_EN
SPARE
BITS
ID_FLOAT_EN
ID_RES_EN
BVALID_FALL BVALID_RISE
SPARE
FIELD NAME
DESCRIPTION
TYPE
RESET
7
6
5
4
3
2
1
0
SPARE
RW
RW
RW
RW
RW
RW
RW
RW
0
0
0
0
0
0
0
0
MNTR_VUSBIN_OK_EN
ID_FLOAT_EN
ID_RES_EN
BVALID_FALL
BVALID_RISE
SPARE
ABNORMALSTRESS_EN
Copyright © 2014, Texas Instruments Incorporated
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TUSB1210-Q1
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www.ti.com.cn
7.5.28 VENDOR_SPECIFIC1_CLR
ADDRESS OFFSET
PHYSICAL ADDRESS
DESCRIPTION
0x3F
0x3F
INSTANCE
USB_SCUSB
This register doesn't physically exist.
It is the same as the func_ctrl register with read/clear-only property (write '1' to clear a particular bit, a
write '0' has no-action).
TYPE
RW
WRITE LATENCY
7
6
5
4
3
2
1
0
MNTR_VUSBI
N_OK_EN
ABNORMALST
RESS_EN
SPARE
BITS
ID_FLOAT_EN
ID_RES_EN
BVALID_FALL BVALID_RISE
SPARE
FIELD NAME
DESCRIPTION
TYPE
RESET
7
6
5
4
3
2
1
0
SPARE
RW
RW
RW
RW
RW
RW
RW
RW
0
0
0
0
0
0
0
0
MNTR_VUSBIN_OK_EN
ID_FLOAT_EN
ID_RES_EN
BVALID_FALL
BVALID_RISE
SPARE
ABNORMALSTRESS_EN
42
Copyright © 2014, Texas Instruments Incorporated
TUSB1210-Q1
www.ti.com.cn
ZHCSCV8A –SEPTEMBER 2014–REVISED OCTOBER 2014
7.5.29 VENDOR_SPECIFIC2
ADDRESS OFFSET
PHYSICAL ADDRESS
DESCRIPTION
TYPE
0x80
0x80
INSTANCE
USB_SCUSB
Eye diagram programmability and DP/DM swap control .
RW
WRITE LATENCY
7
6
5
4
3
2
1
0
DATAPOLARIT
Y
SPARE
BITS
ZHSDRV
IHSTX
FIELD NAME
DESCRIPTION
TYPE
RESET
7
6
SPARE
RW
RW
RW
0
1
DATAPOLARITY
ZHSDRV
Control data polarity on dp/dm
5:04
High speed output impedance configuration for eye diagram tuning :
0x0
00 45.455 Ω
01 43.779 Ω
10 42.793 Ω
11 42.411 Ω
3:00
IHSTX
High speed output drive strength configuration for eye diagram tuning :
0000 17.928 mA
RW
0x1
0001 18.117 mA
0010 18.306 mA
0011 18.495 mA
0100 18.683 mA
0101 18.872 mA
0110 19.061 mA
0111 19.249 mA
1000 19.438 mA
1001 19.627 mA
1010 19.816 mA
1011 20.004 mA
1100 20.193 mA
1101 20.382 mA
1110 20.570 mA
1111 20.759 mA
IHSTX[0] is also the AC BOOST enable
IHSTX[0] = 0 à AC BOOST is disabled
IHSTX[0] = 1 à AC BOOST is enabled
Copyright © 2014, Texas Instruments Incorporated
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TUSB1210-Q1
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www.ti.com.cn
7.5.30 VENDOR_SPECIFIC2_SET
ADDRESS OFFSET
PHYSICAL ADDRESS
DESCRIPTION
0x81
0x81
INSTANCE
USB_SCUSB
This register doesn't physically exist.
It is the same as the VENDOR_SPECIFIC1 register with read/set-only property (write '1' to set a
particular bit, a write '0' has no-action).
TYPE
RW
WRITE LATENCY
7
6
5
4
3
2
1
0
DATAPOLARIT
Y
SPARE
ZHSDRV
IHSTX
BITS
7
FIELD NAME
SPARE
DESCRIPTION
TYPE
RW
RESET
0
6
DATAPOLARITY
ZHSDRV
RW
1
5:04
3:00
RW
0x0
0x1
IHSTX
RW
7.5.31 VENDOR_SPECIFIC2_CLR
ADDRESS OFFSET
PHYSICAL ADDRESS
DESCRIPTION
0x82
0x82
INSTANCE
USB_SCUSB
This register doesn't physically exist.
It is the same as the VENDOR_SPECIFIC1 register with read/clear-only property (write '1' to clear a
particular bit, a write '0' has no-action).
TYPE
RW
WRITE LATENCY
7
6
5
4
3
2
1
0
DATAPOLARIT
Y
SPARE
ZHSDRV
IHSTX
BITS
7
FIELD NAME
SPARE
DESCRIPTION
TYPE
RW
RESET
0
6
DATAPOLARITY
ZHSDRV
RW
1
5:04
3:00
RW
0x0
0x1
IHSTX
RW
44
Copyright © 2014, Texas Instruments Incorporated
TUSB1210-Q1
www.ti.com.cn
ZHCSCV8A –SEPTEMBER 2014–REVISED OCTOBER 2014
7.5.32 VENDOR_SPECIFIC1_STS
ADDRESS OFFSET
PHYSICAL ADDRESS
DESCRIPTION
TYPE
0x83
0x83
INSTANCE
USB_SCUSB
Indicates the current value of the interrupt source signal.
R
WRITE LATEN CY
7
6
5
4
3
2
1
0
MNTR_VUSBI ABNORMALST ID_FLOAT_ST
Reserved
ID_RESC_STS ID_RESB_STS ID_RESA_STS BVALID_STS
N_OK_STS
RESS_STS
S
BITS
FIELD NAME
DESCRIPTION
TYPE
R
RESET
7
6
5
4
3
2
1
0
Reserved
0
0
0
0
0
0
0
0
MNTR_VUSBIN_OK_STS
ABNORMALSTRESS_STS
ID_FLOAT_STS
Current value of MNTR_VUSBIN_OK output
Current value of ABNORMALSTRESS output
Current value of ID_FLOAT output
Current value of ID_RESC output
R
R
R
ID_RESC_STS
R
ID_RESB_STS
Current value of ID_RESB output
R
ID_RESA_STS
Current value of ID_RESA output
R
BVALID_STS
Current value of VB_SESS_VLD output
R
Copyright © 2014, Texas Instruments Incorporated
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www.ti.com.cn
7.5.33 VENDOR_SPECIFIC1_LATCH
ADDRESS OFFSET
PHYSICAL ADDRESS
DESCRIPTION
0x84
0x84
INSTANCE
USB_SCUSB
These bits are set by the PHY when an unmasked change occurs on the corresponding internal signal.
The PHY will automatically clear all bits when the Link reads this register, or when Low Power Mode is
entered. The PHY also clears this register when Serial mode is entered regardless of the value of
ClockSuspendM.
The PHY follows the rules defined in Table 26 of the ULPI spec for setting any latch register bit.
R
TYPE
WRITE LATENCY
7
6
5
4
3
2
1
0
MNTR_VUSBI ABNORMALST ID_FLOAT_LA ID_RESC_LAT ID_RESB_LAT ID_RESA_LAT BVALID_LATC
Reserved
N_OK_LATCH RESS_LATCH
TCH
CH
CH
CH
H
BITS
FIELD NAME
DESCRIPTION
TYPE RESET
7
6
Reserved
R
R
0
0
MNTR_VUSBIN_OK_LATCH
Set to 1 when an unmasked event occurs on MNTR_VUSBIN_OK_LATCH.
Clear on read register.
5
4
3
2
1
0
ABNORMALSTRESS_LATCH Set to 1 when an unmasked event occurs on ABNORMALSTRESS. Clear on
read register.
R
R
R
R
R
R
0
0
0
0
0
0
ID_FLOAT_LATCH
ID_RESC_LATCH
ID_RESB_LATCH
ID_RESA_LATCH
BVALID_LATCH
Set to 1 when an unmasked event occurs on ID_FLOAT. Clear on read
register.
Set to 1 when an unmasked event occurs on ID_RESC. Clear on read
register.
Set to 1 when an unmasked event occurs on ID_RESB. Clear on read
register.
Set to 1 when an unmasked event occurs on ID_RESA. Clear on read
register.
Set to 1 when an unmasked event occurs on VB_SESS_VLD. Clear on read
register.
46
Copyright © 2014, Texas Instruments Incorporated
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ZHCSCV8A –SEPTEMBER 2014–REVISED OCTOBER 2014
7.5.34 VENDOR_SPECIFIC3
ADDRESS OFFSET
PHYSICAL ADDRESS
DESCRIPTION
TYPE
0x85
0x85
INSTANCE
USB_SCUSB
RW
WRITE LATENCY
7
6
5
4
3
2
1
VUSB3V3_VSEL
TYPE
0
RESERVED
SOF_EN
CPEN_OD
CPEN_ODOS
IDGND_DRV
BITS
FIELD NAME
DESCRIPTION
RESET
7
6
Reserved
SOF_EN
RW
0
0
0: HS USB SOF detector disabled.
RW
1: Enable HS USB SOF detection when PHY is set in device mode.
SOF are output on CPEN pin. HS USB SOF (start-of-frame) output
clock is available on CPEN pin when this bit is set. HS USB SOF
packet rate is 8 kHz.
This bit is provided for debugging purpose only. It must never been
write to ‘1’ in functional mode
5
CPEN_OD
This bit has no effect when CPEN_ODOS = ‘0’, else :
0: CPEN pad is in OS (Open Source) mode.
RW
0
In this case CPEN pin has an internal NMOS driver, and will be active
LOW.
Externally there should be a pullup resistor on CPEN (min 1kohm) to a
supply voltage (max 3.6V).
1: CPEN pad is in OD (Open Drain) mode
In this case CPEN pin has an internal PMOS driver, and will be active
HIGH.
Externally there should be a pull-down resistor on CPEN (min 1 kΩ to
GND.
4
CPEN_ODOS
Mode selection bit for CPEN pin.
0 : CPEN pad is in CMOS mode
RW
0
1: CPEN pad is in OD (Open Drain) or OS (Open Source) mode
(controlled by CPEN_OD bit)
3
IDGND_DRV
Drives ID pin to ground
RW
RW
0x0
0x3
2:00
VUSB3V3_VSEL
000 VRUSB3P1V = 2.5 V
001 VRUSB3P1V = 2.75 V
010 VRUSB3P1V = 3.0 V
011 VRUSB3P1V = 3.10 V (default)
100 VRUSB3P1V = 3.20 V
101 VRUSB3P1V = 3.30 V
110 VRUSB3P1V = 3.40 V
111 VRUSB3P1V = 3.50 V
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www.ti.com.cn
7.5.35 VENDOR_SPECIFIC3_SET
ADDRESS OFFSET
PHYSICAL ADDRESS
DESCRIPTION
TYPE
0x86
0x86
INSTANCE
USB_SCUSB
RW
WRITE LATENCY
7
6
5
4
3
2
1
0
RESERVED
SOF_EN
CPEN_OD
CPEN_ODOS
IDGND_DRV
VUSB3V3_VSEL
BITS
FIELD NAME
DESCRIPTION
TYPE
RW
RW
RW
RW
RW
RW
RESET
7
6
Reserved
SOF_EN
0
0
5
CPEN_OD
0
4
CPEN _ODOS
IDGND_DRV
VUSB3V3_VSEL
0
3
0x0
0x3
2:00
7.5.36 VENDOR_SPECIFIC3_CLR
ADDRESS OFFSET
PHYSICAL ADDRESS
DESCRIPTION
TYPE
0x87
0x87
INSTANCE
USB_SCUSB
RW
WRITE LATENCY
7
6
5
4
3
2
1
0
RESERVED
SOF_EN
CPEN_OD
CPEN_ODOS
IDGND_DRV
DESCRIPTION
VUSB3V3_VSEL
BITS
FIELD NAME
TYPE
RW
RW
RW
RW
RW
RW
RESET
7
6
Reserved
SOF_EN
0
0
5
CPEN_OD
0
4
CPEN_ODOS
IDGND_DRV
VUSB3V3_VSEL
0
3
0x0
0x3
2:00
48
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ZHCSCV8A –SEPTEMBER 2014–REVISED OCTOBER 2014
8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
Figure 5 shows the suggested application diagram (Host or OTG, ULPI input-clock mode).
8.2 Typical Application
8.2.1 Host or OTG, ULPI Input Clock Mode Application
Figure 5 shows a suggested application diagram for TUSB1210-Q1 in the case of ULPI input-clock mode (60
MHz ULPI clock is provided by link processor), in Host or OTG application. Note this is just one example, it is of
course possible to operate as HOST or OTG while also in ULPI output-clock mode.
Link Controller
TUSB1210-Q1
V
Supply
DDIO
CS_OUT
(See Note D)
14
11
27
13
10
9
CFG
CS
RESETB
DATA7
DATA6
DATA5
RESETB
DATA7
DATA6
DATA5
DATA4
DATA3
DATA2
DATA1
DATA0
STP
(See Note A)
17
12
CPEN
7
DATA4
DATA3
DATA2
DATA1
DATA0
STP
V
6
DD15
VBUS Switch
EN
5
C
VDD15
22
4
3
29
2
V
5 V
IN OUT
BUS
NXT
NXT
3.1–5.5 V
Supply
31
1
DIR
DIR
(See Note B)
REFCLK
21
CLOCK
V
BAT
C
(See Note C)
20
BYP
26
32
V
Supply
C
CLOCK
DDIO
USB Receptacle
ESD
V
DD33
C
V
VDD33
DDIO
C
VBUS
1.8-V Supply
C
V
BUS
ID
28, 30
VDDIO
V
23
19
18
DD18
ID
25
24
16
15
8
VDD18
DM
DP
DM
DP
N/C
N/C
N/C
N/C
N/C
SHIELD
GND
(See Note E)
GND
A. Pin 11 (CS) : can be tied high to VIO if CS_OUT pin unavailable; Pin 14 (CFG) : tie-high is Don’t Care since ULPI
clock is used in input mode
B. Pin 1 (REFCLK) : must be tied low
C. Ext 3 V supply supported
D. Pin 27 (RESETB) can be tied to VDDIO if unused.
E. Pins labeled N/C (no-connect) are truly no-connect, and can be tied or left floating.
Figure 5. Host or OTG, ULPI Input Clock Mode Application Diagram
Copyright © 2014, Texas Instruments Incorporated
49
TUSB1210-Q1
ZHCSCV8A –SEPTEMBER 2014–REVISED OCTOBER 2014
www.ti.com.cn
Typical Application (continued)
8.2.1.1 Design Requirements
Table 9. Design Parameters
DESIGN PARAMETER
VBAT
EXAMPLE VALUE
3.3 V
VDDIO
1.8 V
VBUS
5.0 V
USB Support
USB On the Go (OTG)
Clock Sources
HS, FS, LS
Yes
60 MHz Clock
8.2.1.2 Detailed Design Procedure
Connect the TUSB1210 device as is shown in Figure 5.
Follow the Board Guidelines of the Application Report, SWCA124.
8.2.1.2.1 Unused Pins Connection
•
•
•
VBUS: Input. Recommended to tie to GND if unused. However leaving VBUS floating is also acceptable since
internally there is an 80 kΩ resistance to ground.
REFCLK: Input. If REFCLK is unused, and 60 MHz clock is provided by MODEM (60 MHz should be
connected to CLOCK pin in this case) then tie REFCLK to GND.
CFG: Tie to GND if REFCLK is 19.2MHz, or tie to VDDIO if REFCLK is 26 MHz. Tie to either GND or VDDIO
(doesn't matter which) if REFCLK not used (i.e., ULPI input clock configuration).
8.2.1.3 Application Curve
Figure 6. High-Speed Eye Diagram
50
Copyright © 2014, Texas Instruments Incorporated
TUSB1210-Q1
www.ti.com.cn
ZHCSCV8A –SEPTEMBER 2014–REVISED OCTOBER 2014
8.2.2 Device, ULPI Output Clock Mode Application
Figure 7 shows a suggested application diagram for TUSB1210-Q1 in the case of ULPI output clock mode (60
MHz ULPI clock is provided by TUSB1210-Q1, while link processor or another external circuit provides
REFCLK), in Device mode application. Note this is just one example, it is of course possible to operate as Device
while also in ULPI input-clock mode. Refer also to Figure 5.
Link Controller
TUSB1210-Q1
V
Supply
DDIO
CS_OUT
RESETB
(See Note D)
27
13
10
9
RESETB
14
11
CFG
CS
DATA7
DATA6
DATA5
DATA4
DATA3
DATA2
DATA1
DATA0
STP
(See Note A)
DATA7
DATA6
DATA5
DATA4
DATA3
DATA2
DATA1
DATA0
STP
7
17
12
CPEN
6
V
DD15
5
C
4
VDD15
22
3
29
2
V
NXT
BUS
NXT
31
1
DIR
DIR
3.1–5.5 V
Supply
REFCLK
CLKIN
REFCLK
21
V
BAT
(See Note B)
26
C
(See Note C)
20
BYP
CLOCK
V
Supply
C
DDIO
USB Receptacle
ESD
V
32
DD33
V
DDIO
C
1.8-V Supply
C
VDD33
C
VBUS
28, 30
VDDIO
V
V
DD18
BUS
23
19
18
ID
VDD18
25
24
16
15
8
N/C
N/C
N/C
N/C
N/C
DM
DP
DM
DP
SHIELD
GND
(See Note E)
GND
A. Pin 11 (CS) : can be tied high to VIO if CS_OUT pin unavailable; Pin 14 (CFG) : Tied to VDDIO for 26MHz REFCLK
mode here, tie to GND for 19.2MHz mode.
B. Pin 1 (REFCLK) : connect to external 3.3V square-wave reference clock
C. Ext 3 V supply supported
D. Pin 27 (RESETB) can be tied to VDDIO if unused.
E. Pins labeled N/C (no-connect) are truly no-connect, and can be tied or left floating.
Figure 7. Device, ULPI Output Clock Mode Application Diagram
Copyright © 2014, Texas Instruments Incorporated
51
TUSB1210-Q1
ZHCSCV8A –SEPTEMBER 2014–REVISED OCTOBER 2014
www.ti.com.cn
8.2.2.1 Design Requirements
Table 10. Design Parameters
DESIGN PARAMETER
VBAT
EXAMPLE VALUE
3.3 V
VDDIO
1.8 V
5.0 V
VBUS
USB Support
Clock Sources
HS, FS, LS
26 MHz or 19.2 MHz Oscillator
8.2.2.2 Detailed Design Procedure
Connect the TUSB1210 device as is shown in Figure 7.
Follow the Board Guidelines of the Application Report, SWCA124.
8.2.2.2.1 Unused Pins Connection
•
•
•
ID: Input. Leave floating if unused or TUSB1210-Q1 is Device mode only. Tie to GND through RID < 1 kOhm
if Host mode.
REFCLK: Input. If REFCLK is unused, and 60 MHz clock is provided by MODEM (60 MHz should be
connected to CLOCK pin in this case) then tie REFCLK to GND.
CFG: Tie to GND if REFCLK is 19.2MHz, or tie to VDDIO if REFCLK is 26 MHz. Tie to either GND or VDDIO
(doesn't matter which) if REFCLK not used (i.e., ULPI input clock configuration).
8.2.2.3 Application Curve
Figure 8. Full-Speed Eye Diagram
52
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TUSB1210-Q1
www.ti.com.cn
ZHCSCV8A –SEPTEMBER 2014–REVISED OCTOBER 2014
8.3 External Components
Table 11. TUSB1210-Q1 External Components
FUNCTION
COMPONENT
REFERENCE
VALUE
NOTE
LINK
VDDIO
Capacitor
CVDDIO
100 nF
Suggested value, application
dependent
Figure 5
VDD33
VDD15
VDD18
Capacitor
Capacitor
Capacitor
CVDD33
CVDD15
2.2 μF
2.2 μF
100 nF
Range: [0.45 μF : 6.5 μF] ,
ESR = [0 : 600 mΩ] for f> 10 kHz
Figure 5
Figure 5
Figure 5
Range: [0.45 μF : 6.5 μF] ,
ESR = [0 : 600 mΩ] for f> 10 kHz
Ext 1.8V supply
CVDD18
Suggested value, application
dependent
VBAT
VBUS
Capacitor
Capacitor
CBYP
100 nF(1)
Range: [0.45 μF : 6.5 μF] ,
ESR = [0 : 600 mΩ] for f> 10 kHz
Figure 5
Figure 5
CVBUS
See Table 12
Place close to USB connector
(1) Recommended value but 2.2 uF may be sufficient in some applications
Table 12. TUSB1210-Q1 VBUS Capacitors
FUNCTION
VBUS - HOST
VBUS – DEVICE
VBUS - OTG
COMPONENT
Capacitor
REFERENCE
CVBUS
VALUE
>120 μF
4.7 μF
NOTE
LINK
Figure 5
Figure 5
Figure 5
Capacitor
CVBUS
Range: 1.0 μF to 10.0 μF
Range: 1.0 μF to 6.5 μF
Capacitor
CVBUS
4.7 μF
Copyright © 2014, Texas Instruments Incorporated
53
TUSB1210-Q1
ZHCSCV8A –SEPTEMBER 2014–REVISED OCTOBER 2014
www.ti.com.cn
9 Power Supply Recommendations
VBUS, and VBAT, and VDDIO, are needed for power the TUSB1210-Q1. Recommended operation is for VBAT to be
present before VDDIO. Applying VDDIO before VBAT to TUSB1210 is not recommended as there is a diode from
VDDIO to VBAT which will be forward biased when VDDIO is present but VBAT is not present. TUSB1210-Q1 does
not strictly require VBUS to function.
9.1 TUSB1210 Power Supply
•
•
•
•
The VDDIO pins of the TUSB1210-Q1 supply 1.8 V (nominal) power to the core of the TUSB1210-Q1. This
power rail can be isolated from all other power rails by a ferrite bead to reduce noise.
The VBAT pin of the TUSB1210-Q1 supply 3.3 V (nominal) power rail to the TUSB1210-Q1. This power rail
can be isolated from all other power rails by a ferrite bead to reduce noise.
The VBUS pin of the TUSB1210-Q1 supply 5.0 V (nominal) power rail to the TUSB1210-Q1. This pin is
normally connected to the VBUS pin of the USB connector.
The VBUS pin of the TUSB1210-Q1 supply 5.0 V (nominal) power rail to the TUSB1210-Q1. This pin is
normally connected to the VBUS pin of the USB connector.
9.2 Ground
It is recommended that almost one board ground plane be used in the design. This provides the best image
plane for signal traces running above the plane. An earth or chassis ground is implemented only near the USB
port connectors on a different plane for EMI and ESD purposes.
9.3 Power Providers
Table 13 is a summary of TUSB1210-Q1 power providers.
Table 13. Power Providers(1)
TYPICAL
VOLTAGE (V)
MAXIMUM
CURRENT (mA)
NAME
USAGE
TYPE
VDD15
VDD18
VDD33
Internal
External
Internal
LDO
LDO
LDO
1.5
1.8
3.1
50
30
15
(1) VDD33 may be supplied externally, or by shorting the VDD33 pin to VBAT pin provided VBAT min is in
range [3.2 V : 3.6 V]. Note that the VDD33 LDO will always power-on when the chip is enabled,
irrespective of whether VDD33 is supplied externally or not. In the case the VDD33 pin is not supplied
externally in the application, the electrical specs for this LDO are provided below.
9.4 Power Modules
9.4.1 VDD33 Regulator
The VDD33 internal LDO regulator powers the USB PHY, charger detection, and OTG functions of the USB
subchip inside TUSB1210-Q1. Power Characteristics describes the regulator characteristics.
VDD33 regulator takes its power from VBAT
.
Since the USB2.0 standard requires data lines to be biased with pullups biased from a supply greater than 3 V,
and since VDD33 regulator has an inherent voltage drop from its input, VBAT, to its regulated output, TUSB1210-
Q1 will not meet USB 2.0 Standard if operated from
3.3 V.
a battery whose voltage is lower than
9.4.2 VDD18 Supply
The VDD18 supply is powered externally at the VDD18 pin. See Table 11 for external components.
9.4.3 VDD15 Regulator
The VDD15 internal LDO regulator powers the USB subchip inside TUSB1210-Q1. Power Characteristics
describes the regulator characteristics.
54
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TUSB1210-Q1
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ZHCSCV8A –SEPTEMBER 2014–REVISED OCTOBER 2014
9.5 Power Consumption
Table 14 describes the power consumption depending on the use cases.
NOTE
The typical power consumption is obtained in the nominal operating conditions and with
the TUSB1210-Q1 standalone.
Table 14. Power Consumption
TYPICAL
CONSUMPTION
MODE
CONDITIONS
SUPPLY
UNIT
IVBAT
IVDDIO
IVDD18
ITOTAL
IVBAT
8
3
VBAT = 3.6 V, VDDIO = 1.8 V, VDD18
= 1.8 V, CS = 0 V
OFF Mode
µA
5
16
204
3
IVDDIO
IVDD18
ITOTAL
IVBAT
VBUS = 5 V, VBAT = 3.6 V, VDDIO
1.8 V, No clock
=
Suspend Mode
µA
mA
mA
µA
3
210
24.6
1.89
21.5
48
IVDDIO
IVDD18
ITOTAL
IVBAT
HS USB Operation
(Synchronous Mode)
VBAT = 3.6 V, VDDIO = 1.8 V, VDD18
= 1.8 V, active USB transfer
25.8
1.81
4.06
31.7
237
3
IVDDIO
IVDD18
ITOTAL
IVBAT
FS USB Operation
(Synchronous Mode)
VBAT = 3.6 V, VDDIO = 1.8 V, active
USB transfer
IVDDIO
IVDD18
ITOTAL
RESETB = 0 V, VBUS = 5 V, VBAT
= 3.6 V, VDDIO = 1.8 V, No clock
Reset Mode
3
243
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TUSB1210-Q1
ZHCSCV8A –SEPTEMBER 2014–REVISED OCTOBER 2014
www.ti.com.cn
10 Layout
10.1 Layout Guidelines
•
•
•
•
The VDDIO pins of the TUSB1210-Q1 supply 1.8-V (nominal) power to the core of the TUSB1210-Q1. This
power rail can be isolated from all other power rails by a ferrite bead to reduce noise.
The VBAT pin of the TUSB1210-Q1 supply 3.3-V (nominal) power rail to the TUSB1210-Q1. This power rail
can be isolated from all other power rails by a ferrite bead to reduce noise.
The VBUS pin of the TUSB1210-Q1 supply 5-V (nominal) power rail to the TUSB1210-Q1. This pin is normally
connected to the VBUS pin of the USB connector.
All power rails require 0.1 μF decoupling capacitors for stability and noise immunity. The smaller decoupling
capacitors should be placed as close to the TUSB1210-Q1 power pins as possible with an optimal grouping
of two of differing values per pin.
10.2 Layout Example
Figure 9. TUSB1210-Q1 Layout Example
56
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TUSB1210-Q1
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ZHCSCV8A –SEPTEMBER 2014–REVISED OCTOBER 2014
11 器件和文档支持
11.1 文档支持
SLLZ066
芯片勘误表。 描述了 TUSB1210-Q1 功能技术规格的已知例外情况。
11.2 社区资源
下列链接提供到 TI 社区资源的连接。 链接的内容由各个分销商“按照原样”提供。 这些内容并不构成 TI 技术规范和
标准且不一定反映 TI 的观点；请见 TI 的使用条款。
TI E2E™ 在线社区 TI 工程师对工程师 (E2E) 社区。 此社区的创建目的是为了促进工程师之间协作。 在
e2e.ti.com 中，您可以咨询问题、共享知识、探索思路，在同领域工程师的帮助下解决问题。
德州仪器 (TI) 嵌入式处理器维基网站 德州仪器 (TI) 嵌入式处理器维基网站。 此网站的建立是为了帮助开发人员从
德州仪器 (TI) 的嵌入式处理器入门并且也为了促进与这些器件相关的硬件和软件的总体知识的创新和
增长。
11.3 商标
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.4 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
11.5 术语表
11.5.1 术语表
SLYZ022 — TI 术语表。
这份术语表列出并解释术语、首字母缩略词和定义。
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TUSB1210-Q1
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12 机械封装和可订购信息
12.1 Via Channel
T 封装采用 Via Channel 技术进行了特别设计。 这使得 PCB 设计中能够采用 0.65mm 间距封装，实现比正常尺寸
更大的 PCB 过孔和布线，从而减小 PCB 信号层数，并大幅降低 PCB 成本。 由于 Via Channel BGA 技术提升了
分层效率，因此该器件允许仅在两个信号层（共四层）中进行 PCB 布线。
利用 [所用封装] 封装中实施的 Via Channel 技术可构建基于 [所用器件] 的产品，该产品采用 4 层 PCB 设计，但这
可能达不到系统性能目标要求。 因此，产品设计期间必须对采用 4 层 PCB 设计的系统的性能进行评估。
12.2 封装信息
以下页中包括机械封装和可订购信息。 这些信息是针对指定器件可提供的最新数据。 这些数据会在无通知且不对
本文档进行修订的情况下发生改变。 欲获得该数据表的浏览器版本，请查阅左侧的导航栏。
58
版权 © 2014, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
23-Apr-2022
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TUSB1210BRHBRQ1
TUSB1210BRHBTQ1
ACTIVE
ACTIVE
VQFN
VQFN
RHB
RHB
32
32
3000 RoHS & Green
250 RoHS & Green
NIPDAUAG
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 85
-40 to 85
T1210Q1
T1210Q1
NIPDAUAG
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
23-Apr-2022
OTHER QUALIFIED VERSIONS OF TUSB1210-Q1 :
Catalog : TUSB1210
•
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
•
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Apr-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TUSB1210BRHBRQ1
TUSB1210BRHBTQ1
VQFN
VQFN
RHB
RHB
32
32
3000
250
330.0
180.0
12.4
12.4
5.3
5.3
5.3
5.3
1.1
1.1
8.0
8.0
12.0
12.0
Q2
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Apr-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TUSB1210BRHBRQ1
TUSB1210BRHBTQ1
VQFN
VQFN
RHB
RHB
32
32
3000
250
346.0
210.0
346.0
185.0
33.0
35.0
Pack Materials-Page 2
GENERIC PACKAGE VIEW
RHB 32
5 x 5, 0.5 mm pitch
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224745/A
www.ti.com
PACKAGE OUTLINE
RHB0032E
VQFN - 1 mm max height
S
C
A
L
E
3
.
0
0
0
PLASTIC QUAD FLATPACK - NO LEAD
5.1
4.9
B
A
PIN 1 INDEX AREA
(0.1)
5.1
4.9
SIDE WALL DETAIL
20.000
OPTIONAL METAL THICKNESS
C
1 MAX
SEATING PLANE
0.08 C
0.05
0.00
2X 3.5
(0.2) TYP
3.45 0.1
9
EXPOSED
THERMAL PAD
16
28X 0.5
8
17
SEE SIDE WALL
DETAIL
2X
SYMM
33
3.5
0.3
0.2
32X
24
0.1
C A B
C
1
0.05
32
25
PIN 1 ID
(OPTIONAL)
SYMM
0.5
0.3
32X
4223442/B 08/2019
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
RHB0032E
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(
3.45)
SYMM
32
25
32X (0.6)
1
24
32X (0.25)
(1.475)
28X (0.5)
33
SYMM
(4.8)
(
0.2) TYP
VIA
8
17
(R0.05)
TYP
9
16
(1.475)
(4.8)
LAND PATTERN EXAMPLE
SCALE:18X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4223442/B 08/2019
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
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EXAMPLE STENCIL DESIGN
RHB0032E
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
4X ( 1.49)
(0.845)
(R0.05) TYP
32
25
32X (0.6)
1
24
32X (0.25)
28X (0.5)
(0.845)
SYMM
33
(4.8)
17
8
METAL
TYP
16
9
SYMM
(4.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 33:
75% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:20X
4223442/B 08/2019
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
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