TUSB212RWBT [TI]
具有直流升压功能的 USB 2.0 高速信号调节器 | RWB | 12 | 0 to 70;
| 型号： | TUSB212RWBT |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有直流升压功能的 USB 2.0 高速信号调节器 | RWB | 12 | 0 to 70 电信 电信集成电路 调节器 |
| 文件： | 总27页 (文件大小：1455K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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TUSB212
ZHCSGM7A –AUGUST 2017–REVISED SEPTEMBER 2017
TUSB212 USB 2.0 高速信号调节器
1 特性
3 说明
1
•
•
•
•
•
•
•
与 USB 2.0、OTG 2.0 和 BC 1.2 兼容
TUSB212 是一款 USB 高速 (HS) 信号调节器，专为补
引脚搭接或可通过 I2C 进行配置
偿传输通道中的 ISI 信号损失而设计。
支持 LS、FS 和 HS 信号传输
TUSB212 采用了对 USB 低速 (LS) 和全速 (FS) 信号
无感知的设计，该设计正在申请专利。LS 和 FS 信号
特征不受 TUSB212 的影响，但该器件会对 HS 信号进
行补偿。
超低 USB 断开和关断功耗
在高损耗应用中通过菊花链设备实现可选信号 增益
D1P/M 和 D2P/M 可互换且主机/设备不可知
支持长达 5 米的通道前或 2 米的通道后电缆长度
借助可编程信号交流升压和直流升压，可精调器件性
能，从而优化连接器上的高速信号。这有助于通过
USB 高速电气合规性测试。
–
–
通过外部下拉电阻器实现四种可选交流升压设置
直流升压与交流升压，可实现最佳信号完整性
2 应用
此外，TUSB212 符合 USB On-The-Go (OTG) 和电池
充电 (BC) 协议。
•
•
•
•
•
•
•
•
笔记本电脑
台式机
器件信息 (1)
扩展坞
器件型号
TUSB212
TUSB212I
封装
封装尺寸（标称值）
平板电脑
X2QFN (12)
1.60mm x 1.60mm
手机
有源电缆、电缆扩展器
(1) 如需了解所有可用封装，请参阅产品说明书末尾的可订购产品
附录。
背板
电视
简化的原理图
3.3 V
VCC
D1
USB
Host
USB
Connector
Cable
D2
GND
Copyright © 2017, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SLLSEX5
TUSB212
ZHCSGM7A –AUGUST 2017–REVISED SEPTEMBER 2017
www.ti.com.cn
目录
7.4 Device Functional Modes.......................................... 8
Application and Implementation ........................ 10
8.1 Application Information............................................ 10
8.2 Typical Application ................................................. 10
Power Supply Recommendations...................... 17
1
2
3
4
5
6
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings.............................................................. 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information.................................................. 4
6.5 Electrical Characteristics........................................... 5
6.6 Switching Characteristics.......................................... 6
6.7 Typical Characteristics.............................................. 7
Detailed Description .............................................. 8
7.1 Overview ................................................................... 8
7.2 Functional Block Diagram ......................................... 8
7.3 Feature Description................................................... 8
8
9
10 Layout................................................................... 18
10.1 Layout Guidelines ................................................. 18
10.2 Layout Example .................................................... 18
11 器件和文档支持 ..................................................... 19
11.1 文档支持 ............................................................... 19
11.2 接收文档更新通知 ................................................. 19
11.3 社区资源................................................................ 19
11.4 商标....................................................................... 19
11.5 静电放电警告......................................................... 19
11.6 Glossary................................................................ 19
12 机械、封装和可订购信息....................................... 19
7
4 修订历史记录
注：之前版本的页码可能与当前版本有所不同。
Changes from Original (August 2017) to Revision A
Page
•
Changed Note From: Pull-up resistors for SDA and SCL pins in I2C mode should be 2 kΩ (5%). To: Pull-up resistors
for SDA and SCL pins in I2C mode should be 4.7 kΩ (5%) in the Pin Functions table.......................................................... 3
•
•
•
•
Added Test Conditions to RSTN: VIH and VIL in the Electrical Characteristics table.............................................................. 5
Added new parameters to SCL/SDA: VIH, VIL, VSDA_OL, ISDA_OL the Electrical Characteristics table ..................................... 5
Added Test Conditions To: DC_BOOST: VIH, VIM, and VIL the Electrical Characteristics table ............................................. 5
Added test conditions to trise_dxx and tfall_dxx in the Switching Characteristics table ................................................................. 6
2
Copyright © 2017, Texas Instruments Incorporated
TUSB212
www.ti.com.cn
ZHCSGM7A –AUGUST 2017–REVISED SEPTEMBER 2017
5 Pin Configuration and Functions
RWB Package
12 Pin (X2QFN)
Top View
D1P D1M
VCC
3
4
5
6
12
SDA
SCL/CD
RSTN
EQ
2
1
11 VREG
10 GND
DC_BOOST/
ENA_HS
7
8
9
D2P D2M
Pin Functions
PIN
INTERNAL
PULLUP/PULLDOWN
I/O
DESCRIPTION
NAME
D1M
NO.
1
I/O
I/O
N/A
N/A
USB High Speed negative port..
USB High Speed positive port.
I2C Mode:
D1P
2
Bidirectional I2C data pin [I2C address = 0x2C].
In non I2C mode:
Reserved for TI test purpose.
SDA(1)
3
4
I/O
RSTN asserted: 500 kΩ PD
In I2C mode:
I2C clock pin [I2C address = 0x2C].
Non I2C mode:
After reset: Output CD. Flag indicating that a USB device is attached (connection
detected). Asserted from an unconnected state upon detection of DP or DM pull-up
resistor. De-asserted upon detection of disconnect.
SCL(1)/CD
I/O
RSTN asserted: 500 kΩ PD
Device disable/enable.
Low – Device is at reset and in shutdown, and
High – Normal operation.
RSTN
EQ
5
6
I
I
500 kΩ PU
Recommend 0.1-µF external capacitor to GND to ensure clean power on reset if not
driven.
If the pin is driven, it must be held low until the supply voltage for the device reaches
within specifications.
USB High Speed AC boost select via external pull down resistor.
Sampled upon de-assertion of RSTN. Does not recognize real time adjustments.
Auto selects max AC Boost when left floating.
N/A
D2P
D2M
7
8
I/O
I/O
N/A
N/A
USB High Speed positive port.
USB High Speed negative port.
In I2C mode:
Reserved for TI test purpose.
In non-I2C mode:
At reset: 3-level input signal DC_BOOST. USB High Speed DC signal boost selection.
H (pin is pulled high) – 80 mV
M (pin is left floating) – 60 mV
L (pin is pulled low) – 40 mV
After reset: Output signal ENA_HS. Flag indicating that channel is in High Speed mode.
Asserted upon:
DC_BOOST(2)
ENA_HS
/
9
I/O
1. Detection of USB-IF High Speed test fixture from an unconnected state followed by
transmission of USB TEST_PACKET pattern.
2. Squelch detection following USB reset with a successful HS handshake [HS
handshake is declared to be successful after single chirp J chirp K pair where each chirp
is within 18 μs – 128 μs].
GND
VREG
VCC
10
11
12
P
O
P
N/A
N/A
N/A
Ground
1.8-V LDO output. Only enabled when operating in High Speed mode. Requires 0.1-µF
external capacitor to GND to stabilize the core.
Supply power
(1) Pull-up resistors for SDA and SCL pins in I2C mode should be 4.7 kΩ (5%). If both SDA and SCL are pulled up at reset the device
enters into I2C mode.
(2) Pull-down and pull-up (to 3.3 V) resistors for DC_BOOST pins must be between 22 kΩ to 47 kΩ in non I2C mode.
Copyright © 2017, Texas Instruments Incorporated
3
TUSB212
ZHCSGM7A –AUGUST 2017–REVISED SEPTEMBER 2017
www.ti.com.cn
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature and voltage range (unless otherwise noted)(1)
MIN
MAX
UNIT
Supply Voltage
VCC
-0.3
3.8
V
Range
Voltage Range
DxP, DxM, RSTN, EQ, SCL, SDA, DC_BOOST, VREG
on I/O pins
-0.3
-65
3.8
V
Tstg
Storage temperature
150
°C
(1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
UNIT
Human body model (HBM), per
±2000
ANSI/ESDA/JEDEC JS-001, all pins(1)
V(ESD)
Electrostatic discharge
V
Charged device model (CDM), per JEDEC
specification JESD22-C101, all pins(2)
±500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature and voltage range (unless otherwise noted)
MIN
3
NOM
MAX
3.6
70
UNIT
V
VCC
TA
Supply Voltage
3.3
TUSB212
TUSB212I
TUSB212
TUSB212I
0
°C
Ambient temperature
-40
0
85
°C
85
°C
TJ
Junction temperature
-40
105
°C
6.4 Thermal Information
TUSB212
RWB (VQFN)
12 PINS
137.4
THERMAL METRIC(1)
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
62
67.2
ΨJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
1.9
ΨJB
67.3
RθJC(bot)
N/A
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
4
版权 © 2017, Texas Instruments Incorporated
TUSB212
www.ti.com.cn
ZHCSGM7A –AUGUST 2017–REVISED SEPTEMBER 2017
6.5 Electrical Characteristics
over operating free-air temperature and voltage range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
POWER
USB channel = HS mode; 480 Mbps
traffic; VCC = 3.3V; VCC supply stable;
DC Boost = 60 mV
IACTIVE_H
S
High-speed (HS) active curent
High-speed idle current
22
14
30
22
mA
mA
USB channel = HS mode; no traffic; VCC
= 3.3V; VCC supply stable; DC Boost =
60 mV
IIDLE_HS
ISUSPEND
_HS
USB channel = HS suspend mode; VCC
= 3.3V; VCC supply stable
High-speed suspend current
Full/Low speed current
Disconnect current
0.55
0.6
0.7
13
1.5
1.5
1.5
80
mA
mA
mA
µA
USB channel = FS mode or LS mode;
VCC = 3.3V
IFS_LS
IDISCONN
ECT
Host side application; No device
attachment; VCC = 3.3V
RSTN driven low; VCC supply stable; VCC
= 3.3V
IRSTN
Disable current
Pin fail-safe leakage current for SDA,
SCL, DC_BOOST, DxP/N, RSTN
ILKG_FS
VCC = 0 V; Pin at 3.6 V
40
µA
RSTN
VIH
VIL
High-level input voltage
Low-level input voltage
High-level input current
Low-level input current
VCC = 3.0V
VCC = 3.6V
VIH = 3.6 V
VIL = 0 V
2
0
3.6
0.8
4
V
V
IIH
-4
µA
µA
IIL
-11
11
EQ
AC Boost Level 0
AC Boost Level 1
AC Boost Level 2
AC Boost Level 3
160
2
Ω
1.4
3.7
6
kΩ
kΩ
kΩ
REQ
External pull-down resistor on EQ pin.
3.9
CD, ENA_HS
VOH
High-level output voltage
IO = -50µA
IO = 50µA
2.4
V
V
VOL
Low-level output voltage
0.4
SCL, SDA
CI2CBUS
VIH
I2C Bus capacitance
4
2
150
3.6
0.8
0.4
pF
V
SDA and SCL input high level voltage
SDA and SCL input low level voltage
VCC = 3.0V
VIL
VCC = 3.6V
V
VSDA_OL SDA low level output voltage
ISDA_OL SDA low level output current
DC_BOOST
4.7kΩ pullup to 3.6V; VCC = 3.0V
VCC = 3.6V
V
1.1
2.4
0
mA
VIH
High-level input voltage
VCC = 3.3V
VCC = 3.3V
VCC = 3.3V
3.6
0.4
V
V
V
VIM
Mid-level input voltage
Low-level input voltage
1.6
2.4
VIL
DxP, DxM
Measured with LCR meter and device
powered down. 1 MHz sinusoid, 30
mVpp ripple
CIO_DXX Capacitance to GND
pF
版权 © 2017, Texas Instruments Incorporated
5
TUSB212
ZHCSGM7A –AUGUST 2017–REVISED SEPTEMBER 2017
www.ti.com.cn
6.6 Switching Characteristics
over operating free-air temperature and voltage range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
480.24
UNIT
USB channel = HS mode; 480 Mbps
traffic; VCC supply stable
FBR_DXX DxP/M bit rate
Mbps
tRISE_DXX DxP/M rise time
10% - 90%; VCC = 3.6V; Max AC Gain;
90% - 10%; VCC = 3.6V; Max AC Gain;
100
100
ps
ps
tFALL_DXX DxP/M fall time
tRSTN_PU Minimum width to detect a valid RSTN
signal assert when the pin is actively
driven
VCC = 3.0 V; Refer to 图 1
Refer to 图 1
20
µs
LSE_WIDT
H
tSTABLE
VCC stable before RSTN de-assertion
100
0.2
µs
tVCC_RAM
P
VCC ramp time
100
ms
tRSTN_PULSE_WIDTH
RSTN
VIL(MAX)
tSTABLE
VCC(MIN)
VCC
图 1. Power On and Reset Timing
6
版权 © 2017, Texas Instruments Incorporated
TUSB212
www.ti.com.cn
ZHCSGM7A –AUGUST 2017–REVISED SEPTEMBER 2017
6.7 Typical Characteristics
图 2. USB2.0 HS Eye Diagram, Host far-end with 2m cable
图 3. USB 2.0 HS Eye Diagram, Host far-end with 2m cable
post-channel loss without TUSB212
post-channel loss with TUSB212
图 4. USB2.0 HS Eye Diagram, Host far-end with 5m cable
图 5. USB2.0 HS Eye Diagram, Host far-end with 5m cable
pre-channel loss without TUSB212
pre-channel loss with TUSB212
版权 © 2017, Texas Instruments Incorporated
7
TUSB212
ZHCSGM7A –AUGUST 2017–REVISED SEPTEMBER 2017
www.ti.com.cn
7 Detailed Description
7.1 Overview
The TUSB212 is a USB High-Speed (HS) signal conditioner, designed to compensate for ISI signal loss in a
transmission channel. TUSB212 has a patent-pending design which is agnostic to USB Low Speed (LS) and Full
Speed (FS) signals and does not alter their signal characteristics, while HS signals are compensated. In addition,
the design is compatible with USB On-The-Go (OTG) and Battery Charging (BC) specifications.
Programmable signal gain through an external resistor permits fine tuning device performance to optimize signals
helping to pass USB HS electrical compliance tests at the connector. Additional DC boost configurable by three
level input DC_BOOST helps overcoming the cable losses.
The footprint of TUSB212 allows a board layout using this device such that it does not break the continuity of the
DP/DM signal traces. This permits risk free system design of a complete USB channel with flexible use of one or
multiple TUSB212 devices as needed for optimal signal integrity. This allows system designers to plan for this
device and use it only if signal integrity analysis and/or lab measurements sow a need. If such a need is not
warranted, the device can be left unpopulated without any board rework.
7.2 Functional Block Diagram
Low and Full
Speed Bypass
D1P
D1M
D2P
D2M
USB
TRANSCEIVER
High Speed
Compensation
ESD
PROTECTION
USB
CONNECTOR
CD
OPTIONAL
PLD
Status Flags
ENA_HS
7.3 Feature Description
7.3.1 EQ
The EQ pin of the TUSB212 is used to configure the AC boost of the device. The four levels are set through
different values of an external pulldown resistor at this pin.
7.3.2 DC BOOST
The DC_BOOST pin of the TUSB212 is a tri-level pin, used to set the DC gain of the device according to 表 1.
表 1. DC Boost Settings
DC BOOST SETTING VIA PIN STRAP
DC_BOOST
DC Boost Setting (mV)
VIL
VIM
VIH
40
60
80
7.4 Device Functional Modes
7.4.1 Low Speed (LS) Mode
TUSB212 automatically detects a LS connection and does not enable signal compensation. CD pin is asserted
high.
8
版权 © 2017, Texas Instruments Incorporated
TUSB212
www.ti.com.cn
ZHCSGM7A –AUGUST 2017–REVISED SEPTEMBER 2017
Device Functional Modes (接下页)
7.4.2 Full Speed (FS) Mode
TUSB212 automatically detects a FS connection and does not enable signal compensation. CD pin is asserted
high.
7.4.3 High Speed (HS) Mode
TUSB212 automatically detects a HS connection and will enable signal compensation as determined by the
configuration of the DC_BOOST pin and the external pulldown resistance on its EQ pin. CD pin is asserted high.
7.4.4 Shutdown Mode
TUSB212 is disabled when its RSTN pin is asserted low. In shutdown mode the USB channel is still fully
operational, but there is neither signal compensation nor any indication from the CD pin as to the status of the
channel.
7.4.5 I2C Mode
TUSB213 supports 100 kHz I2C for device configuration, status readback and test purposes. This controller is
enabled after SCL and SDA pins are sampled high shortly after de-assertion of RSTN. In this mode, the register
as described in 表 2 can be accessed by I2C read/write transaction to 7-bit slave address 0x2C. It is necessary to
set CFG_ACTIVE bit and reset it to zero after making changes to the EQ and DC Boost level registers to restart
the state machine.
注
All registers or fields in 表 2 which are not specifically mentioned are considered reserved.
The default value of these reserved registers or fields must not be changed. It is
suggested to perform a read-modify-write operation to maintain the default value of the
reserved fields.
表 2. Register definition
Offset
Bit(s)
Name
Type
Default
Description
Sets the level of AC Boost
000 : Level 0 AC Boost programmed [MIN]
001 : Level 1 AC Boost programmed
011 : Level 2 AC Boost programmed
111 : Level 3 AC Boost programmed [MAX]
XXX (Sampled from EQ
pin at reset)
0x01
6:4
ACB_LVL
RW
Configuration mode
0 : Normal mode. State machine enabled.
1 : Configuration mode: State machine disabled.
0x03
0x0E
0
CFG_ACTIVE
DCB_LVL
RW
RW
1b
After reset, if I2C mode is true (SCL and SDA are
both pulled high) it is maintained until it is cleared
by an I2C write, but, if I2C mode is not true, it is
cleared automatically.
Sets the level of DC Boost
XXX (Sampled from
DC_BOOST pin at reset)
011 : 40mV (DC_Boost = L)
101 : 60mV (DC_Boost = M, default)
111 : 80mV (DC_Boost = H)
2:0
版权 © 2017, Texas Instruments Incorporated
9
TUSB212
ZHCSGM7A –AUGUST 2017–REVISED SEPTEMBER 2017
www.ti.com.cn
8 Application and Implementation
注
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The primary purpose of the TUSB212 is to re-store the signal integrity of a USB High Speed channel up to the
USB receptacle. The loss in signal quality stems from reduced channel bandwidth due to high loss PCB trace
and other components that contribute a capacitive load. This can cause the channel to fail the USB near end eye
mask. Proper use of the TUSB212 can help to pass this eye mask.
A secondary purpose is to use the CD pin of the TUSB212 to control other blocks on the customer platform if so
desired.
8.2 Typical Application
A typical application is shown in 图 6. In this setup, D2P and D2M face the USB connector while D1P and D1M
face the USB host. If desired, the orientation may be reversed [that is, D2 faces transceiver and D1 faces
connector].
D1M
D1P
D2M
D2P
USB
Host or Hub
Copyright © 2017, Texas Instruments Incorporated
图 6. Typical Application
8.2.1 Design Requirements
For this design example, use parameters shown in the table below.
表 3. Design Parameters
PARAMETER
VALUE
VCC (3.0V to 3.6V)
I2C support required in system (Yes/No)
3.3 V
No
REQ
Level
0 Ω
0
1
2
3
AC Boost Level 2:
REQ = 3.83 K
AC Boost
1.69 k ±1%
3.83 k ±1%
DNI
10
版权 © 2017, Texas Instruments Incorporated
TUSB212
www.ti.com.cn
ZHCSGM7A –AUGUST 2017–REVISED SEPTEMBER 2017
Typical Application (接下页)
表 3. Design Parameters (接下页)
PARAMETER
VALUE
RDC1
RDC2
Level
Mid DC Level:
RDC1 = DNI
RDC2 = DNI
22 kΩ - 47 kΩ
Do Not Install (DNI)
DNI
40 mV Low DC Boost
60 mV Mid DC Boost
80 mV High DC Boost
DC Boost
DNI
DNI
22 kΩ - 47 kΩ
8.2.2 Detailed Design Procedure
TUSB212 requires a valid reset signal as described in the power supply recommendations section. The capacitor
at RSTN pin is not required if a microcontroller drives the RSTN pin according to recommendations.
VREG pin is the internal LDO output that requires a 0.1-μF external capacitor to GND to stabilize the core.
The ideal AC/DC Boost setting is dependent upon the signal chain loss characteristics of the target platform. The
general recommendation is to start with AC Boost level 0, and then increment to AC Boost level 1, etc. when
needed. Same applies to the DC boost setting where it is recommended to plan for the required pad to change
boost settings.
In order for the TUSB212 to recognize any change to the AC or DC boost settings, the RSTN pin must be
toggled. This is because the EQ and DC_BOOST pins are latched on power up and the pins are ignored
thereafter.
Further D1P has to be shorted to D2P and D1M shorted to D2M on the board for correct functionality of the
device.
Placement of the device is also dependent on the application goal. 表 4 summarizes our recommendations.
表 4. Platform Placement Guideline
PLATFORM GOAL
Pass USB Near End Mask
SUGGESTED TUSB212 PLACEMENT
Close to measurement point
Pass USB Far End Eye Mask
Close to USB PHY
Cascade multiple TUSB212 to improve device enumeration
Midway between each USB interconnect
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11
TUSB212
ZHCSGM7A –AUGUST 2017–REVISED SEPTEMBER 2017
www.ti.com.cn
+3.3 V
100 nF
1 mF
REQ
100 nF
+3.3 V
RDC2
RDC1
SCL/CD
VCC
SDA
D1P
D1N
DCBOOST/ENA_HS
USB_DP
USB_DP
USB_DN
D2P
D2M
USB
Host or Hub
USB_DN
100 nF
Copyright © 2017, Texas Instruments Incorporated
D2P must be shorted to D1P on PCB.
D2N must be shorted to D1N on PCB.
图 7. Reference Schematic
8.2.2.1 Test Procedure to Construct USB High Speed Eye Diagram
注
USB-IF certification tests for High Speed eye masks require the mandated use of the
USB-IF developed test fixtures. These test fixtures do not require the use of oscilloscope
probes. Instead they use SMA cables. More information can be found at the USB-IF
Compliance Updates Page. It is located under the ‘Electricals’ section, ID 86 dated March
2013.
The following procedure must be followed before using any oscilloscope compliance software to construct a USB
High Speed Eye Mask:
8.2.2.1.1 For a Host Side Application
1. Configure the TUSB212 to the desired AC and DC boost settings.
2. Power on (or toggle the RSTN pin if already powered on) the TUSB212
3. Using SMA cables, connect the oscilloscope and the USB-IF host-side test fixture to the TUSB212
4. Enable the host to transmit USB TEST_PACKET
5. Execute the oscilloscope USB compliance software.
6. Repeat the above steps in order to re-test TUSB212 with different AC and DC boost settings.
12
版权 © 2017, Texas Instruments Incorporated
TUSB212
www.ti.com.cn
ZHCSGM7A –AUGUST 2017–REVISED SEPTEMBER 2017
8.2.2.1.2 For a Device Side Application
1. Configure the TUSB212 to the desired AC and DC boost settings.
2. Power on (or toggle the RSTN pin if already powered on) the TUSB212
3. Connect a USB host, the USB-IF device-side test fixture, and USB device to the TUSB212. Ensure that the
USB-IF device test fixture is configured to the ‘INIT’ position
4. Allow the host to enumerate the device
5. Enable the device to transmit USB TEST_PACKET
6. Using SMA cables, connect the oscilloscope to the USB-IF device-side test fixture and ensure that the
device-side test fixture is configured to the ‘TEST’ position.
7. Execute the oscilloscope USB compliance software.
8. Repeat the above steps in order to re-test TUSB212 with different AC and DC boost settings.
版权 © 2017, Texas Instruments Incorporated
13
TUSB212
ZHCSGM7A –AUGUST 2017–REVISED SEPTEMBER 2017
www.ti.com.cn
8.2.3 Application Curves
TUSB21xEVM
2m USB A-B Cable
DP
Lecroy 25 GHz Scope
1m SMA to SMA cables
USB Host
DM
USBIF Compliance
Test Fixture
图 8. Eye Diagram Bench Setup
图 9. No TUSB212
14
版权 © 2017, Texas Instruments Incorporated
TUSB212
www.ti.com.cn
ZHCSGM7A –AUGUST 2017–REVISED SEPTEMBER 2017
图 11. Mid DC Boost, AC Boost Level 0
图 10. Low DC Boost, AC Boost Level 0
图 13. Low DC Boost, AC Boost Level 1
图 12. High DC Boost, AC Boost Level 0
图 14. Mid DC Boost, AC Boost Level 1
图 15. High DC Boost, AC Boost Level 1
版权 © 2017, Texas Instruments Incorporated
15
TUSB212
ZHCSGM7A –AUGUST 2017–REVISED SEPTEMBER 2017
www.ti.com.cn
图 17. Mid DC Boost, AC Boost Level 2
图 16. Low DC Boost, AC Boost Level 2
图 18. High DC Boost, AC Boost Level 2
图 19. Low DC Boost, AC Boost Level 3
图 20. Mid DC Boost, AC Boost Level 3
图 21. High DC Boost, AC Boost Level 3
16
版权 © 2017, Texas Instruments Incorporated
TUSB212
www.ti.com.cn
ZHCSGM7A –AUGUST 2017–REVISED SEPTEMBER 2017
9 Power Supply Recommendations
On power up, the interaction of the RSTN pin and power on ramp could result in digital circuits not being set
correctly. The device should not be enabled until the power on ramp has settled to 3 V or higher to ensure a
correct power on reset of the digital circuitry. If RSTN cannot be held low by microcontroller or other circuitry until
the power on ramp has settled, then an external capacitor from the RSTN pin to GND is required to hold the
device in the low power reset state.
The RC time constant should be larger than five times of the power on ramp time (0 to VCC). With a typical
internal pullup resistance of 500 kΩ, the recommended minimum external capacitance is calculated as:
[Ramp Time x 5] ÷ [500 kΩ]
(1)
版权 © 2017, Texas Instruments Incorporated
17
TUSB212
ZHCSGM7A –AUGUST 2017–REVISED SEPTEMBER 2017
www.ti.com.cn
10 Layout
10.1 Layout Guidelines
The USB signal trace must not be broken when placing TUSB212. Thus, even with the TUSB212 powered down,
or not populated, the USB link is still fully operational. To avoid the need for signal vias, it is highly recommend to
route the High Speed traces directly underneath the TUSB212 package, as illustrated in the PCB land pattern
shown in 图 22.
Although the land pattern shown below has matched trace width to pad width, optimal impedance control is
based on the user's own PCB stack-up. It is recommended to maintain 90 Ω differential routing underneath the
device.
All dimensions are in millimetres (mm).
10.2 Layout Example
图 22. DP and DM Routing Underneath Device Package
18
版权 © 2017, Texas Instruments Incorporated
TUSB212
www.ti.com.cn
ZHCSGM7A –AUGUST 2017–REVISED SEPTEMBER 2017
11 器件和文档支持
11.1 文档支持
11.2 接收文档更新通知
要接收文档更新通知，请转至 TI.com 上的器件产品文件夹。单击右上角的通知我 进行注册，即可每周接收产品信
息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
11.3 社区资源
下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，
并且不一定反映 TI 的观点；请参阅 TI 的 《使用条款》。
TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在
e2e.ti.com 中，您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。
设计支持
TI 参考设计支持 可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。
11.4 商标
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.5 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。这些数据如有变更，恕不另行通知
和修订此文档。如欲获取此产品说明书的浏览器版本，请参阅左侧的导航。
版权 © 2017, Texas Instruments Incorporated
19
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TUSB212IRWBR
TUSB212IRWBT
TUSB212RWBR
TUSB212RWBT
ACTIVE
ACTIVE
ACTIVE
ACTIVE
X2QFN
X2QFN
X2QFN
X2QFN
RWB
RWB
RWB
RWB
12
12
12
12
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 85
-40 to 85
0 to 70
22
22
22
22
NIPDAU
NIPDAU
NIPDAU
0 to 70
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
16-Jun-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TUSB212IRWBR
TUSB212IRWBT
TUSB212RWBR
TUSB212RWBT
X2QFN
X2QFN
X2QFN
X2QFN
RWB
RWB
RWB
RWB
12
12
12
12
3000
250
180.0
180.0
180.0
180.0
9.5
9.5
9.5
9.5
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
0.45
0.45
0.45
0.45
4.0
4.0
4.0
4.0
8.0
8.0
8.0
8.0
Q1
Q1
Q1
Q1
3000
250
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
16-Jun-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TUSB212IRWBR
TUSB212IRWBT
TUSB212RWBR
TUSB212RWBT
X2QFN
X2QFN
X2QFN
X2QFN
RWB
RWB
RWB
RWB
12
12
12
12
3000
250
189.0
189.0
189.0
189.0
185.0
185.0
185.0
185.0
36.0
36.0
36.0
36.0
3000
250
Pack Materials-Page 2
PACKAGE OUTLINE
RWB0012A
X2QFN - 0.4 mm max height
SCALE 6.500
PLASTIC QUAD FLATPACK - NO LEAD
1.65
1.55
B
A
PIN 1 INDEX AREA
1.65
1.55
C
0.4 MAX
SEATING PLANE
0.05 C
2X 1.2
SYMM
(0.13)
TYP
0.05
0.00
6X 0.4
3
6
2
1
7
8
SYMM
2X
0.4
0.4
8X
0.2
12
9
0.25
0.15
12X
0.6
4X
0.4
0.07
0.05
C B A
C
4221631/B 07/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
www.ti.com
EXAMPLE BOARD LAYOUT
RWB0012A
X2QFN - 0.4 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(1.3)
6X (0.4)
9
12
4X (0.7)
2X (0.4)
1
8
SYMM
(1.5)
7
2
8X (0.5)
3
6
SYMM
(R0.05) TYP
12X (0.2)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:30X
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
METAL
SOLDER MASK
OPENING
EXPOSED METAL
EXPOSED METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4221631/B 07/2017
NOTES: (continued)
3. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271).
www.ti.com
EXAMPLE STENCIL DESIGN
RWB0012A
X2QFN - 0.4 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(1.3)
6X (0.4)
12
9
4X (0.67)
2X (0.4)
1
2
8
SYMM
(1.5)
7
8X
METAL
8X (0.5)
3
6
(R0.05) TYP
SYMM
12X (0.2)
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
PADS 1,2,7 & 8
96% PRINTED SOLDER COVERAGE BY AREA
SCALE:50X
4221631/B 07/2017
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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