TUSB215-Q1 [TI]
具有直流升压、集成式 CDP 和 Vbus 电源的汽车 USB 2.0 高速信号调节器;型号: | TUSB215-Q1 |
厂家: | TEXAS INSTRUMENTS |
描述: | 具有直流升压、集成式 CDP 和 Vbus 电源的汽车 USB 2.0 高速信号调节器 CD 调节器 |
文件: | 总26页 (文件大小:956K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
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TUSB215-Q1
SLLSF07 –SEPTEMBER 2017
TUSB215-Q1 USB 2.0 High Speed Signal Conditioner with USB BC1.2 CDP
1 Features
2 Applications
1
•
Qualified for Automotive Applications
•
•
•
•
•
•
•
•
•
Automotive Infotainment
Notebooks
•
AEC-Q100 Qualified with the Following Results
Desktops
–
Device Temperature Grade 2: –40°C to 105°C
Ambient Operating Temperature
Docking Stations
Tablets
–
–
Device HBM Classification Level H1C
Device CDM Classification Level C3
Cell Phones
•
•
•
Compatible with USB 2.0, OTG 2.0 and BC 1.2
Pin strap or I2C Configurable
Active Cable, Cable Extenders
Backplane
USB BC1.2 Charging Downstream Port (CDP)
controller
Televisions
3 Description
•
•
Support for LS, FS, HS signaling
The TUSB215-Q1 is a USB High-Speed (HS) signal
conditioner, designed to compensate for ISI signal
loss in a transmission channel which helps passing
USB electrical compliance tests.
Ultra-low USB Disconnect and Shutdown Power
Consumption
•
•
•
Scalable solution - Daisy Chain Device for High
Loss Applications
TUSB215-Q1 has a patent-pending design which is
agnostic to USB Low Speed (LS) and Full Speed
(FS) signals. LS and FS signal characteristics are
unaffected by the TUSB215-Q1 while HS signals are
compensated.
D1P/M and D2P/M Interchangeable and
Host/Device Agnostic
Supports up to 5m pre-channel or 2m post-
channel Cable Length
–
Four Selectable AC Boost Setting Via External
Pulldown Resistor
Programmable signal AC boost and DC boost permits
fine tuning device performance to optimize High
Speed signals at the connector, this allows use in
many different applications.
–
DC Boost Along With AC Boost for Best Signal
Integrity
In addition, TUSB215-Q1 is compatible with the USB
On-The-Go (OTG) and Battery Charging (BC)
protocols. TUSB215-Q1 further acts as Charging
Downstream Port (CDP) controller and handles the
necessary handshakes with the downstream device.
(1)
Device Information
PART NUMBER
PACKAGE
BODY SIZE (NOM)
TUSB215-Q1
VQFN (14)
3.50 mm x 3.50 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
SPACER
Display
Simplified Schematic
5 V
VCC
TUSB215-Q1
D1P
D2P
DP
DP
USB Host
(Head Unit)
USB
Connector
Cable
D1M D2M
GND
DM
DM
ÇÜ{.215-v1
Copyright © 2017, Texas Instruments Incorporated
Copyright © 2017, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TUSB215-Q1
SLLSF07 –SEPTEMBER 2017
www.ti.com
Table of Contents
7.3 Feature Description................................................... 8
7.4 Device Functional Modes.......................................... 9
Application and Implementation ........................ 11
8.1 Application Information............................................ 11
8.2 Typical Application ................................................. 11
Power Supply Recommendations...................... 18
1
2
3
4
5
6
Features.................................................................. 1
Applications ........................................................... 1
Description ............................................................. 1
Revision History..................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings.............................................................. 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information.................................................. 5
6.5 Electrical Characteristics........................................... 5
6.6 Switching Characteristics.......................................... 6
6.7 Typical Characteristics.............................................. 7
Detailed Description .............................................. 8
7.1 Overview ................................................................... 8
7.2 Functional Block Diagram ......................................... 8
8
9
10 Layout................................................................... 19
10.1 Layout Guidelines ................................................. 19
10.2 Layout Example .................................................... 19
11 Device and Documentation Support ................. 20
11.1 Receiving Notification of Documentation Updates 20
11.2 Community Resources.......................................... 20
11.3 Trademarks........................................................... 20
11.4 Electrostatic Discharge Caution............................ 20
11.5 Glossary................................................................ 20
7
12 Mechanical, Packaging, and Orderable
Information ........................................................... 20
4 Revision History
DATE
REVISION
NOTES
September 2017
*
Initial release.
2
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5 Pin Configuration and Functions
RGY Package
14 Pin (VQFN)
Top View
NC
2
13
12
11
10
9
SCL/CD
VCC
NC
3
Thermal
DC_BOOST/ENA_HS
4
5
6
Pad
SDA
D2P
D2M
D1P
D1M
Not to scale
Pin Functions
PIN
INTERNAL
PULLUP/PULLDOWN
I/O
DESCRIPTION
NAME
EQ
NO.
1
USB High Speed AC boost select via external pull down resistor.
Sampled upon de-assertion of RSTN. Does not recognize real time
adjustments.
See application section for details. Auto selects maximum AC boost level
when left floating.
I
N/A
N/A
NC
2, 3
N/A
Leave unconnected.
In I2C mode:
Reserved for TI test purpose.
In non-I2C mode:
At reset: 3-level input signal DC_BOOST. USB High Speed DC signal boost
selection.
H (pin is pulled high) – 80 mV
M (pin is left floating) – 60 mV
L (pin is pulled low) – 40 mV
After reset: Output signal ENA_HS. Flag indicating that channel is in High
Speed mode. Asserted upon:
DC_BOOST(1
)/ENA_HS
4
I/O
1. Detection of USB-IF High Speed test fixture from an unconnected state
followed by transmission of USB TEST_PACKET pattern.
2. Squelch detection following USB reset with a successful HS handshake [HS
handshake is declared to be successful after single chirp J chirp K pair where
each chirp is within 18 μs – 128 μs].
D2P
D2M
GND
5
6
7
I/O
I/O
N/A
N/A
N/A
USB High Speed positive port.
USB High Speed negative port.
Ground
PWR
1.8-V LDO output. Only enabled when operating in High Speed mode.
Requires 0.1-µF external capacitor to GND to stabilize the core.
VREG
8
O
N/A
D1M
D1P
9
I/O
I/O
N/A
N/A
USB High Speed negative port..
USB High Speed positive port.
10
I2C Mode:
Bidirectional I2C data pin [I2C address = 0x2C].
In non I2C mode:
SDA(2)
11
I/O
RSTN asserted: 500 kΩ PD
Reserved for TI test purpose.
(1) Pull-down and pull-up (to 3.3 V) resistors for DC_BOOST pins must be between 22 kΩ to 47 kΩ in non I2C mode.
(2) Pull-up resistors for SDA and SCL pins in I2C mode should be 4.7 kΩ (5%). If both SDA and SCL are pulled up at reset the device
enters into I2C mode.
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Pin Functions (continued)
PIN
INTERNAL
PULLUP/PULLDOWN
I/O
DESCRIPTION
NAME
NO.
VCC
12
PWR
N/A
Supply power
In I2C mode:
I2C clock pin [I2C address = 0x2C].
Non I2C mode:
After reset: Output CD. Flag indicating that a USB device is attached
(connection detected). Asserted from an unconnected state upon detection of
DP or DM pull-up resistor. De-asserted upon detection of disconnect.
SCL(2)/CD
13
14
I/O
RSTN asserted: 500 kΩ PD
Device disable/enable.
Low – Device is at reset and in shutdown, and
High – Normal operation.
Recommend 0.1-µF external capacitor to GND to ensure clean power on reset
if not driven.
RSTN
I
500 kΩ PU
If the pin is driven, it must be held low until the supply voltage for the device
reaches within specifications.
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature and voltage range (unless otherwise noted)(1)
MIN
MAX
UNIT
Supply Voltage
VCC
-0.3
6
V
Range
Voltage Range
DxP, DxM, RSTN, EQ, SCL, SDA, DC_BOOST, VREG
on I/O pins
-0.3
-65
3.8
V
Tstg
Storage temperature
150
°C
(1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
UNIT
Human body model (HBM), per
±2000
ANSI/ESDA/JEDEC JS-001, all pins(1)
V(ESD)
Electrostatic discharge
V
Charged device model (CDM), per JEDEC
specification JESD22-C101, all pins(2)
±500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature and voltage range (unless otherwise noted)
MIN
4.4
-40
-40
NOM
MAX
5.5
UNIT
V
VCC
TA
Supply voltage
5
Ambient temperature
Junction temperature
TUSB215Q1
TUSB215Q1
105
125
°C
TJ
°C
4
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6.4 Thermal Information
RGY (VQFN)
14 PINS
49.1
THERMAL METRIC(1)
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
52.8
24.2
ΨJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
2.2
ΨJB
24.3
RθJC(bot)
7
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Electrical Characteristics
over operating free-air temperature and voltage range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
POWER
USB channel = HS mode; 480 Mbps
traffic; VCC = 5V; VCC supply stable; DC
Boost = 60 mV
IACTIVE_H
S
High-speed active curent
High-speed idle current
18
13
30
22
mA
mA
USB channel = HS mode; no traffic; VCC
= 5V; VCC supply stable; DC Boost = 60
mV
IIDLE_HS
ISUSPEND
_HS
USB channel = HS suspend mode; VCC
= 5V; VCC supply stable
High-speed suspend current
Full/Low speed current
Disconnect current
0.76
0.77
0.86
22
1.5
1.5
1.5
80
mA
mA
mA
µA
USB channel = FS mode or LS mode;
VCC = 5V
IFS_LS
IDISCONN
ECT
Host side application; No device
attachment; VCC = 5V
RSTN driven low; VCC supply stable; VCC
= 5V
IRSTN
Disable current
Pin fail-safe leakage current for SDA,
SCL, DC_BOOST, DxP/N, RSTN
ILKG_FS
VCC = 0 V; Pin at 3.6 V
40
µA
RSTN
VIH
VIL
High-level input voltage
Low-level input voltage
High-level input current
Low-level input current
VCC = 4.4V
VCC = 5.5V
VIH = 3.6 V
VIL = 0 V
2
0
3.6
0.8
4
V
V
IIH
-4
µA
µA
IIL
-11
11
EQ
AC Boost Level 0
AC Boost Level 1
AC Boost Level 2
AC Boost Level 3
160
2
Ω
1.4
3.7
6
kΩ
kΩ
kΩ
REQ
External pull-down resistor on EQ pin.
3.9
CD, ENA_HS
VOH
High-level output voltage
IO = -50µA
IO = 50µA
2.4
V
V
VOL
Low-level output voltage
0.4
SCL, SDA
CI2CBUS
VIH
I2C Bus capacitance
4
2
150
3.6
0.8
0.4
pF
V
SDA and SCL input high level voltage
SDA and SCL input Low level voltage
VCC = 4.4V
VIL
VCC = 5.5V
V
VSDA_OL SDA low-level output voltage
ISDA_OL SDA Low level output current
4.7kΩ pullup to 3.6V; VCC = 4.4V
VCC = 5.5V; I2C pulled up to 3.6V
V
1.1
mA
DC_BOOST
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Electrical Characteristics (continued)
over operating free-air temperature and voltage range (unless otherwise noted)
PARAMETER
High-level input voltage
Mid-level input voltage
Low-level input voltage
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VIH
VCC = 5V
VCC = 5V
VCC = 5V
2.4
3.6
V
V
V
VIM
1.6
VIL
0
0.4
DxP, DxM
Measured with LCR meter and device
powered down. 1 MHz sinusoid, 30
mVpp ripple
CIO_DXX Capacitance to GND
2.7
pF
6.6 Switching Characteristics
over operating free-air temperature and voltage range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
USB channel = HS mode; 480 Mbps
traffic; VCC supply stable
FBR_DXX DxP/M Bit Rate
480.24
Mbps
tRISE_DXX DxP/M rise time
10% - 90%; VCC = 5.5V; Max AC Gain;
90% - 10%; VCC = 5.5V; Max AC Gain;
100
100
ps
ps
tFALL_DXX DxP/M fall time
tRSTN_PU Minimum width to detect a valid RSTN
signal assert when the pin is actively
driven
VCC = 4.4 V; Refer to Figure 1
Refer to Figure 1
20
µs
LSE_WIDT
H
tSTABLE
VCC stable before RSTN de-assertion
100
0.2
µs
tVCC_RAM
P
VCC ramp time
100
ms
tRSTN_PULSE_WIDTH
RSTN
VIL(MAX)
tSTABLE
VCC(MIN)
VCC
Figure 1. Power On and Reset Timing
6
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6.7 Typical Characteristics
Figure 2. USB2.0 HS Eye diagram, Host far-end with 2m
cable post-channel loss without TUSB215-Q1
Figure 3. USB2.0 HS Eye diagram, Host far-end with 2m
cable post-channel loss with TUSB215-Q1
Figure 4. USB2.0 HS Eye diagram, Host far-end with 5m
cable pre-channel loss without TUSB215-Q1
Figure 5. USB2.0 HS Eye diagram, Host far-end with 5m
cable pre-channel loss with TUSB215-Q1
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7 Detailed Description
7.1 Overview
The TUSB215-Q1 is a USB High-Speed (HS) signal conditioner, designed to compensate for ISI signal loss in a
transmission channel. TUSB215-Q1 has a patent-pending design which is agnostic to USB Low Speed (LS) and
Full Speed (FS) signals and does not alter their signal characteristics, while HS signals are compensated. In
addition, the design is compatible with USB On-The-Go (OTG) and Battery Charging (BC) specifications. The
TUSB215-Q1 provides USB Charging Downstream Port (CDP) controller for applications in which USB host or
hub do not have this function.
Programmable signal AC boost through an external resistor on EQ pin permits fine tuning device performance to
optimize signals helping to pass USB HS electrical compliance tests at the connector. Additional DC Boost
configurable by three level input DC_BOOST pin helps overcoming the cable losses.
7.2 Functional Block Diagram
Low and Full
Speed Bypass
D1P
D1M
D2P
D2M
USB
TRANSCEIVER
High Speed
Compensation
ESD
PROTECTION
USB
CONNECTOR
CDP Controller
CD
OPTIONAL
PLD
Status Flags
ENA_HS
7.3 Feature Description
7.3.1 EQ
The EQ pin of the TUSB215-Q1 is used to configure the AC boost of the device. The four levels of AC boost are
set through different values of an external pulldown resistor at this pin.
7.3.2 DC BOOST
The DC_BOOST pin of the TUSB215-Q1 is a tri-level pin, used to set the DC gain of the device according to
Table 1.
Table 1. DC Boost Settings
DC BOOST SETTING VIA PIN STRAP
DC_BOOST
DC Boost Setting (mV)
VIL
VIM
VIH
40
60
80
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7.3.3 BC1.2 CDP Support
The TUSB215-Q1 main function is a signal conditioner offering the EQ/Boost features to the incoming DP/DM
signals. For applications in which USB host or hub do not provide USB BC charging downstream port (CDP)
functionality, the TUSB215-Q1 can perform this task.
7.4 Device Functional Modes
7.4.1 Low Speed (LS) Mode
TUSB215-Q1 automatically detects a LS connection and does not enable signal compensation. CD pin is
asserted high.
7.4.2 Full Speed (FS) Mode
TUSB215-Q1 automatically detects a FS connection and does not enable signal compensation. CD pin is
asserted high.
7.4.3 High Speed (HS) Mode
TUSB215-Q1 automatically detects a HS connection and will enable signal compensation as determined by the
configuration of the DC_BOOST pin and the external pulldown resistance on its EQ pin. CD pin asserted high.
7.4.4 Shutdown Mode
TUSB215-Q1 is disabled when its RSTN pin is asserted low. In shutdown mode, the USB channel is still fully
operational but there is neither signal compensation nor any indication from the CD pin as to the status of the
channel.
7.4.5 I2C Mode
TUSB215-Q1 support 100 kHz I2C for device configuration, status readback and test purposes. This controller is
enabled after SCL and SDA pins are sampled high shortly after de-assertion of RSTN. In this mode, the register
as described in Table 2 can be accessed by I2C read/write transaction to 7-bit slave address 0x2C. It is
necessary to set CFG_ACTIVE bit and reset it to zero after making changes to the EQ and DC Boost level
registers to restart the state machine.
NOTE
All registers or fields in Table 2 which are not specifically mentioned are considered
reserved. The default value of these reserved registers or fields must not be changed. It is
suggested to perform a read-modify-write operation to maintain the default value of the
reserved fields.
Table 2. Register definition
Offset
Bit(s)
Name
Type
Default
Description
Sets the level of AC boost
000 :Level 0 AC boost programmed [MIN]
001 : Level 1 AC boost programmed
011 : Level 2 AC boost programmed
111 : Level 3 AC boost programmed [MAX]
XXX (Sampled from EQ
pin at reset)
0x01
6:4
ACB_LVL
RW
Configuration mode
0 : Normal mode. State machine enabled.
1 : Configuration mode: State machine disabled.
0x03
0
CFG_ACTIVE
RW
1b
After reset, if I2C mode is true (SCL and SDA are
both pulled high) it is maintained until it is cleared
by an I2C write, but, if I2C mode is not true, it is
cleared automatically.
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Device Functional Modes (continued)
Table 2. Register definition (continued)
Offset
Bit(s)
Name
Type
Default
Description
Sets the level of DC Boost
XXX (Sampled from
DC_BOOST pin at reset)
011 : 40mV (DC_Boost = L)
0x0E
2:0
DCB_LVL
RW
101 : 60mV (DC_Boost = M, default)
111 : 80mV (DC_Boost = H)
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The primary purpose of the TUSB215-Q1 is to re-store the signal integrity of a USB High Speed channel up to
the USB connector. The loss in signal quality stems from reduced channel bandwidth due to high loss PCB trace
and other components that contribute a capacitive load. This can cause the channel to fail the USB near end eye
mask. Proper use of the TUSB215-Q1 can help to pass this eye mask. Additionally the DC Boost helps
overcoming DC losses from cables and traces.
A secondary purpose is to use the CD pin of the TUSB215-Q1 to control other blocks on the customer platform if
so desired. The TUSB215-Q1 also provides CDP controller function.
8.2 Typical Application
A typical application is shown in Figure 6. In this setup, D2P and D2M face the USB connector while D1P and
D1M face the USB host or hub. If desired, the orientation may be reversed [that is, D2 faces transceiver and D1
faces connector].
D1M
D1P
D2M
D2P
USB
Host or Hub
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Figure 6. Typical Application
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Typical Application (continued)
8.2.1 Design Requirements
For this design example, use the parameters shown in the table below.
Table 3. Design Parameters
PARAMETER
VALUE
5 V
VCC (4.4 V to 5.5 V)
I2C support required in system (Yes/No)
No
REQ
Level
0-Ω
0
AC Boost Level 2:
REQ = 3.83 k
AC Boost
DC Boost
1.69 k ±1%
3.83 k ± 1%
DNI
1
2
3
RDC1
22 kΩ - 47 kΩ
DNI
RDC2
Level
Mid DC Level:
RDC1 = DNI
RDC2 = DNI
Do Not Install (DNI)
DNI
40 mV Low DC boost
60 mV Mid DC boost
80 mV High DC boost
47 kΩ
24 kΩ
8.2.2 Detailed Design Procedure
TUSB215-Q1 requires a valid reset signal as described in the power supply recommendations section. The
capacitor at RSTN pin is not required if a microcontroller drives the RSTN pin according to recommendations.
VREG pin is the internal LDO output that requires a 0.1-μF external capacitor to GND to stabilize the core.
The ideal AC boost setting is dependent upon the signal chain loss characteristics of the target platform. The
general recommendation is to start with AC boost level 0, and then increment to AC boost level 1, etc. if
permissible. Same applies to the DC Boost setting where it is recommended to plan for the required pads or
connections to change boost settings, but to start with DC boost level 1.
In order for the TUSB215-Q1 to recognize any change to the AC and DC Boost settings, the RSTN pin must be
toggled. This is because the configuration is latched on power up and the inputs are ignored thereafter.
NOTE
The TUSB215-Q1 compensates for DC attenuation in the signal path according to the
configuration of the DC_BOOST pin. This pin is not 5V tolerant and therefore when
selecting the highest DC boost level, the voltage level at DC_BOOST pin must be less
than 3.6V.
Placement of the device is also dependent on the application goal. Table 4 summarizes our recommendations.
Table 4. Platform Placement Guideline
PLATFORM GOAL
Pass USB Near End Mask
SUGGESTED DEVICE PLACEMENT
Close to measurement point
Pass USB Far End Eye Mask
Close to USB PHY
Cascade multiple devices to improve device enumeration
Midway between each USB interconnect
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+5 V
100 nF
1 mF
REQ
100 nF
+5 V
RDC2
RDC1
NC
SCL/CD
NC
VCC
SDA
D1P
D1N
DCBOOST/ENA_HS
CON_D2P
CON_D2N
USB_D1P
USB_D1N
D2P
D2M
USB
Host or Hub
100 nF
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Figure 7. Reference Schematic
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8.2.2.1 Test Procedure to Construct USB High Speed Eye Diagram
NOTE
USB-IF certification tests for High Speed eye masks require the mandated use of the
USB-IF developed test fixtures. These test fixtures do not require the use of oscilloscope
probes. Instead they use SMA cables. More information can be found at the USB-IF
Compliance Updates Page. It is located under the ‘Electricals’ section, ID 86 dated March
2013.
The following procedure must be followed before using any oscilloscope compliance software to construct a USB
High Speed Eye Mask:
8.2.2.1.1 For a Host Side Application
1. Configure the TUSB215-Q1 to the desired AC and DC Boost settings
2. Power on (or toggle the RSTN pin if already powered on) the TUSB215-Q1
3. Using SMA cables, connect the oscilloscope and the USB-IF host-side test fixture to the TUSB215-Q1
4. Enable the host to transmit USB TEST_PACKET
5. Execute the oscilloscope USB compliance software.
6. Repeat the above steps in order to re-test TUSB215-Q1 with a different settings
8.2.2.1.2 For a Device Side Application
1. Configure the TUSB215-Q1 to the desired AC and DC Boost settings
2. Power on (or toggle the RSTN pin if already powered on) the TUSB215-Q1
3. Connect a USB host, the USB-IF device-side test fixture, and USB device to the TUSB215-Q1. Ensure that
the USB-IF device test fixture is configured to the ‘INIT’ position
4. Allow the host to enumerate the device
5. Enable the device to transmit USB TEST_PACKET
6. Using SMA cables, connect the oscilloscope to the USB-IF device-side test fixture and ensure that the
device-side test fixture is configured to the ‘TEST’ position.
7. Execute the oscilloscope USB compliance software.
8. Repeat the above steps in order to re-test TUSB215-Q1 with a different settings
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8.2.3 Application Curves
TUSB21xEVM
2m USB A-B Cable
DP
[ecroy 25 DIz {cope
1m SMA to SMA cables
Ü{. Iost
DM
Ü{.LC /ompliance
Çest Cixture
Figure 8. Eye Diagram Bench Setup
Figure 9. No TUSB215-Q1
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Figure 10. Low DC Boost, AC Boost Level 0
Figure 11. Mid DC Boost, AC Boost Level 0
Figure 13. Low DC Boost, AC Boost Level 1
Figure 12. High DC Boost, AC Boost Level 0
Figure 14. Mid DC Boost, AC Boost Level 1
Figure 15. High DC Boost, AC Boost Level 1
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Figure 17. Mid DC Boost, AC Boost Level 2
Figure 16. Low DC Boost, AC Boost Level 2
Figure 18. High DC Boost, AC Boost Level 2
Figure 20. Mid DC Boost, AC Boost Level 3
Figure 19. Low DC Boost, AC Boost Level 3
Figure 21. High DC Boost, AC Boost Level 3
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9 Power Supply Recommendations
On power up, the interaction of the RSTN pin and power on ramp could result in digital circuits not being set
correctly. The device should not be enabled until the power on ramp has settled to 4.4 V or higher to ensure a
correct power on reset of the digital circuitry. If RSTN cannot be held low by microcontroller or other circuitry until
the power on ramp has settled, then an external capacitor from the RSTN pin to GND is required to hold the
device in the low power reset state.
The RC time constant should be larger than five times of the power on ramp time (0 to VCC). With a typical
internal pullup resistance of 500 kΩ, the recommended minimum external capacitance is calculated as:
CRSTN = [Ramp Time × 5] ÷ [500 kΩ]
(1)
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10 Layout
10.1 Layout Guidelines
To avoid the need for signal vias, it is highly recommend to route the High Speed traces on the same surface
layer than the TUSB215-Q1 is placed. shows an example how one could layout the PCB for TUSB215-Q1.
The layout should use impedance controlled traces to maintain 90 Ω differential impedance for the whole signal
path as required per USB 2.0 specification. General guidelines for highspeed signal routing apply.
10.2 Layout Example
213_VCC
C1
L/CD
SCLKD
GND
RSTN
VREG
RSTN
C2
C3
0.1 µF
0.1 µF
EQ
GND GND
EQ
Figure 22. Layout Example
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11 Device and Documentation Support
11.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.3 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
11.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OUTLINE
RGY0014B
VQFN - 1 mm max height
S
C
A
L
E
3
.
3
0
0
PLASTIC QUAD FLATPACK - NO LEAD
3.6
3.4
B
0.5
0.3
A
0.3
0.2
DETAIL
OPTIONAL TERMINAL
TYPICAL
PIN 1 INDEX AREA
3.6
3.4
0.1 MIN
(0.05)
A
-
A
2
5
.
0
0
0
SECTION A-A
TYPICAL
C
1 MAX
SEATING PLANE
0.08 C
0.05
0.00
2.05 0.05
2X 1.5
(0.2) TYP
8
7
EXPOSED
THERMAL PAD
8X 0.5
9
6
2X
2
A
A
15
SYMM
SEE TERMINAL
DETAIL
2
13
0.3
14X
0.2
14
0.5
1
0.1
0.05
C A B
PIN 1 ID
(OPTIONAL)
SYMM
14X
0.3
4223385/A 11/2016
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
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EXAMPLE BOARD LAYOUT
RGY0014B
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(
2.05)
2X (1.5)
SYMM
1
14
14X (0.6)
2
13
14X (0.25)
15
SYMM
(3.3)
(0.775)
8X (0.5)
9
6
(
0.2) TYP
VIA
8
7
(0.775)
(R0.05)
TYP
(3.3)
LAND PATTERN EXAMPLE
SCALE:20X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4223385/A 11/2016
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
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EXAMPLE STENCIL DESIGN
RGY0014B
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
2X (1.5)
(0.56)
TYP
1
14
14X (0.6)
2
15
13
14X (0.25)
(0.56)
TYP
SYMM
(3.3)
4X
0.92)
(
8X (0.5)
6
9
METAL
TYP
7
8
SYMM
(R0.05) TYP
(3.3)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 15
80% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:20X
4223385/A 11/2016
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TUSB215QRGYRQ1
TUSB215QRGYTQ1
ACTIVE
ACTIVE
VQFN
VQFN
RGY
RGY
14
14
3000 RoHS & Green
250 RoHS & Green
SN
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 105
-40 to 105
USB215
USB215
SN
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
OTHER QUALIFIED VERSIONS OF TUSB215-Q1 :
Catalog: TUSB215
•
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
•
Addendum-Page 2
IMPORTANT NOTICE AND DISCLAIMER
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IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
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