TUSB217-Q1 [TI]
具有直流升压、集成式 CDP 和宽电源的汽车 USB 2.0 高速信号调节器;
| 型号： | TUSB217-Q1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有直流升压、集成式 CDP 和宽电源的汽车 USB 2.0 高速信号调节器 CD 调节器 |
| 文件： | 总32页 (文件大小：1825K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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TUSB217-Q1
ZHCSIS9A –SEPTEMBER 2018–REVISED DECEMBER 2018
TUSB217-Q1 USB 高速信号调节器
1 特性
3 说明
1
•
符合面向汽车应用的 AEC-Q100 标准
TUSB217-Q1 是第三代 USB 2.0 高速信号调节器，旨
在补偿传输通道中的交流损失（由于电容性负载）和直
流损失（由于电阻性负载）。
–
器件温度等级 2：
–40°C 至 105°C TA
•
•
•
•
•
•
•
宽电源电压范围：2.3 - 6.5V
超低 USB 断开和关断功耗
可提供 USB 2.0 高速信号调节
与 USB 2.0、OTG 2.0 和 BC 1.2 兼容
支持低速、全速和高速信号传输
主机/设备无关
TUSB217-Q1 采用了专利设计，可通过边缘加速器来
对 USB 2.0 高速信号的传输边缘进行加速，并通过直
流升压功能来提高静态电平。此外，TUSB217-Q1 还
具有预均衡功能，可提高接收器的灵敏度并补偿较长线
缆应用中的 ISI 抖动。USB 低速和全速信号特征不受
TUSB217-Q1 的影响。
支持长达 5m 的电缆
TUSB217-Q1 可在不改变数据包计时或增加传播延迟
的情况下提高信号质量，是需要低延迟的 应用 的理想
选择。
–
通过外部下拉电阻器实现四种可选的信号增强
（边沿升压与直流升压）设置
–
通过上拉或下拉可配置引脚实现三种可选的 RX
灵敏度，以补偿高损耗应用中的 ISI 抖动
TUSB217-Q1 可使用长达 5 米的线缆帮助系统通过
USB 2.0 高速电气近端眼图合规性测试。
•
•
可扩展解决方案 - 用于高损耗应用的 菊花链器件
与 TUSB213 (5V) 引脚兼容
TUSB217-Q1 与 USB On-The-Go (OTG) 和电池充电
(BC 1.2) 协议兼容。
2 应用
•
•
•
•
•
•
•
•
汽车信息娱乐系统
器件信息
汽车音响主机
汽车媒体中心
笔记本电脑/台式计算机/扩展坞
平板电脑/手机
电视
器件编号
封装
VQFN (14)
封装尺寸（标称值）
TUSB217-Q1
3.50mm x 3.50mm
简化原理图
2.3 œ 6.5V
有源电缆、电缆扩展器
背板
VCC
USB
Host
USB
Connector
Cable
D2
D1
GND
1
本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。 有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确
性和有效性。 在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLLSF89
TUSB217-Q1
ZHCSIS9A –SEPTEMBER 2018–REVISED DECEMBER 2018
www.ti.com.cn
目录
7.4 Device Functional Modes.......................................... 8
7.5 TUSB217 Registers .................................................. 9
Application and Implementation ........................ 12
8.1 Application Information............................................ 12
8.2 Typical Application ................................................. 12
Power Supply Recommendations...................... 21
1
2
3
4
5
6
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings.............................................................. 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information.................................................. 5
6.5 Electrical Characteristics........................................... 5
6.6 Switching Characteristics.......................................... 6
6.7 Timing Requirements................................................ 7
Detailed Description .............................................. 8
7.1 Overview ................................................................... 8
7.2 Functional Block Diagram ......................................... 8
7.3 Feature Description................................................... 8
8
9
10 Layout................................................................... 22
10.1 Layout Guidelines ................................................. 22
10.2 Layout Example .................................................... 22
11 器件和文档支持 ..................................................... 23
11.1 文档支持 ............................................................... 23
11.2 接收文档更新通知 ................................................. 23
11.3 社区资源................................................................ 23
11.4 商标....................................................................... 23
11.5 静电放电警告......................................................... 23
11.6 术语表 ................................................................... 23
12 机械、封装和可订购信息....................................... 24
7
4 修订历史记录
Changes from Original (September 2018) to Revision A
Page
•
将文档状态从预告信息 更改为生产数据.................................................................................................................................. 1
2
Copyright © 2018, Texas Instruments Incorporated
TUSB217-Q1
www.ti.com.cn
ZHCSIS9A –SEPTEMBER 2018–REVISED DECEMBER 2018
5 Pin Configuration and Functions
RGY Package
14 Pin (VQFN)
Top View
NC
2
3
4
5
6
13
12
11
10
9
SCL/CD
VCC
NC
RX_SEN/ENA_HS
D2P
Thermal
Pad
SDA
D1P
D2M
D1M
Not to scale
Pin Functions
PIN
INTERNAL
PULLUP/PULLDOWN
I/O
DESCRIPTION
NAME
NO. (RGY)
USB High Speed boost select via external pull down resistor.
Both edge boost and DC boost are controlled by a single pin
in non-I2C mode. In I2C mode edge boost and DC boost can
be individually controlled.
BOOST
1
I
N/A
Sampled upon power up. Does not recognize real time
adjustments.
Auto selects BOOST LEVEL = 3 when left floating.
NC
2,3
8
I
Leave unconnected
RESERVED
O
Leave unconnected or connect a decoupling cap 0.1μF
In I2C mode:
Reserved for TI test purpose.
In non-I2C mode:
At reset: 3-level input signal RX_SEN. USB High Speed RX
Sensitivity Setting to Compensate ISI Jitter
H (pin is pulled high) – high RX sensitivity (high loss channel)
M (pin is left floating) – medium RX sensitivity (medium loss
channel)
L (pin is pulled low) – low RX sensitivity (low loss channel)
After reset: Output signal ENA_HS. Flag indicating that
channel is in High Speed mode. Asserted upon:
1. Detection of USB-IF High Speed test fixture from an
unconnected state followed by transmission of USB
TEST_PACKET pattern.
RX_SEN(1)/ENA_HS
4
I/O
N/A
2. Squelch detection following USB reset with a successful HS
handshake [HS handshake is declared to be successful after
single chirp J chirp K pair where each chirp is within 18 μs –
128 μs].
D2P
D2M
GND
D1M
D1P
5
6
I/O
I/O
P
N/A
N/A
N/A
N/A
N/A
USB High Speed positive port.
USB High Speed negative port.
Ground
7
9
I/O
I/O
USB High Speed negative port..
USB High Speed positive port.
10
(1) Pull-down and pull-up resistors for RX_SEN pin must follow RRXSEN1 and RRXSEN2 resistor recommendations in non I2C mode.
Copyright © 2018, Texas Instruments Incorporated
3
TUSB217-Q1
ZHCSIS9A –SEPTEMBER 2018–REVISED DECEMBER 2018
www.ti.com.cn
Pin Functions (continued)
PIN
INTERNAL
PULLUP/PULLDOWN
I/O
DESCRIPTION
NAME
SDA(2)
VCC
NO. (RGY)
I2C Mode:
500 kΩ PU
1.8 MΩ PD
Bidirectional I2C data pin [7-bit I2C slave address = 0x2C].
In non I2C mode:
Reserved for TI test purpose.
11
12
I/O
P
N/A
Supply power
Device disable/enable.
Low – Device is at reset and in shutdown, and
High - Normal operation.
Recommend 0.1-µF external capacitor to GND to ensure clean
power on reset if not driven. If the pin is driven, it must be held
low until the supply voltage for the device reaches within
specifications.
500 kΩ PU
1.8 MΩ PD
RSTN
14
I
In I2C mode:
I2C clock pin [I2C address = 0x2C].
Non I2C mode:
When RSTN asserted there is
a 500 kΩ PD
SCL(2)/CD
13
I/O
After reset: Output CD. Flag indicating that a USB device is
attached (connection detected). Asserted from an
unconnected state upon detection of DP or DM pull-up
resistor. De-asserted upon detection of disconnect.
Thermal Pad is electrically not connected to device ground.
Connection to board ground is optional.
Thermal Pad
TPAD
N/A
N/A
(2) Pull-up resistors for SDA and SCL pins in I2C mode should be RPull-up (depending on I2C bus voltage). If both SDA and SCL are pulled
up at power-up the device enters into I2C mode.
6 Specifications
6.1 Absolute Maximum Ratings
Over operating free-air temperature range (unless otherwise noted)
(1)
MIN
–0.3
–0.3
-0.3
-0.3
–65
MAX
7
UNIT
V
Supply voltage range
VCC
Voltage range USB data
DxP, DxM
5.5
1.98
5
V
Voltage range on BOOST pin BOOST
V
Voltage range other pins
SCL, SDA, RX_SEN, RSTN
V
Storage temperature, Tstg
150
125
°C
°C
Maximum junction temperature, TJ (max)
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
UNIT
Human-body model (HBM), per AEC Q100-002(1)
HBM ESD Classification Level 2
±2000
Electrostatic
discharge
V(ESD)
V
Charged-device model (CDM), per AEC Q100- 011
CDM ESD Classification Level C4A
±750
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
2.3
NOM
MAX
6.5
UNIT
V
VCC
TA
Supply voltage
5
Operating free-air temperature (AEC-Q100)
Junction temperature (AEC-Q100)
I2C Bus Voltage
–40
105
115
3.6
°C
°C
V
TJ
VI2C_BUS
1.62
4
Copyright © 2018, Texas Instruments Incorporated
TUSB217-Q1
www.ti.com.cn
ZHCSIS9A –SEPTEMBER 2018–REVISED DECEMBER 2018
Recommended Operating Conditions (continued)
over operating free-air temperature range (unless otherwise noted)
MIN
0
NOM
MAX
3.6
UNIT
V
DxP, DxM
BOOST
Voltage range USB data
Voltage range BOOST pin
0
1.98
V
SCL, SDA,
RX_SEN,
RSTN
Voltage range other pins (SCL, SDA, RX_SEN, RSTN)
0
3.6
V
6.4 Thermal Information
RGY (VQFN)
(1)
THERMAL METRIC
UNIT
14 PINS
49.1
52.8
24.2
2.2
RθJA
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
ψJB
24.3
7
RθJC(bot)
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
6.5 Electrical Characteristics
Over operating free-air temperature range (unless otherwise noted)
(1)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
POWER
USB channel = HS mode. 480 Mbps
traffic. VCC supply stable, with Boost =
Max
IACTIVE_HS
High Speed Active Current
22
22
36
mA
USB channel = HS mode, no traffic.
VCC supply stable, Boost = Max
IIDLE_HS
IHS_SUPSPEND
IFS
High Speed Idle Current
High Speed Suspend Current
Full-Speed Current
36
1.4
1.4
mA
mA
mA
USB channel = HS Suspend mode.
VCC supply stable
0.75
0.75
USB channel = FS mode, 12 Mbps traffic,
Vcc supply stable
Host side application. No device
attachment.
IDISCONN
ISHUTDN
Disconnect Power
Shutdown Power
0.80
35
1.4
95
mA
µA
RSTN driven low, VCC supply stable
CONTROL PIN LEAKAGE
Pin failsafe leakage current for
SDA, RSTN
ILKG_FS
ILKG_FS
ILKG_FS
VCC = 0 V, pin at VIH, max
VCC = 0 V, pin at VIH, max
VCC = 0 V, pin at VIH, max
10
6
15
10
70
µA
µA
nA
Pin failsafe leakage current for
BOOST, RX_SEN
Pin failsafe leakage current for
SCL
INPUT RSTN
VIH
VIL
IIH
High level input voltage
Low-level input voltage
High level input current
Low level input current
1.5
0
3.6
0.5
V
V
VIH = 3.6 V, RPU enabled
VIL = 0V, RPU enabled
±15
±20
µA
µA
IIL
INPUT RX_SEN (3-level input, for mid level leave pin floating)
High level input voltage
RRXSEN1=47kΩ, RRXSEN2=10kΩ
VIH
VIH
VCC<=4.3V
VCC>4.3V
1.8
2.0
3.6
3.6
V
V
High level input voltage
RRXSEN1=37kΩ, RRXSEN2=47kΩ
(1) All typical values are at VCC = 5 V, and TA = 25°C.
Copyright © 2018, Texas Instruments Incorporated
5
TUSB217-Q1
ZHCSIS9A –SEPTEMBER 2018–REVISED DECEMBER 2018
www.ti.com.cn
Electrical Characteristics (continued)
Over operating free-air temperature range (unless otherwise noted)
(1)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Low level input voltage
22kΩ <= RRXSEN1 <= 33kΩ
VIL
0.4
V
INPUT BOOST
RBOOST_LVL0
External pulldown resistor for
BOOST Level 0
160
2
Ω
External pulldown resistor for
BOOST Level 1
RBOOST_LVL1
RBOOST_LVL2
RBOOST_LVL3
1.5
3.4
7.5
1.8
3.6
kΩ
kΩ
kΩ
External pulldown resistor for
BOOST Level 2
3.96
External pulldown resistor for
BOOST Level 3
OUTPUTS CD, ENA_HS
VOH
High level output voltage
High level output voltage
Low level output voltage
IO = –50 µA, VCC >= 3.0V
IO = –50 µA, VCC = 2.3V
IO = 50 µA
2.5
1.8
V
V
V
VOH
VOL
0.3
I2C
I2C Bus Capacitance
CI2C_BUS
4
150
pF
mA
%
I2C open drain output current
VI2C_BUS = 1.8V +/-10%
VI2C_BUS = 3.3V +/-10%
VI2C_BUS = 1.8V +/-10%
VI2C_BUS = 3.3V +/-10%
VI2C_BUS = 1.8V +/-10%
VI2C_BUS = 3.3V +/-10%
IOL
VOL = 0.4V
1.5
VIL
RPull-up =1.6kΩ to 2.5kΩ, % of VI2C_BUS
RPull-up =2.8kΩ to 7kΩ, % of VI2C_BUS
RPull-up =1.6kΩ to 2.5kΩ, % of VI2C_BUS
RPull-up =2.8kΩ to 7kΩ, % of VI2C_BUS
25
25
VIL
%
VIH
75
75
%
VIH
%
RPull-up
RPull-up
SCL Frequency
DxP, DxM
1.6
2.8
2
2.5
7
kΩ
kΩ
kHz
4.7
100
Measured with VNA at 240 MHz,
VCC supply stable, Redriver off
CIO_DXX
Capacitance to GND
2.5
pF
6.6 Switching Characteristics
Over operating free-air temperature range (unless otherwise noted)
(1)
PARAMETER
DxP, DxM USB Signals
TEST CONDITIONS
MIN
TYP
MAX
UNIT
USB channel = HS mode. 480 Mbps
traffic. VCC supply stable
FBR_DXX
Bit Rate
480
Mbps
ps
tR/F_DXX
Rise/Fall time
100
(1) All typical values are at VCC = 5 V, and TA = 25°C.
6
Copyright © 2018, Texas Instruments Incorporated
TUSB217-Q1
www.ti.com.cn
ZHCSIS9A –SEPTEMBER 2018–REVISED DECEMBER 2018
6.7 Timing Requirements
MIN
NOM
MAX
UNIT
POWER UP TIMING
Minimum width to detect a valid RSTN signal assert when the pin is actively
driven low
TRSTN_PW
TSTABLE
TREADY
100
300
µs
µs
µs
ms
VCC must be stable before RSTN de-assertion
Maximum time needed for the device to be ready after RSTN is de-
asserted.
500
100
TRAMP
VCC ramp time
0.2
I2C (STD)
Stop setup time, SCL (Tr=600ns-1000ns), SDA (Tf=6.5ns-106.5ns), 100kHz
STD
tSUSTO
tHDSTA
tSUSTA
tSUDAT
tHDDAT
4
4
µs
µs
µs
ns
µs
Start hold time, SCL (Tr=600ns-1000ns), SDA (Tf=6.5ns-106.5ns), 100kHz
STD
Start setup time, SCL (Tr=600ns-1000ns), SDA (Tf=6.5ns-106.5ns), 100kHz
STD
4.7
250
5
Data input or False start/stop, setup time, SCL (Tr=600ns-1000ns), SDA
(Tf=6.5ns-106.5ns), 100kHz STD
Data input or False start/stop, hold time, SCL (Tr=600ns-1000ns), SDA
(Tf=6.5ns-106.5ns), 100kHz STD
tBUF
tLOW
tHIGH
tF
Bus free time between START and STOP conditions
Low period of the I2C clock
4.7
4.7
4
µs
µs
µs
ns
ns
High period of the I2C clock
Fall time of both SDA and SCL signals
Rise time of both SDA and SCL signals
300
tR
1000
tRSTN_PW
RSTN
tSTABLE
VCC
VIL(MAX)
VCC(MIN)
tRAMP
图 1. Power On and Reset Timing
70%
30%
SDA
SCL
t
t
R
t
F
HDSTA
tHIGH
t
t
LOW
BUF
70%
30%
S
P
P
S
t
t
SUSTO
t
t
SUDAT
HDDAT
HDSTA
t
SUSTA
图 2. I2C Timing
版权 © 2018, Texas Instruments Incorporated
7
TUSB217-Q1
ZHCSIS9A –SEPTEMBER 2018–REVISED DECEMBER 2018
www.ti.com.cn
7 Detailed Description
7.1 Overview
The TUSB217-Q1 is a USB High-Speed (HS) signal conditioner designed to compensate for ISI signal loss in a
transmission channel. TUSB217-Q1 has a patented design for USB Low Speed (LS) and Full Speed (FS)
signals. It does not alter the signal characteristics. HS signals are compensated. The design is compatible with
USB On-The-Go (OTG) and Battery Charging (BC) specifications.
Programmable signal gain through an external resistor permits fine tuning device performance to optimize
signals. This helps pass USB HS electrical compliance tests at the connector. Additional RX sensitivity, tuned by
external pull-up resistor and pull-down resistor, allows to overcome attenuation in cables. The TUSB217-Q1
allows application in series to cover longer distances, or high loss transmission paths. A maximum of 4 devices
can be daisy-chained.
7.2 Functional Block Diagram
Functional Block Diagram
Low and Full
Speed Bypass
D2P
D1P
USB
High Speed
Compensation
ESD
USB
D1M
D2M
TRANSCEIVER
PROTECTION
CONNECTOR
CD
ENA_HS
OPTIONAL
PLD
Status flags
Copyright © 2018, Texas Instruments Incorporated
7.3 Feature Description
7.3.1 High speed boost
The high speed booster (combination of edge boost and DC boost) improves the eye width for USB2.0 high
speed signals. It is direction independent and by that is compatible to OTG systems. The BOOST pin is
configuring the booster strength with different values of pull down resistors to set 4 levels of boosts, alternatively
the boost level can be set via I2C register according to I2C mode. Internal circuitry of the signal conditioner
reduces possible overshoot.
7.3.2 RX Sensitivity
The RX_SEN pin is a tri-level pin. It is used to set the gain of the device according to system channel loss. RX
sensitivity can be increased to recover incoming signals with low vertical eye opening to be able to boost weak
signals and helps overcoming high attenuation.
7.4 Device Functional Modes
7.4.1 Low Speed (LS) mode
TUSB217-Q1 automatically detects a LS connection and does not enable signal compensation. CD pin is
asserted high but ENA_HS will be low.
7.4.2 Full Speed (FS) mode
TUSB217-Q1 automatically detects a FS connection and does not enable signal compensation. CD pin is
asserted high but ENA_HS will be low
8
版权 © 2018, Texas Instruments Incorporated
TUSB217-Q1
www.ti.com.cn
ZHCSIS9A –SEPTEMBER 2018–REVISED DECEMBER 2018
Device Functional Modes (接下页)
7.4.3 High Speed (HS) mode
TUSB217-Q1 automatically detects a HS connection and will enable signal compensation as determined by the
configuration of the RX_SEN pin and the external pull down resistance on its BOOST pin.
CD pin and ENA_HS pin are asserted high when high speed boost is active.
7.4.4 High Speed downstream port electrical compliance test mode
TUSB217-Q1 will detect HS compliance test fixture and enter downstream port high speed eye diagram test
mode. CD pin will be low and ENA_HS pin is asserted high when TUSB217-Q1 is in HS eye compliance test
mode.
If RSTN pin is asserted low and de-asserted high while TUSB217-Q1 is operating in HS functional mode,
TUSB217-Q1 will transition to HS eye compliance test mode and CD asserts low and ENA_HS remains high.
When this occurs signal compensation is enabled.
7.4.5 Shutdown mode
TUSB217-Q1 can be disabled when its RSTN pin is asserted low. DP, DM traces are continuous through the
device in shutdown mode. The USB channel is still fully operational, but there is neither signal compensation, nor
any indication from the CD pin as to the status of the channel.
表 1. CD and ENA_HS Pins in Different Modes
MODE
CD
ENA_HS
LOW
Low speed
Full speed
HIGH
HIGH
HIGH
LOW
LOW
LOW
High speed
HIGH
HIGH
LOW
High speed downstream port electrical test
Shutdown
7.4.6 I2C mode
TUSB217-Q1 supports 100 KHz I2C for device configuration, status read back and test purposes. For detail
electrical and functional specifications refer to I2C Bus Specification 2.1, 2001 – STANDARD MODE. This
controller is enabled after SCL and SDA pins are sampled high shortly after return from shutdown. In this mode,
the CSR can be accessed by I2C read/write transaction to 7-bit slave address 0x2C. It is advised to set
CFG_ACTIVE bit before changing values. This halts the FSM, and reset it after all changes are made. This
ensure proper startup into high speed mode.
7.5 TUSB217 Registers
Table 2 lists the memory-mapped registers for the TUSB217 registers. All register offset addresses not listed in
Table 2 should be considered as reserved locations and the register contents should not be modified.
Table 2. TUSB217 Registers
Offset
0x1
Acronym
Register Name
Section
Go
EDGE_BOOST
CONFIGURATION
DC_BOOST
RX_SEN
This register is setting EDGE BOOST level.
This register is selecting device mode.
This register is setting DC BOOST level.
This register is setting RX Sensitivity level.
0x3
Go
0xE
Go
0x25
Go
Complex bit access types are encoded to fit into small table cells. Table 3 shows the codes that are used for
access types in this section.
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TUSB217-Q1
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Table 3. TUSB217 Access Type Codes
Access Type
Read Type
RH
Code
Description
H
R
Set or cleared by hardware
Read
Write Type
W
W
Write
Reset or Default Value
-n
Value after reset or the default
value
7.5.1 EDGE_BOOST Register (Offset = 0x1) [reset = X]
EDGE_BOOST is shown in Figure 3 and described in Table 4.
Return to Summary Table.
This register is setting EDGE BOOST level.
Figure 3. EDGE_BOOST Register
7
6
5
4
3
2
1
0
ACB_LVL
RH/W-X
RESERVED
RH/W-X
Table 4. EDGE_BOOST Register Field Descriptions
Bit
7-4
Field
Type
Reset
Description
ACB_LVL
RH/W
X
XXXXb (sampled at startup from BOOST pin)
0000b to 1111b range
0x0 = BOOST PIN LEVEL 0 (lowest edge boost setting)
0x3 = BOOST PIN LEVEL 1
0x6 = BOOST PIN LEVEL 2
0x8 = BOOST PIN LEVEL 3
0xF = (highest edge boost setting)
3-0
RESERVED
RH/W
X
These bits are reserved bits and set by hardware at reset.
When this register is modified the software should first read these
reserved bits and rewrite with the same values
7.5.2 CONFIGURATION Register (Offset = 0x3) [reset = X]
CONFIGURATION is shown in Figure 4 and described in Table 5.
Return to Summary Table.
This register is selecting device mode.
Figure 4. CONFIGURATION Register
7
6
5
4
3
2
1
0
RESERVED
RH/W-X
CFG_ACTIVE
RH/W-0x1
Table 5. CONFIGURATION Register Field Descriptions
Bit
7-1
Field
RESERVED
Type
Reset
Description
RH/W
X
These bits are reserved bits and set by hardware at reset.
When this register is modified the software should first read these
reserved bits and rewrite with the same values
10
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ZHCSIS9A –SEPTEMBER 2018–REVISED DECEMBER 2018
Table 5. CONFIGURATION Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
0
CFG_ACTIVE
RH/W
0x1
Configuration mode
After reset, if I2C mode is true (SCL and SDA are both pulled high)
set the bit to get into configuration mode and clear to return to
normal mode.
0x0 = NORMAL MODE
0x1 = CONFIGURATION MODE
7.5.3 DC_BOOST Register (Offset = 0xE) [reset = X]
DC_BOOST is shown in Figure 5 and described in Table 6.
Return to Summary Table.
This register is setting DC BOOST level.
Figure 5. DC_BOOST Register
7
6
5
4
3
2
1
0
RESERVED
RH/W-X
DCB_LVL
RH/W-X
Table 6. DC_BOOST Register Field Descriptions
Bit
Field
Type
Reset
Description
7-4
RESERVED
RH/W
X
These bits are reserved bits and set by hardware at reset.
When this register is modified the software should first read these
reserved bits and rewrite with the same values
3-0
DCB_LVL
RH/W
X
XXXXb (sampled at startup from BOOST pin)
0000b to 1111b range
0x0 = BOOST PIN LEVEL 0 (lowest dc boost setting)
0x2 = BOOST PIN LEVEL 1 and 2
0x6 = BOOST PIN LEVEL 3
0xF = (highest dc boost setting)
7.5.4 RX_SEN Register (Offset = 0x25) [reset = X]
RX_SEN is shown in Figure 6 and described in Table 7.
Return to Summary Table.
This register is setting RX Sensitivity level.
Figure 6. RX_SEN Register
7
6
5
4
3
2
1
0
RX_SEN
RH/W-X
Table 7. RX_SEN Register Field Descriptions
Bit
7-0
Field
Type
Reset
Description
RX_SEN
RH/W
X
XXXXb (sampled at startup from RX_SEN pin)
00000000b to 11111111b range
0x0 = RX_SEN LEVEL LOW
0x44 = RX_SEN LEVEL MID
0x77 = RX_SEN LEVEL HIGH
0xFF = (highest setting)
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8 Application and Implementation
注
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The purpose of the TUSB217-Q1 is to re-store the signal integrity of a USB High Speed channel up to the USB
connector. The loss in signal quality stems from reduced channel bandwidth due to high loss PCB trace and
other components that contribute a capacitive load. This can cause the channel to fail the USB near end eye
mask. Proper use of the TUSB217-Q1 can help to pass this eye mask.
A secondary purpose is to use the CD pin of the TUSB217-Q1 to control other blocks on the customer platform,
if so desired.
8.2 Typical Application
A typical application is shown in 图 7. In this setup, D2P and D2M face the USB connector while D1P and D1M
face the USB host. The orientation may be reversed [that is, D2 faces transceiver and D1 faces connector].
Supply
3.3V or 5 V or 2.3V-4.3V (VBAT)
1uF
(optional)
Supply
3.3V or 5 V or 2.3V-4.3V (VBAT)
100 nF
RBOOST
100 nF
RRXSEN2
RESERVED
RRXSEN1
NC
SCL/CD
NC
VCC
SDA
D1P
D1N
RX_SEN/ENA_HS
CON_D2P
CON_D2N
USB_D1P
USB_D1N
D2P
USB
Host or Hub
D2M
(optional)
Copyright © 2018, Texas Instruments Incorporated
图 7. Reference Schematic (design example)
12
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Typical Application (接下页)
8.2.1 Design Requirements
TUSB217-Q1 requires a valid reset signal as described in the power supply recommendations section. The
capacitor at RSTN pin is not required if a micro controller drives the RSTN pin according to recommendations.
For this design example, use the parameters shown in 表 8, 表 9 and 表 10
表 8. Design Parameters for 5 V Supply with High Loss System
PARAMETER
VALUE(1)
5 V ±10%
No
VCC
I2C support required in system (Yes/No)
RBOOST
0-Ω
BOOST Level
0
Boost Level 1:
RBOOST = 1.8 kΩ
Edge and DC Boost
1.8 kΩ ±1%
3.6 kΩ ± 1%
1
2
3
Do Not Install (DNI)
RRXSEN2
RRXSEN1
RX_SEN Level
Low
High RX
22 kΩ - 33 kΩ (27 kΩ typical)
Do Not Install (DNI)
Do Not Install (DNI)
47 kΩ
Sensitivity Level:
RRXSEN1 = 37 kΩ
RRXSEN2 = 47 kΩ
RX Sensitivity
Do Not Install (DNI)
Medium
High
37 kΩ(2)
(1) These parameters are starting values for a high loss system. Further tuning might be required based on specific host and/or device as
well as cable length and loss profile. These settings are not specific to a 5V supply system could be applicable to 3.3V supply system as
well.
(2) This resistor is needed for a 5V supply to divide the voltage down so the BOOST pin voltage does not exceed 3.6V
表 9. Design Parameters for 3.3 V Supply with Low to Medium Loss System
PARAMETER
VALUE(1)
3.3 V ±10%
No
VCC
I2C support required in system (Yes/No)
RBOOST
0-Ω
BOOST Level
0
Boost Level 0:
RBOOST = 0-Ω
Edge and DC Boost
1.8 kΩ ±1%
3.6 kΩ ±1%
1
2
3
Do Not Install (DNI)
RRXSEN2
RRXSEN1
RX_SEN Level
Low
Medium RX
Sensitivity Level:
RRXSEN1 = DNI
RRXSEN2 = DNI
22 kΩ - 33 kΩ (27 kΩ typical)
Do Not Install (DNI)
Do Not Install (DNI)
22 kΩ - 33 kΩ (27 kΩ typical)
RX Sensitivity
Do Not Install (DNI)
Do Not Install (DNI)
Medium
High
(1) These parameters are starting values for a low to medium loss system. Further tuning might be required based on specific host and/or
device as well as cable length and loss profile. These settings are not specific to a 3.3V supply system could be applicable to 5V supply
system as well.
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表 10. Design Parameters for 2.3V - 4.3V VBAT Supply with Low to Medium Loss System
PARAMETER
VALUE(1)
VCC
2.3 V to 4.3V
No
I2C support required in system (Yes/No)
RBOOST
0-Ω
BOOST Level
0
Boost Level 0:
RBOOST = 0-Ω
Edge and DC Boost
1.8 kΩ ±1%
3.6 kΩ ±1%
1
2
3
Do Not Install (DNI)
RRXSEN2
RRXSEN1
RX_SEN Level
Low
Medium RX
Sensitivity Level:
RRXSEN1 = DNI
RRXSEN2 = DNI
22 kΩ - 33 kΩ (27 kΩ typical)
Do Not Install (DNI)
Do Not Install (DNI)
10 kΩ
RX Sensitivity
Do Not Install (DNI)
Medium
High
37 kΩ(2)
(1) These parameters are starting values for a low to medium loss system. Further tuning might be required based on specific host and/or
device as well as cable length and loss profile. These settings are not specific to a 2.3V-4.3V supply system could be applicable to 5V
supply system as well.
(2) This resistor is needed for a VBAT supply (2.3V - 4.3V) to divide the voltage down so the BOOST pin voltage does not exceed 3.6V
8.2.2 Detailed Design Procedure
The ideal BOOST setting is dependent upon the signal chain loss characteristics of the target platform. The
recommendation is to start with BOOST level 0, and then increment to BOOST level 1, and so on. if permissible.
Same applies to the RX sensitivity setting where it is recommended to plan for the required pads or connections
to change boost settings, but to start with RX sensitivity level 1.
In order for the TUSB217-Q1 to recognize any change to the BOOST setting, the RSTN pin must be toggled.
This is because the BOOST pin is latched on power up and the pin is ignored thereafter.
注
The TUSB217-Q1 compensates for extra attenuation in the signal path according to the
configuration of the RX_SEN pin. This pin is not 5 V tolerant and therefore when selecting
the highest RX sensitivity level, the voltage level at RX_SEN pin must be less than 3.6V.
Placement of the device is also dependent on the application goal. 表 11 summarizes our recommendations.
表 11. Platform Placement Guideline
PLATFORM GOAL
Pass USB Near End Mask at the receptacle
Pass USB Far End Eye Mask at the plug
SUGGESTED TUSB217-Q1 PLACEMENT
Close to measurement point (connector)
Close to USB PHY
Cascade multiple TUSB217s to improve device enumeration
Midway between each USB interconnect
表 12. Table of Recommended Settings
BOOST and RX_SEN settings (1)for channel loss
Pre-channel cable length (Between USB
PHY and TUSB217-Q1)
BOOST
RX_SEN
0-3 meter
2-5 meter
Level 0
Level 1
Medium or High
Medium or High
Post-channel cable length (Between
TUSB217-Q1 and inter-connect)
BOOST
RX_SEN
0-2 meter
1-4 meter
Level 0
Level 1
Medium or High
Medium or High
(1) These parameters are starting values for different cable lengths. Further tuning might be required based on specific host and/or device
as well as cable length and loss profile.
14
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ZHCSIS9A –SEPTEMBER 2018–REVISED DECEMBER 2018
8.2.2.1 Test Procedure to Construct USB High Speed Eye Diagram
注
USB-IF certification tests for High Speed eye masks require the mandated use of the
USB-IF developed test fixtures. These test fixtures do not require the use of oscilloscope
probes. Instead they use SMA cables. More information can be found at the USB-IF
Compliance Updates Page. It is located under the Electrical Specifications section, ID 86
dated March 2013.
The following procedure must be followed before using any oscilloscope compliance software to construct a USB
High Speed Eye Mask:
8.2.2.1.1 For a Host Side Application
1. Configure the TUSB217-Q1 to the desired BOOST setting
2. Power on (or toggle the RSTN pin if already powered on) the TUSB217-Q1
3. Using SMA cables, connect the oscilloscope and the USB-IF host-side test fixture to the TUSB217-Q1
4. Enable the host to transmit USB TEST_PACKET
5. Execute the oscilloscope USB compliance software.
6. Repeat the above steps in order to re-test TUSB217-Q1 with a different BOOST setting (must reset to
change)
8.2.2.1.2 For a Device Side Application
1. Configure the TUSB217-Q1 to the desired BOOST setting
2. Power on (or toggle the RSTN pin if already powered on) the TUSB217-Q1
3. Connect a USB host, the USB-IF device-side test fixture, and USB device to the TUSB217-Q1. Ensure that
the USB-IF device test fixture is configured to the ‘INIT’ position
4. Allow the host to enumerate the device
5. Enable the device to transmit USB TEST_PACKET
6. Using SMA cables, connect the oscilloscope to the USB-IF device-side test fixture and ensure that the
device-side test fixture is configured to the ‘TEST’ position.
7. Execute the oscilloscope USB compliance software.
8. Repeat the above steps in order to re-test TUSB217-Q1 with a different BOOST setting (must reset to
change)
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TUSB217-Q1
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8.2.3 Application Curves
TUSB217Q1EVM
Various
cable
lengths
图 8. Near End Eye Measurement Set up With Pre-channel Cable
图 9. 6 inches without TUSB217-Q1
图 10. 6 inches pre-channel with TUSB217-Q1 BOOST=0
RX_SEN=MED
图 11. 6 inches pre-channel with TUSB217-Q1 BOOST=0
图 12. 3 meter without TUSB217-Q1
RX_SEN=HIGH
16
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TUSB217-Q1
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ZHCSIS9A –SEPTEMBER 2018–REVISED DECEMBER 2018
图 13. 3 meter pre-channel with TUSB217-Q1 BOOST=0
图 14. 3 meter pre-channel with TUSB217-Q1 BOOST=0
RX_SEN=MED
RX_SEN=HIGH
图 15. 2 meter without TUSB217-Q1
图 16. 2 meter pre-channel with TUSB217-Q1 BOOST=1
RX_SEN=MED
图 17. 2 meter pre-channel with TUSB217-Q1 BOOST=1
图 18. 5 meter without TUSB217-Q1
RX_SEN=HIGH
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图 19. 5 meter pre-channel with TUSB217-Q1 BOOST=1
图 20. 5 meter pre-channel with TUSB217-Q1 BOOST=1
RX_SEN=MED
RX_SEN=HIGH
18
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ZHCSIS9A –SEPTEMBER 2018–REVISED DECEMBER 2018
TUSB217Q1EVM
Various
cable
lengths
图 21. Near end eye measurement set up with post-channel cable
图 22. 6 inches without TUSB217-Q1
图 23. 6 inches post-channel with TUSB217-Q1 BOOST=0
RX_SEN=MED
图 24. 6 inches post-channel with TUSB217-Q1 BOOST=0
图 25. 1 meter without TUSB217-Q1
RX_SEN=HIGH
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TUSB217-Q1
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图 26. 1 meter post-channel with TUSB217-Q1 BOOST=0
图 27. 1 meter post-channel with TUSB217-Q1 BOOST=0
RX_SEN=MED
RX_SEN=HIGH
图 28. 2 meter without TUSB217-Q1
图 29. 2 meter post-channel with TUSB217-Q1 BOOST=1
RX_SEN=MED
图 30. 2 meter post-channel with TUSB217-Q1 BOOST=1
图 31. 4 meter without TUSB217-Q1
RX_SEN=HIGH
20
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ZHCSIS9A –SEPTEMBER 2018–REVISED DECEMBER 2018
图 32. 4 meter post-channel with TUSB217-Q1 BOOST=1
图 33. 4 meter post-channel with TUSB217-Q1 BOOST=1
RX_SEN=MED
RX_SEN=HIGH
9 Power Supply Recommendations
On power up, the interaction of the RSTN pin and power on ramp could result in digital circuits not being set
correctly. The device should not be enabled until the power on ramp has settled to minimum recommended
supply voltage or higher to ensure a correct power on reset of the digital circuitry. If RSTN cannot be held low by
microcontroller or other circuitry until the power on ramp has settled, then an external capacitor from the RSTN
pin to GND is required to hold the device in the low power reset state.
The RC time constant should be larger than five times of the power on ramp time (0 to VCC). With a typical
internal pullup resistance of 500 kΩ, the recommended minimum external capacitance is calculated as:
[Ramp Time x 5] ÷ [500 kΩ]
(1)
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TUSB217-Q1
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10 Layout
10.1 Layout Guidelines
Although the land pattern has matched trace width to pad width, optimal impedance control is based on the
user's own PCB stack-up. The recommendation is to maintain 90 Ω differential routing underneath the device.
All dimensions are in millimetres (mm).
10.2 Layout Example
217_VCC
C1
0.1uF
L/CD
SCLKD
RSTN
RSTN
GND
RESERVED
C2
0.1 µF
GND GND
BOOST
BOOST
图 34. Layout Example (thermal pad grounding is optional)
22
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TUSB217-Q1
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ZHCSIS9A –SEPTEMBER 2018–REVISED DECEMBER 2018
11 器件和文档支持
11.1 文档支持
11.2 接收文档更新通知
要接收文档更新通知，请导航至 TI.com.cn 上的器件产品文件夹。单击右上角的通知我进行注册，即可每周接收产
品信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
11.3 社区资源
下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，
并且不一定反映 TI 的观点；请参阅 TI 的 《使用条款》。
TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在
e2e.ti.com 中，您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。
设计支持
TI 参考设计支持 可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。
11.4 商标
E2E is a trademark of Texas Instruments.
11.5 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
11.6 术语表
SLYZ022 — TI 术语表。
这份术语表列出并解释术语、缩写和定义。
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TUSB217-Q1
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12 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且
不会对此文档进行修订。如需获取此数据表的浏览器版本，请查阅左侧的导航栏。
24
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TUSB217-Q1
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ZHCSIS9A –SEPTEMBER 2018–REVISED DECEMBER 2018
PACKAGE OUTLINE
RGY0014B
VQFN - 1 mm max height
S
C
A
L
E
3
.
3
0
0
PLASTIC QUAD FLATPACK - NO LEAD
3.6
3.4
B
0.5
0.3
A
0.3
0.2
DETAIL
OPTIONAL TERMINAL
TYPICAL
PIN 1 INDEX AREA
3.6
3.4
0.1 MIN
(0.05)
A
-
A
2
5
.
0
0
0
SECTION A-A
TYPICAL
C
1 MAX
SEATING PLANE
0.08 C
0.05
0.00
2.05 0.05
2X 1.5
(0.2) TYP
8
7
EXPOSED
THERMAL PAD
8X 0.5
9
6
2X
2
A
A
15
SYMM
SEE TERMINAL
DETAIL
2
13
0.3
14X
0.2
14
0.5
1
0.1
0.05
C A B
PIN 1 ID
(OPTIONAL)
SYMM
14X
0.3
4223385/A 11/2016
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
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TUSB217-Q1
ZHCSIS9A –SEPTEMBER 2018–REVISED DECEMBER 2018
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EXAMPLE BOARD LAYOUT
RGY0014B
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(
2.05)
2X (1.5)
SYMM
1
14
14X (0.6)
2
13
14X (0.25)
SYMM
15
(3.3)
(0.775)
8X (0.5)
6
9
(
0.2) TYP
VIA
8
7
(0.775)
(R0.05)
TYP
(3.3)
LAND PATTERN EXAMPLE
SCALE:20X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4223385/A 11/2016
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
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TUSB217-Q1
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ZHCSIS9A –SEPTEMBER 2018–REVISED DECEMBER 2018
EXAMPLE STENCIL DESIGN
RGY0014B
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
2X (1.5)
(0.56)
TYP
1
14
14X (0.6)
2
15
13
14X (0.25)
(0.56)
TYP
SYMM
(3.3)
4X
0.92)
(
8X (0.5)
6
9
METAL
TYP
7
8
SYMM
(R0.05) TYP
(3.3)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 15
80% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:20X
4223385/A 11/2016
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
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27
PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TUSB217RGYRQ1
TUSB217RGYTQ1
ACTIVE
ACTIVE
VQFN
VQFN
RGY
RGY
14
14
3000 RoHS & Green
250 RoHS & Green
SN
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 105
-40 to 105
U217Q1
U217Q1
SN
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
12-Apr-2022
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TUSB217RGYRQ1
TUSB217RGYTQ1
VQFN
VQFN
RGY
RGY
14
14
3000
250
330.0
180.0
12.4
12.4
3.75
3.75
3.75
3.75
1.15
1.15
8.0
8.0
12.0
12.0
Q2
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
12-Apr-2022
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TUSB217RGYRQ1
TUSB217RGYTQ1
VQFN
VQFN
RGY
RGY
14
14
3000
250
367.0
213.0
367.0
191.0
38.0
35.0
Pack Materials-Page 2
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