TUSB564RNQR [TI]
USB Type-C™ 8.1Gbps DP 交替模式灌电流侧线性转接驱动器交叉点开关 | RNQ | 40 | 0 to 70;
| 型号： | TUSB564RNQR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | USB Type-C™ 8.1Gbps DP 交替模式灌电流侧线性转接驱动器交叉点开关 | RNQ | 40 | 0 to 70 开关 驱动 驱动器 |
| 文件： | 总50页 (文件大小：2930K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TUSB564
ZHCSGZ9G –OCTOBER 2017 –REVISED NOVEMBER 2022
TUSB564 USB TYPE-C™ DP 交替模式8.1Gbps
灌电流侧线性转接驱动器交叉点开关
1 特性
2 应用
• USB Type-C™ 交叉点开关支持
• 监控器
• HDTV
• 投影仪
• 扩展坞
– USB 3.1 第1 代+ 2 条DP 1.4 信道
– 4 条DP 1.4 信道
• USB 3.1 第1 代高达5Gbps
• DisplayPort 1.4 高达8.1Gbps (HBR3)
• 支持C、D、E 引脚分配的VESA DisplayPort™ 交
替模式UFP_D 转接驱动交叉点开关
• 超低功耗架构
• 具有高达12dB 均衡功能的线性转接驱动器
• 透明呈现DisplayPort 链路训练
• 自动LFPS 去加重控制，满足USB 3.1 认证要求
• 可通过GPIO 或I2C 进行配置
3 说明
TUSB564 是一种 VESA USB Type-C™ 交替模式转接
驱动开关， 对于上行端口（ 灌电流） ， 支持高达
5Gbps 的 USB 3.1 数据传输速率以及高达 8.1Gbps 的
DisplayPort 1.4 数据传输速率。该器件以 USB Type-C
标准的 VESA DisplayPort 交替模式进行 UFP_D 引脚
分配C、D 和E。
• 支持热插拔
TUSB564 提供有多个接收线性均衡级别，用于补偿由
于线缆或电路板走线损耗产生的码间串扰 (ISI)。该器
件由 3.3V 单电源供电运行，支持商业级温度范围和工
业级温度范围。
• 工业温度范围：–40°C 至85°C (TUSB564I)
• 商用温度范围：0°C 至70°C (TUSB564)
• 4mm x 6mm、0.4mm 间距WQFN 封装
封装信息(1)
封装尺寸（NOM）
器件型号
TUSB564
TUSB564I
封装
RNQ（WQFN，40） 4.00mm × 6.00mm
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
D+/-
TUSB564
SSRX
SSTX
USB Hub
TUSB564
TX1
RX1
RX2
TX2
DP0
DP1
DP2
DP RX
DP3
SBU1
SBU2
AUXn
TUSB564 使用示例
AUXp
HPDIN
CTL 1 0 FLIP
PD Controller
CC1
CC2
HPD
Control
Copyright © 2017, Texas Instruments Incorporated
简化版电路原理图
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLLSF29
TUSB564
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ZHCSGZ9G –OCTOBER 2017 –REVISED NOVEMBER 2022
Table of Contents
8.4 Device Functional Modes..........................................20
8.5 Programming............................................................ 25
8.6 Register Maps...........................................................27
9 Application and Implementation..................................32
9.1 Application Information............................................. 32
9.2 Typical Application.................................................... 32
9.3 System Examples..................................................... 37
10 Power Supply Recommendations..............................40
11 Layout...........................................................................41
11.1 Layout Guidelines................................................... 41
11.2 Layout Example...................................................... 41
12 Device and Documentation Support..........................42
12.1 接收文档更新通知................................................... 42
12.2 支持资源..................................................................42
12.3 Trademarks.............................................................42
12.4 Electrostatic Discharge Caution..............................42
12.5 术语表..................................................................... 42
13 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................4
6 Specifications.................................................................. 7
6.1 Absolute Maximum Ratings........................................ 7
6.2 ESD Ratings............................................................... 7
6.3 Recommended Operating Conditions.........................7
6.4 Thermal Information....................................................7
6.5 Electrical Characteristics.............................................8
6.6 Switching Characteristics..........................................11
6.7 Timing Requirements................................................12
6.8 Typical Characteristics..............................................13
7 Parameter Measurement Information..........................15
8 Detailed Description......................................................17
8.1 Overview...................................................................17
8.2 Functional Block Diagram.........................................18
8.3 Feature Description...................................................19
Information.................................................................... 42
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
Changes from Revision F (September 2019) to Revision G (November 2022)
Page
• 更新了整个文档中的表格、图和交叉参考的编号格式.........................................................................................1
• 在整个数据表中添加了包容性术语......................................................................................................................1
• 将MSL 级别从2 更新为1.................................................................................................................................. 1
Changes from Revision E (May 2019) to Revision F (September 2019)
Page
• Added note to disable AUX snoop to resolve interop issues with a non-compliant AUX source......................19
Changes from Revision D (November 2018) to Revision E (May 2019)
Page
• Added following to pin 38 description: If I2C_EN = “F”, then this pin must be set to “F”or “0”. .......... 4
• Changed GLF min, typ, and max values from -1, 0, 1 to -2.5, 0.5, and 3.5 respectively.....................................8
• Added GLF_LFPS_TX1/2 parameter to AC electrical...............................................................................................8
Changes from Revision C (February 2018) to Revision D (November 2018)
Page
• Changed the RNQ pin image appearance .........................................................................................................4
• Changed the EN pin Description in the Pin Functions table...............................................................................4
• Changed the HPDIN pin From: I/O To: 2 Level I ................................................................................................4
• Added pull-down indicator (PD) in the I/O column on FLIP/SCL and CTL0/SDA pins ...................................... 4
• Added Junction temperature to absolute maximum ratings table.......................................................................7
• From: Internal pull-down resistance for CTL1. To: Internal pull-down resistance for CTL1, CTL0, FLIP, and
EN.......................................................................................................................................................................8
• Deleted EN from Note 1 of 表8-8 ....................................................................................................................24
Changes from Revision B (January 2018) to Revision C (February 2018)
Page
• Changed the column on EN From: I To: 2 Level I (PD) ..................................................................................... 4
• Updated AUX_SBU_OVR Description field in 表8-15 to match 表8-6 ...........................................................29
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ZHCSGZ9G –OCTOBER 2017 –REVISED NOVEMBER 2022
Changes from Revision A (October 2017) to Revision B (January 2018)
Page
• Changed From: DP0EQ_SEL To: DP3EQ_SEL ..............................................................................................27
• Changed From: DP3EQ_SEL To: DP0EQ_SEL ..............................................................................................28
Changes from Revision * (October 2017) to Revision A (October 2017)
Page
• 将器件状态从预告信息更改为量产数据.............................................................................................................1
• 将UFP_D 引脚分配C 和D 更改为UFP_D 引脚分配C、D 和E.......................................................................1
• Added Note which describes AUX snoop feature is only supported in I2C mode. In GPIO mode, AUX snoop
is disabled and all four lanes are enabled. ...................................................................................................... 19
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ZHCSGZ9G –OCTOBER 2017 –REVISED NOVEMBER 2022
5 Pin Configuration and Functions
NC
1
28
27
26
25
24
23
22
21
VCC
DPEQ1
SSEQ1
2
3
AUXn
AUXp
SSRXn
SSRXp
VCC
4
5
6
7
8
SBU2
Thermal
Pad
SBU1
CTL1
SSTXn
SSTXp
CTL0/SDA
FLIP/SCL
Not to scale
图5-1. RNQ Package 40-Pin (WQFN) Top View
表5-1. Pin Functions
PIN
I/O
DESCRIPTION
NAME
DP0p
DP0n
DP1p
DP1n
DP2p
DP2n
DP3p
DP3n
NO.
40
39
37
36
34
33
31
30
Diff O
Diff O
Diff O
Diff O
Diff O
Diff O
Diff O
Diff O
DP Differential positive output for DisplayPort Lane 0.
DP Differential negative output for DisplayPort Lane 0.
DP Differential positive output for DisplayPort Lane 1.
DP Differential negative output for DisplayPort Lane 1.
DP Differential positive output for DisplayPort Lane 2.
DP Differential negative output for DisplayPort Lane 2.
DP Differential positive output for DisplayPort Lane 3.
DP Differential negative output for DisplayPort Lane 3.
Differential negative input for DisplayPort or differential negative output for USB3.1
upstream facing port.
TX1n
TX1p
10
9
Diff I/O
Diff I/O
Differential positive input for DisplayPort or differential positive output for USB3.1
upstream facing port.
RX1n
RX1p
RX2p
RX2n
13
12
16
15
Diff I
Diff I
Diff I
Diff I
Differential negative input for DisplayPort or USB3.1 upstream facing port.
Differential positive input for DisplayPort or USB 3.1 upstream facing port.
Differential positive input for DisplayPort or USB 3.1 upstream facing port.
Differential negative input for DisplayPort or USB 3.1 upstream facing port.
Differential positive input for DisplayPort or differential positive output for USB3.1
upstream Facing port.
TX2p
TX2n
19
18
Diff I/O
Diff I/O
Differential negative input for DisplayPort or differential negative output for USB3.1
upstream Facing port.
SSTXp
SSTXn
SSRXp
8
7
5
Diff I
Diff I
Differential positive input for USB3.1 downstream facing port.
Differential negative input for USB3.1 downstream facing port.
Differential positive output for USB3.1 downstream facing port.
Diff O
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表5-1. Pin Functions (continued)
PIN
I/O
DESCRIPTION
NAME
NO.
SSRXn
4
Diff O
Differential negative output for USB3.1 downstream facing port.
This pin along with EQ0 sets the USB receiver equalizer gain for upstream facing RX1
and RX2 when USB used. Up to 11dB of EQ available.
EQ1
EQ0
14
11
4 Level I
This pin along with EQ1 sets the USB receiver equalizer gain for upstream facing RX1
and RX2 when USB used. Up to 11 dB of EQ available.
4 Level I
Device Enable, when I2C_EN = '0'. Device disable function not used when I2C_EN ≠
'0'.
2 Level I
(PD)
L = Device Disabled
H = Device Enabled
EN
29
32
17
On rising edge of EN pin, the device will sample all 4-level inputs including the I2C_EN
pin. EN pin will not reset the I2C registers.
Hot Plug Detect. This pin is an input for Hot Plug Detect received from DisplayPort sink.
When HPDIN is Low for greater than 2ms, all DisplayPort lanes are disabled while the
AUX to SBU switch will remain closed.
HPDIN
I2C_EN
2 Level I
4 Level I
I2C Programming Mode or GPIO Programming Select. I2C is only disabled when this
pin is ‘0'.
0 = GPIO mode (I2C disabled)
R = TI Test Mode (I2C enabled at 3.3 V)
F = I2C enabled at 1.8 V
1 = I2C enabled at 3.3 V.
SBU1. This pin should be DC coupled to the SBU1 pin on the Type-C receptacle. A 2-M
ohm resistor to GND is also recommended.
SBU1
SBU2
24
25
I/O, CMOS
I/O, CMOS
SBU2. This pin should be DC coupled to the SBU2 pin on the Type-C receptacle. A 2-M
ohm resistor to GND is also recommended.
AUXp. DisplayPort AUX positive I/O connected to the DisplayPort sink through a AC
coupling capacitor. In addition to AC coupling capacitor, this pin also requires a 1M
resistor to DP_PWR (3.3 V). This pin along with AUXN is used by the TUSB564 for
AUX snooping and is routed to SBU1/2 based on the orientation of the Type-C.
AUXp
AUXn
26
27
I/O, CMOS
I/O, CMOS
AUXn. DisplayPort AUX negative I/O connected to the DisplayPort sink through a AC
coupling capacitor. In addition to AC coupling capacitor, this pin also requires a 1M
resistor to GND. This pin along with AUXP is used by the TUSB564 for AUX snooping
and is routed to SBU1/2 based on the orientation of the Type-C.
DisplayPort Receiver EQ. This along with DPEQ0 will select the DisplayPort receiver
equalization gain.
DPEQ1
2
35
3
4 Level I
4 Level I
4 Level I
DisplayPort Receiver EQ. This along with DPEQ1 will select the DisplayPort receiver
equalization gain. When I2C_EN ≠'0', this pin will also set the TUSB564 I2C address.
DPEQ0/A1
SSEQ1
Along with SSEQ0, sets the USB receiver equalizer gain for downstream facing
SSTXP/N.
Along with SSEQ1, sets the USB receiver equalizer gain for downstream facing
SSTXP/N. When I2C_EN ≠'0', this pin will also set the TUSB564 I2C address. If
I2C_EN = “F”, then this pin must be set to “F”or “0”.
SSEQ0/A0
FLIP/SCL
CTL0/SDA
38
21
22
4 Level I
2 Level I
(Failsafe)
(PD)
When I2C_EN = ’0’this is Flip control pin, otherwise this pin is I2C clock. . When
used for I2C clock pullup to I2C controller's VCC I2C supply.
2 Level I
(Failsafe)
(PD)
When I2C_EN = '0' this is a USB3.1 Switch control pin, otherwise this pin is I2C data.
When used for I2C data pullup to I2C controller's VCC I2C supply.
DP Alt mode Switch Control Pin. When I2C_EN = ‘0’, this pin will enable or disable
DisplayPort functionality. Otherwise, when I2C_EN ≠'0', DisplayPort functionality is
enabled and disabled through I2C registers.
2 Level I
(Failsafe)
(PD)
CTL1
23
L = DisplayPort Disabled.
H = DisplayPort Enabled.
VCC
NC
6, 20, 28
1
P
3.3-V Power Supply
NC
No connect pin. Leave open.
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ZHCSGZ9G –OCTOBER 2017 –REVISED NOVEMBER 2022
表5-1. Pin Functions (continued)
PIN
I/O
DESCRIPTION
NAME
NO.
GND
Thermal Pad
G
Ground
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature and voltage range (unless otherwise noted)(1)
MIN
MAX
4
UNIT
V
VCC
Supply Voltage Range
-0.3
VIN_DIFF
VIN_SE
VIN_CMOS
Differential Voltage at Differential Inputs
Input Voltage at Differential Inputs
Input Voltage at CMOS Inputs
TUSB564 Junction Temperature
TUSB564I Junction Temperature
Storage temperature
±2.5
4
V
-0.5
-0.3
V
4
V
110
125
150
°C
°C
°C
TJ
TSTG
-65
(1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
6.2 ESD Ratings
VALUE
UNIT
Human body model (HBM), per ANSI/ESDA/
JEDEC JS-001, all pins(1)
±5000
V(ESD)
Electrostatic discharge
V
Charged device model (CDM), per JEDEC
specification JESD22-C101, all pins(2)
±1500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature and voltage range (unless otherwise noted)
MIN
0
NOM
MAX
70
UNIT
°C
TA
Ambient temperature for TUSB564
Ambient temperature for TUSB564I
Supply voltage
TA
-40
3
85
°C
VCC
3.3
3.6
100
3.6
100
V
VCC_RAMP Power supply ramp
0.1
1.7
ms
V
VI2C
Supply that external resistors on SDA and SCL are pulled up to
Power supply noise on VCC
VPSN
mV
6.4 Thermal Information
TUSB564
THERMAL METRIC(1)
RNQ (WQFN)
UNIT
40 PINS
37.6
20.7
9.5
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
0.2
ΨJT
9.4
ΨJB
RθJC(bot)
2.3
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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6.5 Electrical Characteristics
over operating free-air temperature and voltage range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Power
PCC-
Average active power in USB-only mode CTL1 = L; CTL0 = H; Link in U0 at 5
while in U0. Gbps;
330
660
mW
mW
ACTIVE-
USB
PCC-
Average active power in USB + 2 lane DP CTL1 = H; CTL0 = H; USB in U0 at 5
ACTIVE-
USB-DP
mode.
Gbps; DP at 8.1 Gbps;
PCC-
CTL1 = H; CTL0 = L; Four DP lanes at
8.1 Gbps
Average active power in 4 lane DP mode.
660
2.5
2.5
mW
mW
mW
ACTIVE-DP
PCC-NC- Average power in USB mode while in
CTL1 = L; CTL0 = H; No USB device
detected;
disconnect state.
USB
Average power in USB mode while in
U2/U3 state
PCC-U2U3
CTL1 = L; CTL0 = H; Link in U2 or U3;
CTL1 = L; CTL0 = L; I2C_EN = "0";
PCC-
Average power in Shutdown mode.
0.7
mW
SHUTDOW
N
4-State CMOS Inputs(EQ[1:0], SSEQ[1:0], DPEQ[1:0], I2C_EN)
IIH
IIL
High-level input current
Low-level input current
Threshold 0 / R
VCC = 3.6 V; VIN = 3.6 V
VCC = 3.6 V; VIN = 0 V
VCC = 3.3 V
20
80
µA
µA
V
-160
-40
0.55
1.65
2.7
45
4-Level
VTH
Threshold R/ Float
VCC = 3.3 V
V
Threshold Float / 1
VCC = 3.3 V
V
RPU
RPD
Internal pull up resistance
Internal pull-down resistance
kΩ
kΩ
95
2-State CMOS Input (CTL0, CTL1, FLIP, EN, HPDIN) CTL1, CTL0 and FLIP are Failsafe
VIH
VIL
High-level input voltage
Low-level input voltage
2
0
3.6
0.8
V
V
Internal pull-down resistance for CTL1,
CTL0, FLIP, and EN.
RPD
500
kΩ
IIH
IIL
High-level input current
Low-level input current
VIN = 3.6 V
-25
-25
25
25
µA
µA
VIN = GND, VCC = 3.6 V
I2C Control Pins SCL, SDA
0.7 x
VI2C
VIH
VIL
High-level input voltage
Low-level input voltage
I2C_EN ! = 0
I2C_EN ! = 0
3.6
V
V
0.3 ×
VI2C
0
VOL
Low-level output voltage
Low-level output current
Input current on SDA pin
Input capacitance
I2C_EN ! = 0; IOL = 3 mA
0
20
0.4
V
IOL
I2C_EN ! = 0; VOL = 0.4 V
0.1 × VI2C < Input voltage < 3.3 V
mA
µA
pF
Ii_I2C
Ci_I2C
-10
10
10
USB Differential Receiver (RX1P/N, RX2P/N, SSTXP/N)
AC-coupled differential peak-to-peak
signal measured post CTLE through a
reference channel
VRX-DIFF- Input differential peak-peak voltage swing
2000
0
mVpp
linear dynamic range
PP
VRX-DC-
Common-mode voltage bias in the
receiver (DC)
V
CM
RRX-DIFF-
Present after a USB3.1 device is detected
on TXP/TXN
Differential input impedance (DC)
72
120
Ω
DC
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6.5 Electrical Characteristics (continued)
over operating free-air temperature and voltage range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
RRX-CM-
Present after a USB3.1 device is detected
on TXP/TXN
Receiver DC Common Mode impedance
18
30
Ω
DC
ZRX-HIGH-
Present when no USB3.1 device is
detected on TXP/TXN. Measured over the
range of 0-500 mV with respect to GND.
Common-mode input impedance with
termination disabled (DC)
25
kΩ
mV
mV
mV
IMP-DC-
POS
VSIGNAL-
Input Differential peak-to-peak Signal
Detect Assert Level
at 5 Gbps, No loss and bit rate PRBS7
pattern
70
50
DET-DIFF-
PP
VRX-IDLE-
Input Differential peak-to-peak Signal
Detect De-assert Level
at 5 Gbps, No loss and bit rate PRBS7
pattern
DET-DIFF-
PP
VRX-LFPS-
Low-frequency Periodic Signaling (LFPS)
Detect Threshold
Below the minimum is squelched.
100
300
1
DET-DIFF-
PP
CRX
RX input capacitance to GND
At 2.5 GHz
0.5
-16
-17
-12
12
pF
dB
dB
dB
dB
50 MHz –1.25 GHz at 90 Ω
2.5 GHz at 90 Ω
RLRX-DIFF Differential Return Loss
RLRX-CM Common Mode Return Loss
50 MHz –2.5 GHz at 90 Ω
SSEQ[1:0] and EQ[1:0] at 2.5 GHz.
EQSSP
Receiver equalization
USB Differential Transmitter (TX1P/N, TX2P/N, SSRXP/N)
VTX-DIFF- Transmitter dynamic differential voltage
1300
mVpp
mV
swing range.
PP
VTX-RCV- Amount of voltage change allowed during
at 3.3 V
600
600
2
Receiver Detection
DETECT
Transmitter idle common-mode voltage
change while in U2/U3 and not actively
transmitting LFPS
measured at the connector side of the AC
coupling caps with 50 Ω load
VTX-CM-
-600
0
mV
V
IDLE-DELTA
VTX-DC-
Common-mode voltage bias in the
transmitter (DC)
CM
VTX-CM-
At 3.3V; Max mismatch from Txp+Txn for
both time and amplitude
Tx AC Common-mode voltage active
100 mVpp
AC-PP-
ACTIVE
VTX-IDLE- AC Electrical idle differential peak-to-peak
At package pins
0
0
10
14
mV
mV
output voltage
DIFF-AC-PP
VTX-IDLE- DC Electrical idle differential output
At package pins after low-pass filter to
remove AC component
voltage
DIFF-DC
VTX-CM-
Absolute DC common mode voltage
between U1 and U0
DC-
At package pin
At 2.5 GHz
200
mV
ACTIVE-
IDLE-DELTA
CTX
TX input capacitance to GND
1.25
120
pF
RTX-DIFF Differential impedance of the driver
75
75
Ω
CAC-
AC Coupling capacitor
265
nF
COUPLING
Measured with respect to AC ground over
0-500 mV
RTX-CM
Common-mode impedance of the driver
18
30
67
Ω
ITX-SHORT TX short circuit current
RLTX-DIFF Differential Return Loss
TX± shorted to GND
mA
dB
-17
-12
-10
50 MHz –1.25 GHz at 90 Ω
RLTX-
Differential Return Loss
dB
dB
2.5 GHz at 90 Ω
DIFF-2.5G
RLTX-CM Common Mode Return Loss
50 MHz –2.5 GHz at 90 Ω
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6.5 Electrical Characteristics (continued)
over operating free-air temperature and voltage range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
AC Electrical Characteristics for USB and DP
Differential Cross Talk between TX and
RX signal Pairs
Crosstalk
at 2.5 GHz
-27
0.5
0.8
dB
dB
dB
GLF
Low-frequency voltage gain.
at 100 MHz, 600 mVpp VID
-2.5
0
3.5
1.6
GLF_LFPS Low-frequency voltage gain for SSTX-
at 10 to 50MHz sine wave; 1.0Vpp VID;
EQ = 0; FLIP = 0 and 1;
>TX1/TX2 path.
_TX1/2
at 100 MHz, 200 mVpp < VID < 2000
mVpp
CP1 dB-LF Low-frequency 1-dB compression point
CP1 dB-HF High-frequency 1-dB compression point
1000
mVpp
at 2.5 GHz, 200 mVpp < VID < 2000
mVpp
1000
20
mVpp
kHz
fLF
Low-frequency cutoff
200 mVpp < VID < 2000 mVpp
50
200 mVpp < VID < 2000 mVpp, PRBS7, 5
Gbps
DJ_5G
TX output deterministic jitter
0.04
UIpp
200 mVpp < VID < 2000 mVpp, PRBS7,
8.1 Gbps
DJ_8.1G
TJ_5G
TX output deterministic jitter
TX output total jitter
0.08
0.07
0.12
UIpp
UIpp
UIpp
200 mVpp < VID < 2000 mVpp, PRBS7, 5
Gbps
200 mVpp < VID < 2000 mVpp, PRBS7,
8.1 Gbps
TJ_8.1G
TX output total jitter
DisplayPort Receiver (TX1P/N, TX2P/N, RX1P/N, RX2P/N)
Peak-to-peak input differential dynamic
voltage range
VID_PP
2000
0
mV
VIC
Input Common Mode Voltage
AC coupling capacitance
Receiver Equalizer
V
CAC
EQDP
dR
75
80
265
nF
dB
DPEQ1, DPEQ0 at 4.05 GHz
HBR3
12
Data rate
8.1 Gbps
Rti
Input Termination resistance
100
120
Ω
DisplayPort Transmitter (DP[3:0]P/N)
VTX-
VOD dynamic range
1300
mV
mA
DIFFPP
ITX-SHORT TX short circuit current
TX± shorted to GND
67
AUXP/N and SBU1/2
VCC = 3.3 V; VIN = 0 to 0.4 V for AUXP;
VIN = 2.7 V to 3.6 V for AUXN
RON
Output ON resistance
5
10
1
Ω
Ω
RON-
VCC = 3.3 V; VIN = 0 to 0.4 V for AUXP;
VIN= 2.7 V to 3.6 V for AUXN
ΔON resistance mismatch within pair
MISMATCH
ON resistance flatness (RONmax–RON
min) measured at identical VCC and
temperature
VCC = 3.3 V; VIN = 0 to 0.4 V for AUXP;
VIN = 2.7 V to 3.6 V for AUXN
RON_FLAT
2
Ω
VAUXP_DC AUX Channel DC common mode voltage
VCC = 3.3 V
VCC = 3.3 V
0
0.4
3.6
V
V
for AUXP and SBU2.
_CM
VAUXN_D AUX Channel DC common mode voltage
2.7
for AUXN and SBU1
C_CM
CAUX_ON ON-state capacitance
CAUX_OFF OFF-state capacitance
VCC = 3.3 V; CTL1 = 1; VIN = 0 V or 3.3 V
VCC = 3.3 V; CTL1 = 0; VIN = 0 V or 3.3 V
4
3
7
6
pF
pF
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6.6 Switching Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
AUXp/n and SBU1/2
TAUX_PD Switch propagation delay
1400
7500
ps
ns
TAUX_SW_ Switching time CTL1 to switch OFF. Not
including TCTL1_DEBOUNCE
.
OFF
TAUX_SW_
Switching time CTL1 to switch ON
Intra-pair output skew
3000
400
ns
ps
ON
TAUX_INT
RA
USB3.1 and DisplayPort mode transition requirement (GPIO mode)
Min overlap of CTL0 and CTL1 when
TGP_USB_
transitioning from USB 3.1 only mode to
4
3
µs
4DP
4-Lane DisplayPort mode or vice versa
TCTL1_DE CTL1 and HPDIN debounce time when
10
1
ms
transitioning from H to L
BOUNCE
I2C (SDA and SCL)
fSCL
tBUF
I2C clock frequency
MHz
µs
Bus free time between START and STOP
conditions
0.5
Hold time after repeated START
condition. After this period, the first clock
pulse is generated
tHDSTA
0.26
µs
tLOW
tHIGH
Low period of the I2C clock
High period of the I2C clock
0.5
µs
µs
0.26
Setup time for a repeated START
condition
tSUSTA
0.26
µs
tHDDAT
tSUDAT
tR
Data hold time
0
µs
ns
ns
Data setup time
50
Rise time of both SDA and SCL signals
120
120
20 ×
(VI2C/5.5
V)
tF
Fall time of both SDA and SCL signals
ns
tSUSTO
Cb
Setup time for STOP condition
Capacitive load for each bus line
0.26
µs
pF
100
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6.7 Timing Requirements
MIN
NOM
MAX
UNIT
USB 3.1
tIDLEEntry
,
Delay from U0 to electrical idle
10
6
ns
ns
tIDLEExit_U1 U1 exist time: break in electrical idle to the transmission of LFPS
tIDLEExit_U2U
U2/U3 exit time: break in electrical idle to transmission of LFPS
10
µs
3
tRXDET_INTV
RX detect interval while in Disconnect
12
ms
L
tIDLEExit_DIS
Disconnect Exit Time
10
1
µs
ms
ps
C
tExit_SHTDN Shutdown Exit Time (CTL0 = VCC/2 to U2/U3)
Differential Propagation Delay (20%-80% of differential voltage measured
1.7 inch from the output pin)
tDIFF_DLY
300
1
tPWRUPACTI
Time when Vcc reaches 70% to device active
ms
ps
ps
VE
tR, tF
Output Rise/Fall Time
40
Output Rise/Fall time mismatch (20%-80% of differential voltage measured
1.7 inch from the output pin)
tRF-MM
5
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6.8 Typical Characteristics
图6-1. DisplayPort EQ Settings Curves
图6-2. USB RX (DFP) EQ Settings Curves
1600
1400
1200
1000
800
600
400
200
0
EQ0
EQ6
EQ12
EQ2
EQ7
EQ15
EQ4
EQ10
0
200
400
600
800
1000
1200
1400
1600
1800
2000
Differential Input Voltage (mV)
图6-4. DisplayPort Linearity Curves at 4.05 GHz
图6-3. USB TX (UFP) EQ Settings Curves
1600
1400
1200
1000
800
600
400
200
0
1800
1600
1400
1200
1000
800
600
400
200
0
EQ0
EQ6
EQ12
EQ2
EQ7
EQ15
EQ4
EQ10
EQ0
EQ6
EQ12
EQ2
EQ7
EQ15
EQ4
EQ10
0
200
400
600
800
1000
1200
1400
1600
1800
2000
0
200
400
600
800
1000
1200
1400
1600
1800
2000
Differential Input Voltage (mV)
Differential Input Voltage (mV)
图6-5. USB TX (DFP) Linearity Curves at 2.5 GHz
图6-6. USB RX (UFP) Linearity Curves at 2.5 GHz
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6.8 Typical Characteristics (continued)
0
-5
0
-5
-10
-15
-20
-25
-30
-10
-15
-20
-25
RX1
TX1
SSTX
DP0
DP3
SSRX
TX1
-30
0.01
0.1
1
10
0.01
0.1
1
10
Frequency(GHz)
Frequency(GHz)
图6-7. Input Return Loss Performance
图6-8. Output Return Loss Performance
)
)
v
v
i
i
D
D
/
/
V
V
m
m
0
0
5
5
1
1
(
(
e
e
tag
tag
l
l
o
o
V
V
t
t
u
u
p
p
t
t
u
u
O
O
Time (20.57 ps/Div)
Time (33.33 ps/Div)
图6-9. DisplayPort HBR3 Eye-Pattern Performance with 12-inch
图6-10. USB 3.1 Gen1 Eye-Pattern Performance with 12-inch
Input PCB Trace at 8.1 Gbps
Input PCB Trace at 5 Gbps
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7 Parameter Measurement Information
70%
SDA
30%
t
t
t
F
HDSTA
R
tHIGH
t
t
LOW
BUF
70%
30%
SCL
S
P
P
S
t
t
SUSTO
t
t
SUDAT
HDDAT
HDSTA
t
SUSTA
图7-1. I2C Timing Diagram Definitions
4us
(min)
CTL1 pin
CTL0 pin
图7-2. USB3.1 to 4-Lane DisplayPort in GPIO Mode
IN
T
T
DIFF_DLY
DIFF_DLY
OUT
图7-3. Propagation Delay
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IN+
V
Vcm
RX-LFPS-DET-DIFF-PP
IN-
T
T
IDLEEntry
IDLEExit
OUT+
Vcm
OUT-
图7-4. Electrical Idle Mode Exit and Entry Delay
80%
20%
t
r
t
f
图7-5. Output Rise and Fall Times
50%
50%
CTL1
90%
10%
V
OUT
T
AUX_SW_ON
T
+ T
CTL1_DEBOUNCE
AUX_SW_OFF
图7-6. AUX and SBU Switch ON and OFF Timing Diagram
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8 Detailed Description
8.1 Overview
The TUSB564 is a VESA USB Type-C Alt Mode redriving switch supporting data rates up to 8.1 Gbps for
upstream facing port. This device uses 5th generation USB redriver technology. The device is used for UFP pin
assignments C and D from the VESA DisplayPort Alt Mode on USB Type-C Standard.
The TUSB564 provides several levels of receive equalization to compensate for cable and board trace loss
which if not equalized causes inter-symbol interference (ISI) when USB 3.1 Gen 1 or DisplayPort 1.4 signals
travel across a PCB or cable. This device requires a 3.3-V power supply. It comes in a commercial temperature
range and industrial temperature range.
For a sink application, the TUSB564 enables the system to pass both transmitter compliance and receiver jitter
tolerance tests for USB 3.1 Gen 1 and DisplayPort version 1.4 HBR3. The re-driver recovers incoming data by
applying equalization that compensates for channel loss, and drives out signals with a high differential voltage.
Each channel has a receiver equalizer with selectable gain settings. The equalization should be set based on
the amount of insertion loss in the channels connected to the TUSB564. Independent equalization control for
each channel can be set using EQ[1:0], SSEQ[1:0], and DPEQ[1:0] pins.
The TUSB564 advanced state machine makes it transparent to hosts and devices. After power up, the TUSB564
periodically performs receiver detection on the TX pairs. If it detects a USB 3.1 receiver, the RX termination is
enabled, and the TTUSB564 is ready to re-drive.
The device ultra-low-power architecture operates at a 3.3-V power supply and achieves Enhanced performance.
The automatic LFPS De-Emphasis control further enables the system to be USB3.1 compliant.
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8.2 Functional Block Diagram
SSRXp
SSRXn
Driver
DPEQ_SEL
EQ
SSEQ_SEL
SSTXp
SSTXn
EQ
TX1p
Driver
TX1n
EQ_SEL
DPEQ_SEL
DP0p
DP0n
Driver
RX1p
EQ
RX1n
MUX
RX2n
EQ
RX2p
DP1p
DP1n
DPEQ_SEL
EQ_SEL
Driver
TX2n
Driver
DP2p
DP2n
TX2p
Driver
EQ
DPEQ_SEL
DP3p
DP3n
Driver
EQ_SEL
SSEQ_SEL
DPEQ_SEL
DPEQ[1:0]/A1
EQ[1:0]
I2C_EN
SSEQ[1:0]/A0
FSM, Control Logic and
Registers
FLIP/SCL
CTL0/SDA
HPDIN
EN
I2C
Target
CTL1
M
U
X
SBU1
SBU2
AUXn
AUXp
VREG
VCC
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8.3 Feature Description
8.3.1 USB 3.1
The TUSB564 supports USB 3.1 Gen 1 datarates up to 5 Gbps. The TUSB564 supports all the USB defined
power states (U0, U1, U2, and U3). Because the TUSB564 is a linear redriver, it can’t decode USB3.1 physical
layer traffic. The TUSB564 monitors the actual physical layer conditions like receiver termination, electrical idle,
LFPS, and SuperSpeed signaling rate to determine the USB power state of the USB 3.1 interface.
The TUSB564 features an intelligent low frequency periodic signaling (LFPS) detector. The LFPS detector
automatically senses the low frequency signals and disables receiver equalization functionality. When not
receiving LFPS, the TUSB564 enables receiver equalization based on the EQ[1:0] and SSEQ[1:0] pins or values
programmed into EQ1_SEL, EQ2_SEL, and SSEQ_SEL registers.
8.3.2 DisplayPort
The TUSB564 supports up to 4 DisplayPort lanes at datarates up to 8.1Gbps (HBR3). The TUSB564, when
configured in DisplayPort mode, monitors the native AUX traffic as it traverses between DisplayPort source and
DisplayPort sink. For the purposes of reducing power, the TUSB564 manages the number of active DisplayPort
lanes based on the content of the AUX transactions. The TUSB564 snoops native AUX writes to DisplayPort
sink ’ s DPCD registers 0x00101 (LANE_COUNT_SET) and 0x00600 (SET_POWER_STATE).
TUSB564disables/enables lanes based on value written to LANE_COUNT_SET. The TUSB564 disables all
lanes when SET_POWER_STATE is in the D3. Otherwise, active lanes are based on value of
LANE_COUNT_SET.
DisplayPort AUX snooping is enabled by default but can be disabled by changing the AUX_SNOOP_DISABLE
register. Once AUX snoop is disabled, management of TUSB564 DisplayPort lanes are controlled through
various configuration registers.
备注
AUX snooping feature is only supported when TUSB564 is configured for I2C mode. When TUSB564
is configured for GPIO mode, the AUX snoop feature is disabled and all four DP lanes are enabled if
HPDIN is asserted high.
When TUSB564’s AUX snoop feature is enabled, the syncs defined by the DisplayPort standard
must be received in order for AUX snoop feature to function properly. AUX writes to panel’s DPCD
address 0x00600 and 0x00101 should result in SET_POWER_STATE and LANE_COUNT_SET fields
at TUSB564’s offset 0x12 to get set to the appropriate value. If these fields do not get set correctly,
then incoming AUX may not be compliant. If this is the case, then it is best to disable AUX snoop by
setting the AUX_SNOOP_DISABLE field at offset 0x13.
8.3.3 4-Level Inputs
The TUSB564 has (I2C_EN, EQ[1:0], DPEQ[1:0], and SSEQ[1:0]) 4-level inputs pins that are used to control the
equalization gain and place TUSB564 into different modes of operation. These 4-level inputs utilize a resistor
divider to help set the 4 valid levels and provide a wider range of control settings. There is an internal 35 kΩ pull-
up and a 95 kΩ pull-down. These resistors, together with the external resistor connection combine to achieve the
desired voltage level.
表8-1. 4-Level Control Pin Settings
LEVEL
SETTINGS
Option 1: Tie 1 KΩ 5% to GND.
Option 2: Tie directly to GND.
0
R
F
Tie 20 KΩ 5% to GND.
Float (leave pin open)
Option 1: Tie 1 KΩ 5%to VCC
.
.
1
Option 2: Tie directly to VCC
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备注
All four-level inputs are latched on rising edge of internal reset. After tcfg_hd, the internal pull-up and
pull-down resistors will be isolated in order to save power.
8.3.4 Receiver Linear Equalization
The purpose of receiver equalization is to compensate for channel insertion loss and the resulting inter-symbol
interference in the system before the input or after the output of the TUSB564. The receiver overcomes these
losses by attenuating the low frequency components of the signals with respect to the high frequency
components. The proper gain setting should be selected to match the channel insertion loss. Two 4-level input
pins enable up to 16 possible equalization settings. USB3.1 upstream path, USB3.1 downstream path, and
DisplayPort each have their own two 4-level inputs. The TUSB564 also provides the flexibility of adjusting
settings through I2C registers.
8.4 Device Functional Modes
8.4.1 Device Configuration in GPIO Mode
The TUSB564 is in GPIO configuration when I2C_EN = “0”. The TUSB564 supports the following
configurations: USB 3.1 only, 2 DisplayPort lanes + USB 3.1, or 4 DisplayPort lanes (no USB 3.1). The CTL1 pin
controls whether DisplayPort is enabled. The combination of CTL1 and CTL0 selects between USB 3.1 only, 2
lanes of DisplayPort, or 4-lanes of DisplayPort as detailed in 表 8-2. The AUXp or AUXn to SBU1 or SBU2
mapping is controlled based on 表8-3.
After power-up (VCC from 0 V to 3.3 V), the TUSB564 defaults to USB3.1 mode. The USB PD controller upon
detecting no device attached to Type-C port or USB3.1 operation not required by attached device must take
TUSB564 out of USB3.1 mode by transitioning the CTL0 pin from L to H and back to L.
表8-2. GPIO Configuration Control
VESA DisplayPort ALT MODE
UFP_D CONFIGURATION
CTL1 PIN
CTL0 PIN
FLIP PIN
CONFIGURATION
L
L
L
L
L
H
L
Power Down
Power Down
—
—
—
—
C
L
H
H
L
One Port USB 3.1 - No Flip
One Port USB 3.1 –With Flip
4 Lane DP - No Flip
L
H
L
H
H
H
H
L
H
L
C
4 Lane DP –With Flip
H
H
One Port USB 3.1 + 2 Lane DP- No Flip
One Port USB 3.1 + 2 Lane DP–With Flip
D
H
D
表8-3. GPIO AUXp or AUXn to SBU1 or SBU2 Mapping
CTL1 PIN
FLIP PIN
MAPPING
SBU1 →AUXn
SBU2 →AUXp
H
L
SBU2 →AUXn
SBU1 →AUXp
H
H
X
L > 2 ms
Open
表8-4 details the TUSB564 mux routing. This table is valid for both I2C and GPIO configuration modes.
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表8-4. INPUT to OUTPUT Mapping
FROM
TO
OUTPUT PIN
NA
CTL1 PIN
CTL0 PIN
FLIP PIN
INPUT PIN
NA
L
L
L
L
L
H
NA
NA
RX1p
RX1n
SSTXp
SSTXn
RX2p
RX2n
SSTXp
SSTXn
TX2p
TX2n
RX2p
RX2n
RX1p
RX1n
TX1p
TX1n
TX1p
TX1n
RX1p
RX1n
RX2p
RX2n
TX2p
TX2n
RX1p
RX1n
SSTXp
SSTXn
TX2p
TX2n
RX2p
RX2n
RX2p
RX2n
SSTXp
SSTXn
TX1p
TX1n
RX1p
RX1n
SSRXp
SSRXn
TX1p
L
L
H
H
L
TX1n
SSRXp
SSRXn
TX2p
H
TX2n
DP0p
DP0n
DP1p
DP1n
DP2p
DP2n
DP3p
DP3n
DP0p
DP0n
DP1p
DP1n
DP2p
DP2n
DP3p
DP3n
SSRXp
SSRXn
TX1p
H
H
H
H
L
L
H
L
L
TX1n
H
DP0p
DP0n
DP1p
DP1n
SSRXp
SSRXn
TX2p
TX2n
H
H
DP0p
DP0n
DP1p
DP1n
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8.4.2 Device Configuration In I2C Mode
The TUSB564 is in I2C mode when I2C_EN is not equal to “0”. The same configurations defined in GPIO
mode are also available in I2C mode. The TUSB564 USB3.1 and DisplayPort configuration is controlled based
on 表8-5. The AUXp or AUXn to SBU1 or SBU2 mapping control is based on 表8-6.
表8-5. I2C Configuration Control
REGISTERS
VESA DisplayPort ALT MODE
UFP_D CONFIGURATION
CONFIGURATION
CTLSEL1
CTLSEL0
FLIPSEL
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Power Down
Power Down
—
—
—
—
C
One Port USB 3.1 - No Flip
One Port USB 3.1 –With Flip
4 Lane DP - No Flip
C
4 Lane DP –With Flip
One Port USB 3.1 + 2 Lane DP- No Flip
One Port USB 3.1 + 2 Lane DP–With Flip
D
D
表8-6. I2C AUXp or AUXn to SBU1 or SBU2 Mapping
REGISTERS
MAPPING
AUX_SBU_OVR
CTLSEL1
FLIPSEL
SBU1 →AUXn
SBU2 →AUXp
00
1
0
SBU2 →AUXn
SBU1 →AUXp
00
00
01
1
0
X
1
X
X
Open
SBU1 →AUXn
SBU2 →AUXp
SBU2 →AUXn
SBU1 →AUXp
10
11
X
X
X
X
Open
8.4.3 DisplayPort Mode
The TUSB564 supports up to four DisplayPort lanes at datarates up to 8.1 Gbps. TUSB564 can be enabled for
DisplayPort through GPIO control pin CTL1 or through I2C register CTLSEL1. When I2C_EN is ‘0’,
DisplayPort is controlled based on 表 8-2. When not in GPIO mode, DisplayPort functionality is controlled
through I2C registers. Data transfer through the DisplayPort lanes is further controlled by the HPDIN pin.
DisplayPort needs to be enabled using CTL1 pin or CTLSEL1 register and also HPDIN needs to be pulled high
for the DisplayPort data trasfer to be enabled through the DisplayPort lanes.
备注
When operating in 4-lane DP mode (CTLSEL[1:0]
=
2h) with AUX snoop disabled
(AUX_SNOOP_DISABLE = 1), all four DP lanes must be enabled (DP0_DISABLE = DP1_DISABLE =
DP2_DISABLE = DP3_DISABLE = 0).
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8.4.4 Linear EQ Configuration
Each of the TUSB564 receiver lanes has individual controls for receiver equalization. The receiver equalization
gain value can be controlled either through I2C registers or through GPIOs. 表8-7 details the gain value for each
available combination when TUSB564 is in GPIO mode. These same options are also available in I2C mode by
updating registers DP0EQ_SEL, DP1EQ_SEL, DP2EQ_SEL, DP3EQ_SEL, EQ1_SEL, EQ2_SEL, and
SSEQ_SEL. Each of the 4-bit EQ configuration registers is mapped to the configuration pins as follows: x_SEL =
{x1[1:0],x0[1:0]} where xn[1:0] are the EQ configuration pins with pin levels mapped to 2-bit values as: 0 = 00, R
= 01, F = 10, 1 = 11.
表8-7. TUSB564 Receiver Equalization GPIO Control
USB3.1 UPSTREAM FACING PORTS
USB 3.1 DOWNSTREAM FACING PORT
ALL DISPLAYPORT LANES
Equalization
Setting #
EQ GAIN at
SSEQ1 PIN
LEVEL
SSEQ0 PIN
LEVEL
EQ GAIN at 2.5
GHz (dB)
DPEQ1 PIN
LEVEL
DPEQ0 PIN
LEVEL
EQ GAIN at
EQ1 PIN LEVEL EQ0 PIN LEVEL
2.5 GHz (dB)
-0.9
0.2
4.05 GHz (dB)
-0.3
1.6
0
1
0
0
0
R
F
1
0
0
0
R
F
1
-2.4
-1.3
-0.4
0.7
1.5
2.5
3.2
4.0
4.8
5.5
6.0
6.6
7.1
7.6
8.0
8.5
0
0
0
R
F
1
2
0
1.2
0
0
3.0
3
0
2.2
0
0
4.4
4
R
R
R
R
F
F
F
F
1
0
3.1
R
R
R
R
F
F
F
F
1
0
R
R
R
R
F
F
F
F
1
0
5.4
5
R
F
1
4.0
R
F
1
R
F
1
6.5
6
4.8
7.3
7
5.6
8.1
8
0
6.3
0
0
8.9
9
R
F
1
7.0
R
F
1
R
F
1
9.5
10
11
12
13
14
15
7.5
10.0
10.6
11.0
11.4
11.8
12.1
8.1
0
8.5
0
0
1
R
F
1
9.1
1
R
F
1
1
R
F
1
1
9.5
1
1
1
9.9
1
1
8.4.5 USB3.1 Modes
The TUSB564 monitors the physical layer conditions like receiver termination, electrical idle, LFPS, and
SuperSpeed signaling rate to determine the state of the USB3.1 interface. Depending on the state of the USB
3.1 interface, the TUSB564 can be in one of four primary modes of operation when USB 3.1 is enabled (CTL0 =
H or CTLSEL0 = 1b1): Disconnect, U2/U3, U1, and U0.
The Disconnect mode is the state in which TUSB564 has not detected far-end termination on upstream facing
port (UFP) or downstream facing port (DFP). The disconnect mode is the lowest power mode of each of the four
modes. The TUSB564 remains in this mode until far-end receiver termination has been detected on both UFP
and DFP. The TUSB564 immediately exits this mode and enter U0 once far-end termination is detected.
Once in U0 mode, the TUSB564 will redrive all traffic received on UFP and DFP. U0 is the highest power mode
of all USB3.1 modes. The TUSB564 remains in U0 mode until electrical idle occurs on both UFP and DFP. Upon
detecting electrical idle, the TUSB564 immediately transitions to U1.
The U1 mode is the intermediate mode between U0 mode and U2/U3 mode. In U1 mode, the TUSB564 UFP
and DFP receiver termination remains enabled. The UFP and DFP transmitter DC common mode is maintained.
The power consumption in U1 is similar to power consumption of U0.
Next to the disconnect mode, the U2/U3 mode is next lowest power state. While in this mode, the TUSB564
periodically performs far-end receiver detection. Anytime the far-end receiver termination is not detected on
either UFP or DFP, the TUSB564 leaves the U2/U3 mode and transitions to the Disconnect mode. It also
monitors for a valid LFPS. Upon detection of a valid LFPS, the TUSB564 immediately transitions to the U0
mode. In U2/U3 mode, the TUSB564 receiver terminations remain enabled but the TX DC common mode
voltage is not maintained.
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8.4.6 Operation Timing –Power Up
Tctl_db
Mode of operation
determined by value of
FLIPSEL bit and CTLSEL[1:0]
bits at offset0x0A. Default
is USB3.1- only no Flip.
USB3.1-only
FLIP = 0
DISABLED
In I2C mode
If(( CTL[1:0 ] ==2'b 00 | CTL[1:0 ] ==2'b01 ) & FLIP == 0 ) {
USB3.1- only no FLIP;
} ELSEIF((CTL[1:0 ] ==2'b 00 | CTL[1:0 ] ==2'b01 ) & FLIP == 1 ){
USB3.1- only with FLIP;
} ELSEIF(CTL[1:0 ] ==2'b10 & FLIP ==0 ) {
4-Lane DP no FLIP;
} ELSEIF(CTL[1:0 ] ==2'b10 & FLIP ==1 ){
4-Lane DP with FLIP;
} ELSEIF(CTL[1:0 ] ==2'b11 & FLIP ==0 ) {
2-Lane DP USB3.1 no FLIP;
USB3.1-only
FLIP = 0
DISABLED
In GPIO mode
} ELSE{
2-Lane DP USB3.1 with FLIP ;
};
CTL[1:0 pins
]
FLIP pin
VCC (min)
VCC
Td_pg
Internal
Power
Good
T Cfg_su
TCfg_hd
CFG pins
图8-1. Power-Up Timing
表8-8. Power-Up Timing(1) (2)
PARAMETER
MIN
MAX
UNIT
µs
td_pg
VCC (minimum) to Internal Power Good asserted high
CFG(1) pins setup(2)
500
tcfg_su
tcfg_hd
50
10
µs
CFG(1) pins hold
µs
tCTL_DB
CTL[1:0] and FLIP pin debounce
VCC supply ramp requirement
16
ms
ms
tVCC_RAMP
0.1
100
(1) Following pins comprise CFG pins: I2C_EN, EQ[1:0], SSEQ[1:0], and DPEQ[1:0].
(2) Recommend CFG pins are stable when VCC is at minimum value.
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8.5 Programming
For further programmability, the TUSB564 can be controlled using I2C. The SCL and SDA pins are used for I2C
clock and I2C data respectively.
表8-9. TUSB564 I2C Target Address
DPEQ0/A1
PIN LEVEL
SSEQ0/A0
PIN LEVEL
Bit 7 (MSB)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0 (W/R)
0
0
0
R
F
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0
0
R
R
R
R
F
F
F
F
1
0
R
F
1
0
R
F
1
0
1
R
F
1
1
1
The following procedure should be followed to write to TUSB564 I2C registers:
1. The controller initiates a write operation by generating a start condition (S), followed by the TUSB564 7-bit
address and a zero-value “W/R”bit to indicate a write cycle.
2. The TUSB564 acknowledges the address cycle.
3. The controller presents the sub-address (I2C register within TUSB564) to be written, consisting of one byte
of data, MSB-first.
4. The TUSB564 acknowledges the sub-address cycle.
5. The controller presents the first byte of data to be written to the I2C register.
6. The TUSB564 acknowledges the byte transfer.
7. The controller may continue presenting additional bytes of data to be written, with each byte transfer
completing with an acknowledge from the TUSB564.
8. The controller terminates the write operation by generating a stop condition (P).
The following procedure should be followed to read the TUSB564 I2C registers:
1. The controller initiates a read operation by generating a start condition (S), followed by the TUSB564 7-bit
address and a one-value “W/R”bit to indicate a read cycle.
2. The TUSB564 acknowledges the address cycle.
3. The TUSB564 transmit the contents of the memory registers MSB-first starting at register 00h or last read
sub-address+1. If a write to the I2C register occurred prior to the read, then the TUSB564 shall start at the
sub-address specified in the write.
4. The TUSB564 shall wait for either an acknowledge (ACK) or a not-acknowledge (NACK) from the controller
after each byte transfer; the I2C controller acknowledges reception of each data byte transfer.
5. If an ACK is received, the TUSB564 transmits the next byte of data.
6. The controller terminates the read operation by generating a stop condition (P).
The following procedure should be followed for setting a starting sub-address for I2C reads:
1. The controller initiates a write operation by generating a start condition (S), followed by the TUSB564 7-bit
address and a zero-value “W/R”bit to indicate a write cycle.
2. The TUSB564 acknowledges the address cycle.
3. The controller presents the sub-address (I2C register within TUSB564) to be written, consisting of one byte
of data, MSB-first.
4. The TUSB564 acknowledges the sub-address cycle.
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5. The controller terminates the write operation by generating a stop condition (P).
备注
If no sub-addressing is included for the read procedure, and reads start at register offset 00h and
continue byte by byte through the registers until the I2C controller terminates the read operation. If a
I2C address write occurred prior to the read, then the reads start at the sub-address specified by the
address write.
表8-10. Register Legend
ACCESS TAG
NAME
Read
MEANING
R
W
S
The field may be read by software
The field may be written by software
Write
Set
The field may be set by a write of one. Writes of zeros to the field have no effect.
The field may be cleared by a write of one. Write of zero to the field have no effect.
Hardware may autonomously update this field.
C
Clear
U
Update
No Access
NA
Not accessible or not applicable
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8.6 Register Maps
8.6.1 General Register (address = 0x0A) [reset = 00000001]
图8-2. General Registers
7
6
5
4
3
2
1
0
Reserved
R
Reserved
EQ_OVERRIDE HPDIN_OVRRI
DE
FLIPSEL
CTLSEL[1:0].
R/W
R
R/W
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表8-11. General Registers
Bit
Field
Type
Reset
Description
7:5
Reserved.
R
00
Reserved.
Setting of this field will allow software to use EQ settings from
registers instead of value sample from pins.
0 –EQ settings based on sampled state of the EQ pins
(SSEQ[1:0], EQ[1:0], and DPEQ[1:0]).
4
EQ_OVERRIDE
R/W
0
1 –EQ settings based on programmed value of each of the EQ
registers
Controls whether DisplayPort functionality is controlled by
CTLSEL1 register or CTL1 pin.
0 –DisplayPort enable/disable is based on CTLSEL1 register.
1 –DisplayPort enable/disable is based on state of CTL1 pin.
3
2
DP_EN_CTRL
FLIPSEL
R/W
R/W
0
0
FLIPSEL. Refer to 表8-5 and 表8-6 for this field functionality.
00 –Disabled. All RX and TX for USB3 and DisplayPort are
disabled.
1:0
CTLSEL[1:0].
R/W
01
01 –USB3.1 only enabled. (Default)
10 –Four DisplayPort lanes enabled.
11 –Two DisplayPort lanes and one USB3.1
8.6.2 DisplayPort Control/Status Registers (address = 0x10) [reset = 00000000]
图8-3. DisplayPort Control/Status Registers (0x10)
7
6
5
4
3
2
1
0
DP1EQ_SEL
R/W/U
DP3EQ_SEL
R/W/U
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表8-12. DisplayPort Control/Status Registers (0x10)
Bit
Field
Type
Reset
Description
Field selects EQ level for DP lane 1. When EQ_OVERRIDE =
1’b0, this field reflects the sampled state of DPEQ[1:0] pins.
When EQ_OVERRIDE = 1’b1, software can change the EQ
setting for DP lane 1 based on value written to this field.
7:4
DP1EQ_SEL
R/W/U
0000
Field selects EQ level for DP lane 3. When EQ_OVERRIDE =
1’b0, this field reflects the sampled state of DPEQ[1:0] pins.
When EQ_OVERRIDE = 1’b1, software can change the EQ
setting for DP lane 3 based on value written to this field.
3:0
DP3EQ_SEL
R/W/U
0000
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8.6.3 DisplayPort Control/Status Registers (address = 0x11) [reset = 00000000]
图8-4. DisplayPort Control/Status Registers (0x11)
7
6
5
4
3
2
1
0
DP0EQ_SEL
R/W/U
DP2EQ_SEL
R/W/U
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表8-13. DisplayPort Control/Status Registers (0x11)
Bit
Field
Type
Reset
Description
Field selects EQ level for DP lane 0. When EQ_OVERRIDE =
1’b0, this field reflects the sampled state of DPEQ[1:0] pins.
When EQ_OVERRIDE = 1’b1, software can change the EQ
setting for DP lane 0 based on value written to this field.
7:4
DP0EQ_SEL
R/W/U
0000
Field selects EQ level for DP lane 2. When EQ_OVERRIDE =
1’b0, this field reflects the sampled state of DPEQ[1:0] pins.
When EQ_OVERRIDE = 1’b1, software can change the EQ
setting for DP lane 2 based on value written to this field.
3:0
DP2EQ_SEL
R/W/U
0000
8.6.4 DisplayPort Control/Status Registers (address = 0x12) [reset = 00000000]
图8-5. DisplayPort Control/Status Registers (0x12)
7
Reserved
R
6
5
4
3
2
LANE_COUNT_SET
RU
1
0
SET_POWER_STATE
RU
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表8-14. DisplayPort Control/Status Registers (0x12)
Bit
Field
Type
Reset
Description
7
Reserved
R
0
Reserved
This field represents the snooped value of the AUX write to
DPCD address 0x00600. When AUX_SNOOP_DISABLE = 1’
b0, the TUSB564 will enable/disable DP lanes based on the
snooped value. When AUX_SNOOP_DISABLE = 1’b1, then
DP lane enable/disable are determined by state of
DPx_DISABLE registers, where x = 0, 1, 2, or 3. This field is
reset to 2’b00 by hardware when CTLSEL1 changes from a
1’b1 to a 1’b0.
6:5
SET_POWER_STATE
R/U
00
This field represents the snooped value of AUX write to DPCD
address 0x00101 register. When AUX_SNOOP_DISABLE = 1’
b0, TUSB564 will enable DP lanes specified by the snoop value.
Unused DP lanes will be disabled to save power. When
AUX_SNOOP_DISABLE = 1’b1, then DP lanes enable/disable
are determined by DPx_DISABLE registers, where x = 0, 1, 2, or
3. This field is reset to 0x0 by hardware when CTLSEL1
changes from a 1’b1 to a 1’b0.
4:0
LANE_COUNT_SET
R/U
00000
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8.6.5 DisplayPort Control/Status Registers (address = 0x13) [reset = 00000000]
图8-6. DisplayPort Control/Status Registers (0x13)
7
6
5
4
3
2
1
0
AUX_SNOOP_
DISABLE
Reserved
AUX_SBU_OVR
R/W
DP3_DISABLE DP2_DISABLE DP1_DISABLE DP0_DISABLE
R/W
R
R/W R/W R/W R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表8-15. DisplayPort Control/Status Registers (0x13)
Bit
7
Field
Type
R/W
R
Reset
Description
0 –AUX snoop enabled. (Default)
1 –AUX snoop disabled.
AUX_SNOOP_DISABLE
Reserved
0
0
6
Reserved
This field overrides the AUXp or AUXn to SBU1 or SBU2
connect and disconnect based on CTL1 and FLIP. Changing this
field to 2’b01 or 2'b10 will allow traffic to pass through AUX to
SBU regardless of the state of CTLSEL1 and FLIPSEL register
00 –AUX to SBU connect/disconnect determined by CTLSEL1
and FLIPSEL (Default)
5:4
AUX_SBU_OVR
R/W
00
01 –AUXn -> SBU1 and AUXp -> SBU2 connection always
enabled.
10 –AUXn -> SBU2 and AUXp -> SBU1 connection always
enabled.
11 –AUX to SBU open.
When AUX_SNOOP_DISABLE = 1’b1, this field can be used
to enable or disable DP lane 3. When AUX_SNOOP_DISABLE
= 1’b0, changes to this field will have no effect on lane 3
functionality.
0 –DP Lane 3 Enabled (default)
1 –DP Lane 3 Disabled.
3
2
1
0
DP3_DISABLE
DP2_DISABLE
DP1_DISABLE
DP0_DISABLE
R/W
R/W
R/W
R/W
0
0
0
0
When AUX_SNOOP_DISABLE = 1’b1, this field can be used
to enable or disable DP lane 2. When AUX_SNOOP_DISABLE
= 1’b0, changes to this field will have no effect on lane 2
functionality.
0 –DP Lane 2 Enabled (default)
1 –DP Lane 2 Disabled.
When AUX_SNOOP_DISABLE = 1’b1, this field can be used
to enable or disable DP lane 1. When AUX_SNOOP_DISABLE
= 1’b0, changes to this field will have no effect on lane 1
functionality.
0 –DP Lane 1 Enabled (default)
1 –DP Lane 1 Disabled.
DISABLE. When AUX_SNOOP_DISABLE = 1’b1, this field
can be used to enable or disable DP lane 0. When
AUX_SNOOP_DISABLE = 1’b0, changes to this field will have
no effect on lane 0 functionality.
0 –DP Lane 0 Enabled (default)
1 –DP Lane 0 Disabled.
8.6.6 USB3.1 Control/Status Registers (address = 0x20) [reset = 00000000]
图8-7. USB3.1 Control/Status Registers (0x20)
7
6
5
4
3
2
1
0
EQ2_SEL
R/W/U
EQ1_SEL
R/W/U
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LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表8-16. USB3.1 Control/Status Registers (0x20)
Bit
Field
Type
Reset
Description
Field selects EQ level for USB3.1 RX2 receiver. When
EQ_OVERRIDE = 1’b0, this field reflects the sampled state of
EQ[1:0] pins. When EQ_OVERRIDE = 1’b1, software can
change the EQ setting for USB3.1 RX2 receiver based on value
written to this field.
7:4
EQ2_SEL
R/W/U
0000
Field selects EQ level for USB3.1 RX1 receiver. When
EQ_OVERRIDE = 1’b0, this field reflects the sampled state of
EQ[1:0] pins. When EQ_OVERRIDE = 1’b1, software can
change the EQ setting for USB3.1 RX1 receiver based on value
written to this field.
3:0
EQ1_SEL
R/W/U
0000
8.6.7 USB3.1 Control/Status Registers (address = 0x21) [reset = 00000000]
图8-8. USB3.1 Control/Status Registers (0x21)
7
6
5
4
3
2
1
0
Reserved
R
SSEQ_SEL
R/W/U
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表8-17. USB3.1 Control/Status Registers (0x21)
Bit
Field
Type
Reset
Description
7:4
Reserved
R
0000
Reserved
Field selects between 0 to 11 dB of EQ for USB3.1 SSTXP/N
receiver. When EQ_OVERRIDE = 1’b0, this field reflects the
sampled state of SSEQ[1:0] pins. When EQ_OVERRIDE = 1’
b1, software can change the EQ setting for USB3.1 SSTXP/N
receiver based on value written to this field.
3:0
SSEQ_SEL
R/W/U
0000
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8.6.8 USB3.1 Control/Status Registers (address = 0x22) [reset = 00000000]
图8-9. USB3.1 Control/Status Registers (0x22)
7
6
5
4
3
2
1
0
CM_ACTIVE
LFPS_EQ
U2U3_LFPS_D DISABLE_U2U
DFP_RXDET_INTERVAL
R/W
USB3_COMPLIANCE_CTRL
EBOUNCE
3_RXDET
R/U
R/W
R/W
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表8-18. USB3.1 Control/Status Registers (0x22)
Bit
Field
Type
Reset
Description
0 –device not in USB 3.1 compliance mode. (Default)
1 –device in USB 3.1 compliance mode
7
CM_ACTIVE
R/U
0
Controls whether settings of EQ based on EQ1_SEL, EQ2_SEL
and SSEQ_SEL applies to received LFPS signal.
0 –EQ set to zero when receiving LFPS (default)
1 –EQ set to EQ1_SEL, EQ2_SEL, and SSEQ_SEL when
receiving LFPS.
6
LFPS_EQ
R/W
0
0 –No debounce of LFPS before U2/U3 exit. (Default)
1 –200us debounce of LFPS before U2/U3 exit.
5
4
U2U3_LFPS_DEBOUNCE
DISABLE_U2U3_RXDET
R/W
R/W
0
0
0 –Rx.Detect in U2/U3 enabled. (Default)
1 –Rx.Detect in U2/U3 disabled.
This field controls the Rx.Detect interval for the Downstream
facing port (TX1P/N and TX2P/N).
00 –8 ms
01 –12 ms (default)
10 –Reserved
3:2
1:0
DFP_RXDET_INTERVAL
R/W
R/W
00
00
11 –Reserved
00 –FSM determined compliance mode. (Default)
01 –Compliance Mode enabled in DFP direction (SSTX ->
TX1/TX2)
10 –Compliance Mode enabled in UFP direction (RX1/RX2 ->
SSRX)
USB3_COMPLIANCE_CTRL
11 –Compliance Mode Disabled.
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9 Application and Implementation
备注
以下应用部分中的信息不属于TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客 户应负责确定
器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。
9.1 Application Information
The TUSB564 is a linear redriver designed specifically to compensation for intersymbol interference (ISI) jitter
caused by signal attenuation through a passive medium like PCB traces and cables. Because the TUSB564 has
four independent DisplayPort 1.4 inputs, one upstream facing USB 3.1 Gen 1 input, and two downstream facing
USB 3.1 Gen 1 inputs, it can be optimized to correct ISI on all those seven inputs through 16 different
equalization choices. Placing the TUSB564 between a USB3.1 Host/DisplayPort 1.4 GPU and a USB3.1 Type-C
receptacle can correct signal integrity issues resulting in a more robust system.
9.2 Typical Application
E
A
B
F
PCB Trace of Length XEF
PCB Trace of Length XAB
SSRXP
SSRXN
SSTXP
USB3.1
Hub
RX2P
SSTXN
RX2N
TX2P
TX2N
TUSB564
DP0P
DP0N
DP1P
DP1N
TX1N
TX1P
DP 1.4
RX
DP2P
RX1N
RX1P
DP2N
DP3P
DP3N
PCB Trace of Length XGH
PCB Trace of Length XCD
H
G
D
C
Copyright © 2017, Texas Instruments Incorporated
图9-1. TUSB564 in a Host Application
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9.2.1 Design Requirements
For this design example, use the parameters shown in 表9-1.
表9-1. Design Parameters
PARAMETER
A to B PCB trace length, XAB
C to D PCB trace length, XCD
E to F PCB trace length, XEF
G to H PCB trace length, XGH
PCB trace width
VALUE
12 inches
12 inches
2 inches
2 inches
4 mils
AC-coupling capacitor (75 nF to 265 nF)
VCC supply (3 V to 3.6 V)
I2C Mode or GPIO Mode
100 nF
3.3 V
I2C Mode. (I2C_EN pin != "0")
3.3V I2C. Pull-up the I2C_EN pin to 3.3V with a 1K ohm resistor.
CTL1, EQ[1:0], SSEQ[1:0], and DPEQ[1:0] pin unconnected.
1.8V or 3.3V I2C Interface
EQ setting for DisplayPort Lanes
EQ setting for Downstream USB Data Path
EQ setting for Upstream USB Data Path
EQ Setting # 5 (Register 0x0A[4] = 1'b1, 0x10 = 0x55; 0x11 = 0x55)
EQ Setting # 6 (Register 0x0A[4] = 1'b1, 0x20 = 0x66)
EQ Setting # 6 (Register 0x0A[4] = 1'b1, 0x21 = 0x08)
9.2.2 Detailed Design Procedure
A typical usage of the TUSB564 device is shown in 图 9-2. The device can be controlled either through its GPIO
pins or through its I2C interface. In the example shown below, a Type-C PD controller is used to configure the
device through the I2C interface. In I2C mode, the equalization settings for each receiver can be independently
controlled through I2C registers. For this reason, the configuration pin CTL1 and all of the equalization pins
(EQ[1:0], SSEQ[1:0], and DPEQ[1:0]) can be left unconnected. If these pins are left unconnected, the TUSB564
7-bit I2C target address will be 0x12 because both DPEQ/A1 and SSEQ0/A0 will be at pin level "F". If a different
I2C target address is desired, DPEQ/A1 and SSEQ0/A0 pins should be set to a level which produces the desired
I2C target address.
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3.3V
100nF
100nF
100nF
10mF
USB 3.1 Hub
100nF
SSRXP
RX2p
RX2n
TX2p
TX2n
SSRXp
SSRXn
100nF
100nF
100nF
USB Type-C
Receptacle
SSRXN
100nF
100nF
SSTXp
SSTXn
SSTXP
SSTXN
A12
A11
A10
A9
GND
GND
B1
DP_PWR (3.3V)
RXP2
TXP2
TXN2
B2
1M (± 5%)
DP1.4 RX
RXN2
NC
SRC_DET#
B3
100nF
100nF
AUXp
AUXn
AUXP
VBUS
AUXN
B4
VBUS
CC2
SRC_DET
A8
SBU1
SBU1
SBU2
B5
1M (± 5%)
DN1
A7
100nF
100nF
DP2
DN2
B6
DP0p
DP_ML0P
2M
DP1
A6
2M
DP0n
DP1p
DP_ML0N
DP_ML1P
DP_ML1N
DP_ML2P
DP_ML2N
DP_ML3P
DP_ML3N
B7
100nF
100nF
100nF
100nF
100nF
100nF
CC1
A5
SBU2
VBUS
B8
DP1n
VBUS
A4
100 nF
100 nF
TX1n
DP2p
DP2n
B9
A3
TXN1
B10
TX1p
RX1n
RXN1
RXP1
GND
DP3p
DP3n
TXP1
A2
RX1p
B11
3.3V
A1
GND
B12
I2C_EN
3.3V
3.3V
SSEQ0/A0
SSEQ1
VI2C
R
R
DPEQ0/A1
DPEQ1
EQ0
FLIP/SCL
3.3V
3.3V
3.3V
3.3V
CTL0/SDA
CTL1
Type-C
PD
Controller
EQ1
HPDIN
EN
Copyright © 2017, Texas Instruments Incorporated
图9-2. Application Circuit
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9.2.3 Support for DisplayPort UFP_D Pin Assignment E
The TUSB564 device can be used in a system that handles DisplayPort UFP_D Pin Assignment E use-case if
special measures are taken as described below. With UFP_D Pin Assignment E, the polarity of both the main
link and AUX signals is inverted on the Type-C receptacle pins relative to Pin Assignment C. Moreover, on the
Type-C receptacle, the location of Lane 0 is swapped with Lane 1 and that of Lane 2 is swapped with Lane 3
relative to Pin Assignment C. For correct reception of the DisplayPort video signal, the system has to
comprehend the above-described signaling variation.
The use of the TUSB564 device in a system that handles Pin Assignment E depends on whether AUX-to-SBU
switching of the DisplayPort AUX signal is performed internally by the TUSB564 or by external devices such as a
PD controller. It also depends on the configuration mode used: I2C Mode or GPIO Mode. In all those scenarios
the TUSB564 passes the polarity of the Main Link signals as received. The DisplayPort sink has to handle the
polarity inversion of those signals. Moreover, the DisplayPort sink has to handle the lane swapping with the
following lane-to-pin mapping as received by the TUSB564 device: Lane 0 → DP1, Lane 1 → DP0, Lane 2 →
DP3, and Lane 3 →DP2.
The use-case with the AUX-to-SBU switching performed internally by the TUSB564 device is shown in 图 9-3. If
the TUSB564 device configuration is through the I2C Mode, AUX snooping has to be disabled by setting
AUX_SNOOP_DISABLE register 0x13[7] = 1'b1, and manual AUX-to-SBU switching has to be performed
through the AUX_SBU_OVR register 0x13[5:4]: AUX_SBU_OVR = 2’b01 for normal USB Type-C plug
orientation, or AUX_SBU_OVR = 2’b10 for flipped USB Type-C plug orientation when Pin Assignment E
signals are received. If the TUSB564 device configuration is through the GPIO Mode, all 4 DisplayPort lanes are
automatically activated. The DisplayPort sink device has to handle the polarity inversion of both the AUX and
Main Link signals as well as main link lane swapping.
TX1
RX1
DP0
DP1
ML0
ML1
RX2
TX2
DP2
DP3
ML2
ML3
TUSB564
SBU1
SBU2
AUXn
AUXp
DP SINK
3.3V
1M (+/-5%)
Make AUX connections as short as
possible to minimize stub effects
SRC_DET#
AUXP
100nF
100nF
SBU2
SBU1
SBU2
PD Controller
AUXP
AUXN
AUXN
SBU1
SRC_DET
2M
1M (+/-5%)
2M
Copyright © 2017, Texas Instruments Incorporated
图9-3. DisplayPort AUX Connections for UFP_D Pin Assignment E with Internal AUX Switching
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The use-case with the AUX-to-SBU switching performed by an external device is shown in 图 9-4. In this case, it
is assumed that the PD controller is capable of correcting the polarity inversion of the AUX signal and the
TUSB564 is provided with the corrected polarity of the AUX signal through its AUXp/AUXn pins. If the TUSB564
device configuration is through the I2C Mode, AUX snooping should be disabled by setting
AUX_SNOOP_DISABLE register 0x13[7] = 1'b1. The DisplayPort sink device has to handle the polarity inversion
of the Main Link signals as well as the Main Link lane swapping.
TX1
RX1
DP0
DP1
ML0
ML1
RX2
TX2
DP2
DP3
ML2
ML3
TUSB564
SBU1
SBU2
AUXn
AUXp
DP SINK
3.3V
1M (+/-5%)
Make AUX connections as short as
possible to minimize stub effects
SRC_DET#
AUXP
100nF
100nF
SBU2
SBU1
SBU2
PD Controller
AUXP
AUXN
AUXN
SBU1
SRC_DET
2M
1M (+/-5%)
2M
Copyright © 2017, Texas Instruments Incorporated
图9-4. DisplayPort AUX Connections for UFP_D Pin Assignment E with External AUX Switching
9.2.4 PCB Insertion Loss Curves
0
-5
-10
-15
-20
-25
-30
-35
-40
-45
-50
-55
-60
Length=12in, Width=6mil
Length=16in, Width=6mil
Length=20in, Width=6mil
Length=24in, Width=6mil
Length=4in, Width=4mil
Length=8in, Width=10mil
Length=8in, Width=6mil
0
2
4
6
8
10
Frequency (GHz)
12
14
16
D009
图9-5. Insertion Loss of FR4 PCB Traces
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9.3 System Examples
9.3.1 USB 3.1 Only
The TUSB564 is in USB3.1 only when the CTL1 pin is low and CTL0 pin is high.
D+/-
D+/-
1 Port USB
USB Host
TUSB546A-DCI
SSTX
USB Hub
TUSB564
SSRX
SSTX
SSRX
RX2
TX1
RX1
RX2
TX2
TX2
TX1
DP0
DP0
DP1
DP2
DP1
DP2
RX1
GPU
DP RX
DP3
DP3
SBU1
SBU2
SBU2
SBU1
AUXn
AUXp
AUXp
HPDIN
AUXn
HPDIN
FLIP 0 1 CTL
PD Controller
FLIP 0 1 CTL
CC1
CC2
HPD
HPD
Control
CC1
CC2
PD Controller
Control
CTL1/0/FLIP=L/H/L
CTL1/0/FLIP=L/H/L
Copyright © 2017, Texas Instruments Incorporated
图9-6. USB3.1 Only –No Flip (CTL1 = L, CTL0 = H, FLIP = L)
D+/-
D+/-
1 Port USB
USB Host
USB Hub
TUSB564
TUSB546A-DCI
SSTX
SSRX
SSRX
SSTX
RX2
TX1
RX1
RX2
TX2
TX2
TX1
DP0
DP1
DP2
DP0
DP1
RX1
DP2
GPU
DP RX
DP3
DP3
AUXp
SBU1
SBU2
SBU2
SBU1
AUXn
AUXp
AUXn
HPDIN
HPDIN
FLIP 0 1 CTL
PD Controller
FLIP 0 1 CTL
PD Controller
CC1
CC2
HPD
HPD
Control
CC1
CC2
Control
CTL1/0/FLIP=L/H/H
CTL1/0/FLIP=L/H/H
Copyright © 2017, Texas Instruments Incorporated
图9-7. USB3.1 Only –With Flip (CTL1 = L, CTL0 = H, FLIP = H)
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9.3.2 USB 3.1 and 2 Lanes of DisplayPort
The TUSB564 operates in USB3.1 and 2 Lanes of DisplayPort mode when the CTL1 pin is high and CTL0 pin is
high.
1 Port USB &
2 Lane DP
D+/-
D+/-
USB Host
USB Hub
SSRX
SSTX
SSTX
SSRX
TUSB546A-DCI
TUSB564
TX1
RX1
RX2
TX2
RX2
TX2
TX1
RX1
DP0
DP1
DP0
DP1
DP2
DP2
GPU
DP RX
DP3
DP3
AUXp
AUXn
SBU1
SBU2
SBU1
SBU2
AUXp
AUXn
HPDIN
HPDIN
FLIP 0 1 CTL
PD Controller
FLIP 0 1 CTL
PD Controller
HPD
HPD
Control
CC1
CC2
CC1
CC2
Control
CTL1/0/FLIP=H/H/L
CTL1/0/FLIP=H/H/L
Copyright © 2016, Texas Instruments Incorporated
图9-8. USB3.1 + 2 Lane DP –No Flip (CTL1 = H, CTL0 = H, FLIP = L)
1 Port USB &
2 Lane DP
D+/-
D+/-
USB Host
USB Hub
TUSB546A-DCI
TUSB564
SSRX
SSTX
SSTX
SSRX
RX2
TX1
RX1
RX2
TX2
TX2
TX1
RX1
DP0
DP1
DP2
DP0
DP1
DP2
GPU
DP RX
DP3
DP3
SBU1
SBU2
AUXp
AUXn
SBU1
SBU2
AUXn
AUXp
HPDIN
HPDIN
FLIP 0 1 CTL
PD Controller
FLIP 0 1 CTL
PD Controller
HPD
Control
HPD
Control
CC1
CC2
CC1
CC2
CTL1/0/FLIP=H/H/H
CTL1/0/FLIP=H/H/H
Copyright © 2016, Texas Instruments Incorporated
图9-9. USB 3.1 + 2 Lane DP –Flip (CTL1 = H, CTL0 = H, FLIP = H)
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9.3.3 DisplayPort Only
The TUSB564 operates in 4 Lanes of DisplayPort only mode when the CTL1 pin is high and CTL0 pin is low.
D+/-
D+/-
4 Lane DP
USB Host
USB Hub
TUSB564
TUSB546A-DCI
SSTX
SSRX
SSRX
SSTX
RX2
TX1
RX1
TX2
TX1
RX1
DP0
DP0
RX2
TX2
DP1
DP2
DP1
DP2
GPU
DP RX
DP3
DP3
AUXp
AUXn
SBU1
SBU2
SBU1
SBU2
AUXn
AUXp
HPDIN
HPDIN
FLIP 0 1 CTL
PD Controller
FLIP 0 1 CTL
PD Controller
HPD
Control
HPD
Control
CC1
CC2
CC1
CC2
CTL1/0/FLIP=H/L/L
CTL1/0/FLIP=H/L/L
Copyright © 2017, Texas Instruments Incorporated
图9-10. Four Lane DP –No Flip (CTL1 = H, CTL0 = L, FLIP = L)
D+/-
D+/-
4 Lane DP
USB Host
USB Hub
SSRX
SSTX
SSTX
TUSB546A-DCI
TUSB564
SSRX
TX1
RX1
RX2
TX2
RX2
TX2
TX1
RX1
DP0
DP1
DP0
DP1
DP2
DP3
DP2
GPU
DP RX
DP3
SBU1
SBU2
AUXn
AUXp
SBU1
SBU2
AUXp
AUXn
HPDIN
HPDIN
CTL
FLIP 0 1
FLIP 0 1 CTL
PD Controller
HPD
Control
HPD
Control
CC1
CC2
CC1
CC2
PD Controller
CTL1/0/FLIP=H/L/H
CTL1/0/FLIP=H/L/H
Copyright © 2017, Texas Instruments Incorporated
图9-11. Four Lane DP –With Flip (CTL1 = H, CTL0 = L, FLIP = H)
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10 Power Supply Recommendations
The TUSB564 is designed to operate with a 3.3-V power supply. Levels above those listed in the table should
not be used. If using a higher voltage system power supply, a voltage regulator can be used to step down to 3.3
V. Decoupling capacitors should be used to reduce noise and improve power supply integrity. A 0.1-µF capacitor
should be used on each power pin.
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11 Layout
11.1 Layout Guidelines
1. RXP/N and TXP/N pairs should be routed with controlled 90-Ωdifferential impedance (±15%).
2. Keep away from other high speed signals.
3. Intra-pair routing should be kept to within 2 mils.
4. Length matching should be near the location of mismatch.
5. Each pair should be separated at least by 3 times the signal trace width.
6. The use of bends in differential traces should be kept to a minimum. When bends are used, the number of
left and right bends should be as equal as possible and the angle of the bend should be ≥135 degrees.
This will minimize any length mismatch causes by the bends and therefore minimize the impact bends have
on EMI.
7. Route all differential pairs on the same of layer.
8. The number of VIAS should be kept to a minimum. It is recommended to keep the VIAS count to 2 or less.
9. Keep traces on layers adjacent to ground plane.
10. Do NOT route differential pairs over any plane split.
11. Adding Test points will cause impedance discontinuity, and therefore, negatively impact signal performance.
If test points are used, they should be placed in series and symmetrically. They must not be placed in a
manner that causes a stub on the differential pair.
11.2 Layout Example
To USB Hub
AC Coupling
capacitors
TX1
RX1
DP0
DP1
GND
RX2
TX2
DP2
DP3
图11-1. Layout Example
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12 Device and Documentation Support
12.1 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
12.2 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
12.3 Trademarks
USB Type-C™ is a trademark of USB Implementers Forum.
DisplayPort™ is a trademark of VESA.
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
12.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.5 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TUSB564IRNQR
TUSB564IRNQT
TUSB564RNQR
TUSB564RNQT
ACTIVE
ACTIVE
ACTIVE
ACTIVE
WQFN
WQFN
WQFN
WQFN
RNQ
RNQ
RNQ
RNQ
40
40
40
40
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 85
-40 to 85
0 to 70
TUSB64
Samples
Samples
Samples
Samples
NIPDAU
NIPDAU
NIPDAU
TUSB64
TUSB64
TUSB64
0 to 70
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
18-Nov-2022
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
19-Nov-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TUSB564IRNQR
TUSB564IRNQT
TUSB564RNQR
TUSB564RNQT
WQFN
WQFN
WQFN
WQFN
RNQ
RNQ
RNQ
RNQ
40
40
40
40
3000
250
330.0
180.0
330.0
180.0
12.4
12.4
12.4
12.4
4.3
4.3
4.3
4.3
6.3
6.3
6.3
6.3
1.1
1.1
1.1
1.1
8.0
8.0
8.0
8.0
12.0
12.0
12.0
12.0
Q2
Q2
Q2
Q2
3000
250
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
19-Nov-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TUSB564IRNQR
TUSB564IRNQT
TUSB564RNQR
TUSB564RNQT
WQFN
WQFN
WQFN
WQFN
RNQ
RNQ
RNQ
RNQ
40
40
40
40
3000
250
367.0
210.0
367.0
210.0
367.0
185.0
367.0
185.0
35.0
35.0
35.0
35.0
3000
250
Pack Materials-Page 2
PACKAGE OUTLINE
RNQ0040A
WQFN - 0.8 mm max height
S
C
A
L
E
2
.
5
0
0
PLASTIC QUAD FLATPACK - NO LEAD
6.1
5.9
B
A
PIN 1 INDEX AREA
4.1
3.9
C
0.8 MAX
SEATING PLANE
0.08
0.05
0.00
4.7±0.1
2X 4.4
(0.2) TYP
9
20
EXPOSED
THERMAL PAD
36X 0.4
8
21
2X
2.8
2.7±0.1
1
28
0.25
40X
0.15
29
40
PIN 1 ID
0.1
C A
B
0.5
0.3
(OPTIONAL)
40X
0.05
4222125/B 01/2016
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
RNQ0040A
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(4.7)
2X (2.1)
6X (0.75)
40
29
40X (0.6)
1
28
40X (0.2)
SYMM
4X
(1.1)
(3.8)
(2.7)
36X (0.4)
8
21
(R0.05) TYP
9
20
SYMM
(5.8)
(
0.2) TYP
VIA
LAND PATTERN EXAMPLE
SCALE:15X
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4222125/B 01/2016
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
www.ti.com
EXAMPLE STENCIL DESIGN
RNQ0040A
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
SYMM
4X (1.5)
40
29
40X (0.6)
1
28
40X (0.2)
SYMM
6X
(0.695)
(3.8)
6X
(1.19)
36X (0.4)
8
21
(R0.05) TYP
METAL
TYP
9
20
6X (1.3)
(5.8)
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
EXPOSED PAD
73% PRINTED SOLDER COVERAGE BY AREA
SCALE:18X
4222125/B 01/2016
NOTES: (continued)
5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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