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TUSB8020B

ZHCSDC7C –JULY 2014–REVISED JUNE 2017

TUSB8020B 双端口 USB 3.0 集线器

1 特性

3 说明

1

•

双端口 USB 3.0 标准集线器，USBIF

TUSB8020B 是一款双端口 USB 3.0 标准集线器。该

TID#330000057

器件在上行端口上可提供同步超快速和高速/全速 USB

连接，在下行端口上可提供超快速、高速、全速或者低

速 USB 连接。当上行端口连接到一个仅支持高速或全

速/低速连接的电气环境中时，下行端口上的超快速

USB 连接将会禁用。当上行端口被连接到一个只支持

全速/低速连接的电气环境中时，下行端口上的超快速

USB 和高速连接被禁用。

•

USB 2.0 集线器特性

–

多事务转换器 (MTT) 集线器：两个事务转换器

每个事务转换器有四个异步端点缓冲器

•

支持电池充电

–

充电下行端口 (CDP) 模式（上行端口已连接）

专用充电端口 (DCP) 模式（上行端口未连接）

DCP 模式符合中国电信行业标准 YD/T 1591-

TUSB8020B 支持每端口或者成组电源开关和过流保

护。

2009

•

支持 D+/D– 分压器模式

按照 USB 主机的要求，一个端口电源单独控制集线器

开关为每个下行端口加电或者断电。同样，当一个端口

电源单独控制集线器感测到一个过流事件时，仅关闭受

影响的下行端口的电源。

支持作为一个 USB 3.0 或者 USB 2.0 复合器件运

行

•

支持每端口或成组电源开关以及过流告知输入

可使用一次性可编程 (OTP) ROM、串行 EEPROM

或 I²C/SMBus 受控接口进行自定义配置：

当需要为任一端口供电时，一个成组集线器开关打开到

其所有下行端口的电源。只有当所有端口处于电源可被

移除的状态时，到下行端口的电源才可被关闭。同样，

当一个成组集线器感测到一个过流事件时，将关闭所有

下行端口的电源。

–

VID 和 PID

端口定制

生产商和产品字串（OTP ROM 不支持）

序列号（OTP ROM 不支持）

可使用引脚选择或 EEPROM/I²C/SMBus 受控接口

•

器件信息⁽¹⁾

选择应用特性

•

提供 128 位通用唯一标识符 (UUID)

器件型号

TUSB8020B

封装

封装尺寸（标称值）

支持通过 USB 2.0 上行端口进行板载和系统内

OTP/EEPROM 编程

HTQFP (48)

7.00mm × 7.00mm

(1) 要了解所有可用封装，请参阅数据表末尾的可订购产品附录。

•

单时钟输入，24MHz 晶振或者振荡器

USB 3.0

HDD

无特殊驱动程序要求；可与任一支持 USB 堆叠的

操作系统无缝工作

USB 2.0

Webcam

USB 2.0

Hub

•

48 引脚耐热增强型薄型四方扁平 (HTQFP) 封装

(PHP)

USB 2.0

HDD

Personal

Computer

TUSB8020B

USB 3.0

HDD

2 应用

USB 3.0

Hub

•

计算机系统

USB 1.1

Mouse

USB 2.0

Bluray

扩展坞

监视器

机顶盒

USB 1.x Connection

USB 2.0 Connection

USB 3.0 Hub

USB 2.0 Device

USB 1.x Device

USB 3.0 Connection

USB 3.0 Device

1

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

English Data Sheet: SLLSEF6

TUSB8020B

ZHCSDC7C –JULY 2014–REVISED JUNE 2017

www.ti.com.cn

8.4 Device Functional Modes........................................ 12

8.5 Register Maps......................................................... 13

Application and Implementation ........................ 25

9.1 Application Information............................................ 25

9.2 Typical Application .................................................. 25

1

2

3

4

5

6

7

特性.......................................................................... 1

应用.......................................................................... 1

说明.......................................................................... 1

修订历史记录 ........................................................... 2

说明（续）.............................................................. 2

Pin Configuration and Functions......................... 3

Specifications......................................................... 6

7.1 Absolute Maximum Ratings ..................................... 6

7.2 ESD Ratings.............................................................. 6

7.3 Recommended Operating Conditions....................... 6

7.4 Thermal Information.................................................. 6

7.5 3.3-V I/O Electrical Characteristics ........................... 7

7.6 Power-Up Timing Requirements............................... 7

7.7 Hub Input Supply Current ......................................... 8

Detailed Description .............................................. 9

8.1 Overview ................................................................... 9

8.2 Functional Block Diagram ......................................... 9

8.3 Feature Description................................................... 9

9

10 Power Supply Recommendations ..................... 30

10.1 Power Supply........................................................ 30

10.2 Downstream Port Power ....................................... 30

10.3 Ground .................................................................. 30

11 Layout................................................................... 31

11.1 Layout Guidelines ................................................. 31

11.2 Layout Example .................................................... 32

12 器件和文档支持 ..................................................... 34

12.1 社区资源................................................................ 34

12.2 商标....................................................................... 34

12.3 静电放电警告......................................................... 34

12.4 Glossary................................................................ 34

13 机械、封装和可订购信息....................................... 34

8

4 修订历史记录

Changes from Revision B (March 2017) to Revision C

Page

•

Added SMBUS Programming current to the Hub Input Supply Current table........................................................................ 8

Added Note to the SMBus Slave Operation section ............................................................................................................ 12

Changes from Revision A (July 2014) to Revision B

Page

•

Replaced the Absolute Maximum Ratings table..................................................................................................................... 6

Changes from Original (July 2004) to Revision A

Page

•

将器件状态更改为生产数据..................................................................................................................................................... 1

5 说明（续）

TUSB8020B 下行端口可提供电池充电连接下行端口 (CDP) 握手支持，从而为电池充电应用提供支持。未连接上

行端口时，该器件还支持专用充电端口 (DCP) 模式。DCP 模式支持 USB 电池充电并且符合中国电信行业标准

YD/T 1591-2009，能够为 USB 器件提供支持。此外，未连接上行端口时，自动模式能够为 BC 器件以及支持分压

器模式充电解决方案的器件提供透明支持。

TUSB8020B 能够为包括电池充电支持在内的部分特性提供终端搭接配置，还能够通过 OTP ROM、I²C

EEPROM 或 I²C/SMBus 受控接口为 PID、VID、自定义端口和物理层配置提供定制支持。使用 I²C EEPROM 或

I²C/SMBus 受控接口时，还可以提供定制字串支持。

该器件采用 48 引脚 HTQFP 封装，商用版 (TUSB8020B) 的工作温度范围为 0°C 到 70°C，工业版 (TUSB8020BI)

的工作温度范围为 -40℃ 到 85°C。

2

TUSB8020B

www.ti.com.cn

ZHCSDC7C –JULY 2014–REVISED JUNE 2017

6 Pin Configuration and Functions

PHP Package

36 Pin (HTQFP)

(Top View)

36

35

34

33

32

31

30

29

28

27

26

25

37

38

39

40

41

42

43

44

45

46

47

48

24

23

22

21

20

19

18

17

16

15

14

13

USB_R1

VDD33

XI

VDD33

XO

SMBUSz / SS_DN2

PWRCTL_POL / SS_DN1

USB_SSRXM_DN2

USB_SSRXP_DN2

VDD

VDD33

USB_DP_DN1

USB_DM_DN1

USB_SSTXP_DN1

USB_SSTXM_DN1

VDD

Thermal Pad

USB_SSTXM_DN2

USB_SSTXP_DN2

USB_DM_DN2

USB_DP_DN2

VDD33

USB_SSRXP_DN1

USB_SSRXM_DN1

VDD33

1

2

3

4

5

6

7

8

9

10

11

12

3

TUSB8020B

ZHCSDC7C –JULY 2014–REVISED JUNE 2017

www.ti.com.cn

Pin Functions

TYPE

DESCRIPTION

NAME

NO.

CLOCK AND RESET SIGNALS

I

Global power reset. This reset brings all of the TUSB8020B internal registers to their default states. When GRSTz is asserted,

the device is completely nonfunctional.

GRSTz

XI

11

38

39

PU

Crystal input. This terminal is the crystal input for the internal oscillator. The input may alternately be driven by the output of an

external oscillator. When using a crystal a 1-MΩ feedback resistor is required between XI and XO.

I

Crystal output. This terminal is the crystal output for the internal oscillator. If XI is driven by an external oscillator this pin may be

left unconnected. When using a crystal a 1-MΩ feedback resistor is required between XI and XO.

XO

O

USB UPSTREAM SIGNALS

USB_SSTXP_UP

USB_SSTXM_UP

USB_SSRXP_UP

USB_SSRXM_UP

USB_DP_UP

29

28

32

31

26

27

24

O

I

USB SuperSpeed transmitter differential pair (positive)

USB SuperSpeed transmitter differential pair (negative)

USB SuperSpeed receiver differential pair (positive)

I

USB SuperSpeed receiver differential pair (negative)

I/O

I

USB high-speed differential transceiver (positive)

USB_DM_UP

USB high-speed differential transceiver (negative)

USB_R1

Precision resistor reference. A 9.53-kΩ ±1% resistor should be connected between USB_R1 and GND.

USB upstream port power monitor. The VBUS detection requires a voltage divider. The signal USB_VBUS must be connected to

VBUS through a 90.9-kΩ ±1% resistor, and to ground through a

USB_VBUS

9

I

10-kΩ ±1% resistor from the signal to ground.

USB DOWNSTREAM SIGNALS

USB_SSTXP_DN1

USB_SSTXM_DN1

USB_SSRXP_DN1

USB_SSRXM_DN1

USB_DP_DN1

43

44

46

47

41

42

O

I

USB SuperSpeed transmitter differential pair (positive) downstream port 1.

USB SuperSpeed transmitter differential pair (negative) downstream port 1.

USB SuperSpeed receiver differential pair (positive) downstream port 1.

USB SuperSpeed receiver differential pair (negative) downstream port 1.

USB high-speed differential transceiver (positive) downstream port 1.

USB high-speed differential transceiver (negative) downstream port 1.

I

I/O

USB_DM_DN1

USB port 1 power-on control for downstream power or battery charging enable. The terminal is used for control of the

downstream power switch for Port 1.

I/O

PD

In addition, the value of the terminal is sampled at the deassertion of reset to determine the value of the battery charging

support for Port 1 as indicated in the Battery Charging Support register.

PWRCTL1/BATEN1

4

5

0 = Battery charging not supported

1 = Battery charging supported

USB DS port 1 overcurrent detection input. This terminal is used to connect the over current output of the downstream port

power switch for port 1.

0 = An overcurrent event has occurred

1 = An overcurrent event has not occurred

I

OVERCUR1z

PU

If power management is enabled, the external circuitry needed should be determined by the power switch. In ganged mode,

either OVERCUR1z or OVERCUR2z can be used. In ganged mode, the overcurrent will be reported as a hub event instead of a

port event.

USB_SSTXP_DN2

USB_SSTXM_DN2

USB_SSRXP_DN2

USB_SSRXM_DN2

USB_DP_DN2

16

17

19

20

14

15

O

I

USB SuperSpeed transmitter differential pair (positive) downstream port 2.

USB SuperSpeed transmitter differential pair (negative) downstream port 2.

USB SuperSpeed receiver differential pair (positive) downstream port 2.

USB SuperSpeed receiver differential pair (negative) downstream port 2.

USB high-speed differential transceiver (positive) downstream port 2.

USB high-speed differential transceiver (negative) downstream port 2.

I

I/O

USB_DM_DN2

Power-on control /battery charging enable for downstream port 2. This terminal is used for control of the downstream power

switch for port 2.

I/O

PD

The value of the terminal is sampled at the deassertion of reset to determine the value of the battery charging support for port 2

as indicated in the Battery Charging Support register.

PWRCTL2/BATEN2

6

8

0 = Battery charging not supported

1 = Battery charging supported

Overcurrent detection for downstream port 2. This terminal is used to connect the over current output of the downstream port

power switch for port 2.

0 = An overcurrent event has occurred

1 = An overcurrent event has not occurred

I

OVERCUR2z

PU

If power management is enabled, the external circuitry needed should be determined by the power switch. In ganged mode

either OVERCUR1z or OVERCUR2z can be used. In ganged mode the overcurrent will be reported as a hub event instead of a

port event.

4

TUSB8020B

www.ti.com.cn

ZHCSDC7C –JULY 2014–REVISED JUNE 2017

Pin Functions (continued)

TYPE

DESCRIPTION

NAME

NO.

I²C/SMBUS SIGNALS

I²C clock/SMBus clock. Function of terminal depends on the setting of the SMBUSz input.

When SMBUSz = 1, this terminal acts as the serial clock interface for an I²C EEPROM.

When SMBUSz = 0, this terminal acts as the serial clock interface for an SMBus host.

This pin must be pulled up to use the OTP ROM.

I/O

PD

SCL/SMBCLK

2

Can be left unconnected if external interface not implemented.

I²C data/SMBus data. Function of terminal depends on the setting of the SMBUSz input.

When SMBUSz = 1, this terminal acts as the serial data interface for an I²C EEPROM.

When SMBUSz = 0, this terminal acts as the serial data interface for an SMBus host.

This pin must be pulled up to use the OTP ROM.

I/O

PD

SDA/SMBDAT

3

Can be left unconnected if external interface not implemented.

TEST AND MISCELLANEOUS SIGNALS

SMBUS mode / SuperSpeed USB Status for downstream port 2

The value of the terminal is sampled at the deassertion of reset to enable I²C or SMBus mode.

I

0 = SMBus mode selected

1 = I²C mode selected

SMBUSz/SS_DN2

22

PU

After reset, this signal indicates the SuperSpeed USB connection status of downstream port 2. A value of 1 indicates the

connection is SuperSpeed USB.

Power control polarity / SuperSpeed USB status for downstream port 1.

The value of the terminal is sampled at the deassertion of reset to set the polarity of PWRCTL[2:1].

I/O

PD

0 = PWRCTL polarity is active high.

1 = PWRCTL polarity is active low.

PWRCTL_POL/SS_DN1

21

After reset, this signal indicates the SuperSpeed USB connection status of downstream port 1. A value of 1 indicates the

connection is SuperSpeed USB.

Ganged operation enable/SMBus address bit 2/ high-speed status for upstream port

The value of the terminal is sampled at the deassertion of reset to set the power switch and over current detection mode as

follows:

0 = Individual power control supported when power switching is enabled.

1 = Power control gangs supported when power switching is enabled.

GANGED/SMBA2/

HS_UP

I

35

PU

When SMBus mode is enabled using SMBUSz, this terminal sets the value of the SMBus slave address bit 2. SMBus slave

address bits 2 and 3 are always 1 for the TUSB8020B.

After reset, this signal indicates the high-speed USB connection status of the upstream port. A value of 1 indicates the upstream

port is connected to a high-speed USB capable port.

Full power management enable/ SMBus Address bit 1/ Super-Speed USB status for upstream port

The value of the terminal is sampled at the deassertion of reset to set the power switch control follows:

0 = Power switching supported

1 = Power switching not supported

Full power management is the ability to control power to the downstream ports of the TUSB8020B using

PWRCTL[2:1]/BATEN[2:1].

FULLPWRMGMTz/

SMBA1/SS_UP

36

I, PU

When SMBus mode is enabled using SMBUSz, this terminal sets the value of the SMBus slave address bit 1. SMBus slave

address bit 3 is always 1 for the TUSB8020B.

Can be left unconnected if full power management and SMBus are not implemented.

After reset, this signal indicates the SuperSpeed USB connection status of the upstream port. A value of 1 indicates the

upstream port is connected to a SuperSpeed USB capable port.

I

TEST mode enable. When this terminal is asserted high at reset enables test mode. This terminal is reserved for factory use. It

is recommended to pull-down this terminal to ground.

TEST

10

PD

POWER AND GROUND SIGNALS

1, 12, 18, 30,

34, 45

VDD

PWR

1.1-V power rail

7, 13, 23, 25,

33, 37, 40, 48

VDD33

GND

PWR

—

3.3-V power rail

Ground

PAD

5

TUSB8020B

ZHCSDC7C –JULY 2014–REVISED JUNE 2017

www.ti.com.cn

7 Specifications

7.1 Absolute Maximum Ratings⁽¹⁾

over operating free-air temperature range (unless otherwise noted)

MIN

–0.3

MAX

1.4

UNIT

V

V_DDSteady-state supply voltage

Supply Voltage Range

V_DD33Steady-state supply voltage

3.8

V

USB_SSRXP_UP, USB_SSRXN_UP, USB_SSRXP_DN[4:1],

USB_SSRXN_DP[4:1] and USB_VBUS terminals

-0.3

1.4

V

Voltage Range

XI terminals

-0.3

–65

2.45

3.8

V

All other terminals

Storage temperature, T_stg

150

°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

7.2 ESD Ratings

MIN

MAX UNIT

T_stg

Storage temperature range

–65

150

°C

Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins⁽¹⁾

Charged device model (CDM), per JEDEC specification JESD22-C101, all pins⁽²⁾

–2000 2000

–500 500

Electrostatic

discharge

V_(ESD)

V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN

0.99

3

NOM

1.1

MAX

UNIT

VDD⁽¹⁾

1.1-V supply voltage

1.26

3.6

V

VDD33

3.3-V supply voltage

3.3

USB_VBUS

Voltage at USB_VBUS PAD

0

1.155

70

TUSB8020B

TUSB8020BI

0

25

T_A

T_J

Operating free-air temperature range

Operating junction temperature range

°C

–40

85

105

(1) A 1.05-V, 1.1-V, or 1.2-V supply may be used as long as minimum and maximum supply conditions are met.

7.4 Thermal Information

TUSB8020B

PHP

THERMAL METRIC⁽¹⁾

UNIT

48 PINS

31.8

R_θJA

Junction-to-ambient thermal resistance

°C/W

R_θJC(top)

R_θJB

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

16.1

13

ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

0.5

ψ_JB

12.9

R_θJC(bot)

0.9

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

6

TUSB8020B

www.ti.com.cn

ZHCSDC7C –JULY 2014–REVISED JUNE 2017

7.5 3.3-V I/O Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)

PARAMETER

High-level input voltage⁽¹⁾

Low-level input voltage⁽¹⁾

Input voltage

OPERATION

VDD33

TEST CONDITIONS

MIN

2

TYP

MAX

VDD33

0.8

UNIT

V

V_IH

V_IL

V_I

VDD33

0

V

0

VDD33

25

V

V_O

t_t

Output voltage⁽²⁾

0

V

Input transition time (t_riseand t_fall

)

0

ns

0.13 ×

VDD33

V_hys

Input hysteresis⁽³⁾

V

V_OH

V_OL

I_OZ

High-level output voltage

Low-level output voltage

High-impedance, output current⁽²⁾

VDD33

I_OH= –4 mA

I_OL= 4 mA

2.4

V

0.4

V_I= 0 to VDD33

±20

µA

High-impedance, output current with

internal pullup or pulldown resistor⁽⁴⁾

Input current⁽⁵⁾

I_OZP

I_I

VDD33

V_I= 0 to VDD33

±225

±15

µA

(1) Applies to external inputs and bidirectional buffers

(2) Applies to external outputs and bidirectional buffers

(3) Applies to GRSTz

(4) Applies to pins with internal pullups/pulldowns

(5) Applies to external input buffers

7.6 Power-Up Timing Requirements

MIN

0

TYP

MAX

UNIT

ms

µs

t_d1

V_DD33stable before V_DDstable. No timing relationship between V_DD33and V_DD

V_DDand V_DD33stable before deassertion of GRSTZ.

Setup for MISC inputs sampled at the deassertion of GRSTZ⁽¹⁾

Hold for MISC inputs sampled at the deassertion of GRSTZ.⁽¹⁾

t_d2

3

t_{su_io}

t_{hd_io}

0.1

0.2

µs

t_{VDD33_RAMP}V_DD33supply ramp requirements

t_{VDD_RAMP}V_DDsupply ramp requirements

100

ms

(1) Miscellaneous pins sampled at deassertion of GRSTZ: FULLPWRMGMTz, GANGED, PWRCTL_POL, SMBUSz, BATEN1, and BATEN2

Td2

GRSTz

VDD33

Td1

VDD

Tsu_io

Thd_io

MISC_IO

Figure 1. Power-Up Timing Requirements

7

TUSB8020B

ZHCSDC7C –JULY 2014–REVISED JUNE 2017

www.ti.com.cn

7.7 Hub Input Supply Current

Typical values measured at T_A= 25°C

VDD33

3.3 V

VDD11

PARAMETER

UNIT

1.1 V

LOW-POWER MODES

Power-on (after reset)

5

6

39

40

mA

Disconnect from host

Suspend (USB2 host)

Suspend (USB3 host)

ACTIVE MODES (US STATE / DS STATE)

3.0 host / 1 SS device and hub in U1

3.0 host / 1 SS device and hub in U0

3.0 host / 2 SS devices and hub in U1

3.0 host / 2 SS devices and hub in U0

3.0 host / 1 SS and 1 HS device in U1

3.0 host / 1 SS and 1 HS device in U0

2.0 host / 1 HS device active

2.0 host / 2 HS devices active

SMBUS Programming current

50

92

93

48

60

79

218

342

284

456

242

364

71

mA

80

225

8

TUSB8020B

www.ti.com.cn

ZHCSDC7C –JULY 2014–REVISED JUNE 2017

8 Detailed Description

8.1 Overview

The TUSB8020B is a two-port USB 3.0 compliant hub. It provides simultaneous SuperSpeed USB and high-

speed/full-speed connections on the upstream port and provides SuperSpeed USB, high-speed, full-speed,

or low-speed connections on the downstream ports. When the upstream port is connected to an electrical

environment that only supports high-speed or full-speed/low-speed connections, SuperSpeed USB

connectivity is disabled on the downstream ports. When the upstream port is connected to an electrical

environment that only supports full-speed/low-speed connections, SuperSpeed USB and high-speed

connectivity are disabled on the downstream ports.

8.2 Functional Block Diagram

VDD33

VDD

VSS

VBUS

Detect

Power

Distribution

USB 2.0 Hub

SuperSpeed Hub

XI

Oscilator

XO

Clock

and

Reset

GRSTn

TEST

Distribution

GANGED/SMBA2/HS_UP

FULLPWRMGMTz/SMBA1/SS_UP

PWRCTL_POL/SS_DN1

GPIO

I2C

SMBUS

SMBUSz/SS_DN2

SCL/SMBCLK

SDA/SMDAT

Control

Registers

OVERCUR1z

PWRCTL1/BATEN1

OVERCUR2z

PWRCTL2/BATEN2

8.3 Feature Description

8.3.1 Battery Charging Features

The TUSB8020B provides support for battery charging. Battery charging support may be enabled on a per port

basis through the REG_6h(batEn[1:0]).

Battery charging support includes both charging downstream port (CDP) and dedicated charging port (DCP)

modes. The DCP mode is compliant with the Chinese Telecommunications Industry Standard YD/T 1591-2009.

In addition to standard DCP mode, the TUSB8020B provides a mode (AUTOMODE) which automatically

provides support for DCP devices and devices that support custom charging indication. AUTOMODE is enabled

by default. When in AUTOMODE, the port automatically switches between a divider mode and the DCP mode

depending on the portable device connected. The divider mode places a fixed DC voltage on the ports DP and

DM signals which allows some devices to identify the capabilities of the charger. The default divider mode

indicates support for up to 5 W. The divider mode can be configured to report a high-current setting (up to 10 W)

through REG_Ah(HiCurAcpModeEn). When AUTOMODE is enabled, the CDP mode is not functional. CDP

mode can not be used when AUTOMODE is enabled.

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Feature Description (continued)

The battery charging mode for each port depends on the state of Reg_6h(batEn[n]), the status of the VBUS

input, and the state of REG_Ah(autoModeEnz) upstream port, as identified in Table 1. Battery charging can also

be enabled through the PWRCTL1/BATEN1 and PWRCTL2/BATEN2 pins.

Table 1. TUSB8020B Battery Charging Modes

BC Mode Port x

batEn[n]

VBUS

autoModeEnz

(x = n + 1)

Don’t care

Automode^{(1) (2)}

DCP^{(3) (4)}

0

Don’t care

0

1

<4 V

>4 V

1

CDP⁽³⁾

(1) Auto-mode automatically selects divider-mode or DCP mode.

(2) Divider mode can be configured for high-current mode through register or OTP settings.

(3) USB device is USB Battery Charging Specification Revision 1.2 Compliant

(4) USB device is Chinese Telecommunications Industry Standard YD/T 1591-2009

8.3.2 USB Power Management

The TUSB8020B can be configured for power switched applications using either per-port or ganged power-

enable controls and over-current status inputs.

Power switch support is enabled by REG_5h(fullPwrMgmtz) and the per-port or ganged mode is configured by

REG_5h(ganged). It can also be enabled through the FULLPWRMGMTz pin. Also ganged or individual control

can be controlled by the GANGED pin.

The TUSB8020B supports both active-high and active-low power-enable controls. The PWRCTL[2:1] polarity is

configured by REG_Ah(pwrctlPol). The polarity can also be configured by the PWRCTL_POL pin.

8.3.3 One-Time Programmable (OTP) Configuration

The TUSB8020B allows device configuration through OTP non-volatile memory (OTP). The programming of the

OTP is supported using vendor-defined USB device requests. For details using the OTP features, contact your TI

representative.

Table 2 provides a list features which may be configured using the OTP. The bit field section in Table 2 shows

which features can be controlled by OTP ROM. The bits not listed in the table are not accessible by the OTP

ROM.

Table 2. OTP Configurable Features

CONFIGURATION REGISTER OFFSET

BIT FIELD

[7:0]

DESCRIPTION

REG_01h

REG_02h

REG_03h

REG_04h

Vendor ID LSB

Vendor ID MSB

Product ID LSB

Product ID MSB

[7:0]

Port removable configuration for downstream ports 1. OTP configuration is

inverse of rmbl[1:0], that is:

1 = Not removable

0 = Removable

REG_07h

[0]

[1]

Port removable configuration for downstream ports 2. OTP configuration is

inverse of rmbl[1:0], that is:

1 = Not removable

0 = Removable

REG_0Ah

REG_F2h

[1]

[4]

Automode enable

High-current divider mode enable.

USB power switch power-on delay.

[3:1]

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8.3.4 Clock Generation

The TUSB8020B accepts a crystal input to drive an internal oscillator or an external clock source. If a crystal is

used, a 1-MΩ shunt resistor is required. Keep the XI and XO traces as short as possible and away from any

switching leads to minimize noise coupling.

Figure 2. TUSB8020B Clock

8.3.4.1 Crystal Requirements

The crystal must be fundamental mode with load capacitance of 12 to 24 pF and frequency stability rating of

±100 PPM or better. To ensure proper startup oscillation condition, TI recommends a maximum crystal

equivalent series resistance (ESR) of 50 Ω. A parallel load capacitor should be used if a crystal source is used.

The exact load capacitance value used depends on the crystal vendor. Refer to application note Selection and

Specification of Crystals for Texas Instruments USB 2.0 Devices (SLLA122) for details on how to determine the

load capacitance value.

8.3.4.2 Input Clock Requirements

When using an external clock source such as an oscillator, the reference clock should have a ±100 PPM or

better frequency stability and have less than 50-ps absolute peak-to-peak jitter or less than 25-ps peak-to-peak

jitter after applying the USB 3.0 jitter transfer function. XI should be tied to the 1.8-V clock source and XO should

be left floating.

8.3.5 Power-Up and Reset

The TUSB8020B does not have specific power sequencing requirements with respect to the VDD or VDD33

power rails. The VDD or VDD33 power rails may be powered up for an indefinite period of time while the other is

not powered up if all of these constraints are met:

•

All maximum ratings and recommended operating conditions are observed.

All warnings about exposure to maximum rated and recommended conditions are observed, particularly

junction temperature. These apply to power transitions as well as normal operation.

•

Bus contention while VDD33 is powered-up must be limited to 100 hours over the projected lifetime of the

device.

•

Bus contention while VDD33 is powered-down may violate the absolute maximum ratings.

A supply bus is powered up when the voltage is within the recommended operating range. A supply bus is

powered down when it is below that range, either stable or in transition.

A minimum reset duration of 3 ms is required, which is defined as the time when the power supplies are in the

recommended operating range to the deassertion of GRSTz. This can be generated using programmable-delay

supervisory device or using an RC circuit.

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8.4 Device Functional Modes

8.4.1 External Configuration Interface

The TUSB8020B supports a serial interface for configuration register access. The device may be configured by

an attached I²C EEPROM or accessed as a slave by a SMBus-capable host controller. The external interface is

enabled when both the SCL/SMBCLK and SDA/SMBDAT terminals are pulled up to 3.3 V at the deassertion of

reset. The mode, I²C master, or SMBus slave is determined by the state of SMBUSz/SS_DN2 terminal at reset.

8.4.2 I²C EEPROM Operation

The TUSB8020B supports a single-master, standard mode (100 kbit/s) connection to a dedicated I²C EEPROM

when the I²C interface mode is enabled. In I²C mode, the TUSB8020B reads the contents of the EEPROM at bus

address 1010000b using 7-bit addressing starting at address 0.

If the value of the EEPROM contents at byte 00h equals 55h, the TUSB8020B loads the configuration registers

according to the EEPROM map. If the first byte is not 55h, the TUSB8020B exits the I²C mode and continues

execution with the default values in the configuration registers. The hub will not connect on the upstream port

until the configuration is completed. If the TUSB8020B detects an unprogrammed EEPROM (value other than

55h), it enters programming mode and a programming endpoint within the hub is enabled.

Note, the bytes located above offset Ah are optional. The requirement for data in those addresses depends on

the options configured in the Device Configuration, Phy Custom Configuration, and Device Configuration 2

registers.

For details on I²C operation, refer to the UM10204 I²C-bus Specification and User Manual.

8.4.3 SMBus Slave Operation

When the SMBus interface mode is enabled, the TUSB8020B supports read block and write block protocols as a

slave-only SMBus device.

The TUSB8020B slave address is 1000 1xyz, where:

•

x is the state of GANGED/SMBA2/HS_UP terminal at reset

y is the state of FULLPWRMGMTz/SMBA1/SS_UP terminal at reset

z is the read/write bit; 1 = read access, 0 = write access.

If the TUSB8020B is addressed by a host using an unsupported protocol, it does not respond. The TUSB8020B

waits indefinitely for configuration by the SMBus host and does not connect on the upstream port until the

SMBus host indicates configuration is complete by clearing the CFG_ACTIVE bit.

For details on SMBus requirements, refer to the System Management Bus Specification.

NOTE

During the SMBUS configuration the hub may draw an extra current, this extra current

consumption will end as soon as the CFG_ACTIVE bit is cleared. For more information,

see Hub Input Supply Current in this datasheet.

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8.5 Register Maps

8.5.1 Configuration Registers

The internal configuration registers are accessed on byte boundaries. The configuration register values are

loaded with defaults but can be overwritten when the TUSB8020B is in I²C or SMBus mode.

Table 3. TUSB8020B Register Map

BYTE ADDRESS

00h

CONTENTS

ROM Signature Register

EEPROM CONFIGURABLE

No

01h

Vendor ID LSB

Yes

02h

Vendor ID MSB

Yes

03h

Product ID LSB

Yes

04h

Product ID MSB

Yes

05h

Device Configuration Register

Battery Charging Support Register

Device Removable Configuration Register

Port Used Configuration Register

Reserved

Yes

06h

Yes

07h

Yes

08h

Yes

Yes, program to 00h

Yes

09h

0Ah

Device Configuration Register 2

Reserved

0Bh to 0Fh

10h to 1Fh

20h to 21h

22h

UUID Byte [15:0]

No

LangID Byte [1:0]

Yes, if customStrings is set

Serial Number String Length

Manufacturer String Length

Product String Length

Reserved

Yes, if customSerNum is set

23h

Yes, if customStrings is set

24h

Yes, if customStrings is set

25h to 2Fh

30h to 4Fh

50h to 8Fh

90h to CFh

D0 to DFh

F0h

Yes

Serial Number String Byte [31:0]

Manufacturer String Byte [63:0]

Product String Byte [63:0]

Reserved

Yes, if customSerNum is set

Yes, if customStrings is set

No

Yes

No

Additional Feature Configuration Register

Reserved

F1h

F2h

Charging Port Control Register

Reserved

F3 to F7h

F8h

Device Status and Command Register

Reserved

No

F9 to FFh

No

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8.5.1.1 ROM Signature Register (offset = 0h) [reset = 0h]

Figure 3. Register Offset 0h

7

0

6

0

5

0

4

0

3

0

2

0

1

0

R/W

LEGEND: R/W = Read/Write; R = Read only; –n = value after reset

Table 4. ROM Signature Register

Bit

Field

Type

Reset

Description

ROM Signature Register. This register is used by the TUSB8020B in I²C mode to

validate the attached EEPROM has been programmed. The first byte of the

EEPROM is compared to the mask 55h and if not a match, the TUSB8020B aborts

the EEPROM load and executes with the register defaults.

7:0

romSignature

R/W

0h

8.5.1.2 Vendor ID LSB Register (offset = 1h) [reset = 51h]

Figure 4. Register Offset 51h

7

0

6

1

5

0

4

1

3

0

2

0

1

0

1

R/W

LEGEND: R/W = Read/Write; R = Read only; –n = value after reset

Table 5. Vendor ID LSB Register

Bit

Field

Type

Reset

Description

Vendor ID LSB. Least significant byte of the unique vendor ID assigned by the

USB-IF; the default value of this register is 51h representing the LSB of the TI

Vendor ID 0451h. The value may be overwritten to indicate a customer vendor ID.

This field is read/write unless the OTP ROM VID and OTP ROM PID values are

non-zero. If both values are non-zero, the value when reading this register shall

reflect the OTP ROM value.

7:0

vendorIdLsb

R/W

51h

8.5.1.3 Vendor ID MSB Register (offset = 2h) [reset = 4h]

Figure 5. Register Offset 2h

7

0

6

0

5

0

4

0

3

0

2

1

0

R/W

LEGEND: R/W = Read/Write; R = Read only; –n = value after reset

Table 6. Vendor ID MSB Register

Bit

Field

Type

Reset

Description

Vendor ID MSB. Most significant byte of the unique vendor ID assigned by the

USB-IF; the default value of this register is 04h representing the MSB of the TI

Vendor ID 0451h. The value may be overwritten to indicate a customer vendor ID.

This field is read/write unless the OTP ROM VID and OTP ROM PID values are

non-zero. If both values are non-zero, the value when reading this register shall

reflect the OTP ROM value.

7:0

vendorIdMsb

R/W

4h

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8.5.1.4 Product ID LSB Register (offset = 3h) [reset = 25h]

Figure 6. Register Offset 3h

7

0

6

0

5

1

4

0

3

0

2

1

0

1

R/W

LEGEND: R/W = Read/Write; R = Read only; –n = value after reset

Table 7. Product ID LSB Register

Bit

Field

Type

Reset

Description

Product ID LSB. Least significant byte of the product ID assigned by TI and reported in

the SuperSpeed device descriptor. The default value of this register is 25h representing

the LSB of the SuperSpeed product ID assigned by TI. The value reported in the USB

2.0 device descriptor is the value of this register bit wise XORed with 00000010b. The

value may be overwritten to indicate a customer product ID.

7:0

productIdLsb

R/W

25h

This field is read/write unless the OTP ROM VID and OTP ROM PID values are non-

zero. If both values are non-zero, the value when reading this register shall reflect the

OTP ROM value.

8.5.1.5 Product ID MSB Register (offset = 4h) [reset = 80h]

Figure 7. Register Offset 4h

7

1

6

0

5

0

4

0

3

0

2

0

1

0

R/W

LEGEND: R/W = Read/Write; R = Read only; –n = value after reset

Table 8. Bit Descriptions – Product ID MSB Register

Bit

Field

Type

Reset

Description

Product ID MSB. Most significant byte of the product ID assigned by TI; the default

value of this register is 80h representing the MSB of the product ID assigned by TI. The

value may be overwritten to indicate a customer product ID.

This field is read/write unless the OTP ROM VID and OTP ROM PID values are non-

zero. If both values are non-zero, the value when reading this register will reflect the

OTP ROM value.

7:0

productIdLsb

R/W

80h

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8.5.1.6 Device Configuration Register (offset = 5h) [reset = 1Xh]

Figure 8. Register Offset 5h

7

0

6

0

5

0

4

1

3

X

2

X

1

0

R/W

R

R/W

R

LEGEND: R/W = Read/Write; R = Read only; –n = value after reset

Table 9. Device Configuration Register

Bit

Field

Type

Reset

Description

Custom strings enable. This bit controls the ability to write to the Manufacturer String

Length, Manufacturer String, Product String Length, Product String, and Language ID

registers.

0 = The Manufacturer String Length, Manufacturer String, Product String Length, Product

String, and Language ID registers are read only.

1 = The Manufacturer String Length, Manufacturer String, Product String Length, Product

String, and Language ID registers may be loaded by EEPROM or written by SMBus.

The default value of this bit is 0.

7

customStrings

R/W

1Xh

Custom serial number enable. This bit controls the ability to write to the serial number

registers.

0 = The Serial Number String Length and Serial Number String registers are read only.

1 = The Serial Number String Length and Serial Number String registers may be loaded

by EEPROM or written by SMBus.

6

customSernum

R/W

The default value of this bit is 0.

U1 U2 Disable. This bit controls the U1/U2 support.

0 = U1/U2 support is enabled.

1 = U1/U2 support is disabled, the TUSB8020B does not initiate or accept any U1 or U2

requests on any port, upstream or downstream, unless it receives or sends a

Force_LinkPM_Accept LMP. After receiving or sending an FLPMA LMP, it continues to

enable U1 and U2 according to USB 3.0 protocol until it gets a power-on reset or is

disconnected on its upstream port.

5

u1u2Disable

R/W

1Xh

When the TUSB8020B is in I²C mode, the TUSB8020B loads this bit from the contents of

the EEPROM.

When the TUSB8020B is in SMBUS mode, the value may be overwritten by an SMBus

host.

4

3

RSVD

R

1Xh

Reserved. This bit is reserved and returns 1 when read.

Ganged. This bit is loaded at the deassertion of reset with the value of the

GANGED/SMBA2/HS_UP terminal.

0 = When fullPwrMgmtz = 0, each port is individually power switched and enabled by the

PWRCTL[2:1]/BATEN[2:1] terminals

1 = When fullPwrMgmtz = 0, the power switch control for all ports is ganged and enabled

by the PWRCTL1/BATEN1 terminal

ganged

R/W

When the TUSB8020B is in I²C mode, the TUSB8020B loads this bit from the contents of

the EEPROM.

When the TUSB8020B is in SMBUS mode, the value may be overwritten by an SMBus

host.

Full Power Management. This bit is loaded at the deassertion of reset with the value of

the FULLPWRMGMTz/SMBA1/SS_UP terminal.

0 = Port power switching and over-current status reporting is enabled

1 = Port power switching and over-current status reporting is disabled

When the TUSB8020B is in I²C mode, the TUSB8020B loads this bit from the contents of

the EEPROM.

2

fullPwrMgmtz

R/W

1Xh

When the TUSB8020B is in SMBUS mode, the value may be overwritten by an SMBus

host.

1

0

RSVD

R/W

R

1Xh

Reserved. This bit is reserved and should not be altered from the default.

Reserved. This field is reserved and returns 0 when read.

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8.5.1.7 Battery Charging Support Register (offset = 6h) [reset = 0Xh]

Figure 9. Register Offset 6h

7

0

6

0

5

0

4

0

3

0

2

0

1

X

0

X

R

R/W

LEGEND: R/W = Read/Write; R = Read only; –n = value after reset

Table 10. Battery Charging Support Register

Bit

Field

Type

Reset

Description

7:2

RSVD

R

0Xh

Reserved. Read only, returns 0 when read.

Battery Charger Support. The bits in this field indicate whether the downstream port

implements the charging port features.

0 = The port is not enabled for battery charging support features

1 = The port is enabled for battery charging support features

Each bit corresponds directly to a downstream port, that is batEn0 corresponds to

downstream port 1, and batEN1 corresponds to downstream port 2.

The default value for these bits are loaded at the deassertion of reset with the value of

PWRCTL/BATEN[1:0].

1:0

batEn[1:0]

R/W

0Xh

When in I2C/SMBus mode the bits in this field may be overwritten by EEPROM contents or

by an SMBus host.

8.5.1.8 Device Removable Configuration Register (offset = 7h) [reset = 0Xh]

Figure 10. Register Offset 7h

7

0

6

0

5

0

4

0

3

0

2

0

1

X

R

0

X

R/W

R

R/W

LEGEND: R/W = Read/Write; R = Read only; –n = value after reset

Table 11. Device Removable Configuration Register

Bit

Field

Type

Reset

Description

Custom removable status. When this field is a 1, the TUSB8020B uses rmbl bits in this

register to identify removable status for the ports.

7

customRmbl

R/W

0Xh

Reserved. Read only, returns 0 when read. Bits 3:2 are RW. They are reserved and

return 0 when read.

6:2

1:0

RSVD

R

0Xh

Removable. The bits in this field indicate whether a device attached to downstream

ports 2 through 1 are removable or permanently attached.

0 = The device attached to the port is not removable

1 = The device attached to the port is removable

rmbl[1:0]

R/W

Each bit corresponds directly to a downstream port n + 1, that is rmbl0 corresponds to

downstream port 1, rmbl1 corresponds to downstream port 2, and so forth.

This field is read only unless the customRmbl bit is set to 1. Otherwise the value of this

filed reflects the inverted values of the OTP ROM non_rmb[1:0] field.

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8.5.1.9 Port Used Configuration Register (offset = 8h) [reset = 0h]

Figure 11. Register Offset 8h

7

0

6

0

5

0

4

0

3

0

2

0

1

0

1

R

LEGEND: R/W = Read/Write; R = Read only; –n = value after reset

Table 12. Port Used Configuration Register

Bit

Field

Type

Reset

Description

7:0

RSVD

R

0h

Reserved. Read only.

8.5.1.10 PHY Custom Configuration Register (offset = 9h) [reset = 0h]

Figure 12. Register Offset 9h

7

0

6

0

5

0

4

0

3

0

2

0

1

0

1

R

R/W

R

R/W

LEGEND: R/W = Read/Write; R = Read only; –n = value after reset

Table 13. PHY Custom Configuration Register

Bit

7:6

5

Field

Type

R

Reset

0h

Description

RSVD

Reserved. Read only, returns 0 when read.

R/W

R

0h

Reserved. This bit is reserved and should not be altered from the default.

Reserved. Read only, returns 0 when read.

4:2

1:0

0h

R/W

0h

Reserved. This field is reserved and should not be altered from the default.

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8.5.1.11 Device Configuration Register 2 (offset = Ah)

Figure 13. Register Offset Ah

7

0

6

0

5

X

4

0

3

0

2

0

1

0

R

RW

R

LEGEND: R/W = Read/Write; R = Read only; –n = value after reset

Table 14. Bit Descriptions – Device Configuration Register 2

Bit

Field Name

Access

Reset

Description

Reserved. Read only, returns 0 when read.

7

RSVD

RO

Custom Battery Charging Feature Enable. This bit controls the ability to write to the

battery charging feature configuration controls.

0 = The HiCurAcpModeEn and AutoModeEnz bits are read only and the values

are loaded from the OTP ROM.

6

customBCfeatures

RW

1 = The HiCurAcpModeEn and AutoModeEnz bits are read/write and can be

loaded by EEPROM or written by SMBus. from this register.

This bit may be written simultaneously with HiCurAcpModeEn and AutoModeEnz.

Power enable polarity. This bit is loaded at the deassertion of reset with the inverse

value of the PWRCTL_POL terminal.

0 = PWRCTL polarity is active low

1 = PWRCTL polarity is active high

When the TUSB8020B is in I²C mode, the TUSB8020B loads this bit from the contents

of the EEPROM.

5

pwrctlPol

RW

When the TUSB8020B is in SMBUS mode, the value may be overwritten by an SMBus

host.

High-current ACP mode enable. This bit enables the high-current tablet charging mode

when the automatic battery charging mode is enabled for downstream ports.

0 = High current divider mode disabled

1 = High current divider mode enabled

4

HiCurAcpModeEn

RO/RW

This bit is read only unless the customBCfeatures bit is set to 1. Otherwise the value of

this bit reflects the value of the OTP ROM HiCurAcpModeEn bit.

3

2

RSVD

RW

Reserved

DSPort ECR enable. This bit enables full implementation of the DSPORT ECR (April

2013).

0 = DSPort ECR (April 2013) is enabled with the exception of changes related

to the CCS bit is set upon entering U0, and changes related to avoiding or

reporting compliance mode entry.

dsportEcrEn

1 = The full DSport ECR (April 2013) is enabled.

Automatic Mode Enable. This bit is loaded from the OTP ROM.

The automatic mode only applies to downstream ports with battery charging enabled

when the upstream port is not connected. Under these conditions:

0 = Automatic mode battery charging features are enabled. Only battery

charging DCP and custom BC (divider mode) is enabled.

1

0

autoModeEnz

RO/RW

1 = Automatic mode is disabled; only battery charging DCP and CDP mode is

supported.

Note: When the upstream port is connected, battery charging CDP mode is supported

on all ports when this field is one.

This bit is read only unless the customBCfeatures bit is set to 1. Otherwise the value of

this bit reflects the value of the OTP ROM AutoModeEnz bit.

RSVD

RO

Reserved. Read only, returns 0 when read.

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8.5.1.12 UUID Registers (offset = 10h to 1Fh)

Figure 14. Register Offset 10h to 1Fh

7

X

R

6

X

R

5

X

R

4

X

R

3

X

R

2

X

R

1

X

R

0

X

R

LEGEND: R/W = Read/Write; R = Read only; –n = value after reset

Table 15. Bit Descriptions – UUID Byte N Register

Bit

Field Name Access

uuidByte[n] RO

Reset

Description

UUID byte N. The UUID returned in the Container ID descriptor. The value of this register

is provided by the device and is meets the UUID requirements of Internet Engineering

Task Force (IETF) RFC 4122 A UUID URN Namespace.

7:0

8.5.1.13 Language ID LSB Register (offset = 20h)

Figure 15. Register Offset 20h

7

0

6

0

5

0

4

0

3

1

2

0

1

0

1

R/W

LEGEND: R/W = Read/Write; R = Read only; –n = value after reset

Table 16. Bit Descriptions – Language ID LSB Register

Bit

Field Name

Access

Reset

Description

Language ID least significant byte. This register contains the value returned in the

LSB of the LANGID code in string index 0. The TUSB8020B only supports one

language ID. The default value of this register is 09h representing the LSB of the

LangID 0409h indicating English United States. When customStrings is 1, this field

may be overwritten by the contents of an attached EEPROM or by an SMBus host.

7:0

langIdLsb

RW

8.5.1.14 Language ID MSB Register (offset = 21h)

Figure 16. Register Offset 21h

7

0

6

0

5

0

4

0

3

0

2

1

0

R/W

LEGEND: R/W = Read/Write; R = Read only; –n = value after reset

Table 17. Bit Descriptions – Language ID MSB Register

Bit

Field Name

Access

Reset

Description

Language ID most significant byte. This register contains the value returned in the MSB of

the LANGID code in string index 0. The TUSB8020B only supports one language ID. The

default value of this register is 04h representing the MSB of the LangID 0409h indicating

English United States.

7:0

langIdMsb

RO/RW

When customStrings is 1, this field may be overwritten by the contents of an attached

EEPROM or by an SMBus host.

20

TUSB8020B

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8.5.1.15 Serial Number String Length Register (offset = 22h)

Figure 17. Register Offset 22h

7

0

6

0

5

0

4

1

3

1

2

0

1

0

R/W

LEGEND: R/W = Read/Write; R = Read only; –n = value after reset

Table 18. Bit Descriptions – Serial Number String Length Register

Bit

Field Name

Access

Reset

Description

Reserved. Read only, returns 0 when read.

7:6

RSVD

RO

Serial number string length. The string length in bytes for the serial number string. The

default value is 18h indicating that a 24-byte serial number string is supported. The

maximum string length is 32 bytes.

5:0

serNumStringLen RO/RW

When customSernum is 1, this field may be overwritten by the contents of an attached

EEPROM or by an SMBus host.

When the field is non-zero, a serial number string of serNumbStringLen bytes is

returned at string index 1 from the data contained in the Serial Number String registers.

8.5.1.16 Manufacturer String Length Register (offset = 23h)

Figure 18. Register Offset 23h

7

0

6

0

5

0

4

3

2

0

1

0

R

R/W

LEGEND: R/W = Read/Write; R = Read only; –n = value after reset

Table 19. Bit Descriptions – Manufacturer String Length Register

Bit

Field Name

Access Reset

Description

Reserved. Read only, returns 0 when read.

7

RSVD

RO

Manufacturer string length. The string length in bytes for the manufacturer string. The default

value is 0, indicating that a manufacturer string is not provided. The maximum string length is

64 bytes.

6:0

mfgStringLen

RO/RW

When customStrings is 1, this field may be overwritten by the contents of an attached

EEPROM or by an SMBus host.

When the field is non-zero, a manufacturer string of mfgStringLen bytes is returned at string

index 3 from the data contained in the Manufacturer String registers.

8.5.1.17 Product String Length Register (offset = 24h)

Figure 19. Register Offset 24h

7

0

6

0

5

0

4

0

3

0

2

0

1

0

R

R/W

LEGEND: R/W = Read/Write; R = Read only; –n = value after reset

Table 20. Bit Descriptions – Product String Length Register

Bit

Field Name

Access

Reset

Description

Reserved. Read only, returns 0 when read.

7

RSVD

RO

Product string length. The string length in bytes for the product string. The default value is

0, indicating that a product string is not provided. The maximum string length is 64 bytes.

When customStrings is 1, this field may be overwritten by the contents of an attached

EEPROM or by an SMBus host.

6:0

prodStringLen

RO/RW

When the field is non-zero, a product string of prodStringLen bytes is returned at string

index 2 from the data contained in the Product String registers.

21

TUSB8020B

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8.5.1.18 Serial Number Registers (offset = 30h to 4Fh)

Figure 20. Register Offset 30h to 4Fh

7

X

6

X

5

x

4

x

3

x

2

x

1

x

0

x

R/W

LEGEND: R/W = Read/Write; R = Read only; –n = value after reset

Table 21. Bit Descriptions – Serial Number Registers

Bit

Field Name

Access

Reset

Description

Serial Number byte N. The serial number returned in the Serial Number string descriptor

at string index 1. The default value of these registers is set by TI. When customSernum is

1, these registers may be overwritten by EEPROM contents or by an SMBus host.

7:0

serialNumber[n] RO/RW

8.5.1.19 Manufacturer String Registers (offset = 50h to 8Fh)

Figure 21. Register Offset 50h to 8Fh

7

0

6

0

5

0

4

3

2

0

1

0

R/W

LEGEND: R/W = Read/Write; R = Read only; –n = value after reset

Table 22. Bit Descriptions – Manufacturer String Registers

Bit

Field Name

Access

Reset

Description

Manufacturer string byte N. These registers provide the string values returned for string

index 3 when mfgStringLen is greater than 0. The number of bytes returned in the string is

equal to mfgStringLen.

7:0

mfgStringByte[n] RO/RW

The programmed data should be in UNICODE UTF-16LE encodings as defined by The

Unicode Standard, Worldwide Character Encoding, Version 5.0.

8.5.1.20 Product String Registers (offset = 90h to CFh)

Figure 22. Register Offset 90h to CFh

7

0

6

0

5

0

4

0

3

0

2

0

1

0

R/W

LEGEND: R/W = Read/Write; R = Read only; –n = value after reset

Table 23. Bit Descriptions – Product String Byte N Register

Bit

Field Name

Access

Reset

Description

Product string byte N. These registers provide the string values returned for string

index 2 when prodStringLen is greater than 0. The number of bytes returned in the

string is equal to prodStringLen.

7:0

prodStringByte[n]

RW

The programmed data should be in UNICODE UTF-16LE encodings as defined by

The Unicode Standard, Worldwide Character Encoding, Version 5.0.

22

TUSB8020B

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ZHCSDC7C –JULY 2014–REVISED JUNE 2017

8.5.1.21 Additional Feature Configuration Register (offset = F0h)

Figure 23. Register Offset F0h

7

0

6

0

5

0

4

0

3

0

2

0

1

0

R

R/W

LEGEND: R/W = Read/Write; R = Read only; –n = value after reset

Table 24. Bit Descriptions – Additional Feature Configuration Register

Bit

Field Name

Access

Reset

Description

Reserved. Read only, returns 0 when read.

7:1

RSVD

RO

USB3 Spread Spectrum Disable. This bit allows firmware to disable the spread spectrum

function of the USB3 phy PLL.

0 = Spread spectrum function is enabled

0

usb3spreadDis

RW

1= Spread spectrum function is disabled

This bit is loaded at the deassertion of reset with the value of the SCL/SMBCLK terminal.

8.5.1.22 Charging Port Control Register (offset = F2h)

Figure 24. Register Offset F2h

7

0

6

0

5

0

4

0

3

0

2

0

1

0

R

R/W

LEGEND: R/W = Read/Write; R = Read only; –n = value after reset

Table 25. Bit Descriptions – Charging Port Control Register

Bit

Field Name

Access

Reset

Description

Reserved. Read only, returns 0 when read.

7:4

RSVD

RO

Power-On Delay Time. When dsportEcrEn is set, this field sets the delay time from the

removal disable of PWRCTL to the enable of PWRCTL when transitioning battery charging

modes. For example, when disabling the power on a transition from custom charging mode

to Dedicated Charging Port Mode. The nominal timing is defined as follows:

3:1

0

pwronTime

RSVD

RW

TPWRON_EN = (pwronTime + 1) × 200 ms

(1)

These registers may be overwritten by EEPROM contents or by an SMBus host.

Reserved. This bit is reserved and should not be altered from the default.

23

TUSB8020B

ZHCSDC7C –JULY 2014–REVISED JUNE 2017

www.ti.com.cn

8.5.1.23 Device Status and Command Register (offset = F8h)

Figure 25. Register Offset F8h

7

0

6

0

5

0

4

0

3

0

2

0

1

0

R

RSU

RCU

LEGEND: R/W = Read/Write; R = Read only; –n = value after reset

Table 26. Bit Descriptions – Device Status and Command Register

Bit

Field Name

Access

Reset

Description

Reserved. Read only, returns 0 when read.

7:2

RSVD

R

SMBus interface reset. This bit loads the registers back to their GRSTz values.

This bit is set by writing a 1 and is cleared by hardware on completion of the reset. A

write of 0 has no effect.

1

0

smbusRst

cfgActive

RSU

RCU

Configuration active. This bit indicates that configuration of the TUSB8020B is currently

active. The bit is set by hardware when the device enters the I²C or SMBus mode. The

TUSB8020B will not connect on the upstream port while this bit is 1.

When in the SMBus mode, this bit must be cleared by the SMBus host to exit the

configuration mode and allow the upstream port to connect.

The bit is cleared by a writing 1. A write of 0 has no effect.

24

TUSB8020B

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ZHCSDC7C –JULY 2014–REVISED JUNE 2017

9 Application and Implementation

9.1 Application Information

The TUSB8020B is a two-port USB 3.0 compliant hub. It provides simultaneous SuperSpeed USB and high-

speed/full-speed connections on the upstream port and provides SuperSpeed USB, high-speed, full-speed, or

low-speed connections on the downstream port. The TUSB8020B can be used in any application that needs

additional USB compliant ports. For example, a specific notebook may only have two downstream USB ports. By

using the TUSB8020B, the notebook can increase the downstream port count to three.

9.2 Typical Application

A common application for the TUSB8020B is as a self-powered standalone USB hub product. The product is

powered by an external 5-V DC power adapter. In this application using a USB cable, TUSB8020B device’s

upstream port is plugged into a USB host controller. The downstream ports of the TUSB8020B are exposed to

users for connecting USB hard drives, camera, flash drive, and so forth.

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Ü{ torꢀ

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5{ torꢀ 1

5{ torꢀ 2

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Figure 26. Discrete USB Hub Product

25

TUSB8020B

ZHCSDC7C –JULY 2014–REVISED JUNE 2017

www.ti.com.cn

Typical Application (continued)

9.2.1 Design Requirements

Table 27. Input Parameters

DESIGN PARAMETER

EXAMPLE VALUE

VDD supply

1.1 V

VDD33 supply

3.3 V

Upstream port USB support (SS, HS, FS)

Downstream port 1 USB support (SS, HS, FS, LS)

Downstream port 2 USB support (SS, HS, FS, LS)

Number of removable downstream ports

Number of non-removable downstream ports

Full power management of downstream ports

Individual control of downstream port power switch

Power switch enable polarity

SS, HS, FS

SS, HS, FS, LS

2

0

Yes (FULLPWRMGMTZ = 0)

Yes (GANGED = 0)

Active high (PWRCTL_POL = 0)

Battery charge support for downstream port 1

Battery charge support for downstream port 2

I²C EEPROM support

Yes

No

24-MHz clock source

Crystal

9.2.2 Detailed Design Procedure

9.2.2.1 Upstream Port Implementation

The upstream of the TUSB8020B is connected to a USB3 type B connector. This particular example has

GANGED terminal and FULLPWRMGMTZ terminal pulled low, which results in individual power support each

downstream port. The VBUS signal from the USB3 type B connector is fed through a voltage divider. The

purpose of the voltage divider is to make sure the level meets USB_VBUS input requirements.

R1

90.9K

0402

1%

R2

C1

10uF

10K 1%

0402

1%

U1A

J1

9

35

36

USB_VBUS

GANGED / SMBA2 / HS_UP

1

2

3

4

5

6

7

8

VBUS

DM

DP

USB_DM_UP

USB_DP_UP

27

26

USB_DM_UP

USB_DP_UP

FULLPWRMGMTZ / SMBA1 / SS_UP

GND

CAP_UP_TXM

CAP_UP_TXP

C2

C3

0.1uF 0201

USB_SSTXM_UP

28

29

SSTXN

SSTXP

GND

SSRXN

SSRXP

SHIELD0

SHIELD1

USB_SSTXM_UP

USB_SSTXP_UP

R3

R4

USB_SSTXP_UP

USB_SSRXM_UP

USB_SSRXP_UP

4.7K

0402

5%

4.7K

0402

5%

31

32

USB_SSRXM_UP

USB_SSRXP_UP

9

10

11

USB3_TYPEB_CONNECTOR

C4

0.1uF

C5

0.001uF

R5

TUSB8020B

1M

0402

5%

Figure 27. Upstream Port Implementation

26

TUSB8020B

www.ti.com.cn

ZHCSDC7C –JULY 2014–REVISED JUNE 2017

9.2.2.2 Downstream Port 1 Implementation

The downstream port 1 of the TUSB8020B is connected to a USB3 type A connector. With BATEN1 terminal

pulled up, battery charge support is enabled for port 1. If battery charge support is not needed, then the pullup

resistor on BATEN1 should be uninstalled. The PWRCTL_POL is pulled-down, which results in active-high power

enable (PWRCTL1 and PWRCTL2) for a USB VBUS power switch.

BOARD_3P3V

FB1

R6

POPULATE

DN1_VBUS

VBUS_DS1

4.7K

0402

5%

DN1_VBUS

FOR BC SUPPORT

220 @ 100MHZ C6

0.1uF

J2

U1B

1

2

3

4

5

6

7

8

9

VBUS

DM

DP

21

42

41

USB_DM_DN1

USB_DP_DN1

PWRCTL_POL / SS_DN1

USB_DM_DN1

USB_DP_DN1

GND

R7

47

46

USB_SSRXM_DN1

USB_SSRXP_DN1

USB_SSRXM_DN1

USB_SSRXP_DN1

SSRXN

SSRXP

GND

SSTXN

SSTXP

4.7K

0402

5%

0.1uF 0201

C7

C8

44

43

USB_SSTXM_DN1

USB_SSTXP_DN1

CAP_DN_TXM1

CAP_DN_TXP1

USB_SSTXM_DN1

USB_SSTXP_DN1

10

11

SHIELD0

SHIELD1

4

5

PWRCTRL1_BATEN1

OVERCUR1Z

PWRCTL1 / BATEN1

OVERCUR1Z

USB3_TYPEA_CONNECTOR

R8

1M

C9

0.001uF

C10

0.1uF

TUSB8020B

0402

5%

Figure 28. Downstream Port 1 Implementation

9.2.2.3 Downstream Port 2 Implementation

The downstream port 2 of the TUSB8020B is connected to a USB3 type A connector. With BATEN2 terminal

pulled up, battery charge support is enabled for port 2. If battery charge support is not needed, then the pullup

resistor on BATEN2 should be uninstalled.

BOARD_3P3V

FB2

R9

DN2_VBUS

VBUS_DS2

DN2_VBUS

POPULATE

4.7K

0402

5%

FOR BC SUPPORT

220 @ 100MHZ

C11

0.1uF

J3

U1C

1

2

3

4

5

6

7

8

9

VBUS

DM

DP

22

15

14

USB_DM_DN2

USB_DP_DN2

SMBUSZ / SS_DN2

USB_DM_DN2

USB_DP_DN2

GND

20

19

USB_SSRXM_DN2

USB_SSRXP_DN2

USB_SSRXM_DN2

USB_SSRXP_DN2

SSRXN

SSRXP

GND

SSTXN

SSTXP

17

16

USB_SSTXM_DN2

USB_SSTXP_DN2

C12

0.1uF 0201

CAP_DN2_TXM

CAP_DN2_TXP

USB_SSTXM_DN2

USB_SSTXP_DN2

C13

10

11

SHIELD0

SHIELD1

6

8

PWRCTRL2_BATEN2

OVERCUR2Z

PWRCTL2 / BATEN2

OVERCUR2Z

R10

1M

C15

0.001uF

USB3_TYPEA_CONNECTOR

C14

0.1uF

0402

5%

TUSB8020B

Figure 29. Downstream Port 2 Implementation

27

TUSB8020B

ZHCSDC7C –JULY 2014–REVISED JUNE 2017

www.ti.com.cn

9.2.2.4 VBUS Power Switch Implementation

This particular example uses the TI TPS2561 dual-channel precision adjustable current-limited power switch. For

details on this power switch or other power switches available from TI, refer to www.ti.com.

BOARD_3P3V

BOARD_5V

R19

10K

0402

5%

R20

10K

0402

5%

C36

0.1uF

U3

2

3

9

DN1_VBUS

DN2_VBUS

ILIM1

DN1_VBUS

OVERCUR1Z

DN2_VBUS

OVERCUR2Z

IN

OUT1

FAULT1Z

OUT2

10

8

PWRCTRL1_BATEN1

PWRCTRL2_BATEN2

4

5

PWRCTRL1_BATEN1

PWRCTRL2_BATEN2

EN1

EN2

6

FAULT2Z

ILIM

1

11

GND

PAD

7

C37

C39

0.1uF

+

C38

150uF

0.1uF

+

C40

150uF

TPS2561

R21

25.5K

0402

5%

Limiting DS Port VBUS current to 2.2A per port.

Figure 30. Power Switch Implementation

9.2.2.5 Clock, Reset, and Miscellaneous

U1D

2

C32

1uF

SCL / SMBCLK

3

SDA / SMBDAT

11

38

GRSTZ

XI

10

24

TEST

R11

1M

USB_R1

39

XO

R12

Y1

R13

1K

9.53K

0402

1%

TUSB8020B

24MHz

C33

C34

18pF

Figure 31. Clock, Reset, and Miscellaneous

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TUSB8020B

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ZHCSDC7C –JULY 2014–REVISED JUNE 2017

9.2.2.6 Power Implementation

BOARD_1P1V

VDD11

FB3

C16

C17

C18

C19

C20

C21

C22

10uF

220 @ 100MHZ

0.1uF

U1E

7

VDD33

13

VDD33

23

BOARD_3P3V

VDD33

25

VDD33

33

VDD33

37

VDD33

40

FB4

VDD33

48

VDD33

C23

C24

0.1uF

C25

0.1uF

C26

0.1uF

C27

0.1uF

C28

0.1uF

C29

0.1uF

C30

0.1uF

C31

1uF

220 @ 100MHZ

0.1uF

TUSB8020B

Figure 32. Power Implementation

9.2.3 Application Curves

Figure 33. SuperSpeed TX Eye for Downstream Port 1

Figure 34. SuperSpeed TX Eye for Downstream Port 2

Figure 35. HighSpeed TX Eye for Downstream Port 1

Figure 36. HighSpeed TX Eye for Downstream Port 2

29

TUSB8020B

ZHCSDC7C –JULY 2014–REVISED JUNE 2017

www.ti.com.cn

10 Power Supply Recommendations

10.1 Power Supply

V_DDshould be implemented as a single power plane, as should V_DD33

.

•

The V_DDterminals of the TUSB8020B supply 1.1-V (nominal) power to the core of the TUSB8020B. This

power rail can be isolated from all other power rails by a ferrite bead to reduce noise.

•

The DC resistance of the ferrite bead on the core power rail can affect the voltage provided to the device due

to the high current draw on the power rail. The output of the core voltage regulator may need to be adjusted

to account for this or a ferrite bead with low DC resistance (less than 0.05 Ω) can be selected.

•

The V_DD33terminals of the TUSB8020B supply 3.3-V power rail to the I/O of the TUSB8020B. This power rail

can be isolated from all other power rails by a ferrite bead to reduce noise.

All power rails require a 10-µF capacitor or 1-µF capacitors for stability and noise immunity. These bulk

capacitors can be placed anywhere on the power rail. The smaller decoupling capacitors should be placed as

close to the TUSB8020B power pins as possible with an optimal grouping of two of differing values per pin.

10.2 Downstream Port Power

•

The downstream port power, VBUS, must be supplied by a source capable of supplying 5 V and at least

900 mA per port. Downstream port power switches can be controlled by the TUSB8020BPHP signals. It is

possible to leave the downstream port power always enabled.

•

Each downstream port’s VBUS requires a large bulk low-ESR capacitor of 22 µF or larger to limit in-rush

current.

TI recommends ferrite beads on the VBUS pins of the downstream USB port connections for both ESD and

EMI reasons. A 0.1-µF capacitor on the USB connector side of the ferrite provides a low-impedance path to

ground for fast rise time ESD current that might have coupled onto the VBUS trace from the cable.

10.3 Ground

TI recommends to use only one board ground plane in the design. This provides the best image plane for signal

traces running above the plane. The thermal pad of the TUSB8020B and any of the voltage regulators should be

connected to this plane with vias. An earth or chassis ground is only implemented near the USB port connectors

on a different plane for EMI and ESD purposes.

30

TUSB8020B

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ZHCSDC7C –JULY 2014–REVISED JUNE 2017

11 Layout

11.1 Layout Guidelines

11.1.1 Placement

1. A 9.53-kΩ ±1% resistor connected to terminal USB_R1 should be placed as close as possible to the

TUSB8020B.

2. A 0.1-µF capacitor should be placed as close as possible on each V_DDand V_DD33power pin.

3. The 100-nF capacitors on the SSTXP and SSTXM nets should be placed close to the USB connector (type

A, type B, and so forth).

4. The ESD and EMI protection devices (if used) should also be placed as possible to the USB connector.

5. If a crystal is used, it must be placed as close as possible to the TUSB8020B device’s XI and XO terminals.

6. Place voltage regulators as far away as possible from the TUSB8020B, crystal, and differential pairs.

7. In general, the large bulk capacitors associated with each power rail should be placed as close as possible to

the voltage regulators.

11.1.2 Package Specific

1. The TUSB8020B package has a 0.5-mm pin pitch.

2. The TUSB8020B package has a 3.6-mm × 3.6-mm thermal pad. This thermal pad must be connected to

ground through a system of vias.

3. All vias under device, except for those connected to thermal pad, should be solder masked to avoid potential

issues with thermal pad layouts.

11.1.3 Differential Pairs

This section describes the layout recommendations for all of the TUSB8020B differential pairs: USB_DP_XX,

USB_DM_XX, USB_SSTXP_XX, USB_SSTXM_XX, USB_SSRXP_XX, and USB_SSRXM_XX.

•

Must be designed with a differential impedance of 90 Ω ±10%.

To minimize crosstalk, TI recommends to keep high-speed signals away from each other. Each pair should

be separated by at least 5× the signal trace width. Separating with ground as depicted in the layout example

also helps minimize crosstalk.

•

Route all differential pairs on the same layer adjacent to a solid ground plane.

Do not route differential pairs over any plane split.

Adding test points causes impedance discontinuity, and therefore, negatively impacts signal performance. If

test points are used, they should be placed in series and symmetrically. They must not be placed in a manner

that causes stub on the differential pair.

•

Avoid 90° turns in trace. The use of bends in differential traces should be kept to a minimum. When bends

are used, the number of left and right bends should be as equal as possible and the angle of the bend should

be ≥135°. Taking this action minimizes any length mismatch caused by the bends, and therefore, minimizes

the impact bends have on EMI.

•

Minimize the trace lengths of the differential pair traces. Eight inches is the maximum recommended trace

length for SS differential-pair signals and USB 2.0 differential-pair signals. Longer trace lengths require very

careful routing to assure proper signal integrity.

Match the etch lengths of the differential pair traces (that is DP and DM or SSRXP and SSRXM or SSTXP

and SSTXM). There should be less than 5-mils difference between a SS differential-pair signal and its

complement. The USB 2.0 differential pairs should not exceed 50-mils relative trace length difference.

•

The etch lengths of the differential pair groups do not need to match (that is the length of the SSRX pair to

that of the SSTX pair), but all trace lengths should be minimized.

Minimize the use of vias in the differential-pair paths as much as possible. If this is not practical, ensure that

the same via type and placement are used for both signals in a pair. Any vias used should be placed as close

as possible to the TUSB8020B device.

•

To ease routing, the polarity of the SS differential pairs can be swapped. This means that SSTXP can be

routed to SSTXM or SSRXM can be routed to SSRXP.

Do not place power fuses across the differential-pair traces.

31

TUSB8020B

ZHCSDC7C –JULY 2014–REVISED JUNE 2017

www.ti.com.cn

11.2 Layout Example

11.2.1 Upstream Port

32

TUSB8020B

www.ti.com.cn

ZHCSDC7C –JULY 2014–REVISED JUNE 2017

Layout Example (continued)

11.2.2 Downstream Port

11.2.3 Thermal Pad

33

TUSB8020B

ZHCSDC7C –JULY 2014–REVISED JUNE 2017

www.ti.com.cn

12 器件和文档支持

12.1 社区资源

下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，

并且不一定反映 TI 的观点；请参阅 TI 的《使用条款》。

TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在

e2e.ti.com 中，您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。

设计支持

TI 参考设计支持可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。

12.2 商标

E2E is a trademark of Texas Instruments.

All other trademarks are the property of their respective owners.

12.3 静电放电警告

这些装置包含有限的内置 ESD 保护。存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损

伤。

12.4 Glossary

SLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

13 机械、封装和可订购信息

以下页面包括机械、封装和可订购信息。这些信息是指定器件的最新可用数据。这些数据发生变化时，我们可能不

会另行通知或修订此文档。如欲获取此产品说明书的浏览器版本，请参阅左侧的导航栏。

34

PACKAGE MATERIALS INFORMATION

www.ti.com

5-Jan-2022

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

A0

B0

K0

P1

W

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

TUSB8020BIPHPR

TUSB8020BPHPR

HTQFP

PHP

48

1000

330.0

16.4

9.6

1.5

12.0

16.0

Q2

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

5-Jan-2022

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

TUSB8020BIPHPR

TUSB8020BPHPR

HTQFP

PHP

48

1000

336.6

31.8

Pack Materials-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

5-Jan-2022

TRAY

Chamfer on Tray corner indicates Pin 1 orientation of packed units.

*All dimensions are nominal

Device

Package Package Pins SPQ Unit array

Max

matrix temperature

(°C)

L (mm)

W

K0

P1

CL

CW

Name

Type

(mm) (µm) (mm) (mm) (mm)

TUSB8020BIPHP

TUSB8020BPHP

PHP

HTQFP

48

250

10 x 25

150

315 135.9 7620 12.2

11.1 11.25

Pack Materials-Page 3

GENERIC PACKAGE VIEW

PHP 48

7 x 7, 0.5 mm pitch

TQFP - 1.2 mm max height

QUAD FLATPACK

This image is a representation of the package family, actual package may vary.

Refer to the product data sheet for package details.

4226443/A

www.ti.com

PACKAGE OUTLINE

PHP0048E

PowerPAD^TMHTQFP - 1.2 mm max height

SCALE 1.900

7.2

6.8

B

NOTE 3

37

48

PIN 1 ID

1

36

7.2

6.8

9.2

TYP

8.8

NOTE 3

12

25

13

24

A

0.27

48X

44X 0.5

0.17

0.08

C A B

4X 5.5

1.2 MAX

C

SEATING PLANE

SEE DETAIL A

(0.13)

TYP

0.08

13

24

12

25

0.25

(1)

GAGE PLANE

3.62

3.15

49

0.75

0.45

0.15

0.05

0 -7

A

16

1

36

DETAIL A

TYPICAL

48

37

4X (0.25) NOTE 5

3.62

3.15

4226616 /A 02/2021

PowerPAD is a trademark of Texas Instruments.

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not

exceed 0.15 mm per side.

4. Reference JEDEC registration MS-026.

5. Feature may not be present.

www.ti.com

EXAMPLE BOARD LAYOUT

PHP0048E

PowerPAD^TMHTQFP - 1.2 mm max height

(

6.5)

NOTE 10

(3.62)

SYMM

48

37

SOLDER MASK

DEFINED PAD

48X (1.6)

1

36

48X (0.3)

(3.62)

SYMM

49

(1.1 TYP)

(8.5)

44X (0.5)

12

25

(R0.05) TYP

(

0.2) TYP

VIA

METAL COVERED

BY SOLDER MASK

13

24

(1.1 TYP)

SEE DETAILS

(8.5)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE:8X

0.05 MAX

ALL AROUND

0.05 MIN

ALL AROUND

SOLDER MASK

OPENING

METAL

EXPOSED METAL

METAL UNDER

SOLDER MASK

OPENING

NON SOLDER MASK

DEFINED

SOLDER MASK

DEFINED

SOLDER MASK DETAILS

4226616 /A 02/2021

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

8. This package is designed to be soldered to a thermal pad on the board. See technical brief, Powerpad thermally enhanced package,

Texas Instruments Literature No. SLMA002 (www.ti.com/lit/slma002) and SLMA004 (www.ti.com/lit/slma004).

9. Vias are optional depending on application, refer to device data sheet. It is recommended that vias under paste be filled, plugged

or tented.

10. Size of metal pad may vary due to creepage requirement.

www.ti.com

EXAMPLE STENCIL DESIGN

PHP0048E

PowerPAD^TMHTQFP - 1.2 mm max height

(3.62)

BASED ON

0.125 THICK STENCIL

SEE TABLE FOR

SYMM

DIFFERENT OPENINGS

FOR OTHER STENCIL

THICKNESSES

48

37

48X (1.6)

1

36

48X (0.3)

(8.5)

(3.62)

SYMM

49

BASED ON

0.125 THICK

STENCIL

44X (0.5)

12

25

(R0.05) TYP

METAL COVERED

BY SOLDER MASK

24

13

(8.5)

SOLDER PASTE EXAMPLE

EXPOSED PAD

100% PRINTED SOLDER COVERAGE BY AREA

SCALE:8X

STENCIL

THICKNESS

SOLDER STENCIL

OPENING

0.1

4.05 X 4.05

3.62 x 3.62 (SHOWN)

3.30 x 3.30

0.125

0.150

0.175

3.06 x 3.06

4226616 /A 02/2021

NOTES: (continued)

11. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

12. Board assembly site may have different recommendations for stencil design.

www.ti.com

重要声明和免责声明

TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，

不保证没有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担

保。

这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验

证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。

这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。

您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成

本、损失和债务，TI 对此概不负责。

TI 提供的产品受 TI 的销售条款或 ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI 提供这些资源并不会扩展或以其他方式更改

TI 针对 TI 产品发布的适用的担保或担保免责声明。

TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE

邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	TUSB8020BIPHPR
厂家：	TEXAS INSTRUMENTS
描述：	两端口 SuperSpeed 5.0Gbps USB 3.0 集线器 \| PHP \| 48 \| -40 to 85 商用集成电路
文件：	总44页 (文件大小：2374K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

TUSB8020BIPHPR [TI]

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