TUSB8042RGCR [TI]
4 端口 SuperSpeed 5.0Gbps USB 3.1 集线器 | RGC | 64 | 0 to 70;型号: | TUSB8042RGCR |
厂家: | TEXAS INSTRUMENTS |
描述: | 4 端口 SuperSpeed 5.0Gbps USB 3.1 集线器 | RGC | 64 | 0 to 70 外围集成电路 |
文件: | 总59页 (文件大小:2498K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
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TUSB8042
ZHCSGM0 –AUGUST 2017
TUSB8042带 USB 告示板的四端口 USB 3.1 1 代集线器
1 特性
2 应用
计算机系统、扩展坞、监视器和机顶盒
1
•
•
四端口 USB 3.1 1 代集线器
USB 2.0 集线器 特性
3 说明
–
–
多事务转换器 (MTT) 集线器:四个事务转换器
TUSB8042 是一款四端口 USB 3.1 1 代集线器。该器
件在上行端口上可提供同步超快速和高速/全速 USB 连
接,在下行端口上可提供超快速、高速、全速或者低速
USB 连接。当上行端口连接到一个仅支持高速或全速/
低速连接的电气环境中时,下行端口上的超快速 USB
连接将会禁用。
每个事务转换器具有两个异步端点缓冲器
•
支持电池充电:
–
在未连接或未配置上行端口的情况下,可支持
D+/D- 分频器充电端口(ACP1、ACP2 和
ACP3)
–
在未连接上行端口的情况下,可支持自动模式以
在 DCP 或 ACP 模式之间进行切换
器件信息(1)
–
–
–
–
支持 Galaxy 充电
器件型号
TUSB8042
封装
封装尺寸(标称值)
充电下行端口 (CDP) 模式(上行端口已连接)
专用充电端口 (DCP) 模式(上行端口未连接)
VQFN (64)
9.00mm x 9.00mm
(1) 如需了解所有可用封装,请见数据表末尾的可订购产品附录。
DCP 模式符合中国电信行业标准 YD/T 1591-
2009
图
•
•
•
•
支持用作 USB 3.1 1 代或者 USB 2.0 复合器件
支持每端口或成组电源开关以及过流通知输入
支持四个外部下行端口
Ü{. 3ꢀ1 {ystem Lmplementation
支持读取和写入 I2C 的供应商请求,并且在 100k
Ü{. 3ꢀx Iost /ontroller
和 400k(默认)条件下支持 EEPROM 读取
•
•
I2C 主机支持时钟拉伸
Ü{. 2ꢀ0
5evice
ÇÜ{.8042
Ü{. 3ꢀx
5evice
可使用一次性可编程 (OTP) ROM、串行 EEPROM
或 I2C/SMBus 受控接口进行自定义配置:
Ü{. 2ꢀ0
5evice
–
–
–
–
VID 和 PID
Ü{. 3ꢀx Iub
Ü{. 2ꢀ0 Iub
端口定制
Ü{. 3ꢀx
5evice
Ü{. 2ꢀ0
5evice
生产商和产品字串(OTP ROM 不支持)
序列号(OTP ROM 不支持)
可使用引脚选择、EEPROM 或 I2C/SMBus 从机接
Ü{. 3ꢀx
5evice
Ü{. 1ꢀ1
5evice
Ü{. 1ꢀ1
5evice
•
口选择应用特性
Ü{. 1ꢀx /onnection
Ü{. 2ꢀ0 /onnection
•
•
•
•
提供 128 位通用唯一标识符 (UUID)
单时钟输入,24MHz 晶振或者振荡器
下行端口仅可对 USB 2.0 进行配置
64 引脚 QFN 封装 (RGC)
Ü{. 2ꢀ0ꢁ3ꢀx 5evice
Ü{. 3ꢀx 5evice
Ü{. 2ꢀ0 5evice
Ü{. 1ꢀx 5evice
Ü{. 3ꢀx /onnection
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SLLSET2
TUSB8042
ZHCSGM0 –AUGUST 2017
www.ti.com.cn
目录
8.5 Register Maps......................................................... 22
Applications and Implementation ...................... 37
9.1 Application Information............................................ 37
9.2 Typical Application .................................................. 37
1
2
3
4
5
6
7
特性.......................................................................... 1
9
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
说明 (续).............................................................. 3
Pin Configuration and Functions......................... 4
Specifications......................................................... 9
7.1 Absolute Maximum Ratings ..................................... 9
7.2 ESD Ratings.............................................................. 9
7.3 Recommended Operating Conditions....................... 9
7.4 Thermal Information.................................................. 9
7.5 Electrical Characteristics, 3.3-V I/O ........................ 10
7.6 Timing Requirements, Power-Up............................ 10
7.7 Hub Input Supply Current ....................................... 11
Detailed Description ............................................ 12
8.1 Overview ................................................................. 12
8.2 Functional Block Diagram ....................................... 12
8.3 Feature Description................................................. 13
8.4 Device Functional Modes........................................ 19
10 Power Supply Recommendations ..................... 46
10.1 TUSB8042 Power Supply ..................................... 46
10.2 Downstream Port Power ....................................... 46
10.3 Ground .................................................................. 46
11 Layout................................................................... 47
11.1 Layout Guidelines ................................................. 47
11.2 Layout Examples................................................... 48
12 器件和文档支持 ..................................................... 50
12.1 接收文档更新通知 ................................................. 50
12.2 社区资源................................................................ 50
12.3 商标....................................................................... 50
12.4 静电放电警告......................................................... 50
12.5 Glossary................................................................ 50
13 机械、封装和可订购信息....................................... 51
8
4 修订历史记录
注:之前版本的页码可能与当前版本有所不同。
表 1.
日期
修订版本
注意
2017 年 8 月
*
初始发行版。
2
版权 © 2017, Texas Instruments Incorporated
TUSB8042
www.ti.com.cn
ZHCSGM0 –AUGUST 2017
5 说明 (续)
当上行端口连接到一个仅支持全速/低速连接的电气环境中时,下行端口上的超快速 USB 和高速连接将会禁用。
TUSB8042 支持每端口或成组电源开关和过流保护,并且还支持电池充电 应用。
按照 USB 主机的要求,一个端口电源单独控制集线器开关为每个下行端口加电或者断电。同样地,当一个端口电
源单独控制集线器感测到一个过流事件时,它只关闭到受影响的下行端口的电源。
当需要为任一端口供电时,一个成组集线器开关打开到其所有下行端口的电源。只有当所有端口处于电源可被移除
的状态时,到下行端口的电源才可被关闭。同样地,当一个成组集线器感测到一个过流事件时,到所有下行端口的
电源将被关闭。
TUSB8042 下行端口可提供电池充电下行端口 (CDP) 握手支持,以此为电池充电 应用 提供支持。在未连接上行端
口的情况下,该器件还支持专用充电端口 (DCP) 模式。DCP 模式为支持 USB 电池充电、Galaxy 充电和符合中国
电信行业标准 YD/T 1591-2009 的 USB 器件提供支持。 此外,在未连接上行端口的情况下,TUSB8042 支持分频
器充电端口模式(ACPx 模式),并且可在所有模式之间进行自动切换,切换顺序从 ACP3 模式开始,到 DCP 模
式结束。
TUSB8042 能够为包括电池充电支持在内的部分 特性 提供引脚搭接配置,还能够通过 OTP ROM、I2C EEPROM
或 I2C/SMBus 从机接口为 PID、VID、自定义端口和物理层配置提供定制支持。使用 I2C EEPROM 或 I2C/SMBus
从机接口时,还可以提供定制字串支持。
该器件采用 64 引脚 RGC 封装,商用版 的工作温度范围为 0°C 至 70°C。
Copyright © 2017, Texas Instruments Incorporated
3
TUSB8042
ZHCSGM0 –AUGUST 2017
www.ti.com.cn
6 Pin Configuration and Functions
RGC Package
64 Pin (VQFN)
(Top View)
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
49
50
51
52
53
TEST
PWRCTL4 / BATEN4
VDD
GRTSz
VDD
VDD33
USB_SSRXM_DN4
USB_SSRXP_DN4
USB_DP_UP
VDD
27
26
25
24
23
22
21
20
19
18
17
USB_DM_UP
54
55
56
57
58
59
60
61
62
63
64
USB_SSTXM_DN4
USB_SSTXP_DN4
USB_DM_DN4
USB_DP_DN4
USB_SSTXP_UP
USB_SSTXM_UP
VDD
VSS
USB_SSRXP_UP
USB_SSRXM_UP
NC
USB_SSRXM_DN3
USB_SSRXP_DN3
VDD
USB_SSTXM_DN3
USB_SSTXP_DN3
XO
XI
VDD33
USB_DM_DN3
USB_DP_DN3
USB_R1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
4
Copyright © 2017, Texas Instruments Incorporated
TUSB8042
www.ti.com.cn
ZHCSGM0 –AUGUST 2017
Pin Functions
PIN
NAME
I/O
DESCRIPTION
NO.
Clock and Reset Signals
I
Global power reset. This reset brings all of the TUSB8042 internal registers to their default
states. When GRSTz is asserted, the device is completely nonfunctional.
GRSTz
50
62
PU
Crystal input. This pin is the crystal input for the internal oscillator. The input may alternately
be driven by the output of an external oscillator. When using a crystal a 1-MΩ feedback
resistor is required between XI and XO.
XI
I
Crystal output. This pin is the crystal output for the internal oscillator. If XI is driven by an
external oscillator this pin may be left unconnected. When using a crystal a 1-MΩ feedback
resistor is required between XI and XO.
XO
61
O
USB Upstream Signals
USB_SSTXP_UP
USB_SSTXM_UP
USB_SSRXP_UP
USB_SSRXM_UP
USB_DP_UP
55
56
58
59
53
54
O
O
I
USB SuperSpeed transmitter differential pair (positive)
USB SuperSpeed transmitter differential pair (negative)
USB SuperSpeed receiver differential pair (positive)
USB SuperSpeed receiver differential pair (negative)
USB High-speed differential transceiver (positive)
USB High-speed differential transceiver (negative)
I
I/O
I/O
I
USB_DM_UP
Precision resistor reference. A 9.53-kΩ ±1% resistor should be connected between USB_R1
and GND.
USB_R1
64
I
USB upstream port power monitor. The VBUS detection requires a voltage divider. The signal
USB_VBUS must be connected to VBUS through a 90.9-KΩ ±1% resistor, and to ground
through a 10-kΩ ±1% resistor from the signal to ground.
USB_VBUS
48
USB Downstream Signals
USB_SSTXP_DN1
USB_SSTXM_DN1
USB_SSRXP_DN1
USB_SSRXM_DN1
USB_DP_DN1
3
4
6
7
1
2
O
O
I
USB SuperSpeed transmitter differential pair (positive)
USB SuperSpeed transmitter differential pair (negative)
USB SuperSpeed receiver differential pair (positive)
USB SuperSpeed receiver differential pair (negative)
USB High-speed differential transceiver (positive)
USB High-speed differential transceiver (negative)
I
I/O
I/O
USB_DM_DN1
USB Port 1 Power On Control for Downstream Power/Battery Charging Enable. The pin is
used for control of the downstream power switch for Port 1. This pin be left unconnected if
power management is not implemented.
In addition, the value of the pin is sampled at the de-assertion of reset to determine the value
of the battery charging support for Port 1 as indicated in the Battery Charging Support
register:
PWRCTL1/BATEN1
36
I/O, PD
0 = Battery charging not supported
1 = Battery charging supported
USB Port 1 Over-Current Detection. This pin is typically connected to the over current output
of the downstream port power switch for Port 1.
0 = An over current event has occurred
1 = An over current event has not occurred
OVERCUR1z
46
I, PU
When GANGED power management is enabled, this pin or one of the other OVERCURz pins
must be connected to the over current output of the power switch or circuit which detects the
over current conditions. For the case when another OVERCURz pin is used, this pin can be
left unconnected.
USB_SSTXP_DN2
USB_SSTXM_DN2
USB_SSRXP_DN2
USB_SSRXM_DN2
USB_DP_DN2
11
12
14
15
9
O
O
I
USB SuperSpeed transmitter differential pair (positive)
USB SuperSpeed transmitter differential pair (negative)
USB SuperSpeed receiver differential pair (positive)
USB SuperSpeed receiver differential pair (negative)
USB High-speed differential transceiver (positive)
USB High-speed differential transceiver (negative)
I
I/O
I/O
USB_DM_DN2
10
Copyright © 2017, Texas Instruments Incorporated
5
TUSB8042
ZHCSGM0 –AUGUST 2017
www.ti.com.cn
Pin Functions (continued)
PIN
I/O
DESCRIPTION
NAME
NO.
USB Port 2 Power On Control for Downstream Power/Battery Charging Enable. The pin is
used for control of the downstream power switch for Port 2. This pin be left unconnected if
power management is not implemented.
In addition, the value of the pin is sampled at the de-assertion of reset to determine the value
of the battery charging support for Port 2 as indicated in the Battery Charging Support
register:
PWRCTL2/BATEN2
35
I/O, PD
0 = Battery charging not supported
1 = Battery charging supported
USB Port 2 Over-Current Detection. This pin is typically connected to the over current output
of the downstream port power switch for Port 2.
0 = An over current event has occurred
1 = An over current event has not occurred
OVERCUR2z
47
I, PU
When GANGED power management is enabled, this pin or one of the other OVERCURz pins
must be connected to the over current output of the power switch or circuit which detects the
over current conditions. For the case when another OVERCURz pin is used, this pin can be
left unconnected.
USB_SSTXP_DN3
USB_SSTXM_DN3
USB_SSRXP_DN3
USB_SSRXM_DN3
USB_DP_DN3
19
20
22
23
17
18
O
O
I
USB SuperSpeed transmitter differential pair (positive)
USB SuperSpeed transmitter differential pair (negative)
USB SuperSpeed receiver differential pair (positive)
USB SuperSpeed receiver differential pair (negative)
USB High-speed differential transceiver (positive)
USB High-speed differential transceiver (negative)
I
I/O
I/O
USB_DM_DN3
USB Port 3 Power On Control for Downstream Power/Battery Charging Enable. The pin is
used for control of the downstream power switch for Port 3. This pin be left unconnected if
power management is not implemented.
In addition, the value of the pin is sampled at the de-assertion of reset to determine the value
of the battery charging support for Port 3 as indicated in the Battery Charging Support
register:
PWRCTL3/BATEN3
33
I/O, PD
0 = Battery charging not supported
1 = Battery charging supported
USB Port 3 Over-Current Detection. This pin is typically connected to the over current output
of the downstream port power switch for Port 3.
0 = An over current event has occurred
1 = An over current event has not occurred
OVERCUR3z
44
I, PU
When GANGED power management is enabled, this pin or one of the other OVERCURz pins
must be connected to the over current output of the power switch or circuit which detects the
over current conditions. For the case when another OVERCURz pin is used, this pin can be
left unconnected.
USB_SSTXP_DN4
USB_SSTXM_DN4
USB_SSRXP_DN4
USB_SSRXM_DN4
USB_DP_DN4
26
27
29
30
24
25
O
O
I
USB SuperSpeed transmitter differential pair (positive)
USB SuperSpeed transmitter differential pair (negative)
USB SuperSpeed receiver differential pair (positive)
USB SuperSpeed receiver differential pair (negative)
USB High-speed differential transceiver (positive)
USB High-speed differential transceiver (negative)
I
I/O
I/O
USB_DM_DN4
USB Port 4 Power On Control for Downstream Power/Battery Charging Enable. The pin is
used for control of the downstream power switch for Port 4. This pin be left unconnected if
power management is not implemented.
In addition, the value of the pin is sampled at the de-assertion of reset to determine the value
of the battery charging support for Port 4 as indicated in the Battery Charging Support
register:
PWRCTL4/BATEN4
32
I/O, PD
0 = Battery charging not supported
1 = Battery charging supported
6
Copyright © 2017, Texas Instruments Incorporated
TUSB8042
www.ti.com.cn
ZHCSGM0 –AUGUST 2017
Pin Functions (continued)
PIN
NAME
I/O
DESCRIPTION
NO.
USB Port 4 Over-Current Detection. This pin is typically connected to the over current output
of the downstream port power switch for Port 4.
0 = An over current event has occurred
1 = An over current event has not occurred
OVERCUR4z
43
I, PU
When GANGED power management is enabled, this pin or one of the other OVERCURz pins
must be connected to the over current output of the power switch or circuit which detects the
over current conditions. For the case when another OVERCURz pin is used, this pin can be
left unconnected.
I2C/SMBUS I2C Signals
I2C clock/SMBus clock. Function of pin depends on the setting of the SMBUSz input.
When SMBUSz = 1, this pin acts as the serial clock interface for an I2C EEPROM.
When SMBUSz = 0, this pin acts as the serial clock interface for an SMBus host.
Can be left unconnected if external interface not implemented.
I2C data/SMBus data. Function of pin depends on the setting of the SMBUSz input.
When SMBUSz = 1, this pin acts as the serial data interface for an I2C EEPROM.
When SMBUSz = 0, this pin acts as the serial data interface for an SMBus host.
Can be left unconnected if external interface not implemented.
SCL/SMBCLK
38
37
I/O, PD
I/O, PD
SDA/SMBDAT
I2C/SMBus mode select/SuperSpeed USB Suspend Status. The value of the pin is sampled
at the de-assertion of reset set I2C or SMBus mode as follows:
1 = I2C Mode Selected
0 = SMBus Mode Selected
SMBUSz/SS_SUSPEND
39
I/O, PU
Can be left unconnected if external interface not implemented.
After reset, this signal indicates the SuperSpeed USB Suspend status of the upstream port if
enabled through the stsOutputEn bit in the Additional Feature Configuration register. When
enabled, a value of 1 indicates the connection is suspended.
Test and Miscellaneous Signals
Full power management enable/SMBus address bit 1/SuperSpeed USB Connection Status
Upstream port.
The value of the pin is sampled at the de-assertion of reset to set the power switch control
follows:
0 = Power switching and over current inputs supported
1 = Power switching and over current inputs not supported
Full power management is the ability to control power to the downstream ports of the
TUSB8042 using PWRCTL[4:1]/BATEN[4:1].
If BATENx = 1 on any port, full power management must be enabled so the value of the
terminal is sampled at the de-assertion to initialize the value of the FULLAUTOz bit.
FULLPWRMGMTz /
FULLAUTOz /
SMBA1/SS_UP
40
I/O, PD
When AUTOENz = 0 and FULLAUTOz = 0: all ACP modes are supported.
When AUTOENz = 0 and FULLAUTOz = 1:only highest current ACP mode is used in auto
mode.
When SMBus mode is enabled, this pin sets the value of the SMBus slave address bit 1.
Can be left unconnected if full power management and SMBus are not implemented.
After reset, this signal indicates the SuperSpeed USB connection status of the upstream port
if enabled through the stsOutputEn bit in the Additional Feature Configuration register. When
enabled a value of 1 indicates the upstream port is connected to a SuperSpeed USB capable
port.
Note: Power switching must be supported for battery charging applications.
Power Control Polarity.
The value of the pin is sampled at the de-assertion of reset to set the polarity of
PWRCTL[4:1].
I/O, PU
PWRCTL_POL
41
0 = PWRCTL polarity is active low
1 = PWRCTL polarity is active high
Copyright © 2017, Texas Instruments Incorporated
7
TUSB8042
ZHCSGM0 –AUGUST 2017
www.ti.com.cn
Pin Functions (continued)
PIN
I/O
DESCRIPTION
NAME
NO.
Ganged operation enable/SMBus Address bit 2/HS Connection Status Upstream Port.
The value of the pin is sampled at the de-assertion of reset to set the power switch and over
current detection mode as follows:
0 = Individual power control supported when power switching is enabled
1 = Power control gangs supported when power switching is enabled
GANGED/SMBA2/
HS_UP
When SMBus mode is enabled using SMBUSz, this pin sets the value of the SMBus slave
address bit 2.
42
I/O, PD
After reset, this signal indicates the High-speed USB connection status of the upstream port if
enabled through the stsOutputEn bit in Additional Feature Configuration register. When
enabled, a value of 1 indicates the upstream port is connected to a High-speed USB capable
port.
Note: Individual power control must be enabled for battery charging applications.
Automatic Charge Mode Enable/HS Suspend Status.
The value of the pin is sampled at the de-assertion of reset to determine if automatic mode is
enabled as follows:
0 = Automatic Mode is enabled on ports that are enabled for battery charging when the
hub is unconnected. Please note that CDP is not supported on Port 1 when operating in
Automatic mode.
AUTOENz/
HS_SUSPEND
45
49
I/O, PU
1 = Automatic Mode is disabled
This value is also used to set the autoEnz bit in the Battery Charging Support Register.
After reset, this signal indicates the High-speed USB Suspend status of the upstream port if
enabled through the stsOutputEn bit in Additional Feature Configuration register. When
enabled, a value of 1 indicates the connection is suspended.
This pin is reserved for factory test. It is suggested to have this pin pulled down to ground on
PCB.
TEST
I, PD
Power and Ground Signals
5, 8,
13, 21,
28, 31,
51, 57
VDD
PWR 1.1-V power rail
16, 34,
52, 63
VDD33
PWR 3.3-V power rail
VSS (Thermal Pad)
NC
PWR Ground. Thermal pad must be connected to ground.
60
—
No connect, leave floating
8
Copyright © 2017, Texas Instruments Incorporated
TUSB8042
www.ti.com.cn
ZHCSGM0 –AUGUST 2017
7 Specifications
7.1 Absolute Maximum Ratings(1)
over operating free-air temperature range (unless otherwise noted)
MIN
–0.3
–0.3
MAX
1.4
UNIT
V
VDD Steady-state supply voltage
Supply Voltage Range
VDD33 Steady-state supply voltage
3.8
V
USB_SSRXP_UP, USB_SSRXN_UP, USB_SSRXP_DN[4:1],
USB_SSRXN_DP[4:1] and USB_VBUS terminals
-0.3
1.4
V
Voltage Range
XI terminals
-0.3
-0.3
–65
2.45
3.8
V
V
All other terminals
Storage temperature, Tstg
150
°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
7.2 ESD Ratings
VALUE
±2000
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
V(ESD)
Electrostatic discharge
V
Charged device model (CDM), per JEDEC specification JESD22-
C101(2)
±500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
0.99
3
NOM
1.1
MAX
UNIT
V
VDD(1)
VDD33
USB_VBUS
TA
1.1V supply voltage
1.26
3.6
3.3V supply voltage
3.3
V
Voltage at USB_VBUS PAD
Operating free-air temperature
Operating junction temperature
0
1.155
70
V
TUSB8042
0
°C
°C
TJ
–40
105
(1) A 1.05-V, 1.1-V, or 1.2-V supply may be used as long as minimum and maximum supply conditions are met.
7.4 Thermal Information
TUSB8042
RGC
64 PINS
26
THERMAL METRIC(1)
UNIT
RθJA
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJCtop
RθJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
11.5
5.3
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
0.2
ψJB
5.2
RθJCbot
1.0
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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7.5 Electrical Characteristics, 3.3-V I/O
over operating free-air temperature range (unless otherwise noted)
PARAMETER
OPERATION TEST CONDITIONS
MIN
2
TYP
MAX
UNIT
VIH
VIL
VI
High-level input voltage(1)
Low-level input voltage(1)
Input voltage
VDD33
VDD33
VDD33
0.8
V
V
V
V
0
0
VDD33
VDD33
VO
Output voltage(2)
0
Input transition time (trise and
tt
0
25
ns
V
tfall)
0.13 x
VDD33
Vhys
Input hysteresis(3)
VOH
VOL
High-level output voltage
Low-level output voltage
VDD33
VDD33
IOH = -4 mA
IOL = 4 mA
2.4
V
V
0.4
High-impedance, output
current(2)
IOZ
VDD33
VI = 0 to VDD33
±20
µA
High-impedance, output current
with internal pullup or pulldown
resistor(4)
Input current(5)
IOZP
VDD33
VDD33
VI = 0 to VDD33
VI = 0 to VDD33
±250
µA
II
±15
27.5
25
µA
KΩ
KΩ
RPD
RPU
Internal pull-down resister
Internal pull-up resistor
13.5
14.5
19
19
(1) Applies to external inputs and bidirectional buffers.
(2) Applies to external outputs and bidirectional buffers.
(3) Applies to GRSTz.
(4) Applies to pins with internal pullups/pulldowns.
(5) Applies to external input buffers.
7.6 Timing Requirements, Power-Up
PARAMETER
DESCRIPTION
VDD33 stable before VDD stable(1)
MIN
TYP
MAX
UNIT
ms
ms
µs
(2)
td1
See
td2
VDD and VDD33 stable before de-assertion of GRSTz
Setup for MISC inputs(3) sampled at the de-assertion of GRSTz
Hold for MISC inputs(3) sampled at the de-assertion of GRSTz
VDD33 supply ramp requirements
3
0.1
0.1
0.2
0.2
tsu_io
thd_io
µs
tVDD33_RAMP
tVDD_RAMP
100
100
ms
ms
VDD supply ramp requirements
(1) An active reset is required if the VDD33 supply is stable before the VDD11 supply. This active Reset shall meet the 3ms power-up delay
counting from both power supplies being stable to the de-assertion of GRSTz.
(2) There is no power-on relationship between VDD33 and VDD unless GRSTz is only connected to a capacitor to GND. Then VDD must
be stable minimum of 10 µs before the VDD33.
(3) MISC pins sampled at de-assertion of GRSTz: BATEN[4:1], AUTOENz, FULLPWRMGMTz, GANGED, SMBUSz, and PWRCTL_POL.
t
d2
GRSTz
VDD33
t
d1
VDD
t
t
hd_io
su_io
MISC_IO
Figure 1. Power-Up Timing Requirements
10
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7.7 Hub Input Supply Current
Typical values measured at TA = 25°C
VDD33
3.3 V
VDD
UNIT
1.1 V
PARAMETER
LOW POWER MODES
Power On (after Reset)
3
3
3
30
24
30
mA
mA
mA
Upstream Disconnect
Suspend
ACTIVE MODES (US state / DS State)
3.0 host / 1 SS Device and Hub in U1 / U2
3.0 host / 1 SS Device and Hub in U0
3.0 host / 2 SS Devices and Hub in U1 / U2
3.0 host / 2 SS Devices and Hub in U0
3.0 host / 3 SS Devices and Hub in U1 / U2
3.0 host / 3 SS Devices and Hub in U0
3.0 host / 4 SS Devices and Hub in U1 / U2
3.0 host / 4 SS Devices and Hub in U0
45
45
45
45
45
45
45
45
84
95
45
76
240
356
301
457
372
563
440
672
372
512
55
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
3.0 host / 1 SS Device in U0 and 1 HS Device
3.0 host / 2 SS Devices in U0 and 2 HS Devices
2.0 host / HS Device
2.0 host / 4 HS Devices
74
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8 Detailed Description
8.1 Overview
The TUSB8042 is a four-port USB 3.1 Gen1 compliant hub. It provides simultaneous SuperSpeed USB and high-
speed/full-speed connections on the upstream port and provides SuperSpeed USB, high-speed, full-speed, or
low-speed connections on the downstream ports. When the upstream port is connected to an electrical
environment that only supports high-speed or full-speed/low-speed connections, SuperSpeed USB connectivity is
disabled on the downstream ports. When the upstream port is connected to an electrical environment that only
supports full-speed/low-speed connections, SuperSpeed USB and high-speed connectivity are disabled on the
downstream ports.
8.2 Functional Block Diagram
VDD33
Power
Distribution
VBUS
Detect
VDD
VSS
USB 2.0 Hub
SuperSpeed Hub
XI
Oscilator
XO
Clock
and
Reset
GRSTz
Distribution
TEST
GANGED/SMBA2/HS_UP
FULLPWRMGMTz/SMBA1/SS_UP
PWRCTL_POL
SMBUSz/SS_SUSPEND
AUTOENz/HS_SUSPEND
SCL/SMBCLK
OTP
ROM
Control
Registers
SDA/SMBDAT
GPIO
I2C
OVERCUR1z
PWRCTL1/BATEN1
SMBUS
OVERCUR2z
PWRCTL2/BATEN2
OVERCUR3z
PWRCTL3/BATEN3
OVERCUR4z
PWRCTL4/BATEN4
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8.3 Feature Description
8.3.1 Battery Charging Features
The TUSB8042 provides support for USB Battery Charging (BC1.2) and custom charging. Battery charging
support may be enabled on a per port basis through the REG_6h(batEn[3:0]).
USB Battery charging support includes both Charging Downstream Port (CDP) and Dedicated Charging Port
(DCP) modes. The DCP mode is compliant with the Chinese Telecommunications Industry Standard YD/T 1591-
2009. CDP is enabled when the upstream port has detected valid VBUS, configured, and host sets port power.
When the upstream port is not connected and battery charging support is enabled, the TUSB8042 will enable
DCP mode.
In addition to USB Battery charging (BC1.2), the TUSB8042 supports custom charging indications: Divider
Charging (ACP3, ACP2, ACP1 modes), and Galaxy compatible charging. These custom charging modes are
only supported when upstream port is unconnected and AUTOMODE is enabled. When in AUTOMODE and
upstream port is disconnected, the port will automatically transition from ACP mode to the DCP mode depending
on the portable device connected. The divided mode places a fixed DC voltage on the ports DP and DM signals
which allows some devices to identify the capabilities of the charger. The default divider mode indicates support
for up to 10W (ACP3). The divider mode can be configured to report a lower-current setting (up to 5 W) through
REG_0Ah (HiCurAcpModeEn).
When the upstream port is not connected and battery charging support is enabled for a port, the TUSB8042
drives the port power enable active. If AUTOMODE is disabled, then DCP mode is used. If AUTOMODE is
enabled and FullAutoEn bit is cleared (Reg_25h Bit 0), then TUSB8042 will start with highest enabled divider
current mode (ACPx). The TUSB8042 will remain in highest current mode as long as a pull-up is not detected on
DP pin. If an pull-up is detected on DP pin, then TUSB8042 will drive the port power enable inactive and switch
to Galaxy mode, if enabled, or to DCP mode if Galaxy mode is disabled. The TUSB8042 will again drive the port
power enable active. The TUSB8042 will remain in Galaxy mode as long as no pull-up is detected on DP pin. If
an pull-up is detected on DP pin, then TUSB8042 will drive the port power enable inactive and transition to DCP
mode. The TUSB8042 will again drive the port power enable active. In DCP mode, the TUSB8042 will look for a
pull-up detected on DP pin or RxVdat. If a pull-up or RxVdat is detected on DP, the TUSB8042 will remain in
DCP mode. If no pull-up or RxVdat is detected on DP pin after 2 seconds, the TUSB8042 will drive the port
power enable inactive and transition back to ACPx mode. This sequence will repeat until upstream port is
connected.
When Automatic mode is enabled and full automatic mode (FullAutoEn Reg_25h bit 0) is enabled, TUSB8042
will perform same sequence described in previous paragraph with the addition of attempting all supported ACPx
modes before sequencing to Galaxy Mode (if enabled) or DCP mode.
The supported battery charging modes when TUSB8042 configured for SMBus or external EEPROM is detailed
in Battery Charging Modes with SMBus/EEPROM Table.
The supported battery charging modes when TUSB8042 configured for I2C but without an external EEPROM is
determined by the sampled state of the pins. These modes are detailed in Battery Charging Modes without
EEPROM Table.
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Feature Description (continued)
Table 2. TUSB8042 Battery Charging Modes with SMBus or I2C EEPROM
Battery Charging Mode Port x
(x = n + 1)
0
1
1
Don’t Care
> 4V
Don't Care
Don't Care
Don't Care
Don’t Care
Don't Care
1
Don't Care
Don't Care
Don't Care
Don't Care
Don't Care
Don't Care
No Charging support
CDP
DCP
< 4V
AUTOMODE enabled. Sequences through all ACPx modes and DCP
with the exception of ACP3
1
< 4V
0
0
1
1
Alternate ACP2, ACP1, DCP
AUTOMODE enabled. Sequences through all ACPx modes and DCP.
Alternate ACP3, ACP2, ACP1, DCP
1
1
1
1
1
1
1
< 4V
< 4 V
< 4V
< 4V
< 4V
< 4V
< 4V
1
0
1
0
1
0
1
0
0
0
0
0
0
0
1
0
0
1
1
0
0
1
1
1
0
0
0
0
AUTOMODE enabled. Sequences between ACP2 and DCP.
Alternate ACP2, DCP
AUTOMODE enabled. Sequences between ACP3 and DCP.
Alternate ACP3, DCP
AUTOMODE enabled with Galaxy compatible charging support.
Alternate ACP2, ACP1, Galaxy, DCP.
AUTOMODE enabled with Galaxy compatible charging support.
Alternate ACP3, ACP2, ACP1, Galaxy, DCP
AUTOMODE enabled with Galaxy compatible charging support.
Alternate ACP2, Galaxy, DCP
AUTOMODE enabled with Galaxy compatible charging support.
Alternate ACP3, Galaxy, DCP
Table 3. TUSB8042 Battery Charging Modes without EEPROM
Battery Charging Mode Port x
(x = n + 1)
0
1
1
Don’t Care Don’t Care
Don't Care
Don't Care
0
No Charging support
> 4V
< 4V
Don't Care
1
CDP
DCP
AUTOMODE enabled with Galaxy compatible charging support. Sequences
through all ACPx modes.
1
< 4V
0
0
Alternate ACP3, ACP2, ACP1, Galaxy, DCP.
AUTOMODE enabled with Galaxy compatible charging support.
Alternate ACP3, Galaxy, DCP
1
1
< 4V
< 4V
0
1
1
1
AUTOMODE enabled. Sequences through all ACPx modes.
Alternate ACP3, ACP2, ACP1, DCP.
14
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8.3.2 USB Power Management
The TUSB8042 can be configured for power switched applications using either per-port (Full power managed) or
ganged power-enable controls and over-current status inputs. When battery charge is enabled, the TUSB8042
will always function in full power managed.
Power switch support is enabled by REG_5h (fullPwrMgmtz) and the per-port or ganged mode is configured by
REG_5h(ganged).
The TUSB8042 supports both active high and active low power-enable controls. The PWRCTL[4:1] polarity is
configured by REG_Ah(pwrctlPol).
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8.3.3 One Time Programmable (OTP) Configuration
The TUSB8042 allows device configuration through one time programmable non-volatile memory (OTP). The
programming of the OTP is supported using vendor-defined USB device requests. For details using the OTP
features please contact your TI representative.
Table 4 provides a list features which may be configured using the OTP.
Table 4. OTP Configurable Features
CONFIGURATION REGISTER
BIT FIELD
DESCRIPTION
OFFSET
REG_01h
REG_02h
REG_03h
REG_04h
[7:0]
[7:0]
[7:0]
[7:0]
Vendor ID LSB
Vendor ID MSB
Product ID LSB
Product ID MSB
Port removable configuration for downstream ports 1. OTP
configuration is inverse of rmbl[3:0], i.e. 1 = not removable, 0 =
removable.
REG_07h
REG_07h
REG_07h
REG_07h
[0]
[1]
[2]
[3]
Port removable configuration for downstream ports 2. OTP
configuration is inverse of rmbl[3:0], i.e. 1 = not removable, 0 =
removable.
Port removable configuration for downstream ports 3. OTP
configuration is inverse of rmbl[3:0], i.e. 1 = not removable, 0 =
removable.
Port removable configuration for downstream ports 4. OTP
configuration is inverse of rmbl[3:0], i.e. 1 = not removable, 0 =
removable.
REG_08h
REG_0Ah
REG_0Ah
REG_0Bh
REG_0Bh
REG_0Bh
REG_0Bh
REG_25h
REG_26h
REG_F0h
[3:0]
[3]
Port used Configured register.
Enable Device Attach Detection..
[4]
High-current divider mode enable.
[0]
USB 2.0 port polarity configuration for downstream ports 1.
USB 2.0 port polarity configuration for downstream ports 2.
USB 2.0 port polarity configuration for downstream ports 3.
USB 2.0 port polarity configuration for downstream ports 4.
Device Configuration Register 3
[1]
[2]
[3]
[4:0]
[3:0]
[3:1]
USB2.0 Only Port Register
USB power switch power-on delay.
16
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8.3.4 Clock Generation
The TUSB8042 accepts a crystal input to drive an internal oscillator or an external clock source. If a clock is
provided to XI instead of a crystal, XO is left open. Otherwise, if a crystal is used, the connection needs to follow
the guidelines below. Since XI and XO are coupled to other leads and supplies on the PCB, it is important to
keep them as short as possible and away from any switching leads. It is also recommended to minimize the
capacitance between XI and XO. This can be accomplished by shielding C1 and C2 with the clean ground lines.
R1
1M
Y1
XI
24 MHz
CLOCK
XO
CL1
CL2
Copyright © 2016, Texas Instruments Incorporated
Figure 2. TUSB8042 Clock
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8.3.5 Crystal Requirements
The crystal must be fundamental mode with load capacitance of 12 pF - 24 pF and frequency stability rating of
±100 PPM or better. To ensure proper startup oscillation condition, a maximum crystal equivalent series
resistance (ESR) of 50 Ω is recommended. A parallel load capacitor should be used if a crystal source is used.
The exact load capacitance value used depends on the crystal vendor. Refer to application note Selection and
Specification for Crystals for Texas Instruments USB2.0 devices (SLLA122) for details on how to determine the
load capacitance value.
8.3.6 Input Clock Requirements
When using an external clock source such as an oscillator, the reference clock should have a ±100 PPM or
better frequency stability and have less than 50-ps absolute peak to peak jitter or less than 25-ps peak to peak
jitter after applying the USB 3.1 jitter transfer function. XI should be tied to the 1.8-V clock source and XO should
be left floating.
8.3.7 Power-Up and Reset
The TUSB8042 does not have specific power sequencing requirements with respect to the core power (VDD) or
I/O and analog power (VDD33) as long as GRSTz is held in an asserted state while supplies ramp. The core
power (VDD) or I/O power (VDD33) may be powered up for an indefinite period of time while the other is not
powered up if all of these constraints are met:
•
•
All maximum ratings and recommended operating conditions are observed.
All warnings about exposure to maximum rated and recommended conditions are observed, particularly
junction temperature. These apply to power transitions as well as normal operation.
•
•
Bus contention while VDD33 is powered up must be limited to 100 hours over the projected life-time of the
device.
Bus contention while VDD33 is powered down may violate the absolute maximum ratings.
A supply bus is powered up when the voltage is within the recommended operating range. It is powered down
when it is below that range, either stable or in transition.
A minimum reset duration of 3 ms is required. This is defined as the time when the power supplies are in the
recommended operating range to the de-assertion of GRSTz. This can be generated using programmable-delay
supervisory device or using an RC circuit. When a RC circuit is used, the external capacitor size chosen must be
large enough to meet the 3ms minimum duration requirement. The R of the RC circuit is the internal RPU
.
18
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8.4 Device Functional Modes
8.4.1 External Configuration Interface
The TUSB8042 supports a serial interface for configuration register access. The device may be configured by an
attached I2C EEPROM or accessed as a slave by an external SMBus master. The external interface is enabled
when both the SCL/SMBCLK and SDA/SMBDAT pins are pulled up to 3.3 V at the de-assertion of reset. The
mode, I2C master or SMBus slave, is determined by the state of SMBUSz/SS_SUSPEND pin at reset.
8.4.2 I2C EEPROM Operation
The TUSB8042 supports a single-master, fast mode (400KHz) connection to a dedicated I2C EEPROM when the
I2C interface mode is enabled. In I2C mode, the TUSB8042 reads the contents of the EEPROM at bus address
1010000b using 7-bit addressing starting at address 0. The TUSB8042 will read the entire EEPROM contents
using a single burst read transaction. The burst read transaction will end when the address reaches FFh.
If the value of the EEPROM contents at address byte 00h equals 55h, the TUSB8042 loads the configuration
registers according to the EEPROM map. If the first byte is not 55h, the TUSB8042 exits the I2C mode and
continues execution with the default values in the configuration registers. The hub will not connect on the
upstream port until the configuration is completed.
NOTE
The bytes located above offset Ah are optional. The requirement for data in those
addresses is dependent on the options configured in the Device Configuration, and Device
Configuration 2 registers.
The minimum size I2C EEPROM required is 2Kbit.
For details on I2C operation refer to the UM10204 I2C-bus Specification and User Manual.
8.4.3 Port Configuration
The TUSB8042 port configurations can be selected by registers or efuse. The Port Used Configuration register
(USED[3:0]) define how many ports can possibly be reported by the hub. The device removable configuration
register (RMBL[3:0]) define if the ports that are reported as used have permanently connected devices or not.
The USB 2.0 Only Port register (USB2_ONLY[3:0]) define whether or a used port is reported as part of the USB
2.0 hub or both the USB2.0 and USB3.1 hubs. The USB2_ONLY field will enable the USB2.0 port even if the
corresponding USED bit is low. The table below shows examples of the possible combinations.
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Device Functional Modes (continued)
Table 5. TUSB8042 Downstream Port Configuration Examples
USB2_ONLY
[3:0]
USED[3:0]
RMBL[3:0]
Reported Port Configuration
Physical to Logical Port mapping
Physical1 => Logical Port1 for USB3.1 and USB2.0.
Physical2 => Logical Port2 for USB3.1 and USB2.0.
Physical3 => Logical Port3 for USB3.1 and USB2.0.
Physical4 => Logical Port4 for USB3.1 and USB2.0.
4 Port USB3.1 Hub
4 Port USB2.0 Hub
1111
1111
0000
0000
0000
0010
0010
1110
Physical1 Not used.
3 Port USB3.1 Hub
Port USB2.0 Hub
Physical2 => Logical Port1 for USB3.1 and USB2.0.
Physical3 => Logical Port2 for USB3.1 and USB2.0.
Physical4 => Logical Port3 for USB3.1 and USB2.0.
1110
1100
0011
1000
1111
1111
0111
1111
1111
1111
Physical1 Not used.
2 Port USB 3.1 Hub
2 Port USB2.0 hub with permanently attached
device on Port 2
Physical2 Not used.
Physical3 => Logical Port1 for USB3.1 and USB2.0.
Physical4 => Logical Port2 for USB3.1 and USB2.0.
Physical1 => Logical Port1 for USB3.1 and USB2.0.
Physical2 => Logical Port2 for USB2.0.
Physical3 Not Used.
1 Port USB 3.1 Hub
2 Port USB 2.0 Hub
Physical4 Not used.
Physical1 Not used.
1 Port USB 3.1 Hub
2 Port USB 2.0 Hub
Physical2 => Logical Port2 for USB2.0.
Physical3 Not used
Physical4 => Logical Port1 for USB3.1 and USB2.0.
Physical1 => Logical Port1 for USB3.1 and USB2.0.
Physical2 => Logical Port2 for USB2.0.
Physical3 => Logical Port3 for USB2.0.
Physical4 => Logical Port4 for USB2.0.
1 Port USB 3.1 Hub
4 Port USB 2.0 Hub
Invalid combination when USB2_ONLY =
0000, 0001, 0100, or 0101. If invalid
combination is used, then physical port 4 will
not operate at USB3.1 Gen 1 speeds.
1010
1011
1110
1111
N/A
N/A
N/A
N/A
0x0x
0x01
010x
0101
Invalid combination when USB2_ONLY =
0001 or 0101. If invalid combination is used,
then physical port 4 will not operate at USB3.1
Gen 1 speeds.
Invalid combination when USB2_ONLY =
0100 or 0101. If invalid combination is used,
then physical port 4 will not operate at USB3.1
Gen 1 speeds.
Invalid combination when USB2_ONLY =
0101. If invalid combination is used, then
physical port 4 will not operate at USB3.1 Gen
1 speeds.
20
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8.4.4 SMBus Slave Operation
When the SMBus interface mode is enabled, the TUSB8042 supports read block and write block protocols as a
slave-only SMBus device.
The TUSB8042 slave address is 1000 1xyz, where:
•
•
•
x is the state of GANGED/SMBA2/HS_UP pin at reset,
y is the state of FULLPWRMGMTz/SMBA1/SS_UP pin at reset, and
z is the read/write bit; 1 = read access, 0 = write access.
If the TUSB8042 is addressed by a host using an unsupported protocol it will not respond. The TUSB8042 waits
indefinitely for configuration by the SMBus host and will not connect on the upstream port until the SMBus host
indicates configuration is complete by clearing the CFG_ACTIVE bit.
For details on SMBus requirements, refer to the System Management Bus Specification.
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8.5 Register Maps
8.5.1 Configuration Registers
The internal configuration registers are accessed on byte boundaries. The configuration register values are
loaded with defaults but can be over-written when the TUSB8042 is in I2C or SMBus mode.
Table 6. TUSB8042 Register Map
BYTE
ADDRESS
CONTENTS
EEPROM CONFIGURABLE
00h
ROM Signature Register
Vendor ID LSB
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
01h
02h
Vendor ID MSB
03h
Product ID LSB
04h
Product ID MSB
05h
Device Configuration Register
Battery Charging Support Register
Device Removable Configuration Register
Port Used Configuration Register
Reserved. Must default to 00h.
Device Configuration Register 2
USB 2.0 Port Polarity Control Register
Reserved
06h
07h
08h
09h
0Ah
0Bh
0Ch-0Fh
10h-1Fh
20h-21h
22h
UUID Byte [15:0]
No
LangID Byte [1:0]
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
Serial Number Length
Manufacturer String Length
Product String Length
Device Configuration Register 3
USB 2.0 Only Port Register
Reserved
23h
24h
25h
26h
27h-2Eh
2Fh
Reserved
30h-4Fh
50h-8Fh
90h-CFh
D0h-D4h
D5h-D7h
D8h-DCh
DDh-EFh
F0h
Serial Number String Byte [31:0]
Manufacturer String Byte [63:0]
Product String Byte [63:0]
Reserved
Yes
Yes
Yes
Yes(1)
No
Reserved
Reserved
Yes(1)
Reserved
No
Additional Features Configuration Register
Reserved
Yes
No
F1h-F7h
F8h
SMBus Device Status and Command Register
Reserved
No
F9h - FFh
No
22
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8.5.2 ROM Signature Register
Figure 3. Register Offset 0h
Bit No.
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
Reset State
Table 7. Bit Descriptions – ROM Signature Register
Bit
Field
Type
Description
ROM Signature Register. This register is used by the TUSB8042 in I2C
mode to validate the attached EEPROM has been programmed. The
first byte of the EEPROM is compared to the mask 55h and if not a
match, the TUSB8042 aborts the EEPROM load and executes with the
register defaults.
7:0
romSignature
RW
8.5.3 Vendor ID LSB Register
Figure 4. Register Offset 1h
Bit No.
7
0
6
1
5
0
4
1
3
0
2
0
1
0
0
1
Reset State
Table 8. Bit Descriptions – Vendor ID LSB Register
Bit
Field
Type
Description
Vendor ID LSB. Least significant byte of the unique vendor ID
assigned by the USB-IF; the default value of this register is 51h
representing the LSB of the TI Vendor ID 0451h. The value may be
over-written to indicate a customer Vendor ID.
7:0
vendorIdLsb
RO/RW
Value used for this field will be the non-zero value written by
EEPROM/SMBus to both PID and VID. If a zero value is written by
EEPROM/SMbus to both PID and VID, then value used for this field
will be the non-zero value from OTP. If a zero value is written by OTP,
then value used for this field will be 51h.
8.5.4 Vendor ID MSB Register
Figure 5. Register Offset 2h
Bit No.
7
0
6
0
5
0
4
0
3
0
2
1
1
0
0
0
Reset State
Table 9. Bit Descriptions – Vendor ID MSB Register
Bit
Field
Type
Description
Vendor ID MSB. Most significant byte of the unique vendor ID
assigned by the USB-IF; the default value of this register is 04h
representing the MSB of the TI Vendor ID 0451h. The value may be
over-written to indicate a customer Vendor ID.
7:0
vendorIdMsb
RO/RW
Value used for this field will be the non-zero value written by
EEPROM/SMBus to both PID and VID. If a zero value is written by
EEPROM/SMbus to both PID and VID, then value used for this field
will be the non-zero value from OTP. If a zero value is written by OTP,
then value used for this field will be 04h.
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8.5.5 Product ID LSB Register
Figure 6. Register Offset 3h
Bit No.
7
0
6
1
5
0
4
0
3
0
2
0
1
0
0
0
Reset State
Table 10. Bit Descriptions – Product ID LSB Register
Bit
Field
Type
Description
Product ID LSB. Least significant byte of the product ID assigned by
Texas Instruments and reported in the SuperSpeed Device descriptor.
the default value of this register is 40h representing the LSB of the
SuperSpeed product ID assigned by Texas Instruments The value
reported in the USB 2.0 Device descriptor is the value of this register
bit wise XORed with 00000010b. The value may be over-written to
indicate a customer product ID.
7:0
productIdLsb
RO/RW
Value used for this field will be the non-zero value written by
EEPROM/SMBus to both PID and VID. If a zero value is written by
EEPROM/SMbus to both PID and VID, then value used for this field
will be the non-zero value from OTP. If a zero value is written by OTP,
then value used for this field will be 40h .
8.5.6 Product ID MSB Register
Figure 7. Register Offset 4h
Bit No.
7
1
6
0
5
0
4
0
3
0
2
0
1
1
0
0
Reset State
Table 11. Bit Descriptions – Product ID MSB Register
Bit
Field
Type
Description
Product ID MSB. Most significant byte of the product ID assigned by
Texas Instruments; the default value of this register is 82h representing
the MSB of the product ID assigned by Texas Instruments. The value
may be over-written to indicate a customer product ID.
7:0
productIdMsb
RO/RW
Value used for this field will be the non-zero value written by
EEPROM/SMBus to both PID and VID. If a zero value is written by
EEPROM/SMbus to both PID and VID, then value used for this field
will be the non-zero value from OTP. If a zero value is written by OTP,
then value used for this field will be 82h.
24
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8.5.7 Device Configuration Register
Figure 8. Register Offset 5h
Bit No.
7
0
6
0
5
0
4
1
3
2
1
0
0
0
Reset State
X
X
Table 12. Bit Descriptions – Device Configuration Register
Bit
Field
Type
Description
Custom strings enable. This bit controls the ability to write to the
Manufacturer String Length, Manufacturer String, Product String
Length, Product String, and Language ID registers
0 = The Manufacturer String Length, Manufacturer String, Product
String Length, Product String, and Language ID registers are read only
1 = The Manufacturer String Length, Manufacturer String, Product
String Length, Product String, and Language ID registers may be
loaded by EEPROM or written by SMBus
7
customStrings
customSernum
RW
The default value of this bit is 0.
Custom serial number enable. This bit controls the ability to write to the
serial number registers.
0 = The Serial Number String Length and Serial Number String
registers are read only
6
RW
1 = Serial Number String Length and Serial Number String registers
may be loaded by EEPROM or written by SMBus
The default value of this bit is 0.
U1 U2 Disable. This bit controls the U1/U2 support.
0 = U1/U2 support is enabled
1 = U1/U2 support is disabled, the TUSB8042 will not initiate or accept
any U1 or U2 requests on any port, upstream or downstream, unless it
receives or sends a Force_LinkPM_Accept LMP. After receiving or
sending an FLPMA LMP, it will continue to enable U1 and U2
according to USB 3.1 protocol until it gets a power-on reset or is
disconnected on its upstream port.
5
u1u2Disable
RW
When the TUSB8042 is in I2C mode, the TUSB8042 loads this bit from
the contents of the EEPROM.
When the TUSB8042 is in SMBUS mode, the value may be over-
written by an SMBus host.
4
3
RSVD
RO
Reserved. This bit is reserved and returns 1 when read.
Ganged. This bit is loaded at the de-assertion of reset with the value of
the GANGED/SMBA2/HS_UP pin.
0 = When fullPwrMgmtz = 0, each port is individually power switched
and enabled by the PWRCTL[4:1]/BATEN[4:1] pins
1 = When fullPwrMgmtz = 0, the power switch control for all ports is
ganged and enabled by the PWRCTL[4:1]/BATEN1 pin
When the TUSB8042 is in I2C mode, the TUSB8042 loads this bit from
the contents of the EEPROM.
ganged
RW
When the TUSB8042 is in SMBUS mode, the value may be over-
written by an SMBus host.
Full Power Management. This bit is loaded at the de-assertion of reset
with the value of the FULLPWRMGMTz/SMBA1/SS_UP pin.
0 = Port power switching status reporting is enabled
1 = Port power switching status reporting is disabled
When the TUSB8042 is in I2C mode, the TUSB8042 loads this bit from
the contents of the EEPROM.
2
fullPwrMgmtz
RW
When the TUSB8042 is in SMBUS mode, the value may be over-
written by an SMBus host.
U1 U2 Timer Override. When this field is set, the TUSB8042 will
override the downstream ports U1/U2 timeout values set by USB3.1
Host software. If software sets value in the range of 1h - FFh, the
TUSB8042 will use the value of FFh. If software sets value to 0, then
TUSB8042 will use value of 0.
1
0
u1u2TimerOvr
RSVD
RW
RO
Reserved. This field is reserved and returns 0 when read.
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8.5.8 Battery Charging Support Register
Figure 9. Register Offset 6h
Bit No.
7
0
6
0
5
0
4
0
3
2
1
0
Reset State
X
X
X
X
Table 13. Bit Descriptions – Battery Charging Support Register
Bit
Field
Type
Description
7:4
RSVD
RO
Reserved. Read only, returns 0 when read.
Battery Charger Support. The bits in this field indicate whether the
downstream port implements the charging port features.
0 = The port is not enabled for battery charging support features
1 = The port is enabled for battery charging support features
Each bit corresponds directly to a downstream port, i.e. batEn0
corresponds to downstream port 1, and batEN1 corresponds to
downstream port 2.
3:0
batEn[3:0]
RW
The default value for these bits are loaded at the de-assertion of reset
with the value of PWRCTL/BATEN[3:0].
When in I2C/SMBus mode the bits in this field may be over-written by
EEPROM contents or by an SMBus host.
8.5.9 Device Removable Configuration Register
Figure 10. Register Offset 7h
Bit No.
7
0
6
0
5
4
3
2
1
0
Reset State
0
0
X
X
X
X
Table 14. Bit Descriptions – Device Removable Configuration Register
Bit
7
Field
Type
Description
Custom Removable. This bit controls the ability to write to the port
removable bits, port used bits, and USB2_ONLY bits.
0 = rmbl[3:0], used[3:0], and USB2_ONLY[3:0] are read only and the
values are loaded from the OTP ROM
1 = rmbl[3:0], used[3:0], and USB2_ONLY[3:0] are read/write and can
be loaded by EEPROM or written by SMBus
customRmbl
RSVD
RW
This bit may be written simultaneously with rmbl[3:0].
6:4
RO
Reserved. Read only, returns 0 when read.
Removable. The bits in this field indicate whether a device attached to
downstream ports 4 through 1 are removable or permanently attached.
0 = The device attached to the port is not removable
1 = The device attached to the port is removable
Each bit corresponds directly to a downstream port n + 1, i.e. rmbl0
corresponds to downstream port 1, rmbl1 corresponds to downstream
port 2, etc.
3:0
rmbl[3:0]
RO/RW
This field is read only unless the customRmbl bit is set to 1. Otherwise
the value of this filed reflects the inverted values of the OTP ROM
non_rmb[3:0] field.
8.5.10 Port Used Configuration Register
Figure 11. Register Offset 8h
Bit No.
7
0
6
0
5
0
4
0
3
1
2
1
1
1
0
1
Reset State
26
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Table 15. Bit Descriptions – Port Used Configuration Register
Bit
Field
Type
Description
7:4
RSVD
RO
Reserved. Read only.
Used. The bits in this field indicate whether a port is enabled.
0 = The port is not used or disabled
1 = The port is used or enabled
Each bit corresponds directly to a downstream port, i.e. used0
corresponds to downstream port 1, used1 corresponds to downstream
port 2, etc. All combinations are supported with the exception of both
ports 1 and 3 marked as disabled. This field is read only unless the
customRmbl bit is set to 1. When the corresponding USB2_ONLY bit is
set, the USB2 port will be used and enabled regardless of the bit
programmed into this field.
3:0
used[3:0]
RO/RW
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8.5.11 Device Configuration Register 2
Figure 12. Register Offset Ah
Bit No.
7
0
6
0
5
4
1
3
0
2
0
1
0
0
0
Reset State
X
Table 16. Bit Descriptions – Device Configuration Register 2
Bit
Field
Type
Description
7
Reserved
RO
Reserved. Read-only, returns 0 when read.
Custom Battery Charging Feature Enable. This bit controls the ability
to write to the battery charging feature configuration controls.
0 = The HiCurAcpModeEn is read only and the values are loaded from
the OTP ROM.
1 = The HiCurAcpModeEn bit is read/write and can be loaded by
EEPROM or written by SMBus.
6
5
customBCfeatures
RW
RW
This bit may be written simultaneously with HiCurAcpModeEn.
Power enable polarity. This bit is loaded at the de-assertion of reset
with the value of the PWRCTL_POL pin.
0 = PWRCTL polarity is active low
1 = PWRCTL polarity is active high
pwrctlPol
When the TUSB8042 is in I2C mode, the TUSB8042 loads this bit from
the contents of the EEPROM.
When the TUSB8042 is in SMBUS mode, the value may be over-
written by an SMBus host.
High-current ACP mode enable. This bit enables the high-current tablet
charging mode when the automatic battery charging mode is enabled
for downstream ports.
0 = High current divider mode disabled . High current is ACP2 (default)
1 = High current divider mode enabled. High current mode is ACP3
This bit is read only unless the customBCfeatures bit is set to 1. If
customBCfeatures is 0, the value of this bit reflects the value of the
OTP ROM HiCurAcpModeEn bit.
4
HiCurAcpModeEn
Reserved
RO/RW
RW
3:2
Reserved
Automatic Mode Enable. This bit is loaded at the de-assertion of reset
with the value of the AUTOENz/HS_SUSPEND pin.
The automatic mode only applies to downstream ports with battery
charging enabled when the upstream port is not connected. Under
these conditions:
1
0
autoModeEnz
RW
RO
0 = Automatic mode battery charging features are enabled.
1 = Automatic mode is disabled; only Battery Charging DCP and CDP
mode is supported.
NOTE: When the upstream port is connected, Battery Charging CDP
mode will be supported on all ports that are enabled for battery
charging support regardless of the value of this bit.
RSVD
Reserved. Read only, returns 0 when read.
28
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8.5.12 USB 2.0 Port Polarity Control Register
Figure 13. Register Offset Bh
Bit No.
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
Reset State
Table 17. Bit Descriptions – USB 2.0 Port Polarity Control Register
Bit
7
Field
Type
Description
Custom USB 2.0 Polarity. This bit controls the ability to write the
p[4:0]_usb2pol bits.
0 = The p[4:0]_usb2pol bits are read only and the values are loaded
from the OTP ROM.
1 = The p[4:0]_usb2pol bits are read/write and can be loaded by
EEPROM or written by SMBus.
This bit may be written simultaneously with the p[4:0]_usb2pol bits
customPolarity
RSVD
RW
6:5
RO
Reserved. Read only, returns 0 when read.
Downstream Port 4 DM/DP Polarity. This controls the polarity of the
port.
0 = USB 2.0 port polarity is as documented by the pin out
1 = USB 2.0 port polarity is swapped from that documented in the pin
out, i.e. DM becomes DP, and DP becomes DM.
This bit is read only unless the customPolarity bit is set to 1. If
customPolarity is 0 the value of this bit reflects the value of the OTP
ROM p4_usb2pol bit.
4
3
2
p4_usb2pol
p3_usb2pol
p2_usb2pol
RO/RW
RO/RW
RO/RW
Downstream Port 3 DM/DP Polarity. This controls the polarity of the
port.
0 = USB 2.0 port polarity is as documented by the pin out
1 = USB 2.0 port polarity is swapped from that documented in the pin
out, i.e. DM becomes DP, and DP becomes DM.
This bit is read only unless the customPolarity bit is set to 1. If
customPolarity is 0 the value of this bit reflects the value of the OTP
ROM p3_usb2pol bit.
Downstream Port 2 DM/DP Polarity. This controls the polarity of the
port.
0 = USB 2.0 port polarity is as documented by the pin out
1 = USB 2.0 port polarity is swapped from that documented in the pin
out, i.e. DM becomes DP, and DP becomes DM.
This bit is read only unless the customPolarity bit is set to 1. If
customPolarity is 0 the value of this bit reflects the value of the OTP
ROM p2_usb2pol bit.
Downstream Port 1 DM/DP Polarity. This controls the polarity of the
port.
0 = USB 2.0 port polarity is as documented by the pin out
1 = USB 2.0 port polarity is swapped from that documented in the pin
out, i.e. DM becomes DP, and DP becomes DM.
This bit is read only unless the customPolarity bit is set to 1. If
customPolarity is 0 the value of this bit reflects the value of the OTP
ROM p1_usb2pol bit.
1
0
p1_usb2pol
p0_usb2pol
RORW
RO/RW
Upstream Port DM/DP Polarity. This controls the polarity of the port.
0 = USB 2.0 port polarity is as documented by the pin out
1 = USB 2.0 port polarity is swapped from that documented in the pin
out, i.e. DM becomes DP, and DP becomes DM.
This bit is read only unless the customPolarity bit is set to 1. If
customPolarity is 0 the value of this bit reflects the value of the OTP
ROM p0_usb2pol bit.
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8.5.13 UUID Registers
Figure 14. Register Offset 10h-1Fh
Bit No.
7
6
5
4
3
2
1
0
Reset State
X
X
X
X
X
X
X
X
Table 18. Bit Descriptions – UUID Byte N Register
Bit
Field
Type
Description
UUID byte N. The UUID returned in the Container ID descriptor. The
value of this register is provided by the device and is meets the UUID
requirements of Internet Engineering Task Force (IETF) RFC 4122 A
UUID URN Namespace.
7:0
uuidByte[n]
RO
8.5.14 Language ID LSB Register
Figure 15. Register Offset 20h
Bit No.
7
0
6
0
5
0
4
0
3
1
2
0
1
0
0
1
Reset State
Table 19. Bit Descriptions – Language ID LSB Register
Bit
Field
Type
Description
Language ID least significant byte. This register contains the value
returned in the LSB of the LANGID code in string index 0. The
TUSB8042 only supports one language ID. The default value of this
register is 09h representing the LSB of the LangID 0409h indicating
English United States.
7:0
langIdLsb
RO/RW
When customStrings is 1, this field may be over-written by the contents
of an attached EEPROM or by an SMBus host.
8.5.15 Language ID MSB Register
Figure 16. Register Offset 21h
Bit No.
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
Reset State
Table 20. Bit Descriptions – Language ID MSB Register
Bit
Field
Type
Description
Language ID most significant byte. This register contains the value
returned in the MSB of the LANGID code in string index 0. The
TUSB8042 only supports one language ID. The default value of this
register is 04h representing the MSB of the LangID 0409h indicating
English United States.
7:0
langIdMsb
RO/RW
When customStrings is 1, this field may be over-written by the contents
of an attached EEPROM or by an SMBus host.
30
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8.5.16 Serial Number String Length Register
Figure 17. Register Offset 22h
Bit No.
7
0
6
0
5
0
4
1
3
1
2
0
1
0
0
0
Reset State
Table 21. Bit Descriptions – Serial Number String Length Register
Bit
Field
Type
Description
7:6
RSVD
RO
Reserved. Read only, returns 0 when read.
Serial number string length. The string length in bytes for the serial
number string. The default value is 18h indicating that a 24 byte serial
number string is supported. The maximum string length is 32 bytes.
When customSernum is 1, this field may be over-written by the
contents of an attached EEPROM or by an SMBus host.
When the field is non-zero, a serial number string of
5:0
serNumStringLen
RO/RW
serNumbStringLen bytes is returned at string index 1 from the data
contained in the Serial Number String registers.
8.5.17 Manufacturer String Length Register
Figure 18. Register Offset 23h
Bit No.
7
0
6
0
5
4
3
2
0
1
0
0
0
Reset State
0
0
0
Table 22. Bit Descriptions – Manufacturer String Length Register
Bit
Field
Type
Description
7
RSVD
RO
Reserved. Read only, returns 0 when read.
Manufacturer string length. The string length in bytes for the
manufacturer string. The default value is 0, indicating that a
manufacturer string is not provided. The maximum string length is 64
bytes.
6:0
mfgStringLen
RO/RW
When customStrings is 1, this field may be over-written by the contents
of an attached EEPROM or by an SMBus host.
When the field is non-zero, a manufacturer string of mfgStringLen
bytes is returned at string index 3 from the data contained in the
Manufacturer String registers.
8.5.18 Product String Length Register
Figure 19. Register Offset 24h
Bit No.
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
Reset State
Table 23. Bit Descriptions – Product String Length Register
Bit
Field
Type
Description
7
RSVD
RO
Reserved. Read only, returns 0 when read.
Product string length. The string length in bytes for the product string.
The default value is 0, indicating that a product string is not provided.
The maximum string length is 64 bytes.
When customStrings is 1, this field may be over-written by the contents
of an attached EEPROM or by an SMBus host.
6:0
prodStringLen
RO/RW
When the field is non-zero, a product string of prodStringLen bytes is
returned at string index 3 from the data contained in the Product String
registers.
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8.5.19 Device Configuration Register 3
Figure 20. Register Offset 25h
Bit No.
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
Reset State
Table 24. Bit Descriptions – Device Configuration Register 3
Bit
Field
Type
Description
7:5
RSVD
RO
Reserved. Read only, returns 0 when read.
USB 2.0 hub reports as 2.0 only. This bit disables the USB 2.0 hub
from reporting 5Gbps support in the wSpeedsSupported field of the
USB SS BOS SS device capability descriptor. This bit will also disable
the USB3.0 hub.
4
USB2.0_only
RW
This bit is read/write but the read value returned is the Boolean OR of
this bit and the corresponding eFuse bit. If either bit is set, this feature
is enabled.
3
2
Reserved
I2C_100k
RO
Switch to reserved
I2C 100kHz. This bit controls the clock rate of the I2C master for both
USB to I2C requests . The EEPROM reads will occur at 400K unless
eFuse is used to set the rate to 100k.
This bit is read/write but the read value returned is the Boolean OR of
this bit and the corresponding eFuse bit. If either bit is set, this feature
is enabled.
R/W
Disable Galaxy compatible modes. When this field is high, Galaxy
charging compatible mode will not be included in AUTOMODE charger
sequence.
This bit is read/write but the read value returned is the Boolean OR of
this bit and the corresponding eFuse bit. If either bit is set, this feature
is disabled.
1
0
Galaxy_Enz
FullAutoEn
R/W
R/W
Enable all divider battery charging modes. When automode is enabled
and this bit is set, any DS port enabled for battery charging will attempt
all divider battery charging modes before DCP, starting with the
highest current option.
The bit is writable, but the value read back is the Boolean OR of this
bit and the corresponding eFuse control.
If either bit is set, eFuse or this register, this feature is enabled.
8.5.20 USB 2.0 Only Port Register
Figure 21. Register Offset 26h
Bit No.
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
Reset State
Table 25. Bit Descriptions – USB 2.0 Only Port Register
Bit
Field
Type
Description
7:4
RSVD
RO
Reserved. Read only, returns 0 when read.
USB 2.0 Only Ports. The bits in this field primarily indicate whether a
port is enabled only for USB 2.0 operation. This field is read-only
unless customRmbl bit is set. Also, these bits will override the
corresponding USED bit.
A value of 0 indicates the hub port is enabled for both USB 3.1 and
USB 2.0.
3:0
USB2_ONLY[3:0]
RO/RW
A value of 1 indicates the hub port is enabled only for USB 2.0
operation.
8.5.21 Serial Number String Registers
32
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Figure 22. Register Offset 30h-4Fh
Bit No.
7
6
5
x
4
x
3
x
2
x
1
x
0
x
Reset State
X
X
Table 26. Bit Descriptions – Serial Number Registers
Bit
Field
Type
Description
Serial Number byte N. The serial number returned in the Serial
Number string descriptor at string index 1. The default value of these
registers is assigned by TI. When customSernum is 1, these registers
may be over-written by EEPROM contents or by an SMBus host.
7:0
serialNumber[n]
RO/RW
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8.5.22 Manufacturer String Registers
Figure 23. Register Offset 50h-8Fh
Bit No.
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
Reset State
Table 27. Bit Descriptions – Manufacturer String Registers
Bit
Field
Type
Description
Manufacturer string byte N. These registers provide the string values
returned for string index 3 when mfgStringLen is greater than 0. The
number of bytes returned in the string is equal to mfgStringLen.
The programmed data should be in UNICODE UTF-16LE encodings
as defined by The Unicode Standard, Worldwide Character Encoding,
Version 5.0.
7:0
mfgStringByte[n]
RW
8.5.23 Product String Registers
Figure 24. Register Offset 90h-CFh
Bit No.
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
Reset State
Table 28. Bit Descriptions – Product String Byte N Register
Bit
Field
Type
Description
Product string byte N. These registers provide the string values
returned for string index 2 when prodStringLen is greater than 0. The
number of bytes returned in the string is equal to prodStringLen.
The programmed data should be in UNICODE UTF-16LE encodings
as defined by The Unicode Standard, Worldwide Character Encoding,
Version 5.0.
7:0
prodStringByte[n]
RO/RW
34
Copyright © 2017, Texas Instruments Incorporated
TUSB8042
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ZHCSGM0 –AUGUST 2017
8.5.24 Additional Feature Configuration Register
Figure 25. Register Offset F0h
Bit No.
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
Reset State
Table 29. Bit Descriptions – Additional Feature Configuration Register
Bit
Field
Type
Description
7:5
Reserved
RW
Reserved. This field defaults to 3'b000 and must not be changed.
Status output enable. This field when set enables of the Status output
signals, HS_UP, HS_SUSPEND, SS_UP, SS_SUSPEND.
0 = STS outputs are disabled.
1 = STS outputs are enabled.
This bit may be loaded by EEPROM or over-written by a SMBUS host.
4
3:1
0
stsOutputEn
pwronTime
RW
RW
RW
Power On Delay Time. When the efuse_pwronTime field is all 0s, this
field sets the delay time from the removal disable of PWRCTL to the
enable of PWRCTL when transitioning battery charging modes. For
example, when disabling the power on a transition from ACP to DCP
Mode. The nominal timing is defined as follows:
TPWRON_EN = (pwronTime x 1) x 200 ms
(1)
This field may be over-written by EEPROM contents or by an SMBus
host.
USB3 Spread Spectrum Disable. This bit allows firmware to disable the
spread spectrum function of the USB3 phy PLL.
0 = Spread spectrum function is enabled
usb3spreadDis
1= Spread spectrum function is disabled
This bit may be loaded by EEPROM or over-written by a SMBUS host.
Copyright © 2017, Texas Instruments Incorporated
35
TUSB8042
ZHCSGM0 –AUGUST 2017
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8.5.25 SMBus Device Status and Command Register
Figure 26. Register Offset F8h
Bit No.
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
Reset State
Table 30. Bit Descriptions – SMBus Device Status and Command Register
Bit
Field
Type
Description
7:2
RSVD
RO
Reserved. Read only, returns 0 when read.
SMBus interface reset. This bit loads the registers back to their GRSTz
values. Note, that since this bit can only be set when in SMBus mode
the cfgActive bit is also reset to 1. When software sets this bit it must
reconfigure the registers as necessary.
This bit is set by writing a 1 and is cleared by hardware on completion
of the reset. A write of 0 has no effect.
1
smbusRst
cfgActive
RSU
RCU
Configuration active. This bit indicates that configuration of the
TUSB8042 is currently active. The bit is set by hardware when the
device enters the I2C or SMBus mode. The TUSB8042 shall not
connect on the upstream port while this bit is 1.
When in I2C mode, the bit is cleared by hardware when the TUSB8042
exits the I2C mode.
0
When in the SMBus mode, this bit must be cleared by the SMBus host
in order to exit the configuration mode and allow the upstream port to
connect.
The bit is cleared by a writing 1. A write of 0 has no effect.
36
Copyright © 2017, Texas Instruments Incorporated
TUSB8042
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ZHCSGM0 –AUGUST 2017
9 Applications and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The TUSB8042 is a four-port USB 3.1 Gen1 compliant hub. It provides simultaneous SuperSpeed USB and high-
speed/full-speed connections on the upstream port and provides SuperSpeed USB, high-speed, full-speed, or
low speed connections on the downstream port. The TUSB8042 can be used in any application that needs
additional USB compliant ports. For example, a specific notebook may only have two downstream USB ports. By
using the TUSB8042, the notebook can increase the downstream port count to five.
9.2 Typical Application
9.2.1 Discrete USB Hub Product
A common application for the TUSB8042 is as a self powered standalone USB hub product. The product is
powered by an external 5V DC Power adapter. In this application, using a USB cable TUSB8042 upstream port
is plugged into a USB Host controller. The downstream ports of the TUSB8042 are exposed to users for
connecting USB hard drives, cameras, flash drives, and so forth.
USB
Type B
DC
PWR
Connector
US Port
TUSB8042
USB
PWR
USB
PWR
SWITCH
SWITCH
DS Port 1
DS Port 2 DS Port 3 DS Port 4
USB Type A
Connector
USB Type A
Connector
USB Type A
Connector
USB Type A
Connector
Figure 27. Discrete USB Hub Product
Copyright © 2017, Texas Instruments Incorporated
37
TUSB8042
ZHCSGM0 –AUGUST 2017
www.ti.com.cn
Typical Application (continued)
9.2.1.1 Design Requirements
Table 31. Design Parameters
DESIGN PARAMETER
VDD Supply
EXAMPLE VALUE
1.1 V
VDD33 Supply
3.3 V
Upstream Port USB Support (SS, HS, FS)
SS, HS, FS
Downstream Port 1 USB Support (SS, HS, FS, LS)
Downstream Port 2 USB Support (SS, HS, FS, LS)
Downstream Port 3 USB Support (SS, HS, FS, LS)
Downstream Port 4 USB Support (SS, HS, FS, LS)
Number of Removable external exposed Downstream Ports
Number of Non-Removable external exposed Downstream Ports
Full Power Management of Downstream Ports
Individual Control of Downstream Port Power Switch
Power Switch Enable Polarity
SS, HS, FS, LS
SS, HS, FS, LS
SS, HS, FS, LS
SS, HS, FS, LS
4
0
Yes. (FULLPWRMGMTZ = 0)
Yes. (GANGED = 0)
Active High. (PWRCTL_POL = 1)
Battery Charge Support for Downstream Port 1
Battery Charge Support for Downstream Port 2
Battery Charge Support for Downstream Port 3
Battery Charge Support for Downstream Port 4
I2C EEPROM Support
Yes
Yes
Yes
Yes
No
24MHz Clock Source
Crystal
9.2.1.2 Detailed Design Procedure
9.2.1.2.1 Upstream Port Implementation
The upstream of the TUSB8042 is connected to a USB3 Type B connector. This particular example has
GANGED pin and FULLPWRMGMTZ pin pulled low which results in individual power support each downstream
port. The VBUS signal from the USB3 Type B connector is feed through a voltage divider. The purpose of the
voltage divider is to make sure the level meets USB_VBUS input requirements
R1
90.9K
0402
1%
R2
C1
10uF
10K 1%
0402
1%
U1A
J1
48
42
40
USB_VBUS
GANGED/SMBA2/HS_UP
1
2
3
4
5
6
7
8
VBUS
VBUS
DM
DP
USB_DM_UP
USB_DP_UP
54
53
USB_DM_UP
USB_DP_UP
FULLPWRMGMTZ/SMBA1/SS_UP
GND
CAP_UP_TXM
CAP_UP_TXP
USB_SSTXM_UP
56
55
C2
C3
0.1uF 0201
0.1uF 0201
SSTXN
SSTXP
GND
SSRXN
SSRXP
SHIELD0
SHIELD1
USB_SSTXM_UP
USB_SSTXP_UP
R3
R4
USB_SSTXP_UP
USB_SSRXM_UP
USB_SSRXP_UP
4.7K
0402
5%
4.7K
0402
5%
59
58
USB_SSRXM_UP
USB_SSRXP_UP
9
10
11
TUSB8042
USB3_TYPEB_CONNECTOR
C4
0.1uF
C5
0.001uF
R5
1M
0402
5%
Copyright © 2016, Texas Instruments Incorporated
Figure 28. Upstream Port Implementation
38
Copyright © 2017, Texas Instruments Incorporated
TUSB8042
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ZHCSGM0 –AUGUST 2017
9.2.1.2.2 Downstream Port 1 Implementation
The downstream port 1 of the TUSB8042 is connected to a USB3 Type A connector. With BATEN1 pin pulled
up, Battery Charge support is enabled for Port 1. If Battery Charge support is not needed, then pull-up resistor on
BATEN1 should be uninstalled.
BOARD_3P3V
FB1
R6
POPULATE
DN1_VBUS
VBUS_DS1
4.7K
0402
5%
DN1_VBUS
FOR BC SUPPORT
220 at 100MHZ C6
0.1uF
J2
1
2
3
4
5
6
7
8
9
U1B
VBUS
DM
DP
2
1
USB_DM_DN1
USB_DP_DN1
USB_DM_DN1
USB_DP_DN1
GND
7
6
USB_SSRXM_DN1
USB_SSRXP_DN1
USB_SSRXM_DN1
USB_SSRXP_DN1
SSRXN
SSRXP
GND
SSTXN
SSTXP
0.1uF 0201
0.1uF 0201
C7
C8
4
3
USB_SSTXM_DN1
USB_SSTXP_DN1
CAP_DN_TXM1
CAP_DN_TXP1
USB_SSTXM_DN1
USB_SSTXP_DN1
10
11
SHIELD0
SHIELD1
36
46
PWRCTRL1_BATEN1
OVERCUR1Z
PWRCTL1/BATEN1
OVERCUR1
USB3_TYPEA_CONNECTOR
R7
1M
C9
0.001uF
C10
0.1uF
TUSB8042
0402
5%
Copyright © 2016, Texas Instruments Incorporated
Figure 29. Downstream Port 1 Implementation
9.2.1.2.3 Downstream Port 2 Implementation
The downstream port 2 of the TUSB8042 is connected to a USB3 Type A connector. With BATEN2 pin pulled
up, Battery Charge support is enabled for Port 2. If Battery Charge support is not needed, then pull-up resistor on
BATEN2 should be uninstalled. For ferrite bead used on the VBUS connection, a lower resistance is
recommended due to noticeable IR drop during high current charging modes. The isolation between the Type-A
connectors shield ground and signal ground pins is not required. Some applications may have better ESD/EMI
performance when the grounds are shorted together.
BOARD_3P3V
FB2
DN2_VBUS
VBUS_DS2
R8
DN2_VBUS
POPULATE
4.7K
0402
5%
FOR BC SUPPORT
220 at 100MHZ
C11
0.1uF
J3
1
2
3
4
5
6
7
8
9
U1C
VBUS
DM
DP
10
USB_DM_DN2
USB_DP_DN2
USB_DM_DN2
9
USB_DP_DN2
GND
15
14
USB_SSRXM_DN2
USB_SSRXP_DN2
USB_SSRXM_DN2
USB_SSRXP_DN2
SSRXN
SSRXP
GND
SSTXN
SSTXP
12
11
USB_SSTXM_DN2
USB_SSTXP_DN2
CAP_DN2_TXM
CAP_DN2_TXP
C12
0.1uF 0201
0.1uF 0201
USB_SSTXM_DN2
USB_SSTXP_DN2
C13
10
11
SHIELD0
SHIELD1
35
47
PWRCTRL2_BATEN2
OVERCUR2Z
PWRCTL2/BATEN2
OVERCUR2
R9
1M
C15
0.001uF
USB3_TYPEA_CONNECTOR
C14
0.1uF
0402
5%
TUSB8042
Copyright © 2016, Texas Instruments Incorporated
Figure 30. Downstream Port 2 Implementation
Copyright © 2017, Texas Instruments Incorporated
39
TUSB8042
ZHCSGM0 –AUGUST 2017
www.ti.com.cn
9.2.1.2.4 Downstream Port 3 Implementation
The downstream port3 of the TUSB8042 is connected to a USB3 Type A connector. With BATEN3 pin pulled up,
Battery Charge support is enabled for Port 3. If Battery Charge support is not needed, then pull-up resistor on
BATEN3 should be uninstalled. For ferrite bead used on the VBUS connection, a lower resistance is
recommended due to noticeable IR drop during high current charging modes. The isolation between the Type-A
connectors shield ground and signal ground pins is not required. Some applications may have better ESD/EMI
performance when the grounds are shorted together.
BOARD_3P3V
FB3
VBUS_DS3
R10
4.7K
0402
5%
DN3_VBUS
POPULATE
FOR BC SUPPORT
220 at 100MHZ
C16
0.1uF
J4
1
2
3
4
5
6
7
8
9
U1D
VBUS
DM
DP
18
USB_DM_DN3
USB_DP_DN3
USB_DM_DN3
17
USB_DP_DN3
GND
23
22
USB_SSRXM_DN3
USB_SSRXP_DN3
USB_SSRXM_DN3
USB_SSRXP_DN3
SSRXN
SSRXP
GND
SSTXN
SSTXP
20
19
USB_SSTXM_DN3
USB_SSTXP_DN3
CAP_DN3_TXM
CAP_DN3_TXP
C17
0.1uF 0201
0.1uF 0201
USB_SSTXM_DN3
USB_SSTXP_DN3
C18
10
11
SHIELD0
SHIELD1
33
44
PWRCTRL3_BATEN3
OVERCUR3Z
PWRCTL3/BATEN3
OVERCUR3
R11
C19
0.001uF
USB3_TYPEA_CONNECTOR
C20
0.1uF
1M
0402
5%
TUSB8042
Copyright © 2016, Texas Instruments Incorporated
Figure 31. Downstream Port 3 Implementation
9.2.1.2.5 Downstream Port 4 Implementation
The downstream port 4 of the TUSB8042 is connected to a USB3 Type A connector. With BATEN4 pin pulled
up, Battery Charge support is enabled for Port 4. If Battery Charge support is not needed, then pull-up resistor on
BATEN4 should be uninstalled. For ferrite bead used on the VBUS connection, a lower resistance is
recommended due to noticeable IR drop during high current charging modes. The isolation between the Type-A
connectors shield ground and signal ground pins is not required. Some applications may have better ESD/EMI
performance when the grounds are shorted together.
BOARD_3P3V
FB4
VBUS_DS4
R12
4.7K
0402
5%
DN4_VBUS
POPULATE
FOR BC SUPPORT
220 at 100MHZ
C21
0.1uF
J5
1
2
3
4
5
6
7
8
9
U1E
VBUS
DM
DP
25
USB_DM_DN4
USB_DP_DN4
USB_DM_DN4
24
USB_DP_DN4
GND
30
29
USB_SSRXM_DN4
USB_SSRXP_DN4
USB_SSRXM_DN4
USB_SSRXP_DN4
SSRXN
SSRXP
GND
SSTXN
SSTXP
27
26
USB_SSTXM_DN4
USB_SSTXP_DN4
CAP_DN4_TXM
CAP_DN4_TXP
C22
0.1uF 0201
0.1uF 0201
USB_SSTXM_DN4
USB_SSTXP_DN4
C23
10
11
SHIELD0
SHIELD1
32
43
PWRCTRL4_BATEN4
OVERCUR4Z
PWRCTL4/BATEN4
OVERCUR4
R13
C25
0.001uF
USB3_TYPEA_CONNECTOR
C24
0.1uF
1M
0402
5%
TUSB8042
Copyright © 2016, Texas Instruments Incorporated
Figure 32. Downstream Port 4 Implementation
40
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TUSB8042
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ZHCSGM0 –AUGUST 2017
9.2.1.2.6 VBUS Power Switch Implementation
This particular example uses the Texas Instruments TPS2561 Dual Channel Precision Adjustable Current-
Limited power switch. For details on this power switch or other power switches available from Texas Instruments,
refer to the Texas Instruments website.
BOARD_3P3V
BOARD_3P3V
BOARD_5V
R19
10K
0402
5%
R20
10K
0402
5%
C42
0.1uF
U2
2
3
9
DN1_VBUS
DN2_VBUS
ILIM1
DN1_VBUS
OVERCUR1Z
DN2_VBUS
OVERCUR2Z
IN
IN
OUT1
FAULT1Z
OUT2
10
8
PWRCTRL1_BATEN1
PWRCTRL2_BATEN2
4
5
PWRCTRL1_BATEN1
PWRCTRL2_BATEN2
EN1
EN2
6
FAULT2Z
ILIM
1
11
GND
PAD
7
C43
C45
0.1uF
+
C44
150uF
0.1uF
+
C46
150uF
TPS2561
R21
25.5K
0402
5%
Limiting DS Port VBUS current to 2.2A per port.
BOARD_3P3V
BOARD_3P3V
BOARD_5V
R22
10K
0402
5%
R23
10K
0402
5%
C47
0.1uF
U3
2
9
DN3_VBUS
DN4_VBUS
ILIM2
DN3_VBUS
IN
IN
OUT1
FAULT1Z
OUT2
3
4
5
10
8
OVERCUR3Z
DN4_VBUS
PWRCTRL3_BATEN3
EN1
EN2
PWRCTRL4_BATEN4
6
OVERCUR4Z
FAULT2Z
ILIM
1
11
GND
PAD
7
C48
0.1uF
C50
+
C49
150uF
0.1uF
+
C51
150uF
TPS2561
R24
25.5K
0402
5%
Limiting DS Port VBUS current to 2.2A per port.
Copyright © 2016, Texas Instruments Incorporated
Figure 33. VBUS Power Switch Implementation
9.2.1.2.7 Clock, Reset, and Misc
The PWRCTL_POL is left unconnected which results in active high power enable (PWRCTL1, PWRCTL2,
PWRCTL3, and PWRCTL4) for a USB VBUS power switch. SMBUSz pin is also left unconnected which will
select I2C mode. Both PWRCTL_POL and SMBUSz pins have internal pull-ups. The 1 µF capacitor on the
GRSTN pin can only be used if the VDD11 supply is stable before the VDD33 supply. The depending on the
supply ramp of the two supplies the capacitor size may have to be adjusted.
Copyright © 2017, Texas Instruments Incorporated
41
TUSB8042
ZHCSGM0 –AUGUST 2017
www.ti.com.cn
U1F
C39
1uF
50
38
37
GRSTN
SCL/SMBCLK
SDA/SMBDAT
39
45
SMBUSZ/SS_SUSPEND
AUTOENZ/HS_SUSPEND
PWRCTL_POL
TEST
62
61
XI
41
49
64
R14
1M
XO
Y1
USB_R1
R15
TUSB8042
R16
4.7K
R18
4.7K
0402
5%
9.53K
0402
1%
24MHz
C40
C41
18pF
18pF
Copyright © 2016, Texas Instruments Incorporated
Figure 34. Clock, Reset, and Misc
42
Copyright © 2017, Texas Instruments Incorporated
TUSB8042
www.ti.com.cn
ZHCSGM0 –AUGUST 2017
9.2.1.2.8 TUSB8042 Power Implementation
BOARD_1P1V
VDD11
FB5
C26
0.1uF
C27
C28
C29
C30
C31
C32
C33
10uF
220 at 100MHZ
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
U1G
16
VDD33
34
VDD33
VDD33
VDD33
60
52
63
VDD33
BOARD_3P3V
NC
FB6
C34
C35
0.1uF
C36
0.1uF
C37
0.1uF
C38
10uF
220 at 100MHZ
0.1uF
TUSB8042
Figure 35. TUSB8042 Power Implementation
Copyright © 2017, Texas Instruments Incorporated
43
TUSB8042
ZHCSGM0 –AUGUST 2017
www.ti.com.cn
9.2.1.3 Application Curves
Figure 36. Upstream Port
Figure 37. Downstream Port 1
Figure 38. Downstream Port 2
Figure 39. Downstream Port 3
Figure 40. Downstream Port 4
Figure 41. High-Speed Upstream Port
44
Copyright © 2017, Texas Instruments Incorporated
TUSB8042
www.ti.com.cn
ZHCSGM0 –AUGUST 2017
Figure 42. High-Speed Downstream Port 1
Figure 43. High-Speed Downstream Port 2
Figure 44. High-Speed Downstream Port 3
Figure 45. High-Speed Downstream Port 4
Copyright © 2017, Texas Instruments Incorporated
45
TUSB8042
ZHCSGM0 –AUGUST 2017
www.ti.com.cn
10 Power Supply Recommendations
10.1 TUSB8042 Power Supply
VDD should be implemented as a single power plane, as should VDD33
.
•
The VDD pins of the TUSB8042 supply 1.1 V (nominal) power to the core of the TUSB8042. This power rail
can be isolated from all other power rails by a ferrite bead to reduce noise.
•
The DC resistance of the ferrite bead on the core power rail can affect the voltage provided to the device due
to the high current draw on the power rail. The output of the core voltage regulator may need to be adjusted
to account for this or a ferrite bead with low DC resistance (less than 0.05 Ω) can be selected.
•
•
The VDD33 pins of the TUSB8042 supply 3.3 V power rail to the I/O of the TUSB8042. This power rail can be
isolated from all other power rails by a ferrite bead to reduce noise.
All power rails require a 10 µF capacitor or 1 µF capacitors for stability and noise immunity. These bulk
capacitors can be placed anywhere on the power rail. The smaller decoupling capacitors should be placed as
close to the TUSB8042 power pins as possible with an optimal grouping of two of differing values per pin.
10.2 Downstream Port Power
•
The downstream port power, VBUS, must be supplied by a source capable of supplying 5V and up to 900 mA
per port. Downstream port power switches can be controlled by the TUSB8042 signals. It is also possible to
leave the downstream port power always enabled.
•
•
A large bulk low-ESR capacitor of 22 µF or larger is required on each downstream port’s VBUS to limit in-rush
current.
The ferrite beads on the VBUS pins of the downstream USB port connections are recommended for both
ESD and EMI reasons. A 0.1µF capacitor on the USB connector side of the ferrite provides a low impedance
path to ground for fast rise time ESD current that might have coupled onto the VBUS trace from the cable.
10.3 Ground
It is recommended that only one board ground plane be used in the design. This provides the best image plane
for signal traces running above the plane. The thermal pad of the TUSB8042 and any of the voltage regulators
should be connected to this plane with vias. An earth or chassis ground is implemented only near the USB port
connectors on a different plane for EMI and ESD purposes.
46
Copyright © 2017, Texas Instruments Incorporated
TUSB8042
www.ti.com.cn
ZHCSGM0 –AUGUST 2017
11 Layout
11.1 Layout Guidelines
11.1.1 Placement
1. 9.53K +/-1% resistor connected to pin USB_R1 should be placed as close as possible to the TUSB8042.
2. A 0.1 µF should be placed as close as possible on each VDD and VDD33 power pin.
3. The 100 nF capacitors on the SSTXP and SSTXM nets should be placed close to the USB connector (Type
A, Type B, and so forth).
4. The ESD and EMI protection devices (if used) should also be placed as close as possible to the USB
connector.
5. If a crystal is used, it must be placed as close as possible to the TUSB8042 XI and XO pins.
6. Place voltage regulators as far away as possible from the TUSB8042, the crystal, and the differential pairs.
7. In general, the large bulk capacitors associated with each power rail should be placed as close as possible to
the voltage regulators.
11.1.2 Package Specific
1. The TUSB8042 package has a 0.5-mm pin pitch.
2. The TUSB8042 package has a 6.0-mm x 6.0-mm thermal pad. This thermal pad must be connected to
ground through a system of vias.
3. All vias under device, except for those connected to thermal pad, should be solder masked to avoid any
potential issues with thermal pad layouts.
11.1.3 Differential Pairs
This section describes the layout recommendations for all the TUSB8042 differential pairs: USB_DP_XX,
USB_DM_XX, USB_SSTXP_XX, USB_SSTXM_XX, USB_SSRXP_XX, and USB_SSRXM_XX.
1. Must be designed with a differential impedance of 90 Ω ±10%.
2. In order to minimize cross talk, it is recommended to keep high speed signals away from each other. Each
pair should be separated by at least 5 times the signal trace width. Separating with ground as depicted in the
layout example will also help minimize cross talk.
3. Route all differential pairs on the same layer adjacent to a solid ground plane.
4. Do not route differential pairs over any plane split.
5. Adding test points will cause impedance discontinuity and will therefore negative impact signal performance.
If test points are used, they should be placed in series and symmetrically. They must not be placed in a
manner that causes stub on the differential pair.
6. Avoid 90 degree turns in trace. The use of bends in differential traces should be kept to a minimum. When
bends are used, the number of left and right bends should be as equal as possible and the angle of the bend
should be ≥ 135 degrees. This will minimize any length mismatch causes by the bends and therefore
minimize the impact bends have on EMI.
7. Minimize the trace lengths of the differential pair traces. The maximum recommended trace length for SS
differential pair signals and USB 2.0 differential pair signals is eight inches. Longer trace lengths require very
careful routing to assure proper signal integrity.
8. Match the etch lengths of the differential pair traces (i.e. DP and DM or SSRXP and SSRXM or SSTXP and
SSTXM). There should be less than 5 mils difference between a SS differential pair signal and its
complement. The USB 2.0 differential pairs should not exceed 50 mils relative trace length difference.
9. The etch lengths of the differential pair groups do not need to match (i.e. the length of the SSRX pair to that
of the SSTX pair), but all trace lengths should be minimized.
10. Minimize the use of vias in the differential pair paths as much as possible. If this is not practical, make sure
that the same via type and placement are used for both signals in a pair. Any vias used should be placed as
close as possible to the TUSB8042 device.
11. To ease routing, the polarity of the SS differential pairs can be swapped. This means that SSTXP can be
routed to SSTXM or SSRXM can be routed to SSRXP.
Copyright © 2017, Texas Instruments Incorporated
47
TUSB8042
ZHCSGM0 –AUGUST 2017
www.ti.com.cn
Layout Guidelines (continued)
12. To ease routing of the USB2 DP and DM pair, the polarity of these pins can be swapped. If this is done, the
appropriate Px_usb2pol register, where x = 0, 1, 2, 3, or 4, must be set.
13. Do not place power fuses across the differential pair traces.
11.2 Layout Examples
11.2.1 Upstream Port
Figure 46. Example Routing of Upstream Port
48
Copyright © 2017, Texas Instruments Incorporated
TUSB8042
www.ti.com.cn
ZHCSGM0 –AUGUST 2017
Layout Examples (continued)
11.2.2 Downstream Port
Figure 47. Example Routing of Downstream Port
The remaining three downstream ports routing can be similar to the example provided.
版权 © 2017, Texas Instruments Incorporated
49
TUSB8042
ZHCSGM0 –AUGUST 2017
www.ti.com.cn
12 器件和文档支持
12.1 接收文档更新通知
要接收文档更新通知,请导航至德州仪器 TI.com.cn 上的器件产品文件夹。请单击右上角的通知我 进行注册,即可
收到任意产品信息更改每周摘要。有关更改的详细信息,请查看任意已修订文档中包含的修订历史记录。
12.2 社区资源
下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范,
并且不一定反映 TI 的观点;请参阅 TI 的 《使用条款》。
TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在
e2e.ti.com 中,您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。
设计支持
TI 参考设计支持 可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。
12.3 商标
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.4 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时,应将导线一起截短或将装置放置于导电泡棉中,以防止 MOS 门极遭受静电损
伤。
12.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
50
版权 © 2017, Texas Instruments Incorporated
TUSB8042
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ZHCSGM0 –AUGUST 2017
13 机械、封装和可订购信息
以下页中包括机械封装、封装和可订购信息。这些信息是针对指定器件可提供的最新数据。这些数据发生变化时,
我们可能不会另行通知或修订此文档。如欲获取此产品说明书的浏览器版本,请参阅左侧的导航栏。
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TUSB8042
ZHCSGM0 –AUGUST 2017
www.ti.com.cn
PACKAGE OUTLINE
RGC0064G
VQFN - 1 mm max height
S
C
A
L
E
1
.
5
0
0
PLASTIC QUAD FLATPACK - NO LEAD
9.1
8.9
B
A
PIN 1 INDEX AREA
9.1
8.9
(0.1) TYP
LEADFRAME PROFILE
OPTION
S
C
A
L
E
8
.
0
0
0
1 MAX
C
SEATING PLANE
0.08
0.05
0.00
2X 7.5
(0.2) TYP
6
0.05
17
32
60X 0.5
16
33
SEE DETAIL
2X
EXPOSED
THERMAL PAD
7.5
1
48
0.30
64X
64
49
PIN 1 ID
(OPTIONAL)
0.18
0.5
0.3
0.1
C A
B
64X
0.05
4222053/B 06/2015
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
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版权 © 2017, Texas Instruments Incorporated
TUSB8042
www.ti.com.cn
ZHCSGM0 –AUGUST 2017
EXAMPLE BOARD LAYOUT
RGC0064G
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(
6)
SYMM
64
49
64X (0.6)
1
48
64X (0.24)
8X (1.01)
60X (0.5)
SYMM
18X (1.16)
(8.8)
(0.58)
TYP
(
0.2) TYP
VIA
(0.58) TYP
33
16
17
32
18X (1.16)
(8.8)
8X (1.01)
(R0.05)
ALL PAD CORNERS
LAND PATTERN EXAMPLE
SCALE:10X
0.07 MIN
ALL SIDES
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4222053/B 06/2015
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
www.ti.com
版权 © 2017, Texas Instruments Incorporated
53
TUSB8042
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EXAMPLE STENCIL DESIGN
RGC0064G
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
25X ( 0.96)
64
(1.16) TYP
(R0.05) TYP
49
64X (0.6)
1
48
64X (0.24)
60X (0.5)
(1.16)
TYP
SYMM
(8.8)
(R0.05) TYP
33
16
METAL
TYP
17
32
SYMM
(8.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD
64% PRINTED SOLDER COVERAGE BY AREA
SCALE:12X
4222053/B 06/2015
NOTES: (continued)
5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
54
版权 © 2017, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TUSB8042RGCR
TUSB8042RGCT
ACTIVE
ACTIVE
VQFN
VQFN
RGC
RGC
64
64
2000 RoHS & Green
250 RoHS & Green
NIPDAU
Level-3-260C-168 HR
Level-3-260C-168 HR
0 to 70
0 to 70
TUSB8042
TUSB8042
NIPDAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
23-Sep-2017
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TUSB8042RGCR
TUSB8042RGCT
VQFN
VQFN
RGC
RGC
64
64
2000
250
330.0
180.0
16.4
16.4
9.3
9.3
9.3
9.3
1.1
1.1
12.0
12.0
16.0
16.0
Q2
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
23-Sep-2017
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TUSB8042RGCR
TUSB8042RGCT
VQFN
VQFN
RGC
RGC
64
64
2000
250
367.0
210.0
367.0
185.0
38.0
35.0
Pack Materials-Page 2
重要声明和免责声明
TI 均以“原样”提供技术性及可靠性数据(包括数据表)、设计资源(包括参考设计)、应用或其他设计建议、网络工具、安全信息和其他资
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所述资源可供专业开发人员应用TI 产品进行设计使用。您将对以下行为独自承担全部责任:(1) 针对您的应用选择合适的TI 产品;(2) 设计、
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束。TI提供所述资源并不扩展或以其他方式更改TI 针对TI 产品所发布的可适用的担保范围或担保免责声明。IMPORTANT NOTICE
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