TUSS4470 [TI]
具有对数放大器的直接驱动超声波传感器 IC;
| 型号： | TUSS4470 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有对数放大器的直接驱动超声波传感器 IC 放大器 驱动 传感器 |
| 文件： | 总50页 (文件大小：3630K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TUSS4470
ZHCSKL2A – DECEMBER 2019 – REVISED MAY 2022
TUSS4470 具有对数放大器的变压器驱动超声波传感器 IC
1 特性
3 说明
•
集成式驱动器，用于直接驱动传感器和接收器级，
TUSS4470 是一款高度集成的直接驱动模拟前端，适
用于工业超声波应用。传感器驱动级是内部 H 桥，可
配置为在直接驱动模式下驱动传感器，从而在传感器上
实现最大电压。内部 H 桥也可以配置为外部 FET 的前
置驱动器，从而为较大的传感器提供更高的电流和电压
驱动。
具有用于超声波应用的模拟输出
86dB 输入动态范围模拟前端
•
– 一级低噪声放大器，增益可调为 10、12.5、15
和 20V/V
– 40KHz 至 500KHz 的可配置带通滤波器
– 宽带对数放大器
接收信号路径包括低噪声线性放大器、带通滤波器，后
跟对数增益放大器，可根据输入决定放大。对数放大器
具有很高的灵敏度，可捕捉弱回波信号，并在整个反射
回波范围内提供出色的输入动态范围。
•
•
•
支持的传感器频率（由外部时钟控制）
– 40KHz 至 1MHz
– 前置驱动器模式：40KHz 至 440KHz
适用于低功耗应用
驱动器可以直接通过微控制器进行控制，以对突发信号
进行完全定制，或者可以通过 SPI 并借助可定制的脉
冲长度进行编程。TUSS4470 可以支持单个传感器发
送和接收突发信号，或者可以设置两个传感器来拆分发
送和接收功能。
– 待机模式：1.7mA（典型值）
– 睡眠模式：220µA（典型值）
可配置软启动驱动级：
– 使用内部 H 桥进行传感器激励的直接驱动
– 用于使用内部 H 桥驱动外部场效应晶体管 (FET)
以实现更高电流驱动的前置驱动器配置
– 使用 IO1 和 IO2 引脚实现的可配置突发模式
输出：
– VOUT 上已解调回波包络的电压输出
– OUT3 引脚上的输入信号过零比较器输出
– OUT4 引脚上的可编程 VOUT 阈值交叉
串行外设接口 (SPI)，可通过微控制器 (MCU) 进行
配置
器件信息(1)
器件型号
TUSS4470
封装
封装尺寸（标称值）
•
•
WQFN (20)
4.00mm × 4.00mm
(1) 要了解所有可用封装，请参阅数据表末尾的可订购产品附录。
D1
RPWR
VIN
>
CPWR1
MCU
GPIO
OUTA
VDRV
IO2
IO1
GPIO
GPIO
OUT3
OUT4
NCS
2 应用
•
•
•
OUTB
FLT
CPWR2
位置传感器
液位变送器
接近传感器
SDO
SDI
CFLT
SPI
RINP
SCLK
VOUT
CINP
INP
INN
ADC
CINN
LDO
VDD
CVDD
TUSS4470 应用示意图
本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLDS251
TUSS4470
ZHCSKL2A – DECEMBER 2019 – REVISED MAY 2022
www.ti.com.cn
Table of Contents
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions ..................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings........................................ 4
6.2 ESD Ratings............................................................... 4
6.3 Recommended Operating Conditions.........................4
6.4 Thermal Information ...................................................5
6.5 Power-Up Characteristics........................................... 5
6.6 Transducer Drive ........................................................5
6.7 Receiver Characteristics.............................................6
6.8 Echo Interrupt Comparator Characteristics.................7
6.9 Digital I/O Characteristics........................................... 7
6.10 Switching Characteristics..........................................8
6.11 Typical Characteristics.............................................. 8
7 Detailed Description......................................................11
7.1 Overview................................................................... 11
7.2 Functional Block Diagram......................................... 11
7.3 Feature Description...................................................11
7.4 Device Functional Modes..........................................20
7.5 Programming............................................................ 21
7.6 Register Maps...........................................................23
8 Application and Implementation..................................30
8.1 Application Information............................................. 30
8.2 Typical Application.................................................... 30
9 Power Supply Recommendations................................36
10 Layout...........................................................................37
10.1 Layout Guidelines................................................... 37
10.2 Layout Example...................................................... 38
11 Device and Documentation Support..........................39
11.1 接收文档更新通知................................................... 39
11.2 支持资源..................................................................39
11.3 Trademarks............................................................. 39
11.4 Electrostatic Discharge Caution..............................39
11.5 术语表..................................................................... 39
12 Mechanical, Packaging, and Orderable
Information.................................................................... 39
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
Changes from Revision * (April 2018) to Revision A (May 2022)
Page
•
•
•
更新了整个文档中的表格、图和交叉参考的编号格式.........................................................................................1
将提到 SPI 的旧术语的所有实例更改为控制器和外设........................................................................................ 1
Changed operating free-air temperature minimum from: –25°C to: –40°C.........................................................4
Copyright © 2022 Texas Instruments Incorporated
2
Submit Document Feedback
Product Folder Links: TUSS4470
TUSS4470
ZHCSKL2A – DECEMBER 2019 – REVISED MAY 2022
www.ti.com.cn
5 Pin Configuration and Functions
OUT3
DGND
NCS
1
2
3
4
5
15
14
13
12
11
OUTA
GND
SGND
INP
Thermal
Pad
SCLK
SDI
INN
Not to scale
图 5-1. RTJ Package 20-Pin WQFN With Exposed Thermal Pad (Top View)
PIN
TYPE(1)
DESCRIPTION
NO.
1
NAME
OUT3
DGND
NCS
O
G
I
General-purpose digital output
Digital ground
2
3
SPI negative chip select
SPI CLK
4
SCLK
SDI
I
5
I
SPI data input
6
SDO
IO1
O
I
SPI data output
7
General-purpose digital input
General-purpose digital input
Demodulated echo analog output
Voltage regulator input
Negative transducer receive
Positive transducer receive
Sensor ground (quiet)
Ground
8
IO2
I
9
VOUT
VDD
O
P
I
10
11
12
13
14
15
16
17
18
19
20
INN
INP
I
SGND
GND
OUTA
OUTB
VDRV
FLT
G
G
O
O
P
I/O
O
P
Transducer driver output A
Transducer driver output B
H-bridge driver supply voltage
Filter components
OUT4
VPWR
General-purpose digital output
Input supply voltage
(1) I = input, O = output, I/O = input and output, G = ground, P = power
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
3
Product Folder Links: TUSS4470
TUSS4470
ZHCSKL2A – DECEMBER 2019 – REVISED MAY 2022
www.ti.com.cn
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
–0.3
–0.3
–0.3
–0.3
0.5
MAX
40
UNIT
V
VVPWR
VVDD
VVDRV
VFLT
Supply voltage range
Voltage regulator input voltage
H-bridge drive voltage
5.5
V
VVPWR + 0.3
VVDD + 0.3
1.3
V
Filter component pin
V
VINX
INP, INN pins input voltage
SCLK, SDI, NCS, IOx pin input voltage
Analog output voltage
V
VDIG_IN
VVOUT
VDIG_OUT
VOUTA_B
TA
–0.3
–0.3
–0.3
–0.3
–40
VVDD + 0.3
VVDD + 0.3
VVDD + 0.3
VVDRV + 0.3
105
V
V
SDO, OUTx, IOx pin output voltage
OUTA, OUTB pins output voltage
Ambient temperature
V
V
TJ
Junction temperature
–40
125
°C
Tstg
Storage temperature
–40
125
(1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress
ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated
under Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
6.2 ESD Ratings
VALUE
UNIT
Human body model (HBM), per ANSI/ESDA/
JEDEC JS-001, all pins(1)
±2000
V(ESD)
Electrostatic discharge
V
Charged device model (CDM), per JEDEC
specification JESD22-C101, all pins(2)
±500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
VVPWR
Supply voltage on VPWR pin
5
36
V
Voltage on VDRV pin, internal regulation on VDRV disabled
(VDRV_HI_Z=1)(1)
5
5
36
15
V
V
VVDRV
VDRV voltage Pre driver mode (PRE_DRIVER_MODE=1), internal
regulation on VDRV disabled (VDRV_HI_Z=1)(1)
VVDIG_IO
VVDD
Digital I/O pins
–0.1
3.1
150
150
7
VVDD
5.5
V
V
Regulated voltage Input
IVPWR_INDIR
IVPWR_STDBY
IVDD_INDIR
IVDD_STDBY
IVDD_SLEEP
TA
Current consumption at VPWR pin during ranging
Current consumption at VPWR in standby mode
Current consumption at VDD pin during ranging
Current consumption at VDD in standby mode
Current consumption in sleep mode
Operating free-air temperature
240
220
11.5
1.5
340
340
13
µA
µA
mA
mA
µA
°C
°C
1.2
2.5
350
105
125
–40
–40
TJ
Operating junction temperature
(1) Always VVPWR > VVDRV + 0.3 V to prevent reverse current from VDRV pin to VPWR pin
Copyright © 2022 Texas Instruments Incorporated
4
Submit Document Feedback
Product Folder Links: TUSS4470
TUSS4470
ZHCSKL2A – DECEMBER 2019 – REVISED MAY 2022
www.ti.com.cn
6.4 Thermal Information
TUSS4470
THERMAL METRIC(1)
RTJ (WQFN)
20 PINS
36.3
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
29.4
14.7
ΨJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
0.4
ΨJB
14.7
RθJC(bot)
4.7
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
6.5 Power-Up Characteristics
over operating free-air temperature range, VVPWR, VVDRV and VVDD recommended voltage range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Time to power
up when SPI
communication is
possible
tPWR_ON
10
ms
VDRV_VOLTAGE_LEVEL = 0x0; VVPWR > VVDRV + 100 mV
VDRV_VOLTAGE_LEVEL = 0x4; VVPWR > VVDRV + 100 mV
VDRV_VOLTAGE_LEVEL = 0x7; VVPWR > VVDRV + 100 mV
VDRV_VOLTAGE_LEVEL = 0x8; VVPWR > VVDRV + 100 mV
VDRV_VOLTAGE_LEVEL = 0xC; VVPWR > VVDRV + 100 mV
VDRV_VOLTAGE_LEVEL = 0xD; VVPWR > VVDRV + 100 mV
VDRV_VOLTAGE_LEVEL = 0xE; VVPWR > VVDRV + 100 mV
VDRV_VOLTAGE_LEVEL = 0xF; VVPWR > VVDRV + 100 mV
VDRV_CURRENT_LEVEL = 0x0; VVPWR > VVDRV + 1 V
VDRV_CURRENT_LEVEL = 0x1; VVPWR > VVDRV + 1 V
4.5
8.1
5
9
5.3
9.9
11.5
12.09
15.81
16.74
17.67
19.0
8.5
12
13
17
18
19
20
10
20
12.6
13.91
18.9
19.26
20.33
21.4
11.5
23
Regulated voltage
on VDRV pin(1)
VVDRV
V
VDRV capacitor
charging current
IVDRV
mA
17
(1) Other VDRV voltage levels possible.
6.6 Transducer Drive
over operating free-air temperature range, VVPWR, VVDRV and VVDD recommended voltage range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
RHS_FET High-side MOSFET on-resistance
RLS_FET Low-side MOSFET on-resistance
TA =+105°C
30
Ω
TA =+105°C
20
Ω
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
5
Product Folder Links: TUSS4470
TUSS4470
ZHCSKL2A – DECEMBER 2019 – REVISED MAY 2022
www.ti.com.cn
6.7 Receiver Characteristics
over operating free-air temperature range, VVPWR, VVDRV and VVDD recommended voltage range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
LNA_GAIN = 0x00; fDRV_CLK = 58 KHz
LNA_GAIN = 0x01; fDRV_CLK = 58 KHz
LNA_GAIN = 0x10; fDRV_CLK = 58 KHz
LNA_GAIN = 0x11; fDRV_CLK = 58 KHz
MIN
13.7
9.4
TYP
MAX
16.8
12
UNIT
GLNA
GLNA
GLNA
GLNA
15
Low-noise
amplifier fixed
gain
10
V/V
17.6
11.6
20
21.8
14.2
12.5
Minimum
DRVIN_MIN
DRVIN_MAX
2.4
48
µVrms
mVrms
receive input(2)
LOGAMP_DIS_FIRST=0x0;LOGAMP_DIS_LAST=0x0
LNA_GAIN=0x00; ERRLOG < ± 3dB; fDRV_CLK < 500KHz
Maximum
receive input(2)
VOUT_SCALE_SEL = 0x0; fDRV_CLK = 58 KHz
VOUT_SCALE_SEL = 0x1; fDRV_CLK = 58 KHz
25
38
29.7
45.1
33
46
Slope of analog
front end(4)
SLAFE
mV/dB
LOGAMP_DIS_FIRST = 0x0; LOGAMP_DIS_LAST = 0x0
ERRLOG < ± 3 dB; fDRV_CLK < 500 KHz
82
74
59
92
86
70
Receiver path
dynamic range
(minimum to
LOGAMP_DIS_FIRST = 0x0; LOGAMP_DIS_LAST = 0x1
ERRLOG < ± 3 dB; fDRV_CLK < 500 KHz
maximum input)
(2)
LOGAMP_DIS_FIRST = 0x1; LOGAMP_DIS_LAST=0x1
ERRLOG < ± 3dB; fDRV_CLK < 500 KHz
DRAFE
dB
Receiver path
dynamic
Range (noise
floor to
LOGAMP_DIS_FIRST = 0x0; LOGAMP_DIS_LAST = 0x0
ERRLOG < ± 3 dB; fDRV_CLK < 500 KHz
74
84
maximum input)
(3)
Logamp
bandwidth
BWLOG
Information only
40
-108
-94
1000
-97
KHz
dBV
LOGAMP_DIS_FIRST=0x0; LOGAMP_DIS_LAST=0x0;
fDRV_CLK = 40 KHz
Intercept point LOGAMP_DIS_FIRST = 0x0; LOGAMP_DIS_LAST=0x1;
in dBV
INTLOG
-86
fDRV_CLK = 40 KHz
LOGAMP_DIS_FIRST = 0x1; LOGAMP_DIS_LAST=0x1;
fDRV_CLK = 40 KHz
-80
-70
Log
ERRLOG
conformance
error
Information only
-3
3
dB
Configurable
range of center BPF_BYPASS = 0x0; BPF_FC_TRIM = 0x0;
fBPF
40
3
500
5.2
KHz
frequency of
BPF
set by different values of BPF_HPF_FREQ
Q of bandpass
filter
QBPF
BPF_BYPASS = 0x0; BPF_Q_SEL = 0x0(1)
4
Internal resistor
on FLT pin to
ground
RLPF
6.25
KΩ
V
VVDD = 3.3 V; fDRV_CLK = 40 KHz; VOUT_SCALE_SEL = 0x0
LOGAMP_DIS_FIRST = 0x0; LOGAMP_DIS_LAST = 0x0
0.3
0.45
Output pedestal
level(2)
VO_PDSTL
VVDD = 5.0 V; fDRV_CLK = 40 KHz; VOUT_SCALE_SEL = 0x1
LOGAMP_DIS_FIRST = 0x0;LOGAMP_DIS_LAST = 0x0
0.45
0.675
Copyright © 2022 Texas Instruments Incorporated
6
Submit Document Feedback
Product Folder Links: TUSS4470
TUSS4470
ZHCSKL2A – DECEMBER 2019 – REVISED MAY 2022
www.ti.com.cn
over operating free-air temperature range, VVPWR, VVDRV and VVDD recommended voltage range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VVDD=3.3 V; fDRV_CLK = 40 KHz; CFLT = 15
nF; VOUT_SCALE_SEL = 0x0
50
200
LOGAMP_DIS_FIRST = 0x0; LOGAMP_DIS_LAST=0x0
Output peak-to-
peak noise
VN_pk_pk
mVpp
VVDD=5.0 V; fDRV_CLK = 40 KHz; CFLT = 15
nF; VOUT_SCALE_SEL = 0x1
75
300
LOGAMP_DIS_FIRST = 0x0; LOGAMP_DIS_LAST = 0x0
(1) Other choices of Q possible.
(2) Measured with effectively very large CFLT. Actual minimum signal detectable will depend on VN_pk_pk. Minimum and maximum input
levels are defined by ERRLOG
.
(3) Measured with different CFLT values according to 方程式 3. Noise floor is set by VN_PK_PK in addition to VO_PDSTL
.
(4) Slope measured with factory trim at fDRV_CLK = 58 KHz. Slope can be adjusted with LOGAMP_SLOPE_ADJ bits for different fDRV_CLK
settings.
6.8 Echo Interrupt Comparator Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VOUT_SCALE_SEL = 0x0
ECHO_INT_THR_SEL = 0x0
ECHO_INT_THR_SEL = 0x5
ECHO_INT_THR_SEL = 0xA
ECHO_INT_THR_SEL = 0xF
0.37
0.56
0.75
0.94
7
0.4
0.6
0.8
1
0.43
0.64
0.85
1.06
68
Echo interrupt comparator
threshold(1)
VECMP_THR_0
V
VECMP_HYS_0 Echo interrupt comparator hysteresis
mV
VOUT_SCALE_SEL = 0x1
ECHO_INT_THR_SEL = 0x0
ECHO_INT_THR_SEL = 0x5
ECHO_INT_THR_SEL = 0xA
ECHO_INT_THR_SEL = 0xF
0.56
0.84
1.13
1.41
0.6
0.9
1.2
1.5
0.64
0.96
1.27
1.59
Echo interrupt comparator
VE_CMP_THR_1
V
threshold(1)
Echo interrupt output threshold level
VECMP_HYS_1
hysteresis
7
68
mV
(1) Other thresholds possible.
6.9 Digital I/O Characteristics
over operating free-air temperature range, VVPWR, VVDRV and VVDD recommended voltage range (unless otherwise noted)
PARAMETER
Digital input high-level
Digital input low-level
TEST CONDITIONS
MIN TYP
MAX
UNIT
VVDD
VVDD
mV
V
VIH_DIGIO
VIL_DIGIO
0.7
NCS, SDI, SCLK and IOx pins
0.3
VHYS_DIGIO Digital input hysteresis
VOH_DIGIO Digital output high-level(1)
100
SDO, OUTx pins; IDIGIO_OUT = – 1 mA
SDO, OUTx pins; IDIGIO_OUT = 1 mA
SDO pin. Information Only
VVDD – 0.1
VOL_DIGIO
VO_CAP
Digital output low-level(1)
0.1
10
V
Maximum output load capacitance
pF
RPU_DIGIO Digital input pullup resistance to VDD
NCS, IO1, IO2 pins
80 100
80 100
130
kΩ
Digital Input pulldown resistance to
RPD_DIGIO
GND
SCLK, SDI pins
130
kΩ
(1) No short-circuit protection on output pins. Damage may occur for currents higher than specified.
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
7
Product Folder Links: TUSS4470
TUSS4470
ZHCSKL2A – DECEMBER 2019 – REVISED MAY 2022
www.ti.com.cn
6.10 Switching Characteristics
over operating free-air temperature range, VVPWR, VVDRV and VVDD recommended voltage range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Frequency of drive clock at IO1 and IO2
pin ; depends on the VDRV voltage
Used as burst frequency;
PRE_DRIVER_MODE = 0x0
40
1000
KHz
fDRV_CLK
Used as burst frequency;
PRE_DRIVER_MODE = 0x1; Load cap
on OUTA/OUTB = 2nF
Frequency of drive clock at IO1 and IO2
pin
40
440
500
KHz
KHz
SPIRATE SPI bit rate
6.11 Typical Characteristics
3
4.5
40 KHz
40 KHz
256 KHz
500 KHz
750 KHz
1MHz
4
3.5
3
256 KHz
500 KHz
750 KHz
1MHz
2.5
2
2.5
2
1.5
1
1.5
1
0.5
0
0.5
0
5E-7
1E-5
1E-4 1E-3
VinRMS (V)
1E-2
1E-1
5E-7
VDD:5.0V
1E-5
1E-4 1E-3
VinRMS (V)
1E-2
1E-1
VDD:3.3V
Temp:25èC
LNA_GAIN=0x0; VOUT_SCALE_SEL=0x0
LOGAMP_DIS_FIRST=0x0; LOGAMP_DIS_LAST=0x0
Temp:25èC
LNA_GAIN=0x0; VOUT_SCALE_SEL=0x1
LOGAMP_DIS_FIRST=0x0; LOGAMP_DIS_LAST=0x0
图 6-1. Receive Signal Path Transfer Function for VDD = 3.3 V
图 6-2. Receive Signal Path Transfer Function for VDD = 5 V
3
3
-40èC
LNA_GAIN
25èC
0x01
0x11
0x00
0x10
2.5
2
2.5
2
125èC
1.5
1
1.5
1
0.5
0
0.5
0
5E-7
1E-5
1E-4
VinRMS (V)
1E-3
1E-2
1E-1
5E-7
1E-5
1E-4
VinRMS (V)
1E-3
1E-2
1E-1
VDD:3.3V
VDD:3.3V; Temp:25èC
Fc:256KHz
VOUT_SCALE_SEL=0x0
LOGAMP_DIS_FIRST=0x0; LOGAMP_DIS_LAST=0x0
Fc:256KHz
LNA_GAIN=0x0; VOUT_SCALE_SEL=0x0
LOGAMP_DIS_FIRST=0x0; LOGAMP_DIS_LAST=0x0
图 6-3. Receive Signal Path Transfer Function Across
图 6-4. Receive Signal Path Transfer Function Across LNA Gain
Temperature
Copyright © 2022 Texas Instruments Incorporated
8
Submit Document Feedback
Product Folder Links: TUSS4470
TUSS4470
ZHCSKL2A – DECEMBER 2019 – REVISED MAY 2022
www.ti.com.cn
6.11 Typical Characteristics (continued)
3
10
5
DEV_CTRL_2
0x00
0x40
0xC0
2.5
2
3dB
0
-3dB
1.5
1
-5
-40.00èC, 40KHz
-40.00èC, 256KHz
-40.00èC, 500KHz
25.00èC, 40KHz
25.00èC, 256KHz
25.00èC, 500KHz
125.00èC, 40KHz
125.00èC, 256KHz
125.00èC, 500KHz
-10
0.5
0
-15
1E-6
5E-7
VDD:3.3V
Fc:256KHz
1E-5
1E-4 1E-3
VinRMS (V)
1E-2
1E-1
1E-5
1E-4
1E-3
1E-2
1E-1
VinRMS (V)
LNA_GAIN=0x0
LOGAMP_DIS_FIRST=0x0; LOGAMP_DIS_LAST=0x0
Temp:25èC
图 6-6. Receive Signal Path Log Conformance Error With All
图 6-5. Receive Signal Path Transfer Function for Various
Stages Enabled
Logamp Stages Disabled
10
7.5
5
10
7.5
5
2.5
2.5
1dB
1dB
0
-2.5
-5
0
-2.5
-5
-40.00èC, 40KHz
-40.00èC, 256KHz
-40.00èC, 500KHz
25.00èC, 40KHz
25.00èC, 256KHz
25.00èC, 500KHz
125.00èC, 40KHz
125.00èC, 256KHz
125.00èC, 500KHz
-40.00èC, 40KHz
-40.00èC, 256KHz
-40.00èC, 500KHz
25.00èC, 40KHz
25.00èC, 256KHz
25.00èC, 500KHz
125.00èC, 40KHz
125.00èC, 256KHz
125.00èC, 500KHz
-7.5
-10
-7.5
-10
-12.5
-15
-12.5
-15
1E-6
1E-5
1E-4
1E-3
1E-2
1E-1
1E-5
1E-4
1E-3
VinRMS (V)
1E-2
1E-1
VinRMS (V)
LNA_GAIN=0x0
LOGAMP_DIS_FIRST=0x0; LOGAMP_DIS_LAST=0x1
LNA_GAIN=0x0
LOGAMP_DIS_FIRST=0x1; LOGAMP_DIS_LAST=0x1
图 6-7. Receive Signal Path Log Conformance Error With Last
图 6-8. Receive Signal Path Log Conformance Error With First
Stage Disabled
and Last Stage Disabled
2.15
6E+5
5E+5
BPF_HPF_FREQ
2.1
2.05
2
-40èC
0x00
0x04
0x08
0x0C
0x10
0x14
0x18
0x1C
0x20
0x24
0x28
0x2C
0x2F
4E+5
25èC
125èC
3E+5
1.95
1.9
2E+5
1.85
1.8
1.75
1.7
1E+5
7E+4
5E+4
1.65
1.6
1.55
4E+4
3E+4
5E+4 7E+4 1E+5
2E+5 3E+5
5E+5 7E+5
0x00 0x06 0x0C 0x12 0x18 0x1E 0x24 0x2A 0x30
BPF_HPF_FREQ Register Value
LNA_GAIN=0x0;
Vin Frequency (Hz)
VDD:3.3V
Temp:25èC
LNA_GAIN=0x0; VOUT_SCALE_SEL=0x0
LOGAMP_DIS_FIRST=0x0; LOGAMP_DIS_LAST=0x0
LOGAMP_DIS_FIRST=0x0; LOGAMP_DIS_LAST=0x0
图 6-10. Receive Signal Path Bandpass Filter frequency for
Various Register Settings
图 6-9. Receive Signal Path Bandpass Filter Transfer Function
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
9
Product Folder Links: TUSS4470
TUSS4470
ZHCSKL2A – DECEMBER 2019 – REVISED MAY 2022
www.ti.com.cn
6.11 Typical Characteristics (continued)
5E+4
9.25E+5
9E+5
1.6E+5
1.4E+5
1.2E+5
1E+5
8E+4
6E+4
4E+4
2E+4
0
4.8E+4
BPF_HPF_FREQ Value
0x00
0x2F
-40èC, 3.3V
-40èC, 5.0V
25èC, 3.3V
25èC, 5.0V
125èC, 3.3V
125èC, 5.0V
4.6E+4
8.75E+5
8.5E+5
8.25E+5
8E+5
4.4E+4
4.2E+4
4E+4
3.8E+4
3.6E+4
3.4E+4
3.2E+4
3E+4
7.75E+5
7.5E+5
7.25E+5
7E+5
6.75E+5
6.5E+5
6.25E+5
6E+5
2.8E+4
2.6E+4
2.4E+4
2.2E+4
2E+4
5.75E+5
5.5E+5
0x10 0x0E 0x0C 0x0A 0x08 0x06 0x04 0x02 0x00
BPF_FC_TRIM Register Value
VDD=3.3V
Temp=25èC
LNA_GAIN=0x0; VOUT_SCALE_SEL=0x0
LOGAMP_DIS_FIRST=0x0; LOGAMP_DIS_LAST=0x0
5E+4
1.5E+5 2.5E+5 3.5E+5 4.5E+5 5.5E+5 6.5E+5
Bandpass Filter Center Frequency (Hz)
LNA_GAIN=0x0
BPF_Q_SEL=0x0
LOGAMP_DIS_FIRST=0x0; LOGAMP_DIS_LAST=0x0
图 6-11. Receive Signal Path Bandpass Filter Center Frequency
Trim
图 6-12. Receive Signal Path Bandpass Filter Bandwidth for
Various Center Frequency Settings
3
3
LOGAMP_INT_ADJ
0x00
0x03
LOGAMP_SLOPE_ADJ
0x0F
0x0C
0x07
0x01
0x03
0x04
2.5
2
2.5
2
1.5
1
1.5
1
0.5
0
0.5
0
5E-7
1E-5
1E-4 1E-3
VinRMS (V)
1E-2
1E-1
5E-7
1E-5
1E-4 1E-3
VinRMS (V)
1E-2
1E-1
VDD:3.3V; Temp:25èC
Fc:256KHz
VDD:3.3V; Temp:25èC
Fc:256KHz
VOUT_SCALE_SEL=0x0
LOGAMP_DIS_FIRST=0x0; LOGAMP_DIS_LAST=0x0
VOUT_SCALE_SEL=0x0
LOGAMP_DIS_FIRST=0x0; LOGAMP_DIS_LAST=0x0
图 6-13. Receive Signal Path Transfer Function for Various
图 6-14. Receive Signal Path Transfer Function for Various
Slope Adjustments
Intercept Adjustments
Copyright © 2022 Texas Instruments Incorporated
10
Submit Document Feedback
Product Folder Links: TUSS4470
TUSS4470
ZHCSKL2A – DECEMBER 2019 – REVISED MAY 2022
www.ti.com.cn
7 Detailed Description
7.1 Overview
The TUSS4470 is a highly integrated driver and receiver IC designed especially for ultrasonic transducers
operating between the range of 40 KHz to 1 MHz. The TUSS4470 integrates an H-bridge to drive the transducer
directly. This is useful in applications where the receive transducer sensitivity is high and large driving voltage
is not required to create sufficient sound pressure level and where short distance measurements are needed.
The driver stage has flexible and configurable controls set through the SPI interface or through digital input
pins that can be driven by an external MCU. The receive stage consists of a logarithmic amplifier receive
chain. The logamp enables the TUSS4470 to have a wide dynamic input range. This enables applications
where objects with different physical properties must be detected with the same sensor. A key advantage of the
TUSS4470 is that it integrates a bandpass filter that can be tuned to the center frequency of the transducer.
A demodulated analog output representing the receive echo, the zero crossing of the input signal, and a
simple threshold crossing indicator enable a variety of end applications from complex object detection to simple
presence detection.
7.2 Functional Block Diagram
VDRV
VPWR
VDD
Control Logic
INTERFACE
NCS
SCLK
SDO
SDI
OUTA
OUTB
IO1
IO2
PULSE GENERATOR
Burst Pulses
DGND
GND
Output Driver
Echo INT
Threshold
Comp
Buffer
OUT4
Analog front-end
receiver
VOUT
OUT3
Zero Crossing
INP
INN
Log
Amp &
Demod
Low Pass
Filter
Band Pass
filter
LNA
FLT
SGND
7.3 Feature Description
7.3.1 Excitation Power Supply (VDRV)
The TUSS4470 device includes a current source which charges a capacitor connected to the VDRV pin. The
VDRV pin serves as the power supply for the integrated H-Bridge driver circuit The voltage on the VDRV pin
(VVDRV) is controlled by an internal voltage monitor which can be configured by the VDRV_VOLTAGE_LEVEL
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
11
Product Folder Links: TUSS4470
TUSS4470
ZHCSKL2A – DECEMBER 2019 – REVISED MAY 2022
www.ti.com.cn
bits. The current source is switched off after VDRV pin voltage crosses the configured VVDRV value. The
charging current (IVDRV) can be configured using VDRV_CURRENT_LEVEL bits.
In applications where VPWR can vary over a wide range, this allows the transducer drive voltage to be fixed for
every burst for a deterministic sound pressure level created by the transducer. This is possible only when the
minimum supply voltage on the VPWR pin is greater than the configured value of VVDRV
.
The VDRV regulation is disabled at device power up indicated by VDRV_HI_Z bit being set. To enable VDRV
this bit must be cleared. This feature enables applications where the the H-Bridge driver supply is connected to
an external power supply source through the VDRV pin.
备注
•
•
When VDRV pin is supplied from an external power supply, it must be ensured that all times
including during power up, VVPWR > VVDRV + 0.3 V to prevent any reverse current from VDRV pin
to VPWR pin. Alternatively a reverse current prevention diode can be used on VPWR pin as shown
in 图 8-1 (D1).
Very fast ramp-up rate on VPWR pin should be avoided to prevent damage to the device. If fast
ramp rates are possible, a series resistor between power supply and VPWR pin as shown in 图 8-1
(RPWR) is recommended.
After a burst is completed and during the long receive time (listen mode), the capacitor on VDRV pin will
discharge causing the charging current to turn on intermittently. This can inject switching noise which can be
picked by the analog front end as a spurious echo. To eliminate this noise, the DIS_VDRV_REG_LSTN bit can
be set. This disables charging of VDRV automatically after the burst is done. The VDRV charging current can be
turned on again by setting the VDRV_TRIGGER bit. Setting this bit may create a spurious echo which can be
ignored by the echo processing in the MCU. The VDRV_READY bit in DEV_STAT register can be monitored to
know when the required voltage level has been reached and the device is ready to generate a new burst. The
VDRV_TRIGGER bit must be un-set through SPI just before the start of burst and will have to be set again for
next charging cycle. If the VDRV_TRIGGER bit is not un-set before next burst cycle, the VDRV charging current
will not be automatically disabled after the burst even when DIS_VDRV_REG_LSTN is set. This functionality is
ignored when the VDRV_HI_Z bit is set.
7.3.2 Burst Generation
TUSS4470 has multiple modes to excite the transducer through OUTA and OUTB pins. For each of the modes,
the desired frequency of burst is supplied through an external clock on the IOx pins. This enables the user
to supply a highly precise clock calibrated to the center frequency of transducer to enable the highest sound
pressure level generation. These modes can be selected by the IO_MODE bits in the DEV_CTRL_3 register.
The burst mode is enabled first, then the start of burst (OUTA/OUTB changing states) happens at the next falling
edge of IO1 or IO2, depending on the mode selected. These modes are described below.
•
IO_MODE = 0: In this mode, the external clock for the transducer is applied at the IO2 pin and the burst
mode is enabled by setting the CMD_TRIGGER in the TOF_CONFIG register through SPI, as shown in 图
7-1. The device then expects a clock at IO2 pin to generate pulses on the OUTA/OUTB pins. The start of
burst happens from the first falling edge of IO2. The number of pulses are counted by counting falling edge to
next falling edge transitions on IO2 once the start of burst is triggered. The end of burst sequence is signaled
when the number of pulses defined in BURST_PULSE are sent, or when the CMD_TRIGGER = 0 is set
through SPI, whichever occurs earlier. TI recommends that IO2 is held high before burst enable to count the
number of pulses correctly. After the start of burst, the state of OUTA and OUTB pins are determined by IO1
and IO2 pins. A transition of CMD_TRIGGER from high to low to high again is required to initiate a new burst
sequence.
Copyright © 2022 Texas Instruments Incorporated
12
Submit Document Feedback
Product Folder Links: TUSS4470
TUSS4470
ZHCSKL2A – DECEMBER 2019 – REVISED MAY 2022
www.ti.com.cn
Start of
Burst
End of Burst
Burst Enable
Burst Disable
CMD_TRIGGER = 1
CMD_TRIGGER = 0
CMD_TRIGGER = 0
IO2
#1
#2
#3
#4
BURST_PULSE=0x04
图 7-1. IO_MODE 0 Description
•
IO_MODE = 1: In this mode, the external clock for the transducer is applied at the IO2 pin and the burst
mode is enabled when IO1 pin transitions low (see 图 7-2). The device then expects a clock at IO2 pin to
generate pulses on the OUTA/OUTB pins. The start of burst happens from the first falling edge of IO2. The
number of pulses are counted by counting falling edge to next falling edge transitions on IO2 once the start of
burst is triggered. End of burst sequence is signaled when the number of pulses defined in BURST_PULSE
are sent or IO1 transitions high, whichever occurs earlier. TI recommends that IO2 is held high before start
of burst to count the number of pulse correctly. After the start of burst, the state of OUTA and OUTB pins are
determined by IO1 and IO2 pins. A transition of IO1 from low to high to low again is required to initiate a new
burst sequence.
Start of
End of Burst
Burst Enable
Burst
Burst Disable
IO1
IO2
#1
#2
#3
#4
BURST_PULSE=0x04
图 7-2. IO_MODE 1 Description
•
IO_MODE = 2: In this mode both IO1 and IO2 are used to control OUTA and OUTB. The burst enable is
triggered when either IO1 or IO2 transitions from high to low. Start of burst (OUTA and OUTB changing
state) happens only at the next falling edge of IO1. 图 7-3 shows the case where a high-to-low transition on
IO2 is used to enable the burst. A burst is emulated when IO1 and IO2 are toggled in a non-overlapping
sequence. After the start of burst, the state of OUTA and OUTB pins are determined by IO1 and IO2 pins.
During a burst, if there is a condition where both IO1 and IO2 are high for more than half period of the
internal clock fINT_CLK (caused by differential delays due to PCB parasitics or MCU code), an end of burst
and burst mode disable will be triggered. Any falling edge just after this condition will be ignored to toggle
OUTA and OUTB as it would be considered as a new burst enable signal. A systematic condition of overlap
can cause a continuous end of burst trigger such that OUTA and OUTB do not toggle even though IO1 and
IO2 are toggling. TI recommends no overlap or minimum non-overlap between the IO1 and IO2 signals when
measured at the pins. BURST_PULSE has no effect in this mode.
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
13
Product Folder Links: TUSS4470
TUSS4470
ZHCSKL2A – DECEMBER 2019 – REVISED MAY 2022
www.ti.com.cn
End of Burst
&
Start of
Burst
Non Overlap
Burst Enable
Burst Disable
. . . . . . .
IO1
IO2
图 7-3. IO_MODE 2 Description
•
IO_MODE = 3: In this mode, burst enable and start of burst are both triggered by the falling edge of IO2. TI
recommends that IO2 pin is kept pulled up to VDD for this mode. The device then expects a clock at IO2
pin to generate pulses on the OUTA/OUTB pins (see 图 7-4). The number of pulses are counted by counting
falling edge to next falling edge transitions on IO2 once the start of burst is triggered. End of burst sequence
is signaled when the number of pulses defined in BURST_PULSE are sent. After end of burst, a blank-out
timer interval defined by the DRV_PLS_FLT_DT register is started to prevent triggering of a new start of burst
in the event if the IO2 pin is still toggling. After the start of burst, the state of OUTA and OUTB pins are
determined by IO1 and IO2 pins.
Start of Burst
&
End of Burst
&
Burst Enable
Burst Disable
IO2
#1
#2
#3
#4
BURST_PULSE=0x04
Blank Out Time
图 7-4. IO_MODE 3 Description
备注
•
•
For IO_MODE 0 and 1, by setting BURST_PULSE = 0, the device will generate continuous
burst pulses on OUTA and OUTB until the end of burst is signaled through SPI or the IO1 pin,
respectively. Continuous bursting is not available for IO_MODE=3.
A higher noise floor at the VOUT pin is expected in continuous mode where one transducer is used
to transmit burst signals and another transducer is used to receive, as the switching noise of the
digital IO pins can couple into the highly sensitive analog front end for the receive channel. This
also applies to the single transducer use case where a continuous clock is applied on IO2 pin when
the device is in indirect or listening mode.
•
•
The range for frequency of switching for the output drivers is given by fDRV_CLK parameter in the
Switching Characteristics table.
When the device is not in direct sensing or bursting mode, the device is always in indirect sensing
or listening mode.
7.3.2.1 Burst Generation Diagnostics
In IO_MODE 0, 1 and 3, a pulse number diagnostic is active after start of burst (not when the burst is enabled) to
monitor if the correct number of pulses (as set in BURST_PULSE) were generated before the end of burst was
signaled through SPI or the IO1 pin. A fault, if detected, is then reported through the PULSE_NUM_FLT bit.
The pulse duration after start of burst (not when the burst is enabled) is monitored to detect a stuck condition,
which will keep the FETs on OUTA or OUTB turned on. This can happen because of loss of external clock
Copyright © 2022 Texas Instruments Incorporated
14
Submit Document Feedback
Product Folder Links: TUSS4470
TUSS4470
ZHCSKL2A – DECEMBER 2019 – REVISED MAY 2022
www.ti.com.cn
or the driving signal on IO1 and IO2 pins being stuck in one state. The device expects to see a toggle on
IOx pins (based on IO_MODE) within the time period as defined in the DRV_PLS_FLT_DT register. If this
diagnostic triggers, it will force an end of burst. The fault is reported by setting the DRV_PULSE_FLT bit. If a
DRV_PULSE_FLT is set in IO_MODE 0, 1 and 3—and the programmed number of pulses were not sent before
end of burst—the PULSE_NUM_FLT will also be set.
备注
•
•
The DRV_PULSE_FLT bit is cleared when a new start of burst is triggered, when
DRV_PLS_FLT_DT = 0x7 is set, or if the device is put into Standby or Sleep mode.
The PULSE_NUM_FLT bit is cleared when a new start of burst is triggered, or if the device is put
into Standby or Sleep mode.
7.3.3 Direct Transducer Drive
图 7-5 shows the internal structure for driving an ultrasonic transducer connected directly to the device output
using an H-bridge output stage. This configuration drives 2 × VVDRV as the peak-to-peak voltage across the
transducer. The voltage on VDRV pin can be set as described in the Excitation Power Supply (VDRV) section.
IO2
VPWR
VDRV
IVDRV
+
œ
VVDRV
OUTA
Burst and Gate
Drive Control
OUTB
图 7-5. Direct Drive Configuration Using Internal FETs
图 7-5 shows the most common application case for the TUSS4470 device, in which the output driver pulses
the two half-bridges out-of-phase. It is also possible to use the driver in half-bridge mode by setting the
HALF_BRG_MODE bit. In this mode, only VVDRV is applied across the transducer. This mode is useful for
transducers where one side of the membrane must be always grounded.
The device can also be configured as a pre-driver to drive external FETs or BJTs to drive higher current and
voltage into the primary side of the transformer, as shown in 图 7-6, by setting the PRE_DRIVER_MODE bit. The
high-side and low-side devices are used to drive the external low-side drivers. The VDRV voltage level can be
configured to ensure that the OUTA and OUTB voltages do not violate the VGS or VBE specification for external
the FET or BJT, respectively. In the configuration shown in 图 7-6, it is possible to use a voltage (VBOOST)
which is higher than the supply of the system for generating higher voltage across the transducer.
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
15
Product Folder Links: TUSS4470
TUSS4470
ZHCSKL2A – DECEMBER 2019 – REVISED MAY 2022
www.ti.com.cn
Refer to Application and Implementation for an application diagram and information on how the polarity and state
of OUTA and OUTB pins are defined with respect to IO1 and IO2 pin states and other register settings.
IO1/IO2
VPWR
IVDRV
VBOOST
VDRV
+
œ
VVDRV
OUTA
OUTB
Burst and Gate
Drive Control
图 7-6. Center-Tap Transformer Drive Using External FETs
7.3.4 Analog Front End
OUT3
OUT4
HYS RANGE: ZC_CMP_HYST
Thr: ECHO_INT_THR_SEL
F. RANGE: BPF_HPF_FREQ
Q: 4; GAIN: 0.9 V/V
COMPARATOR
COMPARATOR
INP
GAIN: LNA_GAIN
DYN. RANGE: DRLOG
GAIN: LOGAMP_SLOPE_ADJ
BPF
VOUT
INN
F. RANGE: BPF_HPF_FREQ
GAIN: 1V/V
LNA
LOGAMP
BUFFER
FLT
HPF
KX: LOGAMP_INT_ADJ
Intercept Correction
图 7-7. TUSS4470 Analog Front-End Block Diagram
图 7-7 shows the analog front-end block diagram that can receive and condition the signals from the transducer
during listen mode. The received echo is first amplified with a fixed linear low-noise amplifier, followed by either a
Copyright © 2022 Texas Instruments Incorporated
16
Submit Document Feedback
Product Folder Links: TUSS4470
TUSS4470
ZHCSKL2A – DECEMBER 2019 – REVISED MAY 2022
www.ti.com.cn
bandpass filter or a high-pass filter to remove noise out of the expected signal band. After filtering the signal, the
signal is fed into a logarithmic amplifier. The output of the logarithmic amplifier is then buffered to the VOUT pin.
In 图 7-7, every block has the register name associated with it that can be used to configure the signal path. The
final equation for the signal path is given by 方程式 2:
)
.0# ® )$2( ® 8
8176 = )8176 ® 5..1) ® 20log10
l
+0p
+06.1) ® -:
(1)
where
•
•
•
•
•
•
•
GVOUT is set by the LOGAMP_SLOPE_ADJ bits.
SLLOG is slope of logarithmic amplifier as specified in the Receiver Characteristics table.
GLNA is set by the LNA_GAIN bits.
GBPF is typically 0.9V/V.
VIN is the input VINP
INTLOG is logarithmic amplifier intercept specified in the Receiver Characteristics table.
KX is the log intercept adjustment set by the LOGAMP_INT_ADJ bits.
The bandpass filter is critical for reducing noise to allow utilization of the complete dynamic range of the
logarithmic amplifier. The center frequency of the bandpass filter can be configured to be close the transducer
frequency which is set by the BPF_HPF_FREQ bits. 表 7-1 shows the nominal values for the BPF center
frequency corresponding to the BPF_HPF_FREQ register value. The TUSS4470 supports a wide range of
frequencies, therefore a factory trim is used to remove process variation for a particular pre-determined
frequency. It is possible that all other frequencies listed in 表 7-1 do not correspond exactly to value of
BPF_HPF_FREQ in a factory trim. The user can vary the value of the BPF_HPF_FREQ register around the
desired center frequency while actively bursting and observing the VOUT signal. The value with maximum
voltage at VOUT pin will the desired setting for the BPF_HPF_FREQ register.
表 7-1. Bandpass Filter Center Frequency Configuration
BPF_HPF_FREQ (HEX)
(BPF_FC_TRIM_FRC = 0)
BPF_Fc (KHz)
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
0x10
0x11
0x12
0x13
0x14
0x15
40.64
44.05
45.6
48.86
50.58
52.96
56.75
60.11
62.95
66.68
71.44
74.81
79.24
82.03
86.89
92.04
97.49
103.27
109.4
114.54
121.33
128.52
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
17
Product Folder Links: TUSS4470
TUSS4470
ZHCSKL2A – DECEMBER 2019 – REVISED MAY 2022
www.ti.com.cn
表 7-1. Bandpass Filter Center Frequency Configuration (continued)
BPF_HPF_FREQ (HEX)
(BPF_FC_TRIM_FRC = 0)
BPF_Fc (KHz)
0x16
0x17
0x18
0x19
0x1A
0x1B
0x1C
0x1D
0x1E
0x1F
0x20
0x21
0x22
0x23
0x24
0x25
0x26
0x27
0x28
0x29
0x2A
0x2B
0x2C
0x2D
0x2E
0x2F
134.58
142.55
151.01
159.94
167.48
177.41
185.77
196.78
206.05
218.26
228.54
244.89
256.43
271.63
284.43
301.28
319.13
338.14
353.97
374.95
397.16
408.17
420.7
455.63
472.03
500
The factory trim can be overridden by setting the BPF_FC_TRIM_FRC bit first and varying the BPF_FC_TRIM
bit after. This is useful in two ways:
•
If the factory trimmed bandpass filter center frequency is higher than the desired value for BPF_HPF_FREQ
= 0x00, or lower than desired value for BPF_HPF_FREQ = 0x2F, then BPF_FC_TRIM can be used to
recover the range.
•
This setting can also be used to extend the frequency range of the bandpass filter center frequency.
The BPF_FC_TRIM acts like an offset on top of the BPF_HPF_FREQ setting. 表 7-2 shows the nominal value of
center frequency when this offset is added to the minimum and maximum BPF_HPF_FREQ code. 图 6-11 shows
the measured data. For BPF_HPF_FREQ values greater than 0x08 and less than 0x27, varying BPF_FC_TRIM
keeping BPF_HPF_FREQ fixed is the same as setting BPF_FC_TRIM = 0x00 and varying BPF_HPF_FREQ to
find the optimum setting.
表 7-2. Bandpass Filter Center Frequency Range Extension
BPF_HPF_FREQ (hex) + BPF_FC_TRIM (hex)
BPF_Fc (KHz)
(BPF_FC_TRIM_FRC = 1)
0x00 + 0x8
0x00 + 0x9
0x00 + 0xA
0x00 + 0xB
0x00 + 0xC
27.48
29.44
30.83
31.19
32.65
Copyright © 2022 Texas Instruments Incorporated
18
Submit Document Feedback
Product Folder Links: TUSS4470
TUSS4470
ZHCSKL2A – DECEMBER 2019 – REVISED MAY 2022
www.ti.com.cn
表 7-2. Bandpass Filter Center Frequency Range Extension (continued)
BPF_HPF_FREQ (hex) + BPF_FC_TRIM (hex)
(BPF_FC_TRIM_FRC = 1)
BPF_Fc (KHz)
0x00 + 0xD
0x00 + 0xE
0x00 + 0xF
0x2F + 0x1
0x2F + 0x2
0x2F + 0x3
0x2F + 0x4
0x2F + 0x5
0x2F + 0x6
0x2F + 0x7
34.19
35.8
38.81
523.56
554.59
587.45
622.23
651.58
690.19
731.09
备注
•
•
The Q factor of the filter is specified in the Receiver Characteristics table, and can be selected by
the BPF_Q_SEL bits.
The bandpass filter can also be converted into a high-pass filter by setting the BPF_BYPASS bit
for transducer frequencies in the range above what is shown in 表 7-1. The corner frequency for
high-pass filter is also controlled by the BPF_HPF_FREQ bits.
•
BPF_Q_SEL and BPF_FC_TRIM have no effect when BPF_BYPASS = 1.
The logamp provides compression for large signal inputs and amplifies linearly small signal inputs. Logamp
simplifies system design to detect varying strengths of echoes that happens because of difference in reflectivity
of different types of objects and objects at different distances. It automatically adjusts its gain based on the input
signal level. The logamp also demodulates the incoming signal.
The logamp consists of multiple gain stages and range extension stages that are combined to give a logarithmic
response. The current consumption of the device can be reduced by turning off the either the first stage, the last
stage of the logamp, or both, by setting the LOGAMP_DIS_FIRST and LOGAMP_DIS_LAST bits. Disabling the
stages will reduce the input dynamic range on the lower side of the range (see 图 6-4). The pedestal noise floor
will be lower because the gain stages are disabled, but the minimum detectable signal value becomes higher
due to the reduced dynamic range. Depending on the received input signal strength, stages can be disabled to
get optimum object detection. For very small inputs, all stages should be enabled to get maximum input dynamic
range even though the noise floor is higher. 图 6-6, 图 6-7, and 图 6-8 show the effect on the log conformance
error when all stages are enabled, when the last stage is disabled, and when both first and last stages are
disabled. When stages are disabled, a lower error is obtained with a lower noise floor, but the input dynamic
range is reduced.
At the output of the logamp, the user can apply an adjustment to the intercept of the logamp curve. This is
denoted by the KX factor in 方程式 1. The intercept adjustment is controlled by the LOGAMP_INT_ADJ bits. 表
7-3 shows the nominal values of KX factor corresponding to register values, and 图 6-14 shows its effect on the
transfer function.
表 7-3. Logamp Intercept Adjustment
LOGAMP_INT_ADJ
KX
0x00
0x01
0x02
0x03
0x04
0x05
1
1.155
1.334
1.54
1.778
2.054
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
19
Product Folder Links: TUSS4470
TUSS4470
ZHCSKL2A – DECEMBER 2019 – REVISED MAY 2022
www.ti.com.cn
表 7-3. Logamp Intercept Adjustment (continued)
LOGAMP_INT_ADJ
KX
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
2.371
2.738
1
0.931
0.866
0.806
0.75
0.698
0.649
0.604
The output of the logamp is filtered using a low-pass filter to remove the high-frequency components and provide
a sufficient peak hold time for the demodulated envelope signal. The cut-off frequency of the low-pass filter is
set by the internal impedance of the FLT pin and the value of an external capacitor connected to the pin. As this
filter capacitance (CFLT) suppresses the high frequency fluctuations, it also slows down the response time of the
logamp. Higher CFLT capacitance will result in lower peak-to-peak voltage variations at VOUT, and slower rise
and fall times for the VOUT voltage to reach its maximum value for a given input signal. A nominal value can be
calculated using 方程式 3, and must be optimized depending on the application.
The output of the low-pass filter is buffered to the VOUT pin using an internal buffer. The buffer is designed
to support an ADC input of a MCU. It is possible to change output dynamic range of the VOUT buffer
using the VOUT_SCALE_SEL bit. Once the range is set, the gain of the VOUT buffer can be set by the
LOGAMP_SLOPE_ADJ bits. The slope variation of the receiver analog front end is show in 图 6-13.
Echo interrupt signal is available on the OUT4 pin that goes high when the signal on the VOUT pin crosses a
threshold as defined by the ECHO_INT_THR_SEL bits. As long as the VOUT signal is higher than this threshold,
the echo interrupt signal is held high. The signal goes low asynchronously when the VOUT signal drops below
the programmed threshold. This signal can be used to interrupt a MCU when an object has been detected. The
threshold value is also dependent on the setting of the VOUT_SCALE_SEL bit.
A zero-crossing signal is output at the OUT3 pin which can be used to validate the frequency of the received
echo signal to provide robustness against interference from other signals. This zero-crossing signal is derived
from the raw amplified input signal from a particular stage as it is being demodulated in the logamp block.
This function is disabled at device power up. but can be enabled by setting the ZC_CMP_EN bit. When
enabled, the ZC_CMP_STG_SEL bits are used to select which logamp gain stage is used to generate the zero
crossing signal while the ZC_CMP_HYST bits control the hysteresis of the zero-crossing comparator. The stage
selection to see the OUT3 pin toggling depends on the strength of signal received by the logamp and has to
be configured depending on the application. For large amplitude of input signal, a lower stage of the logamp
should be selected, whereas for lower amplitude signal, a higher stage should be selected. To avoid switching
noise generated by the toggling of the zero-crossing comparator when the ZC_EN_ECHO_INT bit is set, the
zero-crossing output will be only enabled while the echo interrupt signal is high.
7.4 Device Functional Modes
The device has four functional modes:
Sleep
Mode
Ultra-low current consumption sleep mode
In this mode, all major blocks of the device are disabled, including VDRV regulation. The
SPI interface is still active. This transition into and out of this mode is done using the
SLEEP_MODE_EN register bit. Upon issuing a command to exit this mode, the device transitions
to other modes only when the VDRV pin reaches the programmed regulation voltage.
Copyright © 2022 Texas Instruments Incorporated
20
Submit Document Feedback
Product Folder Links: TUSS4470
TUSS4470
ZHCSKL2A – DECEMBER 2019 – REVISED MAY 2022
www.ti.com.cn
Standby
Mode
Low current standby mode
In this state, the VDRV regulation is active, but other analog blocks are shut down to reduce
quiescent current consumption. The STDBY_MODE_EN bit is used to enter and exit this mode
through SPI. The device can transition very quickly from this state to one of the active states for
bursting and listening.
Listen
Mode
Default mode of the device
This is the default mode of the device when it is not in Sleep mode or Standby mode. In this mode,
there is no activity on the transmitter block and the device is actively listening for any ultrasonic
signals.
Burst
Mode
Mode in which the device is enabled to start a burst to drive the transducer
In this mode, the transmitter blocks are active and enabled to drive the transducer depending on
when the start of burst occurs. The receiving path is also active at the same time listening for
signals at the input. This mode is entered when a burst enable event occurs and exited when an
end of burst occurs as described in Burst Generation section.
图 7-8 shows an example of the transitions between the different modes of the device for IO_MODE = 0, where
the burst is activated through a SPI command and end of burst occurs as the number of programmed pulses are
sent.
CMD_TRIGGER
STDBY_MODE_EN
SLEEP_MODE_EN
DEVICE
MODES
BURST
LISTEN
LISTEN
BURST
SLEEP
STANDBY
Burst Enable
Burst Disable
64ms max
Burst Enable
VDRV in Regulation
图 7-8. Device Modes Timing Diagram
备注
•
•
The transition to standby or active mode (listen or burst) from power-up or sleep mode is done only
once the VDRV voltage crosses the programmed VDRV_VOLTAGE_LEVEL bit, or is higher 64 ms,
whichever occurs earlier.
In the case when VDRV is disabled, the device immediately transitions from power or sleep mode
to standby and active modes.
7.5 Programming
The primary communication between the IC and the external MCU is through an SPI bus that provides full-
duplex communications in a controller-peripheral configuration. The external MCU is always a SPI controller that
sends command requests on the SDI pin and receives device responses on the SDO pin. The device is always
a SPI peripheral device that receives command requests and sends responses to the external MCU over the
SDO line. The following lists the characteristics of the SPI:
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
21
Product Folder Links: TUSS4470
TUSS4470
ZHCSKL2A – DECEMBER 2019 – REVISED MAY 2022
www.ti.com.cn
•
•
The SPI is a 4-pin interface.
The frame size is 16 bits and is assigned as follows:
Controller-to-peripheral (MCU to
TUSS4470 over the SDI line)
1 RW bit, 6 bits for the register address, 1 ODD parity bit for entire
SPI frame, 8 bits for data
Peripheral-to-controller (TUSS4470 1 bit for Controller Parity error reporting during previous frame
to MCU over the SDO line)
reception, 6 bits for the status, 1 bit for ODD parity for entire SPI
frame, 8 bits for data
•
•
•
SPI commands and data are shifted with the MSB first and the LSB last.
The SDO line is sampled on the falling edge of the SCLK pin.
The SDI line is shifted out on the rising edge of the SCLK pin.
The SPI communication begins with the NCS falling edge and ends with the NCS rising edge. The NCS
high-level maintains the SPI peripheral-interface in the RESET state. The SDO output is in the tri-state condition.
The SPI does not support back-to-back SPI frame operation. After each SPI transfer the NCS pin must go from
low to high before the next SPI transfer can begin.
图 7-9 shows an overview of a complete 16-bit SPI frame.
15
MSB
10
9
8
7
6
5
4
3
2
1
0
14
13
12
11
NCS
SCLK
SDI
ADDR
3
ADDR
2
ADDR
1
ADDR
0
C
PRTY
DATA
6
DATA
3
DATA
2
DATA
0
ADDR
5
ADDR
4
DATA
7
DATA
5
DATA
4
DATA
1
R / W
SDO
STAT
2
P
PRTY
DATA
6
DATA
3
DATA
2
DATA
0
STAT
5
STAT
3
STAT
1
STAT
0
DATA
7
DATA
5
DATA
4
DATA
1
PRTY
ERR
STAT
4
Controller/Peripheral SPI Frame Parity
Bit
Register Address Bits
Read/Write Bit
Controller/Peripheral Data Bits
Peripheral Status Bits
图 7-9. 16-Bit SPI Frame
图 7-10 shows a SPI transfer sequence between the controller and the peripheral TUSS4470 device. When the
controller is writing a SPI frame, the parity error bit indicates if there was a parity error for the previous frame.
When the controller is transmitting the data for the SPI write, the peripheral echoes back register address that
was sent just before in the command.
SDI
C
PRTY
Register Address
DATA
W
CONTROLLER WRITE
SPI FRAME
Peripheral Echo Data
SDO
P
PRTY
PRTY
ERR
Status Bits
W
Register Address
0
SDI
C
PRTY
Register Address
0x00
DATA
R
CONTROLLER READ
SPI FRAME
SDO
P
PRTY
PRTY
ERR
Status Bits
图 7-10. SPI Transfer Sequence
Copyright © 2022 Texas Instruments Incorporated
22
Submit Document Feedback
Product Folder Links: TUSS4470
TUSS4470
ZHCSKL2A – DECEMBER 2019 – REVISED MAY 2022
www.ti.com.cn
The status bits are defined in 表 7-4:
表 7-4. SPI Interface Status Bits Description
STATUS BIT
DESCRIPTION
Set when VDRV power regulator has reached the programmed voltage level. This is also
indicated by VDRV_READY bit.
STAT 5 - VDRV_READY
Set if the burst sequence was terminated before completing the pulse number selected. This
is also indicated by PULSE_NUM_FLT bit.
STAT 4- PULSE_NUM_FLT
STAT 3 - DRV_PULSE_FLT
STAT 2 - EE_CRC_FLT
Set if there is a "stuck" fault detected during pulsing in a burst sequence. This is also
indicated by DRV_PULSE_FLT
Set if there is a CRC Error when loading internal EEPROM memory. This is also indicated by
EE_CRC_FLT bit.
Device State:
00 - LISTEN
01 - BURST
10 - STANDBY
11 - SLEEP
STAT <1:0> - DEV_STATE
7.6 Register Maps
This section lists the REG_USER registers that are part of the volatile memory that can be configured by the
MCU at power up or any time during the operation of the device. For register bits that are marked reserved, their
reset value should not be changed.
7.6.1 REG_USER Registers
表 7-5 lists the REG_USER registers. All register offset addresses not listed in 表 7-5 should be considered as
reserved locations and the register contents should not be modified.
表 7-5. REG_USER Registers
Address
0x10
0x11
Acronym
Register Name
Section
Go
BPF_CONFIG_1
BPF_CONFIG_2
DEV_CTRL_1
DEV_CTRL_2
DEV_CTRL_3
VDRV_CTRL
ECHO_INT_CONFIG
ZC_CONFIG
BURST_PULSE
TOF_CONFIG
DEV_STAT
Bandpass filter settings
Bandpass filter settings
Log-amp configuration
Log-amp configuration
Device Configuration
VDRV Regulator Control
Echo Interrupt Control
Zero Crossing configuration
Burst pulse configuration
Time of Flight Config
Fault status bits
Go
0x12
0x13
0x14
0x16
0x17
0x18
0x1A
0x1B
0x1C
0x1D
0x1E
Go
Go
Go
Go
Go
Go
Go
Go
Go
DEVICE_ID
Device ID
Go
REV_ID
Revision ID
Go
Complex bit access types are encoded to fit into small table cells. 表 7-6 shows the codes that are used for
access types in this section.
表 7-6. REG_USER Access Type Codes
Access Type
Read Type
R
Code
Description
R
Read
Write Type
W
W
Write
Reset or Default Value
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
23
Product Folder Links: TUSS4470
TUSS4470
ZHCSKL2A – DECEMBER 2019 – REVISED MAY 2022
www.ti.com.cn
表 7-6. REG_USER Access Type Codes (continued)
Access Type
Code
Description
-n
Value after reset or the default
value
7.6.1.1 BPF_CONFIG_1 Register (Address = 0x10) [reset = 0x0]
BPF_CONFIG_1 is shown in 表 7-7.
Return to the Summary Table.
表 7-7. BPF_CONFIG_1 Register Field Descriptions
Bit
Field
Type
Reset
Description
7
BPF_FC_TRIM_FRC
R/W
0x0
Override factor settings for Bandpass filter trim and control via
BPF_FC_TRIM register. Valid only when BPF_BYPASS = 0
0x0 = Factory trim
0x1 = Override Factory trim
6
BPF_BYPASS
R/W
R/W
0x0
0x0
Select between Bandpass filter or high pass filter
0x0 = BPF Enabled
0x1 = HPF Enabled (BPF Bypass)
5:0
BPF_HPF_FREQ
If BPF_BYPASS = 0:
Band pass filter center frequency. See "Bandpass filter center
frequency configuration" table
If BPF_BYPASS = 1:
High pass filter corner frequency
0x00 - 0x0F - 200kHz
0x10 - 0x1F - 400kHz
0x20 - 0x2F - 50kHz
0x30 - 0x3F - 100kHz
7.6.1.2 BPF_CONFIG_2 Register (Address = 0x11) [reset = 0x0]
BPF_CONFIG_2 is shown in 表 7-8.
Return to the Summary Table.
表 7-8. BPF_CONFIG_2 Register Field Descriptions
Bit
7:6
5:4
Field
Type
Reset
Description
RESERVED
BPF_Q_SEL
R
0x0
Reserved
R/W
0x0
Bandpass filter Q factor. Valid only when BPF_BYPASS = 0
0x0 = 4
0x1 = 5
0x2 = 2
0x3 = 3
3:0
BPF_FC_TRIM
R/W
0x0
Offset BPF_HPF_FREQ when BPF_FC_TRIM_FRC = 1:
BPF_HPF_FREQ = BPF_HPF_FREQ + BPF_FC_TRIM
See "Bandpass filter center frequency range extension" table.
7.6.1.3 DEV_CTRL_1 Register (Address = 0x12) [reset = 0x0]
DEV_CTRL_1 is shown in 表 7-9.
Return to the Summary Table.
Copyright © 2022 Texas Instruments Incorporated
24
Submit Document Feedback
Product Folder Links: TUSS4470
TUSS4470
ZHCSKL2A – DECEMBER 2019 – REVISED MAY 2022
www.ti.com.cn
表 7-9. DEV_CTRL_1 Register Field Descriptions
Bit
Field
Type
Reset
Description
7
LOGAMP_FRC
R/W
0x0
Override for factory settings for LOGAMP_SLOPE_ADJ and
LOGAMP_INT_ADJ
6:4
LOGAMP_SLOPE_ADJ
R/W
0x0
Slope or gain adjustment at the final output on VOUT pin. Slope
adjustment depends on the setting of VOUT_SCALE_SEL.
0x0 = 3.0× VOUT_SCALE_SEL+4.56×VOUT_SCALE_SEL V/V
0x1 = 3.1× VOUT_SCALE_SEL+4.71×VOUT_SCALE_SEL V/V
0x2 = 3.2× VOUT_SCALE_SEL+4.86×VOUT_SCALE_SEL V/V
0x3 = 3.3× VOUT_SCALE_SEL+5.01×VOUT_SCALE_SEL V/V
0x4 = 2.6× VOUT_SCALE_SEL+3.94×VOUT_SCALE_SEL V/V
0x5 = 2.7× VOUT_SCALE_SEL+ 4.10×VOUT_SCALE_SEL V/V
0x6 = 2.8× VOUT_SCALE_SEL+4.25×VOUT_SCALE_SEL V/V
0x7 = 2.9× VOUT_SCALE_SEL+4.4×VOUT_SCALE_SEL V/V
3:0
LOGAMP_INT_ADJ
R/W
0x0
Logamp Intercept adjustment. See "Logamp intercept adjustment"
table in specification for values.
7.6.1.4 DEV_CTRL_2 Register (Address = 0x13) [reset = 0x0]
DEV_CTRL_2 is shown in 表 7-10.
Return to the Summary Table.
表 7-10. DEV_CTRL_2 Register Field Descriptions
Bit
7
Field
Type
Reset
Description
LOGAMP_DIS_FIRST
LOGAMP_DIS_LAST
RESERVED
R/W
0x0
Disable first logamp stage to reduce quiescent current
Disable last logamp stage quiescent current
Reserved
6
R/W
R
0x0
0x0
0x0
3
2
VOUT_SCALE_SEL
R/W
Select VOUT scaling
0x0 = Select Vout gain to map output to 3.3 V
0x1 = Select Vout gain to map output to 5.0 V
1:0
LNA_GAIN
R/W
0x0
Adjust LNA Gain in V/V
0x0 = 15 V/V
0x1 = 10 V/V
0x2 = 20 V/V
0x3 = 12.5 V/V
7.6.1.5 DEV_CTRL_3 Register (Address = 0x14) [reset = 0x0]
DEV_CTRL_3 is shown in 表 7-11.
Return to the Summary Table.
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
25
Product Folder Links: TUSS4470
TUSS4470
ZHCSKL2A – DECEMBER 2019 – REVISED MAY 2022
www.ti.com.cn
表 7-11. DEV_CTRL_3 Register Field Descriptions
Bit
Field
Type
Reset
Description
4:2
DRV_PLS_FLT_DT
R/W
0x0
Driver Pulse Fault Deglitch Time.
In IO_MODE = 0 or IO_MODE = 1, DRV_PULSE_FLT will be set if
start of burst is triggered and IO2 pin has not toggled for greater than
deglitch Time.
In IO_MODE = 2, DRV_PULSE_FLT will be set if start of burst is
triggered and if IO1 or IO2 do not toggle a period longer than the
deglitch time except when both pins are high.
0x0 = 64 µs
0x1 = 48 µs
0x2 = 32 µs
0x3 = 24 µs
0x4 = 16 µs
0x5 = 8 µs
0x6 = 4 µs
0x7 = Check Disabled
1:0
IO_MODE
R/W
0x0
Configuration for low voltage IO pins.
0x0 = IOMODE 0
0x1 = IOMODE 1
0x2 = IOMODE 2
0x3 = IOMODE 3
7.6.1.6 VDRV_CTRL Register (Address = 0x16) [reset = 0x20]
VDRV_CTRL is shown in 表 7-12.
Return to the Summary Table.
表 7-12. VDRV_CTRL Register Field Descriptions
Bit
7
Field
Type
Reset
Description
RESERVED
R
0x0
Reserved
6
DIS_VDRV_REG_LSTN
R/W
0x0
0x1
Automatically disable VDRV charging in listen mode every time after
burst mode is exited given VDRV_TRIGGER =0x0.
0x0 = Do not automatically disable VDRV charging
0x1 = Automatically disable VDRV charging
5
VDRV_HI_Z
R/W
Turn off current source between VPWR and VRDV and disable
VDRV regulation.
0x0 = VDRV not Hi-Z
0x1 = VDRV in Hi-Z mode
4
VDRV_CURRENT_LEVEL R/W
VDRV_VOLTAGE_LEVEL R/W
0x0
0x0
Pull up current at VDRV pin
0x0 = 10 mA
0x1 = 20 mA
3:0
Regulated Voltage at VDRV pin Value is calculated as :
VDRV = VDRV_VOLTAGE_LEVEL + 5 [V]
7.6.1.7 ECHO_INT_CONFIG Register (Address = 0x17) [reset = 0x7]
ECHO_INT_CONFIG is shown in 表 7-13.
Return to the Summary Table.
表 7-13. ECHO_INT_CONFIG Register Field Descriptions
Bit
7:5
4
Field
Type
Reset
0x0
0x0
Description
Reserved
Enable echo interrupt comparator output
RESERVED
ECHO_INT_CMP_EN
R
R/W
Copyright © 2022 Texas Instruments Incorporated
26
Submit Document Feedback
Product Folder Links: TUSS4470
TUSS4470
ZHCSKL2A – DECEMBER 2019 – REVISED MAY 2022
www.ti.com.cn
表 7-13. ECHO_INT_CONFIG Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
3:0
ECHO_INT_THR_SEL
R/W
0x7
Threshold level to issue interrupt on OUT4 pin. Applied to Low pass
filter output.
If VOUT_SCALE_SEL=0x0 :
Threshold = 0.04 x ECHO_INT_THR_SEL + 0.4 [V]
If VOUT_SCALE_SEL=0x1:
Threshold = 0.06 x ECHO_INT_THR_SEL + 0.6 [V]
7.6.1.8 ZC_CONFIG Register (Address = 0x18) [reset = 0x14]
ZC_CONFIG is shown in 表 7-14.
Return to the Summary Table.
表 7-14. ZC_CONFIG Register Field Descriptions
Bit
7
Field
Type
R/W
R/W
R/W
Reset
Description
ZC_CMP_EN
ZC_EN_ECHO_INT
ZC_CMP_IN_SEL
0x0
Enable Zero Cross Comparator for Frequency detection
When set, provides ZC information only when object is detected
6
0x0
5
0x0
Zero Comparator Input Select
0x0 = INP - VCM
0x1 = INP - INN
4:3
2:0
ZC_CMP_STG_SEL
ZC_CMP_HYST
R/W
R/W
0x2
0x4
Zero Cross Comparator Stage Select
Zero Cross Comparator Hysteresis Selection
0x0 = 30 mV
0x1 = 80 mV
0x2 = 130 mV
0x3 = 180 mV
0x4 = 230 mV
0x5 = 280 mV
0x6 = 330 mV
0x7 = 380 mV
7.6.1.9 BURST_PULSE Register (Address = 0x1A) [reset = 0x0]
BURST_PULSE is shown in 表 7-15.
Return to the Summary Table.
表 7-15. BURST_PULSE Register Field Descriptions
Bit
Field
Type
Reset
Description
7
HALF_BRG_MODE
R/W
0x0
Use output driver in half-bridge mode.
When enabled, drive both high-side FET together and low-side FETs
together.
0x0 = Disable half-bridge mode
0x1 = Enable half bridge mode
6
PRE_DRIVER_MODE
BURST_PULSE
R/W
R/W
0x0
0x0
Pre-driver mode to drive external FETs
0x0 = Disable pre-driver mode
0x1 = Enable pre-driver mode
5:0
Number of burst pulses. REG_VALUE=0x00 enables continuous
burst mode
7.6.1.10 TOF_CONFIG Register (Address = 0x1B) [reset = 0x0]
TOF_CONFIG is shown in 表 7-16.
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
27
Product Folder Links: TUSS4470
TUSS4470
ZHCSKL2A – DECEMBER 2019 – REVISED MAY 2022
www.ti.com.cn
Return to the Summary Table.
表 7-16. TOF_CONFIG Register Field Descriptions
Bit
Field
Type
Reset
Description
7
SLEEP_MODE_EN
R/W
0x0
For entering or exiting sleep mode
0x0 = Wake up or exit Sleep Mode
0x1 = Enter sleep mode
6
STDBY_MODE_EN
R/W
0x0
For entering or exiting standby mode
0x0 = Exit Standby Mode
0x1 = Enter Standby mode
5:2
1
RESERVED
R
0x0
0x0
Reserved
VDRV_TRIGGER
R/W
Control charging of VDRV pin when DIS_VDRV_REG_LSTN = 1.
This has no effect when VDRV_HI_Z=0x1.
0x0 = Disable IVDRV
0x1 = Enable IVDRV
0
CMD_TRIGGER
R/W
0x0
For IO_MODE=0x0, control enabling of burst mode. Ignored for other
IO_MODE values.
0x0 = Disable burst mode
0x1 = Enable burst mode
7.6.1.11 DEV_STAT Register (Address = 0x1C) [reset = 0x0]
DEV_STAT is shown in 表 7-17.
Return to the Summary Table.
表 7-17. DEV_STAT Register Field Descriptions
Bit
7:4
3
Field
Type
Reset
Description
RESERVED
VDRV_READY
R
0x0
Reserved
R
0x0
VDRV pin voltage status
0x0 = VDRV is below configured voltage
0x1 = VDRV is equal or above configured voltage
2
1
0
PULSE_NUM_FLT
DRV_PULSE_FLT
EE_CRC_FLT
R
R
R
0x0
0x0
0x0
The Driver has not received the number of pulses defined by
BURST_PULSE
The Driver has been stuck in a single state in burst mode for a period
longer than delgitch time set by DRV_PLS_FLT_DT
CRC error for internal memory
7.6.1.12 DEVICE_ID Register (Address = 0x1D) [reset = X]
DEVICE_ID is shown in 表 7-18.
Return to the Summary Table.
表 7-18. DEVICE_ID Register Field Descriptions
Bit
Field
Type
Reset
Description
7:0
DEVICE_ID
R
X
Device ID: 0xB9
7.6.1.13 REV_ID Register (Address = 0x1E) [reset = 0x2]
REV_ID is shown in 表 7-19.
Return to the Summary Table.
Copyright © 2022 Texas Instruments Incorporated
28
Submit Document Feedback
Product Folder Links: TUSS4470
TUSS4470
ZHCSKL2A – DECEMBER 2019 – REVISED MAY 2022
www.ti.com.cn
表 7-19. REV_ID Register Field Descriptions
Bit
Field
REV_ID
Type
Reset
Description
7:0
R
0x2
Revision ID
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
29
Product Folder Links: TUSS4470
TUSS4470
ZHCSKL2A – DECEMBER 2019 – REVISED MAY 2022
www.ti.com.cn
8 Application and Implementation
备注
以下应用部分中的信息不属于 TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客 户应负责确定
器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。
8.1 Application Information
The TUSS4470 device must be paired with an external ultrasonic transducer. The TUSS4470 device drives
the transducer to generate an ultrasonic echo and applies logarithmic gain scaling to the received echo signal
in the analog front end. The transducer should be chosen based on the resonant frequency, input voltage
requirements, sensitivity, beam pattern, and decay time. The TUSS4470 device is flexible enough to meet most
transducer requirements by adjusting the driving frequency, driving current limit, and center frequency of the
band-pass filter. The only available interface to configure the device registers is SPI. During the burst-and-listen
cycles, an external ADC or analog receiver should be used to capture the echo envelope from the VOUT pin to
compute time of flight (ToF), distance, amplitude, and/or width of the return echo.
8.2 Typical Application
D1
RPWR
VIN
>
CPWR1
MCU
GPIO
OUTA
VDRV
IO2
IO1
GPIO
GPIO
OUT3
OUT4
NCS
OUTB
FLT
CPWR2
SDO
SDI
CFLT
SPI
RINP
SCLK
VOUT
CINP
INP
INN
ADC
CINN
LDO
VDD
CVDD
图 8-1. TUSS4470 Application Diagram
Copyright © 2022 Texas Instruments Incorporated
30
Submit Document Feedback
Product Folder Links: TUSS4470
TUSS4470
ZHCSKL2A – DECEMBER 2019 – REVISED MAY 2022
www.ti.com.cn
表 8-1. Recommended Component Values for Typical Applications
DESIGNATOR
VALUE
COMMENT
Optional (to limit fast voltage transient on VPWR pin during power
up)
RPWR
10 Ω
R(INP)
CPWR1
CPWR2
CVDD
CINP
200Ω (1/4 Watt)
50V, 100nF
40V, 2µF
Optional higher value for EMI/ESD robustness
>5V, 10nF
40V, 330pF
Use equation below to estimate value of CINN depending on the burst
frequency
1
CINN
>5V, CINN
%
+00
=
B
2 ® è ® 150 ® l &48_%.-p
4
(2)
Use equation below to estimate value of CFLT depending on the burst
frequency . Value has to be optimized for application depending on
noise and response time requirements.
CFLT
5V, CFLT
25
%
(.6
=
2 ® è ® k6250 ® B&48_%.-o
(3)
D1
1N4001 or equivalent
Optional for reverse supply and reverse current protection.
Example devices for low-frequency range:
Closed top: 40 kHz: PUI Audio UTR-1440K-TT-R
Open top: muRata MA40H1S-R, SensComp 40LPT16, Kobitone
255-400PT160-ROX
XDCR (transducer)
Example devices for high-frequency range:
Closed top: 300 kHz: Murata MA300D1-1
8.2.1 Transducer Drive Configuration Options
For different transducer drive configurations, the TUSS4470 supports multiple configurations to accommodate
specific system needs as shown in 图 8-2. The typical application diagram in 图 8-1 is considered as "Case 1".
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
31
Product Folder Links: TUSS4470
TUSS4470
ZHCSKL2A – DECEMBER 2019 – REVISED MAY 2022
www.ti.com.cn
HALF_BRG_MODE = 0
HALF_BRG_MODE = 1
VPWR
VDRV
VPWR
VDRV
OUTA
OUTB
OUTA
OUTB
1
2
VPWR/VEXT
VPWR/VEXT
VPWR
VPWR
VDRV
OUTA
VDRV
OUTA
OUTB
OUTB
4
3
图 8-2. TUSS4470 Transducer Drive Options
The behavior of the internal FETs in the TUSS4470 device is different for each configuration in 图 8-2. 表 8-2
and 表 8-3 shows the relationship between the IOx pins and the state of the OUTA and OUTB pins for different
register settings.
表 8-2. OUTA / OUTB Pin Behavior for Different Drive Configurations in IO MODE 2
IO MODE 2
PRE_DRI
VER_MO
DE
START OF
BURST
HALF_BRG_M
ODE
IO1
IO2
OUTA
OUTB
APPLICATION CASE
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
GND
GND
VVDRV
Hi-Z
GND
VVDRV
GND
GND
Hi-Z
YES
CASE 1
NO
Hi-Z
YES
NO
VVDRV
GND
Hi-Z
VVDRV
GND
Hi-Z
CASE 2
CASE 3
CASE 4
GND
GND
VVDRV
GND
GND
VVDRV
GND
GND
GND
VVDRV
GND
GND
GND
VVDRV
GND
GND
YES
NO
YES
NO
Copyright © 2022 Texas Instruments Incorporated
32
Submit Document Feedback
Product Folder Links: TUSS4470
TUSS4470
ZHCSKL2A – DECEMBER 2019 – REVISED MAY 2022
www.ti.com.cn
表 8-3. OUTA / OUTB Pin Behavior for Different Drive Configurations in IO MODE 0, IO MODE 1 and IO
MODE 3
IO MODE 0, IO MODE 1, IO MODE 3
CMD_TRIG
PRE_DRI
VER_MO
DE
IO1
(IO MODE
1)
START OF
BURST
HALF_BRG_M
ODE
GER
(IO MODE
0)
IO2
OUTA
OUTB
APPLICATION CASE
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
NO
Hi-Z
GND
CASE 1
GND
VVDRV
GND
YES
NO
VVDRV
Hi-Z
Hi-Z
CASE 2
CASE 3
CASE 4
GND
GND
YES
NO
VVDRV
VVDRV
GND
GND
GND
VVDRV
GND
YES
NO
VVDRV
GND
GND
GND
GND
YES
VVDRV
VVDRV
8.2.1.1 Design Requirements
For this design example, use the parameters listed in 表 8-4 as the input and operating parameters. All other
device settings can be assumed to be factory default.
表 8-4. Design Parameters
DESIGN PARAMETER
Input voltage range
EXAMPLE VALUE
5 to 36 V
Input voltage recommended
Transducer driving voltage
Transducer frequency
5 V or 20 V
5 VAC or 20 VAC
40 kHz or 400 kHz
16
Transducer pulse count
8.2.1.2 Detailed Design Procedure
To begin the design process, determine the following:
•
Transducer
– Transducer driving voltage
– Transducer resonant frequency
– Transducer pulse count maximum
8.2.1.2.1 Transducer Driving Voltage
When a voltage is applied to piezoelectric ceramics, mechanical distortion is generated according to the voltage
and frequency. The mechanical distortion is measured in units of sound pressure level (SPL) to indicate the
volume of sound, and can be derived from a free-field microphone voltage measurement using 方程式 4.
V
≈
∆
«
’
÷
◊
(MIC)
3.4 mV
SPL (db) = 20 ì log
PO
(4)
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
33
Product Folder Links: TUSS4470
TUSS4470
ZHCSKL2A – DECEMBER 2019 – REVISED MAY 2022
www.ti.com.cn
where
•
•
V(MIC) is the measured sensor sound pressure (mVRMS).
PO is a referenced sound pressure of 20 μPa.
The SPL does not increase indefinitely with the driving voltage. After a particular driving voltage, the amount
of SPL that a transducer can generate becomes saturated. A transducer is given a maximum driving voltage
specification to indicate when the maximum SPL is generated. Driving the transducer beyond the maximum
driving voltage makes the ultrasonic module less power-efficient and can damage or decrease the life
expectancy of the transducer.
8.2.1.2.2 Transducer Driving Frequency
The strength of ultrasonic waves propagated into the air attenuate proportionally with distance. This attenuation
is caused by diffusion, diffraction, and absorption loss as the ultrasonic energy transmits through the medium of
air. As shown in 图 8-3, the higher the frequency of the ultrasonic wave, the larger the attenuation rate and the
shorter the distance the wave reaches.
0
-10
-20
-30
-40
-50
-60
-70
200 kHz
80 kHz
40 kHz
-80
-90
20 kHz
-100
0.1
1
Distance (m)
10
D008
图 8-3. Attenuation Characteristics of Sound Pressure by Distance
An ultrasonic transducer has a fixed resonant center frequency with a typical tolerance of ±2%. The lower
frequency range of 30 kHz to 100 kHz is the default operating range for common long range applications for a
step resolution of 1 cm and typical range of 30 cm to 5 m. The upper frequency range of 100 kHz to 1000 kHz is
reserved for high-precision applications with a step resolution of 1 mm and a typical range of 5 cm to 1 m.
8.2.1.2.3 Transducer Pulse Count
The pulse count determines how many alternating periods are applied to the transducer by the complementary
low-side drivers and determines the total width of the ultrasonic ping that was transmitted. The larger the width
of the transmitted ping, the larger the width of the returned echo signature of the reflected surface and the more
resolution available to set a stable threshold. A disadvantage of a large pulse count is a large ringing-decay
period, which limits how detectable objects are at short distances.
Select a pulse count based on the minimum object distance requirement. If short-distance object detection is not
a priority, a high pulse count is not a concern. Certain transducers can be driven continuously while others have
a limit to the maximum driving-pulse count. Refer to the specification for the selected transducer to determine if
the pulse count must be limited.
Copyright © 2022 Texas Instruments Incorporated
34
Submit Document Feedback
Product Folder Links: TUSS4470
TUSS4470
ZHCSKL2A – DECEMBER 2019 – REVISED MAY 2022
www.ti.com.cn
8.2.1.3 Application Curves
图 8-4 and 图 8-5 show the typical ranging performance of a 40-kHz, closed-top transducer under nominal
operating conditions as indicated in 表 8-4. The targeted object is a PVC pole measuring 1000 mm in
height and 75 mm in diameter. Notable device settings: LNA_GAIN = 0x0; VOUT_SCALE_SEL = 0x0;
LOGAMP_DIS_FIRST = 0x0; LOGAMP_DIS_LAST = 0x1.
3
2.5
2
3
2.5
2
1m
2m
3m
4m
1m
2m
3m
4m
5m
6m
1.5
1
1.5
1
0.5
0
0.5
0
0
6
12
18
Time (ms)
24
30
36
0
6
12
18
Time (ms)
24
30
36
图 8-4. TUSS4470 40 kHz Ranging at 5-V Driver
图 8-5. TUSS4470 40 kHz Ranging at 20-V Driver
With Last Log-Amp Stage Disabled
With Last Log-Amp Stage Disabled
图 8-6 and 图 8-7 show the typical ranging performance of a 400-kHz, closed-top transducer under nominal
operating conditions as indicated in 表 8-4. The targeted object is an aluminum pole measuring 100 mm
in height and 10 mm in diameter. Notable device settings: LNA_GAIN = 0x0; VOUT_SCALE_SEL = 0x0;
LOGAMP_DIS_FIRST = 0x0; LOGAMP_DIS_LAST = 0x0.
3
2.5
2
3
2.5
2
50mm
50mm
100mm
200mm
300mm
400mm
100mm
200mm
300mm
400mm
1.5
1
1.5
1
0.5
0
0.5
0
0
0.5
1
1.5
Time (ms)
2
2.5
3
0
0.5
1
1.5
Time (ms)
2
2.5
3
图 8-6. TUSS4470 400 kHz Ranging at 5-V Drive
图 8-7. TUSS4470 400 kHz Ranging at 20-V Driver
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
35
Product Folder Links: TUSS4470
TUSS4470
ZHCSKL2A – DECEMBER 2019 – REVISED MAY 2022
www.ti.com.cn
9 Power Supply Recommendations
The TUSS4470 device is designed to operate from two independent supplies, a driver supply and a regulated
supply.
The driver input voltage supply (VPWR) range can operate from 5 V to 36 V. In applications where the
TUSS4470 device may be exposed to battery transients and reverse battery currents, use external component-
safeguards, such as component D1 or parallel TVS diodes, to help protect the device. If the input supply is
placed more than a few inches from the TUSS4470 device, additional bulk capacitance may be required in
addition to the ceramic bypass capacitors near the VPWR pin. In the event both the VDRV and pre-driver modes
is enabled, limit the VPWR voltage to the maximum rated voltage of the externally driven transistor’s gate-source
or base-emitter rating. The electrolytic capacitor at the VDRV pin is intended to act as a fast discharge capacitor
during the bursting stage of the TUSS4470 device. The H-bridge high-side voltage can be supplied with an
independent voltage at the VDRV pin to isolate the driver from VPWR, but must remain within the specified
maximum voltage rating of the VDRV, OUTA, and OUTB outputs. If the H-bridge high-side voltage is to be
supplied by an independent source, VDRV should be disabled.
The regulated supply (VDD) is used as the supply reference for the analog front end, filtering, and analog
output blocks, so this supply should be stable for maximum performance. TI recommends using an LDO or other
regulated external power source with bypass capacitor placed closely to the VDD pin. As VDD becomes less
stable, the noise floor of the VOUT signal will increase, and result in a loss of long range object detection as a
consequence.
To prevent damage to the device, always avoid hot-plugging or providing instantaneous power at the VPWR
and VDRV pins at start-up, unless these pins are properly protected with an RC filter or TVS diode to minimize
transient effects. VPWR must always be equal to or greater than the value present at VDRV.
Copyright © 2022 Texas Instruments Incorporated
36
Submit Document Feedback
Product Folder Links: TUSS4470
TUSS4470
ZHCSKL2A – DECEMBER 2019 – REVISED MAY 2022
www.ti.com.cn
10 Layout
10.1 Layout Guidelines
A minimum of two layers is required to accomplish a small-form factor ultrasonic module design. The layers
should be separated by analog and digital signals. The pin map of the device is routed such that the power
and digital signals are on the opposing side of the analog driver and receiver pins. Consider the following best
practices for TUSS4470 device layout in order of descending priority:
•
Separating the grounding types is important to reduce noise at the AFE input of the TUSS4470. In particular,
the transducer sensor ground, supporting driver, and return-path circuitry should have a separate ground
before being connected to the main ground. Separating the sensor and main grounds through a ferrite bead
is best practice, but not require. A copper-trace or 0-Ω short is also acceptable when bridging grounds.
The analog return path pins, INP and INN, are most susceptible to noise and therefore should be routed as
short and directly to the transducer as possible. Ensure the INN capacitor is close to the pin to reduce the
length of the ground wire.
The analog output pin trace should be routed as short and directly to an external ADC or microcontroller input
to avoid signal-to-noise losses due to parasitic-effects or noise coupling onto the trace from external radiating
aggressors.
In applications where protection from an ESD strike on the case of the transducer is important, ground routing
of the capacitor on the INN pin should be separate from the device ground and connected directly with the
shortest possible trace to the connector ground.
The analog drive pins can be high-current, high-voltage, or both and therefore the design limitation of the
OUTA and OUTB pins is based on the copper trace profile. The driver pins are recommended to be as short
and direct as possible when driving a transducer with a high-voltage.
•
•
•
•
•
•
The decoupling capacitors for the VDD and VPWR pins should be placed as close to the pins as possible.
Any digital communication should be routed away from the analog receiver pins. TXD, RXD, SCLK, NCS,
IO1, IO2, OUT3, and OUT4 pins should be routed on the opposite side of the PCB, away from of the analog
signals.
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
37
Product Folder Links: TUSS4470
TUSS4470
ZHCSKL2A – DECEMBER 2019 – REVISED MAY 2022
www.ti.com.cn
10.2 Layout Example
Charging Capacitor
Legend
Copper Trace - Top
2
F
Power
Copper Trace - Bottom
Via
— +
To Controller
OUT3 1
15 OUTA
14 GND
13 SGND
12 INP
To Controller
DGND 2
NCS 3
SCLK 4
SDI 5
Thermal Pad
To Controller
To Controller
To Controller
11 INN
Transducer
To Controller
To/From Controller
To/From Controller
To ADC
From LDO
图 10-1. TUSS4470 Layout Example
Copyright © 2022 Texas Instruments Incorporated
38
Submit Document Feedback
Product Folder Links: TUSS4470
TUSS4470
ZHCSKL2A – DECEMBER 2019 – REVISED MAY 2022
www.ti.com.cn
11 Device and Documentation Support
11.1 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
11.2 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅 TI
的《使用条款》。
11.3 Trademarks
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
11.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
11.5 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
39
Product Folder Links: TUSS4470
PACKAGE OPTION ADDENDUM
www.ti.com
2-Dec-2021
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TUSS4470TRTJR
TUSS4470TRTJT
ACTIVE
ACTIVE
QFN
QFN
RTJ
RTJ
20
20
3000 RoHS & Green
250 RoHS & Green
NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-25 to 105
-25 to 105
USS4470
USS4470
NIPDAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
2-Dec-2021
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
2-Dec-2021
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TUSS4470TRTJR
TUSS4470TRTJT
QFN
QFN
RTJ
RTJ
20
20
3000
250
330.0
180.0
12.4
12.4
4.25
4.25
4.25
4.25
1.15
1.15
8.0
8.0
12.0
12.0
Q2
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
2-Dec-2021
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TUSS4470TRTJR
TUSS4470TRTJT
QFN
QFN
RTJ
RTJ
20
20
3000
250
367.0
210.0
367.0
185.0
35.0
35.0
Pack Materials-Page 2
GENERIC PACKAGE VIEW
RTJ 20
4 x 4, 0.5 mm pitch
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224842/A
www.ti.com
DATA BOOK
PACKAGE OUTLINE
LEADFRAME EXAMPLE
4222370
DRAFTSMAN:
DATE:
DATE:
DATE:
DATE:
DATE:
DATE:
DATE:
H. DENG
09/12/2016
09/12/2016
09/12/2016
DESIGNER:
CHECKER:
ENGINEER:
APPROVED:
RELEASED:
CODE IDENTITY
NUMBER
H. DENG
01295
SEMICONDUCTOR OPERATIONS
V. PAKU & T. LEQUANG
T. TANG
ePOD, RTJ0020D / WQFN,
20 PIN, 0.5 MM PITCH
09/12/2016
10/06/2016
10/24/2016
E. REY & D. CHIN
WDM
SCALE
SIZE
REV
PAGE
OF
TEMPLATE INFO:
4219125
A
15X
04/07/2016
A
EDGE# 4218519
PACKAGE OUTLINE
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
RTJ0020D
A
4.1
3.9
B
PIN 1 INDEX AREA
4.1
3.9
DIM A
OPT 1
(0.1)
OPT 2
(0.2)
C
0.8 MAX
SEATING PLANE
0.08 C
0.05
0.00
16X 0.5
(A) TYP
6
10
EXPOSED
THERMAL PAD
5
11
SYMM
ꢀꢁꢂꢃꢁꢄ
4X 2
21
15
1
0.5
0.3
20X
PIN 1 ID
(OPTIONAL)
20
16
SYMM
0.29
0.19
0.1
20X
C A B
C
0.05
4219125 / A 10/2016
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
WQFN - 0.8 mm max height
RTJ0020D
PLASTIC QUAD FLATPACK - NO LEAD
2.7)
SYMM
20
16
20X (0.6)
1
20X (0.24)
15
(1.1)
TYP
21
SYMM
(3.8)
(0.5)
TYP
ꢅꢃꢁꢀꢆꢇ7<3
VIA
5
11
(R0.05)
TYP
6
10
(3.8)
LAND PATTERN EXAMPLE
SCALE: 20X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
NON SOLDER MASK
SOLDER MASK
DEFINED
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4219125 / A 10/2016
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments
literature number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their
locations shown on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
WQFN - 0.8 mm max height
RTJ0020D
PLASTIC QUAD FLATPACK - NO LEAD
SYMM
(0.69)
TYP
20
16
20X (0.6)
1
20X (0.24)
15
(0.69)
TYP
SYMM
(3.8)
(0.5)
TYP
5
11
(R0.05)
TYP
21
6
10
4X ( 1.19)
(3.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD
78% PRINTED COVERAGE BY AREA
SCALE: 20X
4219125 / A 10/2016
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations..
www.ti.com
R E V I S I O N S
REV
A
DESCRIPTION
ECR
DATE
ENGINEER / DRAFTSMAN
T. TANG / H. DENG
RELEASE NEW DRAWING
2160736
10/24/2016
SCALE
SIZE
REV
PAGE
4219125
5 OF 5
A
NTS
A
重要声明和免责声明
TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，
不保证没有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担
保。
这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验
证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。
这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。
您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成
本、损失和债务，TI 对此概不负责。
TI 提供的产品受 TI 的销售条款或 ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI 提供这些资源并不会扩展或以其他方式更改
TI 针对 TI 产品发布的适用的担保或担保免责声明。
TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE
邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2022，德州仪器 (TI) 公司
相关型号：
TUSS4470TRTJR
具有对数放大器的直接驱动超声波传感器 IC | RTJ | 20 | -25 to 105Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
TI
TUSS4470TRTJT
具有对数放大器的直接驱动超声波传感器 IC | RTJ | 20 | -25 to 105Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
TI
TUW10J100E
RES 100 OHM 10W 5% AXIALWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
OHMITE
TUW10J150E
RES 150 OHM 10W 5% AXIALWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
OHMITE
TUW10J1R0E
RES 1 OHM 10W 5% AXIALWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
OHMITE
TUW10J20RE
RES 20 OHM 10W 5% AXIALWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
OHMITE
TUW10J2R0E
RES 2 OHM 10W 5% AXIALWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
OHMITE
TUW10J2R7E
RES 2.7 OHM 10W 5% AXIALWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
OHMITE
TUW10J390E
RES 390 OHM 10W 5% AXIALWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
OHMITE
TUW10J3R0E
RES 3 OHM 10W 5% AXIALWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
OHMITE
TUW10J3R9E
RES 3.9 OHM 10W 5% AXIALWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
OHMITE
TUW10J470E
RES 470 OHM 10W 5% AXIALWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
OHMITE
©2020 ICPDF网 联系我们和版权申明