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TVB1440

ZHCSD29A –NOVEMBER 2014–REVISED NOVEMBER 2014

TVB1440 具有均衡功能的 4 通道视频转接驱动器

ECCN：3E991

1 特性

3 说明

1

•

兼容电视聚合视频信号发送设备

TVB1440 是一款针对电视应用的 4 通道转接驱动器信

号调节器，能够实现 TV 芯片组与 TCON 板之间的信

号完整性。 I²C 控制可在较宽范围内灵活配置器件以实

现最优信号调节，从而使视频输出设备与接收设备之间

的视频数据链路具备高保真性。 TVB1440 具备出色的

去抖能力，可延长视频输出设备与接收设备之间的距

离。

兼容 FPD-Link II 接口

适合于数字电视芯片组和 TCON 板

四通道转接驱动器，支持 600Mbps 至 5Gbps 范围

内的数据速率

•

采用 3.3V 和 1.1V 电源，可实现低功耗运行

4 通道操作下的运行功耗为 175mW

2mW 关断功耗

该器件可通过 I2C 对接收均衡功能进行多种可选控

制，以补偿其输入端走线或电缆的严重损耗，从而提升

输出信号的视觉效果。每个通道中的发送器有 4 种预

加强级别设置和 4 种输出电压摆幅级别设置，可使从

TVB1440 发送到下游接收器的视频信号达到最佳效

果。

高度可配置的输入均衡功能，有 8 种控制设置

–

0dB 至 15dB

4 种预加强控制设置

0、3、6 和 9dB

4 种输出电压摆幅控制设置

350、500、700 和 1000mV

•

–

通过 I²C 控制来配置器件以实现最佳性能

TVB1440 针对功耗要求较高的应用进行了优化。

TVB1440 不仅运行功耗较低，而且在数据链路输入端

配有一个活动检测电路，当不存在有效输入信号时会切

换至低功耗输出禁用模式。可以根据需要禁用此活动

检测电路。该器件还具有一个关断模式，可使功耗降

至 2mW。

•

扩展温度范围为 -40℃ 至 85°C

2kV 人体模型 (HBM) 和 500V 充电器件模型

(CDM) 静电放电 (ESD) 保护

•

48 引脚四方扁平无引线 (QFN) 封装 (7mm x 7mm)

2 应用

器件信息⁽¹⁾

•

数字电视

器件型号

TVB1440

封装

VQFN (48)

封装尺寸（标称值）

摄像机

7.00mm x 7.00mm

吞吐量要求较高的视频接口

(1) 如需了解所有可用封装，请见数据表末尾的可订购产品附录。

4 简化电路原理图

Driver

EQ

CH0

CH1

TVB1440

EQ

TCON

TVB1440

SoC

Driver

CH2

CH3

I2C

Driver

1

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

English Data Sheet: SLASE51

ECCN：3E991

TVB1440

ZHCSD29A –NOVEMBER 2014–REVISED NOVEMBER 2014

www.ti.com.cn

8.3 Feature Description................................................... 9

8.4 Device Functional Modes.......................................... 9

8.5 Programming............................................................. 9

8.6 Register Maps......................................................... 13

Application and Implementation ........................ 14

9.1 Application Information............................................ 14

1

2

3

4

5

6

7

特性.......................................................................... 1

应用.......................................................................... 1

说明.......................................................................... 1

简化电路原理图........................................................ 1

修订历史记录 ........................................................... 2

Pin Configuration and Functions......................... 3

Specifications......................................................... 4

7.1 Absolute Maximum Ratings ...................................... 4

7.2 Handling Ratings ...................................................... 4

7.3 Recommended Operating Conditions....................... 4

7.4 Thermal Information.................................................. 5

7.5 Electrical Characteristics........................................... 5

7.6 Timing Requirements ............................................... 5

7.7 Switching Characteristics.......................................... 6

7.8 Typical Characteristics.............................................. 7

Detailed Description .............................................. 8

8.1 Overview ................................................................... 8

8.2 Functional Block Diagram ......................................... 8

9

10 Power Supply Recommendations ..................... 19

10.1 Power-Up Sequence............................................. 19

10.2 Power-Down Sequence ........................................ 19

11 Layout................................................................... 20

11.1 Layout Guidelines ................................................. 20

12 器件和文档支持 ..................................................... 22

12.1 商标....................................................................... 22

12.2 静电放电警告......................................................... 22

12.3 Export Control Notice............................................ 22

12.4 术语表 ................................................................... 22

13 机械封装和可订购信息 .......................................... 22

8

5 修订历史记录

Changes from Original (November 2014) to Revision A

Page

•

Changed text in the Package Specific section From: "The TVB1440 package has a 5.6 mm x 5.6 mm thermal pad."

To: "The TVB1440 package has a 4.1 mm x 4.1 mm thermal pad.".................................................................................... 21

2

ECCN：3E991

TVB1440

www.ti.com.cn

ZHCSD29A –NOVEMBER 2014–REVISED NOVEMBER 2014

6 Pin Configuration and Functions

VQFN 0.5 mm Pitch

RGZ 48 Pin

Top View

36 35 34 33 32 31 30 29 28 27

37

26 25

24

VDD

IN0p

IN0n

NC

GND

38

39

40

41

42

43

44

45

46

47

48

23

22

OUT0p

OUT0n

VDD

21

20

19

18

17

16

IN1p

IN1n

OUT1p

OUT1n

GND

VDD

IN2p

IN2n

OUT2p

OUT2n

VDD

15

14

13

NC

IN3p

IN3n

OUT3p

OUT3n

11

1

2

3

4

5

6

7

8

9

10

12

Pin Functions

NO.

DESCRIPTION

SIGNAL

I/O

DATA LANES PINS

IN0p, IN0n

IN1p, IN1n

IN2p, IN2n

IN3p, IN3n

OUT0p, OUT0n

OUT1p, OUT1n

OUT2p, OUT2n

OUT3p, OUT3n

CONTROL PINS

ADDR

38, 39

41, 42

44, 45

47, 48

23, 22

20, 19

17, 16

14, 13

Lane 0 Differential Input

Lane 1 Differential Input

Lane 2 Differential Input

Lane 3 Differential Input

Lane 0 Differential Output

Lane 1 Differential Output

Lane 2 Differential Output

Lane 3 Differential Output

Input

(100Ω diff)

Output

(100Ω diff)

I²C Target Address Select.

3

26

3-level Input

I

EN

Device Enable. This input incorporates internal pullup of 200 kΩ.

NC

7, 40, 46

No Connect. These terminals may be left un-connected, or connect to GND.

Active Low Device Reset. This is 1.1V input. This input includes a 150kΩ resistor to the V_DDDcore

supply. An external capacitor to GND is recommended on the RSTN input to provide a power-up delay.

This signal is used to place the TVB1440 into Shutdown mode for the lowest power consumption. When

the RSTN input is asserted, all outputs are high-impedance, and inputs are ignored; all I²C registers are

reset to their default values. At power up, the RSTN input must not be de-asserted until the V_CCand V_DD

supplies have reached at least the minimum recommended supply voltage level.

RSTN

35

I

RSVD1

RSVD2

RSVD3

RSVD4

10

11

27

28

I

Reserved pins. Please connect the pin to GND through 1K resistor.

Reserved pins. Please connect the pin to VCC through 1K resistor.

Reserved pins. Please connect the pin to GND through 1K resistor.

SCL_CTL

SDA_CTL

4

5

Bidirectional I2C interface to configure TVB1440. This interface is active independent of EN input but

inactive when RSTN is low.

I/O

8, 9, 29, 30,

33, 34

TEST1-6

Test Outputs. Do not connect.

3

ECCN：3E991

TVB1440

ZHCSD29A –NOVEMBER 2014–REVISED NOVEMBER 2014

www.ti.com.cn

Pin Functions (continued)

NO.

DESCRIPTION

SIGNAL

I/O

SUPPLY AND GROUND PINS

18, 24, 31,

GND

PAD

Ground. Reference GND connections include the device package exposed thermal pad.

2, 6, 12, 15,

VDD

VCC

21, 25, 32,

37, 43

Low voltage supply for analog and digital core. Nominally 1.1V

3.3V Supply

1, 36

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)

(1)

MIN

–0.3

MAX

4

UNIT

VCC

Supply voltage

VDD

V

1.3

4

HS Link I/O (OUTx, INx) Differential Voltage

Voltage range

RSTN

V

SCL_CTL, SDA_CTL, ADDR, EN

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

7.2 Handling Ratings

MIN

-65

MAX

150

UNIT

T_STG

Storage temperature range

Human body model (HBM)⁽¹⁾

Charged-device model (CDM)⁽²⁾

·C

Electrostatic

discharge

–2000

–500

2000

500

V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN

3

TYP

MAX UNIT

VCC

VDD

V_IH

Supply Voltage, IO

3.6

1.26

3.6

V

Supply Voltage, CORE

1

High-level input voltage for ADDR, EN

Low-level input voltage for ADDR, EN

High-level input voltage for RSTN (typical hysteresis of 80mV)

Low-level input voltage for RSTN (typical hysteresis of 80mV)

Operating free-air temperature

1.9

0

V

V_IL

0.8

V

V_IH,RSTN

V_IL,RSTN

T_A

0.75

0.3

V

0

85

°C

kHz

f_scl

I2C CK frequency at SCL_CTL (standard I2C mode⁽¹⁾

)

100

(1) The local interface through SCL_CTL and SDA_CTL should follow standard mode I2C specifications

4

ECCN：3E991

TVB1440

www.ti.com.cn

ZHCSD29A –NOVEMBER 2014–REVISED NOVEMBER 2014

7.4 Thermal Information

TVB1440

UNIT

THERMAL METRIC⁽¹⁾

RGZ (48 Pin)

R_θJA

Junction-to-ambient thermal resistance

35.1

21.5

R_θJC(top)

R_θJB

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

11.7

°C/W

1.2

ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

ψ_JB

11.9

6.7

R_θJC(bot)

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

7.5 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)

PARAMETER

Supply current 4 lanes operation⁽¹⁾

Shutdown supply current⁽¹⁾

MIN

TYP

130

1.5

35

MAX

230

3

UNIT

mA

I_CC

I_STDN

I_OD

mA

Squelch (output disable) supply current

50

mA

V_OD0

V_OD1

V_OD2

V_OD3

PE₀

238

357

484

700

340

510

690

1000

0

442

663

897

1300

Output differential voltage swing

Output pre-emphasis

mVpp

dB

PE₁

3

PE₂

6

PE₃

9

R_OUT

I_(TXSHORT)

V_(SQUELCH)

Driver output impedance

50

Ω

Output pins short circuit current limit

Squelch threshold voltage for input signals (default)

50

mA

80

mVpp

(1) Values are V_DDsupply measurements; VCC supply measurements are 5 mA (typical) and 8 mA (max), with zero current in shutdown

mode.

7.6 Timing Requirements

MIN

TYP

MAX

UNIT

t_ramp1

t_ramp2

t_ramp3

Time V_DDmust stable before V_CCis applied

10

µS

Time RSTN must remain asserted until V_CC/V_DDvoltage has reached minimum

recommended operation

100

400

µS

Time device will be available for operation after a valid reset

mS

5

ECCN：3E991

TVB1440

ZHCSD29A –NOVEMBER 2014–REVISED NOVEMBER 2014

www.ti.com.cn

7.7 Switching Characteristics

over operating free-air temperature range (unless otherwise noted)

PARAMETER

MIN

TYP

MAX

UNIT

ps

t_PD

t_sk1

t_sk2

Propagation delay time

300

Intra-pair output skew (Figure 1)

Inter-pair output skew (Figure 1)

20

ps

100

ps

Total peak-to-peak residual jitter

Δt_jit

15

ps

V_OD0; PE₀; EQ = 8dB; clean source; minimum input and output cabling; PRBS7 data

pattern.

Squelch entry time

Time from a loss of valid input signal to ML output off

t_{sq_enter}

t_{sq_exit}

10

120

1

µS

Squelch exit time

Time from valid input signal available while in squelch mode to ML outputs on

Figure 1. Output Skew Definitions

6

ECCN：3E991

TVB1440

www.ti.com.cn

ZHCSD29A –NOVEMBER 2014–REVISED NOVEMBER 2014

7.8 Typical Characteristics

12

10

8

23

22

21

20

19

18

17

16

15

14

6

4

2

0

-2

-4

-6

6 dB Setting

10 dB Setting

15 dB Setting

10M

100M

Frequency (Hz)

1G

10G

0

20

40

60

80

100

120

Total Input Jitter (ps) (pk-pk)

D001

D002

Figure 2. Typical EQ Gain Curves (simulations)

Figure 3. Jitter Performance with Optimal EQ Settings

Figure 4. 3.75-Gbps Input With 20 Inch Trace

Figure 5. 3.75-Gbps Output with 20 Inch Input Trace and

8-dB EQ Setting

Figure 6. 5-Gbps Input with 20 Inches Trace

Figure 7. 5-Gbps Output with 20 Inch Input Trace and

13-dB EQ Setting

7

ECCN：3E991

TVB1440

ZHCSD29A –NOVEMBER 2014–REVISED NOVEMBER 2014

www.ti.com.cn

8 Detailed Description

8.1 Overview

TVB1440 is a 4 channel HS re-driver signal conditioner for TV applications. I2C control provides the wide ranges

of flexibility to configure the device for optimal signal conditioning so that video data link between a source and

sink can achieve high fidelity. TVB1440 allows larger distance between a Chipset and TCON boards through its

excellent jitter cleaning capability.

The TVB1440 is optimized for power conscience applications. Apart from its low active power, TVB1440 contains

activity detection circuitry on the data link input that transitions to a low-power output disable mode in the

absence of a valid input signal. This activity detect circuit can be disabled if desired. The device also has a

shutdown mode when exercised results in 2 mW.

The TVB1440 receiver and driver provide input and output common mode voltage bias. It is required that both

receive and transmit end of the device is ac coupled in application use cases. Suggested value for the ac

coupling capacitors is 75-200 nF.

8.2 Functional Block Diagram

VDD

ADDR

R_RST=150k

RESET

VCC

VDD

GND

RSTN

EN

R_EN=200k

VCC

V_Iterm

V_BIAS

50

IN0p

IN0n

OUT0p

OUT0n

Driver

EQ

V_Iterm

V_BIAS

IN1p

IN1n

OUT1p

OUT1n

Driver

V_Iterm

V_BIAS

50

IN2p

IN2n

OUT2p

OUT2n

Driver

EQ

V_Iterm

V_BIAS

50

IN3p

IN3n

OUT3p

OUT3n

ADDR

EQ_CTL

I²C

Target

SCL_CTL

SDA_CTL

PE_CTL

CTRL

VOD_CTL

EN

8

ECCN：3E991

TVB1440

www.ti.com.cn

ZHCSD29A –NOVEMBER 2014–REVISED NOVEMBER 2014

8.3 Feature Description

8.3.1 Equalization

TVB1440 provides flexible continuous time linear equalization (CTLE) to compensate for large trace or cable loss

at its input resulting improved eye at the output signals. It has selectable control for receive equalization

accessible through I²C.

8.3.2 Configurable Output

Transmitter in each channel has 4 levels of pre-emphasis and 4 levels of output voltage swing settings which

enable optimum video signal performance from the TVB1440 to downstream receiver.

8.3.3 Squelch

TVB1440 has active Squelch feature that allows automatic shutdown of output drivers when it does not have

valid input signal. The feature can be disabled through I2C if not desired.

8.4 Device Functional Modes

8.4.1 Active Mode

Normal operation mode. The data lanes of TVB1440 work normally.

8.4.2 Shutdown Mode

Device is in lowest power mode. This mode is invoked by de-asserting RSTN or EN low.

8.4.3 Squelch Mode

The device does not have valid input signal. Output drivers are turned off.

8.5 Programming

8.5.1 Local I²C Interface

It is required to use the TVB1440’s local I²C interface to configure the TVB1440’s receivers (IN[3:0]P/N) and

transmitters (OUT[3:0]P/N). The TVB1440’s internal registers are accessed through the SCL_CTL pin and

SDA_CTL pin. The 7-bit I²C slave address of the TVB1440 is determined by the ADDR pin.

Table 1. TVB1440 I²C Slave Address Options

ADDR

7-BIT I²C SLAVE ADDRESS

READ SLAVE ADDRESS

WRITE SLAVE ADDRESS

Low (VIL)

V_CC/2 (VIM)

High (VIH)

7’b0101100

‘h59

‘h5B

‘h5D

‘h58

‘h5A

‘h5C

7’b0101101

7’b0101110

Before adjusting the TVB1440’s registers, a writing a zero to bit 2 of address 04h is required to enable the

receiver and transmitter adjustments.

9

ECCN：3E991

TVB1440

ZHCSD29A –NOVEMBER 2014–REVISED NOVEMBER 2014

www.ti.com.cn

8.5.2 Receiver (IN[3:0]P/N) Adjustments

8.5.2.1 Equalization Level

It is recommended to use the TVB1440 local I²C interface to configure the TVB1440 receiver equalization level.

Software should then enable equalization control by writing a one to EQ_I2C_ENABLE bit (bit 7 at address 05h).

After EQ_I2C_ENABLE is set, then software can program the equalization for each lane (IN[3:0]) to the

appropriate value. Refer to Table 2 for details on equalization settings for each lane.

Table 2. TVB1440 Equalization Levels

Address

Bits(s) Description

Access

Receiver and transmitter adjustment.

04h

2

2:0

7

0 – configure receiver and transmitter using I2C (required)

1 – reserved (default)

RW

EQ_LEVEL_LANE0. This field selects the EQ gain level for Lane 0 (IN0P/N).

000 – 0 dB

001 – 2 dB (3.75Gbps); 2.5 dB (5Gbps)

010 – 3.5 dB (3.75Gbps); 5 dB (5Gbps)

011 – 5 dB (3.75Gbps); 6 dB (5Gbps)

100 – 6.5 dB (3.75Gbps); 8 dB (5Gbps)

101 – 8 dB (3.75Gbps); 11 dB (5Gbps)

110 – 9.5 dB (3.75Gbps); 13 dB (5Gbps)

111 – 12 dB (3.75Gbps); 15 dB (5Gbps)

05h

RW

EQ_I2C_ENABLE. This field allows EQ control through I2C

0 – reserved (default)

1 – EQ level is set by I2C (required)

EQ_LEVEL_LANE1. This field selects the EQ gain level for Lane 1 (IN1P/N. Bit definition identical to

that of EQ_LEVEL_LANE0.

07h

09h

0Bh

2:0

RW

EQ_LEVEL_LANE2. This field selects the EQ gain level for Lane 2 (IN2P/N). Bit definition identical

to that of EQ_LEVEL_LANE0.

EQ_LEVEL_LANE3. This field selects the EQ gain level for Lane 3 (IN3P/N. Bit definition identical to

that of EQ_LEVEL_LANE0.

8.5.2.2 Squelch Level

The TVB1440 squelch level defaults to 80mVpp. If it is necessary to adjust the squelch level, it can be done by

changing the SQUELCH_SENSITIVITY register located in the TVB1440’s Local I2C register space.

Table 3. Squelch Sensitivity Levels

Address

Bits(s) Description

Access

SQUELCH_SENSITIVITY. Main link squelch sensitivity is selected by this field, and determines the

transitions to and from the Output Disable mode.

00 – Main Link IN0P/N squelch detection threshold is set to 40mVpp.

01 – Main Link IN0P/N squelch detection threshold is set to 80mVpp. (Default)

10 – Main Link IN0P/N squelch detection threshold is set to 160mVpp.

11 – Main Link IN0P/N squelch detection threshold is set to 250mVpp.

5:4

3

RW

03h

SQUELCH_ENABLE.

0 – Main Link IN0P/N squelch detection is enabled (default)

1 – Main Link IN0P/N squelch detection is disabled.

RW

10

ECCN：3E991

TVB1440

www.ti.com.cn

ZHCSD29A –NOVEMBER 2014–REVISED NOVEMBER 2014

8.5.3 Main Link Output [OUT[3:0]P/N] Adjustments

The TVB1440 Main link outputs (OUT[3:0]) must be set in link address space by following specified I²C access

method.

8.5.3.1 LINK Address Space

Access to and from the TVB1440 LINK address space is indirectly addressable through the local I²C registers as

illustrated in the Figure 8.

TVB1440's Local I2C

Address Space

TVB1440's Link

Address Space

1Ch

1Dh

1Eh

1Fh

LINK_ADDR_HIGH

LINK_ADDR_MID

LINK_ADDR_LOW

LINK_DATA

Local I2C

Acceses

20-bit LINK Register

Data Read/Write

Figure 8. Accessing TVB1440 LINK Registers

The configuration of these registers can be performed through the local I²C interface, where three registers (from

1Ch to 1Eh) are used as the address to the LINK register and another one (1Fh) as a data to be read/written.

11

ECCN：3E991

TVB1440

ZHCSD29A –NOVEMBER 2014–REVISED NOVEMBER 2014

www.ti.com.cn

8.5.4 Example Script

The script below is for a Total Phase Aardvark I²C controller. Details on the Total Phase Aardvark I²C controller

can be obtained from the Total Phase website. This example is for a 5.0 Gbps data rate with 4 active lanes.

space

<i2c_bitrate khz="100"/>

space

======Program the device=====

<i2c_write addr="0x2D" count="1" radix="16">04 00</i2c_write> />

space

======Program Link Bandwidth Settings to 5Gbps======LINK 00100h=====

<i2c_write addr="0x2D" count="1" radix="16">1C 00</i2c_write> />

<i2c_write addr="0x2D" count="1" radix="16">1D 01</i2c_write> />

<i2c_write addr="0x2D" count="1" radix="16">1E 00</i2c_write> />

<i2c_write addr="0x2D" count="1" radix="16">1F 14</i2c_write> />

space

======Program Num of Lanes to 4.s======LINK 00101h=====

<i2c_write addr="0x2D" count="1" radix="16">1C 00</i2c_write> />

<i2c_write addr="0x2D" count="1" radix="16">1D 01</i2c_write> />

<i2c_write addr="0x2D" count="1" radix="16">1E 01</i2c_write> />

<i2c_write addr="0x2D" count="1" radix="16">1F 04</i2c_write> />

space

======Program VOD L1 and Pre-Emphasis L0 for Lane 0======LINK 00103h=====

<i2c_write addr="0x2D" count="1" radix="16">1C 00</i2c_write> />

<i2c_write addr="0x2D" count="1" radix="16">1D 01</i2c_write> />

<i2c_write addr="0x2D" count="1" radix="16">1E 03</i2c_write> />

<i2c_write addr="0x2D" count="1" radix="16">1F 01</i2c_write> />

space

======Program VOD L1 and Pre-Emphasis L0 for Lane 1======LINK 00104h=====

<i2c_write addr="0x2D" count="1" radix="16">1C 00</i2c_write> />

<i2c_write addr="0x2D" count="1" radix="16">1D 01</i2c_write> />

<i2c_write addr="0x2D" count="1" radix="16">1E 04</i2c_write> />

<i2c_write addr="0x2D" count="1" radix="16">1F 01</i2c_write> />

space

======Program VOD L1 and Pre-Emphasis L0 for Lane 2======LINK 00105h=====

<i2c_write addr="0x2D" count="1" radix="16">1C 00</i2c_write> />

<i2c_write addr="0x2D" count="1" radix="16">1D 01</i2c_write> />

<i2c_write addr="0x2D" count="1" radix="16">1E 05</i2c_write> />

<i2c_write addr="0x2D" count="1" radix="16">1F 01</i2c_write> />

space

======Program VOD L1 and Pre-Emphasis L0 for Lane 3======LINK 00106h=====

<i2c_write addr="0x2D" count="1" radix="16">1C 00</i2c_write> />

<i2c_write addr="0x2D" count="1" radix="16">1D 01</i2c_write> />

<i2c_write addr="0x2D" count="1" radix="16">1E 06</i2c_write> />

<i2c_write addr="0x2D" count="1" radix="16">1F 01</i2c_write> />

space

======Set Power Mode to Normal======LINK 00600h=====

<i2c_write addr="0x2D" count="1" radix="16">1C 00</i2c_write> />

<i2c_write addr="0x2D" count="1" radix="16">1D 06</i2c_write> />

<i2c_write addr="0x2D" count="1" radix="16">1E 00</i2c_write> />

<i2c_write addr="0x2D" count="1" radix="16">1F 01</i2c_write> />

space

=====May want to adjust Squelch Level===

<i2c_write addr="0x2D" count="1" radix="16">03 10</i2c_write> />

space

=====Enable EQ===

<i2c_write addr="0x2D" count="1" radix="16">05 80</i2c_write> />

space

=====Set EQ level to 11dB(5Gbps) for lane 0===

<i2c_write addr="0x2D" count="1" radix="16">05 85</i2c_write> />

space

=====Set EQ level to 11dB(5Gbps) for lane 1===

<i2c_write addr="0x2D" count="1" radix="16">07 05</i2c_write> />

space

=====Set EQ level to 11dB(5Gbps) for lane 2===

<i2c_write addr="0x2D" count="1" radix="16">09 05</i2c_write> />

space

=====Set EQ level to 11dB(5Gbps) for lane 3===

<i2c_write addr="0x2D" count="1" radix="16">0B 05</i2c_write> />

</aardvark>

12

ECCN：3E991

TVB1440

www.ti.com.cn

ZHCSD29A –NOVEMBER 2014–REVISED NOVEMBER 2014

8.6 Register Maps

Table 4. TVB1440 LINK Registers

LINK Address

NAME

Value Written

06h

0Ah

14h

00h

01h

02h

04h

00h

08h

10h

18h

01h

09h

11h

02h

0Ah

03h

00h

08h

10h

18h

01h

09h

11h

02h

0Ah

03h

00h

08h

10h

18h

01h

09h

11h

02h

0Ah

03h

00h

08h

10h

18h

01h

09h

11h

02h

0Ah

03h

01h

02h

Value Read

00h

01h

02h

00h

01h

03h

0Fh

00h

04h

08h

0Ch

01h

05h

09h

02h

06h

03h

00h

04h

08h

0Ch

01h

05h

09h

02h

06h

03h

00h

04h

08h

0Ch

01h

05h

09h

02h

06h

03h

00h

04h

08h

0Ch

01h

05h

09h

02h

06h

03h

00h

01h

Description

<1.6Gbps per lane

00100h

LINK_BW_SET

1.6-2.7Gbps per lane

2.7-5.0Gbps per lane

All Lanes disabled

One lane enabled (OUT0).

00101h

LANE_COUNT_SET

Two lanes enabled (OUT[1:0]).

Four lanes enabled (OUT[3:0]).

VOD Level 0 and Pre-emphasis Level 0 for OUT0.

VOD Level 0 and Pre-emphasis Level 1 for OUT0.

VOD Level 0 and Pre-emphasis Level 2 for OUT0.

VOD Level 0 and Pre-emphasis Level 3 for OUT0.

VOD Level 1 and Pre-emphasis Level 0 for OUT0.

VOD Level 1 and Pre-emphasis Level 1 for OUT0.

VOD Level 1 and Pre-emphasis Level 2 for OUT0.

VOD Level 2 and Pre-emphasis Level 0 for OUT0.

VOD Level 2 and Pre-emphasis Level 1 for OUT0.

VOD Level 3 and Pre-emphasis Level 0 for OUT0

VOD Level 0 and Pre-emphasis Level 0 for OUT1.

VOD Level 0 and Pre-emphasis Level 1 for OUT1.

VOD Level 0 and Pre-emphasis Level 2 for OUT1.

VOD Level 0 and Pre-emphasis Level 3 for OUT1.

VOD Level 1 and Pre-emphasis Level 0 for OUT1.

VOD Level 1 and Pre-emphasis Level 1 for OUT1.

VOD Level 1 and Pre-emphasis Level 2 for OUT1.

VOD Level 2 and Pre-emphasis Level 0 for OUT1.

VOD Level 2 and Pre-emphasis Level 1 for OUT1.

VOD Level 3 and Pre-emphasis Level 0 for OUT1

VOD Level 0 and Pre-emphasis Level 0 for OUT2.

VOD Level 0 and Pre-emphasis Level 1 for OUT2.

VOD Level 0 and Pre-emphasis Level 2 for OUT2.

VOD Level 0 and Pre-emphasis Level 3 for OUT2.

VOD Level 1 and Pre-emphasis Level 0 for OUT2.

VOD Level 1 and Pre-emphasis Level 1 for OUT2.

VOD Level 1 and Pre-emphasis Level 2 for OUT2.

VOD Level 2 and Pre-emphasis Level 0 for OUT2.

VOD Level 2 and Pre-emphasis Level 1 for OUT2.

VOD Level 3 and Pre-emphasis Level 0 for OUT2

VOD Level 0 and Pre-emphasis Level 0 for OUT3.

VOD Level 0 and Pre-emphasis Level 1 for OUT3.

VOD Level 0 and Pre-emphasis Level 2 for OUT3.

VOD Level 0 and Pre-emphasis Level 3 for OUT3.

VOD Level 1 and Pre-emphasis Level 0 for OUT3.

VOD Level 1 and Pre-emphasis Level 1 for OUT3.

VOD Level 1 and Pre-emphasis Level 2 for OUT3.

VOD Level 2 and Pre-emphasis Level 0 for OUT3.

VOD Level 2 and Pre-emphasis Level 1 for OUT3.

VOD Level 3 and Pre-emphasis Level 0 for OUT3

Normal Mode

00103h

00104h

00105h

LANE0_SET

LANE1_SET

LANE2_SET

00106h

LANE3_SET

00600h

SET_POWER

Power-Down mode.

13

ECCN：3E991

TVB1440

ZHCSD29A –NOVEMBER 2014–REVISED NOVEMBER 2014

www.ti.com.cn

9 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

9.1 Application Information

TVB1440 is a signal conditioner especially suited for equalizing channel loss due to traces and flexible cable

between digital TV chipset and TCON receiver.

9.1.1 Typical Application

The device can be helpful improving eye diagram by placing it either end of the flexible cable in digital TV chipset

or TCON board or at the both. Figure 9 shows a typical application for TV interface.

TVB

1440

TVB

1440

TVB

1440

TVB

1440

FPC Cable

TVB

1440

TVB

1440

TVB

1440

TVB

1440

Figure 9. Typical Application of TVB1440 in 4K2K Digital TV Interface

9.1.1.1 Design Requirements

Table 5. Design Parameters

PARAMETER

V_DDSupply

V_CCSupply

VALUE

1.1 V

3.3 V

TV Max Resolution Requirement

Pixel Clock (MHz)

Horizontal Active (pixels)

Vertical Active

1194

3840

2160

Color bit Depth (6bpc, 8bpc, 10bpc)

Refresh Rate

10 (30 bpp)

120 Hz

B

Panel Configuration (A or B)

Channel Requirements

Input Channel Insertion Loss

Output Channel Insertion Loss

Up to 12 dB at 3.75 Gbps

TVB1440 Settings

Number of Lanes (1, 2, or 4)

Link Rate (Gbps)

4

3.75

RX EQ Setting (dB)

6.5 dB

TX VOD Setting (Level 0, 1, 2, or 3)

TX Pre-Emphasis Setting (Level 0, 1, 2, or 3)

Level 3 (1000 mVpp)

Level 0 (0 dB)

14

ECCN：3E991

TVB1440

www.ti.com.cn

ZHCSD29A –NOVEMBER 2014–REVISED NOVEMBER 2014

9.1.1.2 Detailed Design Procedure

9.1.1.2.1 Common 4k2k TV Panel Configuration

A common 4k2k TV is broken into four 1920 x 1080 panels or four 960 x 2160 panels. For this particular

implementation, panel configuration B is assumed. It is also assumed that two TVB1440 are used for each panel

(one near SOC and one near TCON) for a total of eight TVB1440.

Configuration A

Configuration B

Figure 10. Common Panel Configurations

9.1.1.2.2 1Max Stream Rate

The maximum stream rate can be derived from the maximum TV resolutions pixel clock and color depth. For this

example, the maximum pixel clock is 1194 MHz. Because the TV is broken into 4 panels, the actual pixel clock

for each panel is 298.5 MHz.

Stream Bit Rate = PixelClock x bpp

Stream Bit Rate = 298.5 x 30

Stream Bit Rate = 8.955 Gbps.

9.1.1.2.3 Encoded Stream Rate

Most high-speed video standards are 8b10b encoded. Because of 8b10b encoding overhead, an additional 20%

must be added to the stream bit rate. On top of the 8b10b, there are some additional overhead due to

packetization before the 8b10b encode that also must be added to the stream bit rate. For example, a particular

video standard may define the actual coded stream rate by the following equation.

Encoded_Stream_Rate = #_of_Bytes_for_bpp x 8 x 1.25 x PixelClock

Encoded_Stream_Rate = 11.94Gbps.

15

ECCN：3E991

TVB1440

ZHCSD29A –NOVEMBER 2014–REVISED NOVEMBER 2014

www.ti.com.cn

9.1.1.2.4 TVB1440 Configuration

The TVB1440 must be configured by the SOC using I2C. Because of the limited number of I2C address available

on the TVB1440, an I2C switch needs to be incorporated in order to configure each of the TVB1440. Figure 11

shows an example implement using the Texas Instruments TCA9546A 4-channel I2C switch.

TVB1440

I2C Address 0x58/59

I2C Address 0x5C/5D

I2C_BUS1

I2C_BUS2

TVB1440

I2C Address 0x58/59

TVB1440

I2C Address 0x5C/5D

SCL

SDA

SOC

I2C Switch

(TCA9546A)

TVB1440

I2C Address 0x58/59

I2C Address 0x5C/5D

I2C_BUS3

I2C_BUS4

TVB1440

I2C Address 0x58/59

TVB1440

I2C Address 0x5C/5D

TCA9546A I2C address options:

7'b1110XYZ where X = A2, Y= A1, Z = A0

Figure 11. Example I2C Switch Implementation

9.1.1.2.5 Receiver Equalization Setting

The TVB1440 has a receiver equalizer that is adjustable from 0dB to 15 dB at 5 Gbps. The common approach to

determine the proper equalizer setting is to measure the insertion loss of the channel at the input of the TVB1440

at the Nyquist frequency of the data rate (1.875 GHz for 3.75 Gbps and 2.5 GHz for 5 Gbps). For example, if the

input channel is 20 inches of trace with 4 mil width over FR4, the insertion loss at 3.75 Gbps would be -7.3 dB

and at 5 Gbps would be -9.1 dB. The register EQ_LEVEL_LANEx, where X = 0, 1, 2, or 3 should be

programmed to 3’b100 for a 3.75 Gbps data rate and should be programmed to 3’b101. The actual setting may

need to be adjusted based on the additional channel parasitics from package, vias, and connectors.

0

m1

-5

m2

-10

-15

-20

-25

-30

-35

0

1

2

3

4

5

6

Frequency (GHz)

7

8

9

10

m1 frequency = 1.876 GHz

m2 frequency = 2.500 GHz

I_L= –7.346

I_L= –9.185

Figure 12. Insertion Loss of 20 Inch FR4 Trace With 4-mil Width

16

ECCN：3E991

TVB1440

www.ti.com.cn

ZHCSD29A –NOVEMBER 2014–REVISED NOVEMBER 2014

9.1.1.2.6 Transmitter Settings

The TVB1440’s transmitter controls have four settings for voltage swing and four settings for pre-emphasis. The

best transmitter setting to use is a function of the output channel insertion loss and the inputs eye requirement of

the device at end of the channel. For the case in which a TVB1440 is at the end of the channel, the output

channel’s insertion loss should not be greater than the receiver equalization of the TVB1440.

To specify the largest eye opening at the end of the channel, the best voltage swing setting should be either level

2 or level 3. It is also recommended to use either a pre-emphasis level of 0 dB or 3dB. The pre-emphasis setting

can be thought of as a way to reduce the amount receiver equalizer required by the device at end channel. For

example, a 3.5dB setting could allow for the receive equalization setting for the TVB1440 to be reduced from

12dB to 10dB. If necessary, these settings can be adjusted up or down in order to improve the eye opening at

the end of the channel.

9.1.1.2.7 RESET

The TVB1440 RSTN input gives control over the device reset and to place the device into shut-down mode.

When RSTN is low, all registers are reset to their default values, which means all HS Link ports are disable.

When the RSTN pin is released back to high, the device comes out of the shut-down mode. To turn on the HS

Link, it is necessary to provision the device registers through the local I²C_CTL interface.

It is critical to transition the RSTN input from a low to a high level after both V_CCand V_DDsupply voltages have

reached the minimum recommended operating voltage. This is achieved by a control signal to the RSTN input, or

by an external capacitor connected between RSTN and GND. To insure that the TVB1440 is properly reset, the

RSTN pin must be de-asserted for at least 100 μs before being asserted.

The RSTN input includes a 150k resistor from the input to the V_DDsupply. An external capacitor connected

between RSTN and GND allows delaying the RSTN signal during power up. When implementing the external

capacitor the size of the external capacitor depends on the power up ramp of the VCC and VDD supplies; a

slower ramp-up results in a larger value external capacitor. Approximately 200 nF capacitor is a reasonable first

estimate for the size of the external capacitor for most applications.

Both RSTN implementations are shown in Figure 13.

VDD

GPO

RSTN

C

150K

C

TVB1440

controller

TVB1440

Figure 13. (a) Reset Implementation Using a Capacitor, (b) Microprocessor Drives the Pin

Figure 14 shows a typical schematic implementation either in TV chipset or TCONS receiver board.

17

ECCN：3E991

TVB1440

ZHCSD29A –NOVEMBER 2014–REVISED NOVEMBER 2014

www.ti.com.cn

VCC_3P3V

R3

VDD_1P1V

R1

1K

r0402 r0402

5% 5%

R2

1K

10K (DNI)

r0402

5%

TVB1440_RSTN

TVB1440_EN

RSTN must be

held low until

VCC and VDD are

active and

C1

0.2uF

U1

stable.

TVB1440RGZ

24

GND

37

38

39

40

41

42

43

44

45

46

47

48

49

VDD

23

22

21

20

19

18

17

16

15

14

13

OUT0P

OUT0N

IN0P

IN0N

IN0P

IN0N

NC2

IN1P

IN1N

VDD

IN2P

IN2N

NC3

IN3P

IN3N

TP

OUT0P

VDD_1P1V

C3

OUT0N

VDD

C2

C4

C5

C6

C7

C8

OUT1P

OUT1N

IN1P

IN1N

OUT1P

OUT1N

GND

0.1uF 0.1uF 0.1uF 10uF 0.1uF 0.01uF 0.01uF

OUT2P

OUT2N

IN2P

IN2N

OUT2P

OUT2N

VDD

VCC_3P3V

OUT3P

OUT3N

IN3P

IN3N

OUT3P

OUT3N

C9

C10

C11

10uF

0.1uF

ADDR

SCL_CTL

SDA_CTL

R5

1K

r0402

5%

R4

1K

VCC_3P3V

r0402

C12

1uF

5%

Figure 14. Schematic Implementation of TVB1440

18

ECCN：3E991

TVB1440

www.ti.com.cn

ZHCSD29A –NOVEMBER 2014–REVISED NOVEMBER 2014

10 Power Supply Recommendations

The following power-up and power-down sequences describe how the RSTN signal is applied to the TVB1440.

10.1 Power-Up Sequence

1. Apply VDD then VCC (recommended both less than 10-ms ramp time). VDD must be asserted first and

stable for greater than 10 μs before VCC is applied.

2. RSTN must remain asserted until VCC/VDD voltage has reached minimum recommended operation for more

than 100 μs.

3. De-assert RSTN (Note: This RSTN is a 1.1V interface and is internally connected to VDD through a 150-kΩ

resistor).

4. Device will be available for operation approximately 400 ms after a valid reset.

VCC

VDD

VCC/VDD

T > 10 µs

RSTN

T > 100 µs

Device

Available

T > 400 ms

Figure 15. Power-up Sequence

10.2 Power-Down Sequence

There is no power-down sequence required.

19

ECCN：3E991

TVB1440

ZHCSD29A –NOVEMBER 2014–REVISED NOVEMBER 2014

www.ti.com.cn

11 Layout

11.1 Layout Guidelines

11.1.1 Differential Pairs

This section describes the layout recommendations for all the TVB1440 differential pairs: IN[3:0] and OUT[3:0].

•

Must be designed with a differential impedance of 100 Ω ± 10% or 50-Ω single-ended impedance.

In order to minimize cross talk, it is recommended to keep high speed signals away from each other. Each

pair should be separated by at least 5 times the signal trace width.

•

Route all differential pairs on the same layer adjacent to a solid ground plane.

Do not route differential pairs over any plane split.

Adding test points causes impedance discontinuity and; therefore, negative impacts signal performance. If

test points are used, they should be placed in series and symmetrically. They must not be placed in a manner

that causes stub on the differential pair.

•

Avoid 90 degree turns in trace. The use of bends in differential traces should be kept to a minimum. When

bends are used, the number of left and right bends should be as equal as possible and the angle of the bend

should be ≥ 135 degrees. This minimizes any length mismatch causes by the bends; and therefore,

minimizes the impact bends have on EMI.

•

Minimize the trace lengths of the differential pair traces. Longer trace lengths require very careful routing to

assure proper signal integrity.

Keep intra-pair skew to a minimum in order to minimize EMI. There should be less than 5 mils difference

between a differential pair signal and its complement.

Minimize the use of vias in the differential pair paths as much as possible. If this is not practical, make sure

that the same via type and placement are used for both signals in a pair. It is recommended to keep the vias

count to 2 or less.

11.1.2 Layout Example

Figure 16. TBV1440 Layout

20

ECCN：3E991

TVB1440

www.ti.com.cn

ZHCSD29A –NOVEMBER 2014–REVISED NOVEMBER 2014

Layout Guidelines (continued)

11.1.3 Placement

•

A 100-nF should be placed as close as possible on each V_DDand V_CCpower pin.

The 100-nF capacitors on the IN[3:0] and OUT[3:0] nets should be placed close to the connector.

The ESD and EMI protection devices (if used) should also be placed as possible to the connector.

11.1.4 Package Specific

•

The TVB1440 package as a 0.5 mm pin pitch

The TVB1440 package has a 4.1 mm x 4.1 mm thermal pad. This thermal pad must be connected to ground

through a system of vias.

•

All vias under device, except for those connected to thermal pad, should be solder masked to avoid any

potential issues with thermal pad layouts.

11.1.5 Ground

It is recommended that only one board plane be used in the design. This provides the best image plane for

signal traces running above the plane. The thermal pad of the TVB1440 should be connected to this plane

through a system of vias.

21

ECCN：3E991

TVB1440

ZHCSD29A –NOVEMBER 2014–REVISED NOVEMBER 2014

www.ti.com.cn

12 器件和文档支持

12.1 商标

All trademarks are the property of their respective owners.

12.2 静电放电警告

这些装置包含有限的内置 ESD 保护。存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损

伤。

12.3 Export Control Notice

Recipient agrees to not knowingly export or re-export, directly or indirectly, any product or technical data (as

defined by the U.S., EU, and other Export Administration Regulations) including software, or any controlled

product restricted by other applicable national regulations, received from disclosing party under nondisclosure

obligations (if any), or any direct product of such technology, to any destination to which such export or re-export

is restricted or prohibited by U.S. or other applicable laws, without obtaining prior authorization from U.S.

Department of Commerce and other competent Government authorities to the extent required by those laws.

12.4 术语表

SLYZ022 — TI 术语表。

这份术语表列出并解释术语、首字母缩略词和定义。

13 机械封装和可订购信息

以下页中包括机械封装和可订购信息。这些信息是针对指定器件可提供的最新数据。这些数据会在无通知且不对

本文档进行修订的情况下发生改变。欲获得该数据表的浏览器版本，请查阅左侧的导航栏。

22

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应用

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数字音频

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能源

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DLP® 产品

DSP - 数字信号处理器

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接口

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安防应用

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IMPORTANT NOTICE

邮寄地址：上海市浦东新区世纪大道1568 号，中建大厦32 楼邮政编码： 200122

PACKAGE MATERIALS INFORMATION

www.ti.com

17-Dec-2014

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

A0

B0

K0

P1

W

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

TVB1440RGZR

VQFN

RGZ

48

2500

330.0

16.4

7.3

1.1

12.0

16.0

Q2

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

17-Dec-2014

*All dimensions are nominal

Device

Package Type Package Drawing Pins

VQFN RGZ 48

SPQ

Length (mm) Width (mm) Height (mm)

367.0 367.0 38.0

TVB1440RGZR

2500

Pack Materials-Page 2

GENERIC PACKAGE VIEW

RGZ 48

7 x 7, 0.5 mm pitch

VQFN - 1 mm max height

PLASTIC QUADFLAT PACK- NO LEAD

Images above are just a representation of the package family, actual package may vary.

Refer to the product data sheet for package details.

4224671/A

www.ti.com

PACKAGE OUTLINE

RGZ0048B

VQFN - 1 mm max height

S

C

A

L

E

2

.

0

PLASTIC QUAD FLATPACK - NO LEAD

7.15

6.85

A

B

PIN 1 INDEX AREA

7.15

6.85

1 MAX

C

SEATING PLANE

0.05

0.00

0.08 C

2X 5.5

4.1 0.1

(0.2) TYP

EXPOSED

THERMAL PAD

13

24

44X 0.5

12

25

49

SYMM

2X

5.5

0.30

0.18

36

48X

1

0.1

0.05

C B A

48

37

SYMM

PIN 1 ID

(OPTIONAL)

0.5

0.3

48X

4218795/B 02/2017

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

www.ti.com

EXAMPLE BOARD LAYOUT

RGZ0048B

VQFN - 1 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

(

4.1)

(1.115) TYP

(0.685)

TYP

37

48

48X (0.6)

1

36

48X (0.24)

(1.115)

TYP

44X (0.5)

(0.685)

TYP

SYMM

49

(

0.2) TYP

VIA

(6.8)

(R0.05)

TYP

12

25

13

24

SYMM

(6.8)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE:12X

0.07 MIN

ALL AROUND

0.07 MAX

ALL AROUND

SOLDER MASK

OPENING

METAL

EXPOSED METAL

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

NON SOLDER MASK

DEFINED

SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

4218795/B 02/2017

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

number SLUA271 (www.ti.com/lit/slua271).

5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown

on this view. It is recommended that vias under paste be filled, plugged or tented.

www.ti.com

EXAMPLE STENCIL DESIGN

RGZ0048B

VQFN - 1 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

(1.37)

TYP

37

48

48X (0.6)

1

36

48X (0.24)

44X (0.5)

(1.37)

TYP

SYMM

49

(R0.05) TYP

(6.8)

9X

METAL

TYP

(

1.17)

12

25

13

24

SYMM

(6.8)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

EXPOSED PAD 49

73% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE

SCALE:12X

4218795/B 02/2017

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

www.ti.com

重要声明和免责声明

TI 均以“原样”提供技术性及可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资

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所述资源可供专业开发人员应用TI 产品进行设计使用。您将对以下行为独自承担全部责任：(1) 针对您的应用选择合适的TI 产品；(2) 设计、

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TI 所提供产品均受TI 的销售条款 (http://www.ti.com.cn/zh-cn/legal/termsofsale.html) 以及ti.com.cn上或随附TI产品提供的其他可适用条款的约

束。TI提供所述资源并不扩展或以其他方式更改TI 针对TI 产品所发布的可适用的担保范围或担保免责声明。IMPORTANT NOTICE

邮寄地址：上海市浦东新区世纪大道 1568 号中建大厦 32 楼，邮政编码：200122


型号：	TVB1440RGZR
厂家：	TEXAS INSTRUMENTS
描述：	具有均衡功能的 4 通道电视转接驱动器 \| RGZ \| 48 \| 0 to 85 驱动电视驱动器
文件：	总31页 (文件大小：3094K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

TVB1440RGZR [TI]

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